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Power and Voltage Control for Single-Phase Cascaded H-Bridge Multilevel Converters Under Unbalanced Loads

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energies
Article
Power and Voltage Control for Single-Phase
Cascaded H-Bridge Multilevel Converters
under Unbalanced Loads
Daliang Yang 1, * , Li Yin 1 , Shengguang Xu 2
1
2
3
*
and Ning Wu 3
College of Electrical Engineering, Guangxi University, Nanning 530004, China; [email protected]
Liuzhou Power Supply Bureau, Gxuangxi Power Grid Corporation, Liuzhou 545005, China;
[email protected]
Electric Power Research Institute, Guangxi Power Grid Corporation, Nanning 530023, China;
[email protected]
Correspondence: [email protected]; Tel.: +86-0771-3232264
Received: 31 August 2018; Accepted: 11 September 2018; Published: 14 September 2018
Abstract: The conventional control method for a single-phase cascaded H-bridge (CHB) multilevel
converter is vector (dq) control; however, dq control requires complicated calculations and additional
time delays. This paper presents a novel power control strategy for the CHB multilevel converter.
A power-based dc-link voltage balance control is also proposed for unbalanced load conditions.
The new control method is designed in a virtual αβ stationary reference frame without coordinate
transformation or phase-locked loop (PLL) to avoid the potential issues related to computational
complexity. Because only imaginary voltage construction is needed in the proposed control method,
the time delay from conventional imaginary current construction can be eliminated. The proposed
method can obtain a sinusoidal grid current waveform with unity power factor. Compared with
the conventional dq control method, the power control strategy possesses the advantage of a fast
dynamic response. The stability of the closed-loop system with the dc-link voltage balance controller
is evaluated. Simulation and experimental results are presented to verify the accuracy of the proposed
power and voltage control method.
Keywords: cascaded H-bridge (CHB); dc-link voltage balance control; multilevel converter;
power control; single-phase system
1. Introduction
Multilevel converters have gained increasing attention as of late. Commonly used multilevel
converters include cascaded H-bridge (CHB), flying capacitor, and neutral-point-clamped converters [1].
Among these, the CHB converter has advantages of simple implementation, high reliability, and low
harmonics [2], hence, it has been widely researched in academia and industry, particularly in relation to
static synchronous compensators [3], solid-state transformers [4], and active power filters [5].
Many control schemes have been proposed to enable the pulse width modulation (PWM) converter
to achieve a high power factor and near-sinusoidal grid current [6]. These strategies can be broadly
classified into two categories: direct power control (DPC) and direct current control (DCC).
DPC was originally proposed by Ohnishi [7], whose method directly controls the active and
reactive power of the PWM converter using three-phase instantaneous power theory. Compared
with DCC, DPC has advantages of simple structure, fast dynamic response, high efficiency, and wide
applicability [8]. Currently, many advanced DPC strategies have been proposed, such as predictive
DPC (P-DPC) [9], deadbeat DPC [10], and slide-mode DPC [11]. In the single-phase PWM converter
Energies 2018, 11, 2435; doi:10.3390/en11092435
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Energies 2018, 11, 2435
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system, instantaneous power estimation is more complicated than in the three-phase system,
which limits the development of DPC schemes in single-phase systems [12].
DCC methods have been frequently used with the PWM converter. The most commonly used
DCC method utilizes vector control theory (dq control) [13–16]. Coordination transformation is needed
in dq control to change the ac signals into dc signals [17]. The grid voltage phase angle is essential in the
coordinate transformation; therefore, a phase-locked loop (PLL) is employed to synchronize the output
voltage with the grid voltage vector [18]. To accurately obtain the information on the grid voltage
including the amplitude and phase angle, some advanced PLLs have been proposed, such as hybrid
filtering technique-based PLL [19], grid sequence separator PLL [20], frequency-fixed SOGI-based
PLL [21], and repetitive learning-based PLL [22]. However, the computational complexity of coordinate
transformation and PLL increases the calculation burden of the embedded processor like the digital
signal processor (DSP) [23]. Therefore, the development of a convenient control method without PLL
or coordination transformation is appealing. Recently proposed control methods of the CHB converter
are based on model-predictive control (MPC) [24,25]. However, three major problems arise in the
MPC scheme used for the CHB converter. First, the calculation burden persists in the MPC method
because the number of switching states increases exponentially as more H-bridges are added [26].
The second one is the MPC system sensitiveness problem like sensitive to the parameter [27]. The third
problem is that under unbalanced load conditions, the MPC strategy cannot provide a proper control
function [28].
It is exceedingly difficult to implement the dq control scheme in the single-phase CHB
converter system; imaginary orthogonal current and voltage signals must be created for coordinate
transformation (αβ to dq) because only one physical axis is accessible [29]. In dq control, the imaginary
orthogonal current signal is essential in acquiring the dc current signals id and iq for the inner
current loop [30]. Thus, an imaginary current construction module is required to produce the
imaginary orthogonal current signal [31]. Although the performance of conventional imaginary
current construction under the steady state is mostly acceptable, the time delay tends to slow down
the system dynamic response and result in further distortion [32,33].
The control scheme performance of the CHB converter in the single-phase system depends on
two key factors: sinusoidal grid current waveform with unity power factor and balanced dc-link
voltages [34,35]. Therefore, the CHB multilevel converters need a control method to balance the
dc-link voltages, especially when the dc-side loads are unbalanced. In [36,37], the dc-link voltages
were controlled using individual capacitor voltage controllers. In [38], the presented voltage balance
control method uses a weighting factor to adjust the dc-link voltages. In [39], two voltage-balancing
techniques were presented, allowing for much more efficient regulation of dc-link voltages. However,
these voltage balanced control methods are all based on ac voltage reference duty cycle regulation;
a power-based dc-link voltage balance controller has not been analyzed in detail.
In the conventional dq control strategy, the current calculation is complicated and additional
time delay is required. For optimization purposes, a power control method without coordinate
transformation, PLL or conventional imaginary current construction is introduced and applied to
control the single-phase CHB multilevel converter system. Moreover, a power-based dc-link voltage
balance control scheme is presented to make the proposed power control strategy available under
unbalanced load conditions. This power and voltage control method can achieve a sinusoidal grid
current waveform and balanced dc-link voltages. Several experimental tests were conducted to
compare dynamic responses of the presented control scheme with those of the classical dq control
method. The proposed voltage balance controller is verified as well.
The remainder of this paper is organized as follows: in Section 2, principles of the proposed
control scheme and dc-link voltage balance controller are discussed, and the stability of the closed-loop
system with the dc-link voltage balance controller is evaluated. Section 3 presents the simulation
results. Experimental results are addressed in Section 4. The proposed control method is discussed in
Section 5. Finally, relevant conclusions are drawn in Section 6.
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2. Control Method Principles
2. Control
Method
2. Control
MethodPrinciples
Principles
2.1. Model of the Cascaded H-Bridge Multilevel Converter
2.1.2.1.
Model
of of
thetheCascaded
Model
CascadedH-Bridge
H-BridgeMultilevel
Multilevel Converter
Converter
Figure 1 presents the topology of a two-cell CHB system in which us is the grid voltage, isa is the
Figure
topology
ofLaatwo-cell
two-cell
CHBsystem
system
in
which
the line
grid
voltage,
isa is
s isand
Figure
the
topology
which
us isuthe
grid
voltage,
isa is the
grid current,
u1c 1presents
ispresents
the acthe
side
voltage,of
and
RL CHB
denote
the in
filter
inductor
resistance,
the
grid
current,
is
the
ac
side
voltage,
L
and
denote
the
filter
inductor
and
line
resistance,
grid
current,
u
c uis
the
ac
side
voltage,
L
and
R
LRdenote
the
filter
inductor
and
line
resistance,
c
L
respectively,. udc1 and udc2 represent the dc-link voltages of the first and second H-bridge, and udc_sum
respectively,.
udc1
and
dc-link voltages
voltagesof
ofthe
thefirst
firstand
andsecond
secondH-bridge,
H-bridge,and
anduudc_sum
respectively,.
uvoltage
dc1
anduu
dc2 represent
represent the dc-link
dc2
is the
total dc-link
(u
dc1 + udc2). R1 and R2 are the resistive loads connected to the dc side dc_sum
of
is the
total
dc-link
voltage(u(u
dc1++uudc2
dc2).
to to
thethe
dcdc
side
of of
is H-bridge.
the
total
dc-link
voltage
). R
R11 and
andRR2 2are
arethe
theresistive
resistiveloads
loadsconnected
connected
side
dc1
each
each
H-bridge.
each
H-bridge.
Figure
1.1. Two-cell
single-phase
CHBconverter.
converter.
Figure
Two-cell
single-phase
CHB
Figure
1. Two-cell
single-phase
CHB
converter.
The
mathematical model
ofofthe
CHB converter
is as follows:
The mathematical
model
the CHB
converter is as follows:
The mathematical
model
of the
CHB
( converter is as follows:
 Ldidisadtsa = us − uc − R L isa
 di
Lsa
u c − R L isa
(1)
L
= u s= −u su=c− −u
R isa u
  udt
(1)
dc_sum
dc1L +
dc2
dt
(1)
 
dc _ sum = u dc1 + u dc 2
 u dc_usum
= u dc1 + u dc 2
 stability,
To simplify analysis of system
according to Equation (1), a small-signal model of the
To simplify analysis of system stability, according to Equation (1), a small-signal model of the
stationary
reference
frame
(αβ frame)
was built,
as illustrated
in Figure
Here, usα equals
, and
To simplify
analysis
of system
stability,
according
to Equation
(1), a2.small-signal
modelusof
theusβ
stationary reference frame (αβ frame)
was~built, as illustrated in Figure 2. Here, usα equals us, and usβ
~ and
is the orthogonal
signal(αβ
of u
u
represent
the
small-signal
ac
variation
of
u
and
s ; u~ sαwas
sα
sβ
stationary
reference frame
frame)
built,
as
illustrated
in
Figure
2.
Here,
u
sα
equals
u
s
,
and
usβusβ ;
orthogonal
signal of us; u sα and u~sβ represent the small-signal ac variation of usα and usβ; u~dc1
~ is the
~
~
~
~
u
and
u
denote
the
small-signal
ac
variation
of
u
and
u
;
i
equals
i
,
and
i
is
sα
is thedc1
orthogonal
acdc2
variation
of usαsaand usβsβ
; u dc1the
dc2signal of us; u sα and u sβ represent the small-signal
and
u~dc2 denote
the small-signal
ac variation of udc1 and udc1
dc2; isα equals isa, and isβ is the orthogonal
~
~
~dc2 denote
signal
of isa~; i sα and
small-signal
ac variation
of
isβ ; Isα and Isβ
andorthogonal
usignal
small-signal
aci variation
of uthe
dc1 and
udc2; isα equals
isa, iand
isβisα
is and
the orthogonal
sβ represent
of isa; the
i~sα and
i sβ represent
the small-signal
ac variation
of isα and
sβ; Isα and Isβ stand for the
~
~
stand
for
the
quiescent
operating
point
of
i
and
i
;
D
,
D
,
D
,
and
D
are
the
duty
cycles
of the
sα
α1
α2
signalquiescent
of isa; i sαoperating
and i sβ represent
sα and isβ;β2
Isα and Isβ stand
for the
sβvariation of iβ1
point of isαthe
andsmall-signal
isβ; Dα1, Dα2, Dac
β1, and Dβ2 are the duty cycles of the first and second
~ , d~ , d~ , and d~
first
and
second
H-bridge;
and
d
represent
the
small-signal
ac
variation
of
Dα2 ,
quiescent
operating
of
sβ
α1α2
, Dα2, β1
Dβ1the
, and
Dβ2β2 are the
cycles
the
and
second
~α1, d~α2
H-bridge;
and dpoint
, di~sαβ1,and
andiα1
d~; β2Drepresent
small-signal
acduty
variation
ofof
Dα2
, Dfirst
β1, and
Dβ2
.
Dβ1 , and
Dβ2
H-bridge;
and
d~.α1, d~α2, d~β1, and d~β2 represent the small-signal ac variation of Dα2, Dβ1, and Dβ2.
u~sα
u ~ sβ
u~sα
i ~ sα
i ~ sα
d ~ α 1 I sα + Dα 1i ~ sα +
+ Dα 1i ~ sα~ +
d β 1 I s β + D β 1i s β
d ~ β 1 I s β + D β 1i ~ s β
d
~
α 1~I sα
C1
C1
u ~ dc1
u ~ dc1
udc1d ~α 1 + Dα 1u ~ dc1 + udc 2 d ~α 2 + Dα 2u ~ dc 2
udc1d ~α 1 + Dα 1u ~ dc1 + udc 2 d ~α 2 + Dα 2u ~ dc 2
udc1d ~ β 1 + Dβ 1u ~ dc1 + udc 2 d ~ β 2 + Dβ 2u ~ dc 2
u ~ sβ
i ~ sβ
i ~ sβ
udc1d ~ β 1 + Dβ 1u ~ dc1 + udc 2 d ~ β 2 + Dβ 2u ~ dc 2
d ~ α 2 I sα + Dα 2 i ~ sα +
d ~ αd 2~Iβs2αI s+β D+αD2 βi ~2siα~ s+β
C2
C2
u ~ dc 2
u ~ dc 2
~
d ~single-phase
Figure 2. Small-signal model of two-cell
in αβ frame coordination.
sβ
β 2 I s β + DCHB
β 2 i converter
Figure
2. Small-signal
model
of two-cell
single-phase
CHB
converter
in αβ
coordination.
Figure
2. Small-signal
model
of two-cell
single-phase
CHB
converter
in frame
αβ frame
coordination.
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2.2. Principle of the Proposed Power Control Method
The main function of CHB multilevel converter is to obtain active power and reactive power
2.2. Principle of the Proposed Power Control Method
from the grid to satisfy load needs. For the CHB converter, the essence of controlling the grid
main as
function
of CHB
multilevel
converter
is toinput
obtainand
active
power
and reactive
powerand
from
currentThe
as well
the dc-link
voltage
is control
of the
output
power.
By rapidly
the grid to
satisfy load
thereactive
CHB converter,
theconverter
essence ofcan
controlling
griddynamic
current as
well
effectively
controlling
theneeds.
activeFor
and
power, the
achieve the
strong
and
as the
dc-link voltage is control of the input and output power. By rapidly and effectively controlling
static
characteristics.
theInactive
and reactive CHB
power,
the converter
canthe
achieve
strong
dynamic
staticpower
characteristics.
the three-phase
converter
system,
active
power
p and and
reactive
q can be
In the
described
as: three-phase CHB converter system, the active power p and reactive power q can be
described as:
"
# "
#"
#
p p   usαusα usβusβisα  isα
(2) (2)
= * ∗ * ∗  
q =
q  u suα sαu suβ sβisβ  isβ
where
=. −usα .
where
u*sαu*=sαu=sβ,uusβ*sβ, u
=*−u
sβ sα
Only
one
phase
physical
variable
is available
in the
single-phase
converter
system;
Only
one
phase
physical
variable
is available
in the
single-phase
CHBCHB
converter
system;
a
a
second-order
generalized
integrator
(SOGI)
block
is
needed
to
introduce
the
imaginary
signal.
second-order generalized integrator (SOGI) block is needed to introduce the imaginary signal. The
The virtual
αβ stationary
reference
is depicted
in Figure
3, the
α-axis
coincides
with
a-axis,
virtual
αβ stationary
reference
frameframe
is depicted
in Figure
3, the
α-axis
coincides
with
thethe
a-axis,
and
β-axis
is orthogonal
α-axis.
and
thethe
β-axis
is orthogonal
to to
thethe
α-axis.
β
b
(α )
0
c
Figure
3. Schematic
diagram
virtual
coordinate
axis.
Figure
3. Schematic
diagram
of of
virtual
αβαβ
coordinate
axis.
single-phase
CHB
converter
system,
p and
q can
described
follows:
In In
thethe
single-phase
CHB
converter
system,
p and
q can
bebe
described
asas
follows:
#"
#
"
#
"
p p  11 usαusα usβusβisα  isα
=
=
q q  33u*suα∗ sαu*suβ ∗sβisβ  isβ
 



(3) (3)
* and
* are
defined
theactive
activepower
powerand
andreactive
reactivepower
powerreference,
reference,respectively;
respectively;i*isα* sαand
andi*sβi* sβ
p* pand
q* qare
defined
asasthe
represent
current
reference.
represent
thethe
current
reference.
Equations(4)
(4)and
and (5) are
as as
follows
according
to Equation
(3), and(3),
theand
coefficient
calculation
Equations
areshown
shown
follows
according
to Equation
the coefficient
of the proposed
power control
is control
shown in
Equation
(6):
calculation
of the proposed
power
is shown
in Equation
(6):
"
#"
#
"
* #
 u *s u
 *
∗
33
β sβ −u s−
β usβp 
p∗
i∗sαi sα  =
 * =
 * ∗
 *
∗
* uu*∗ssβ
−uu*s∗αsα*∗uu
i∗sβi s β  uusα
q  q
sα ∗
β −
s βsβ −u−
sαu sαu sα usα
(4)
(4)
 #
3u*sβ 3u∗ sβ
−3−u3u
∗ *
sβ sβ
* p∗ +
sα
usα*∗u∗ sβ −u* ∗ sα ∗usβ q q 


* usα ∗u*∗ sβ −∗u∗ sα ∗pusβ+
*
=
(5)
* usαsβ
* u sβ −3uusα sα * usβq∗ 
i sα  i∗ sβ usα * u sβ − u s−α 3u
∗us+
α
p
∗ −u∗ ∗u
∗ −u∗ ∗u
u
∗
u
u
∗
u
=
sα
sα
sα
sα
sβ
sβ
sβ
sβ
*  

u*sα
3usα
−3
(5)
i sβ  
*
*
∗
3u
p + sβ
q
* =
*
*
k
 usα * u*sβ 

∗
∗
1
− u sα * uusβsα ∗u sβ −uusαsα*∗uusβsβ − u sα * usβ 

(6)
−3usβ
 k2 =
usα*∗u∗ sβ −u∗ sα ∗usβ

3u sβ
*
*
*
*
 k1 =
*result *of usα * u sβ + u sα * u sβ is constant; p is controlled
If the grid voltage is sinusoidal,
then
the
usα * u sβ − u sα * usβ

*
by the outer power loop; q is constant
because it is given directly; therefore the frequency and phase of

−with
3usβ the instantaneous grid voltage, and the real-time
(6)
the current references isα and isβ are
consistent
k2 =
*
*

*
−
u
*
u
u
*
u
tracking can be achieved. Notably, only i sαsα is used
assthe
current
reference, because the CHB multilevel
sβ
α
sβ
"
i∗

converter is used on a single-phase system.

Energies 2018, 11, x
5 of 19
If the grid voltage is sinusoidal, then the result of usα * u*sβ + u*sα * u*sβ is constant; p* is controlled
by the outer power loop; q* is constant because it is given directly; therefore the frequency and phase
of the current references isα and isβ are consistent with the instantaneous grid voltage, and the
Energies 2018, 11, 2435
5 of 18
real-time tracking can be achieved. Notably, only i*sα is used as the current reference, because the
CHB multilevel converter is used on a single-phase system.
2.3. Presentation of Proposed Dc-Link Balance Controller
2.3. Presentation of Proposed Dc-Link Balance Controller
Figure 4 presents the conventional dc-link voltage balance controller. In this approach, the duty
4 presents
the
conventional
dc-link
voltage
balance
controller.
In this
the duty
cyclesFigure
of each
ac voltage
reference
u* a1 and
u* a2 are
modified
separately
to keep
theapproach,
voltages balanced,
*
*a2 are modified separately to keep the voltages balanced,
cycles
of
each
ac
voltage
reference
u
a1
and
u
and the scheme is suitable for the dq method. A power-based dc-link voltage balance controller
and the scheme
is suitable
for theduty
dq method.
A power-based
balance
controller
adjusting
the ac current
reference
cycle is introduced
in thisdc-link
paper voltage
to regulate
the individual
adjusting dc-link
the ac current
H-bridge
voltage.reference duty cycle is introduced in this paper to regulate the individual
H-bridge dc-link voltage.
Δdu1
Δdu 2
Figure
Conventional voltage
Figure 4.
4. Conventional
voltage balance
balance controller
controller [37].
[37].
If
each
H-bridge
is unbalanced
(mainly
via load
then the
power
If the
thedc-link
dc-linkvoltage
voltageofof
each
H-bridge
is unbalanced
(mainly
via imbalance),
load imbalance),
then
the
of
these
H-bridges
becomes
uneven.
To
keep
the
dc-link
voltage
balanced,
the
uneven
power
should
power of these H-bridges becomes uneven. To keep the dc-link voltage balanced, the uneven power
be
extracted
from thefrom
grid.the
∆dp1
and∆d
∆d
p2 are used as the compensation values to eliminate uneven
should
be extracted
grid.
p1 and ∆dp2 are used as the compensation values to eliminate
power.
∆d
p1 and∆d
p2 are calculated by the voltage balance controller:
uneven∆d
power.
p1 and ∆dp2 are calculated by the voltage balance controller:
∆d p1 = (K p + KKsii )(ure f − udc1 ) · udc1
(7)
 Δd p1 = ( K p + Ksi )(uref − udc1 ) ⋅ udc1
∆d = (K p + s )(ure f − udc2 ) · udc2
(7)
 p2
 Δd = ( K + K i )(u − u ) ⋅ u
pand integral
ref
dc 2
dc 2 of the proportional-integral (PI)
where Kp and Ki represent the proportional
coefficient
 p 2
s
controller, respectively, and uref is the voltage reference of every H-bridge cell.
and Ki represent
proportional
integral
of themodifies
proportional-integral
where
Kppresented
The
voltage the
balance
controllerand
is shown
in coefficient
Figure 5, which
the duty cycles(PI)
of
controller,
respectively,
and
u
ref is the
voltage
reference
of
every
H-bridge
cell.
*
*
each ac current reference i sa1 and i sa2 individually to reduce the dc voltage imbalance. The current
The presented
voltage can
balance
controlleraccording
is shown to
inEquations
Figure 5, which
modifies the duty cycles
reference
for each H-bridge
be calculated
(8)–(10):
*
*
of each ac current reference i sa1 and i sa2 individually to reduce the dc voltage imbalance. The current
(
reference for each H-bridge can be calculated
according
(8)–(10):
i∗ sα1 =
∆di∗ sa1 +toi∗Equations
sα
(8)
∗
∗
= ∆di∗ sa2 *+ i sα
 ii* sαsα2
1 = Δ d i* sa1 + i sα
(8)
*
*
(
 i sα 2 = Δ d i* sa 2 + i sα ∗
∗
∗
i sα1 = ∆d p1 (k1 + k2 ) + p k1 + q k2
(9)
∗
= ∆d p2 (k1 + k2 ) +* p∗ k1 *+ q∗ k2
 ii* sαsα2
1 = Δ d p1 ( k1 + k 2 ) + p k1 + q k 2
(9)
( *
k 2 ∗) )++p *kk1(+
q*k
=Δ
∗
ii∗ sα1
2 ( k1 +
sα 2 =
k1d(p∆d
2 ∆d p1 2+ q )
p1 + p
(10)
i∗*sα2 = k1 (∆d p2 +* p∗ ) + k2 (∆d p2* + q∗ )
(
Energies 2018, 11, x
i sα 1 = k1 ( Δd p1 + p ) + k 2 ( Δd p1 + q )
*
*
*
i sα 2 = k1 ( Δd p 2 + p ) + k 2 ( Δd p 2 + q )
Δd p1
Δd p 2
6 of 19
(10)
Δdi*sa1 = Δd p1 (k1 + k2 )
Δdi*sa 2 = Δd p 2 (k1 + k2 )
Figure 5.
5. Proposed
Proposed voltage
voltage balance
balance controller.
controller.
Figure
2.4. Proposed Power Control of the Cascaded H-Bridge Multilevel Converter
The overall control topology of the proposed control method is depicted in Figure 6. The main
idea of the proposed control is to obtain command signals in the orthogonal αβ frame; as such, the
p1
i sa1
Δd p 2
1
2
Δdi*sa 2 = Δd p 2 (k1 + k2 )
Energies 2018, 11, 2435
6 of 18
Figure 5. Proposed voltage balance controller.
2.4. Proposed Power Control of the Cascaded H-Bridge Multilevel Converter
2.4. Proposed Power Control of the Cascaded H-Bridge Multilevel Converter
The overall
control
topology
of the
control
method
inFigure
Figure6.6.The
The
main idea
The overall
control
topology
of proposed
the proposed
control
methodisisdepicted
depicted in
main
of the proposed
is to
obtain
command
signalssignals
in theinorthogonal
αβ αβ
frame;
asassuch,
idea of thecontrol
proposed
control
is to
obtain command
the orthogonal
frame;
such,the
the dc-link
can be balanced.
voltagesdc-link
can bevoltages
balanced.
udc1 udc 2
q*
−
is a
u*a1
u*a2
i*sa1
i*sa2
p*
2 * uref +
udc1 + udc2
udc 2
is a
usα
udc1
us β
isa
us
us
Figure
6. Proposed
power
control
CHB
converter.
Figure
6. Proposed
powerand
and voltage
voltage control
of of
CHB
converter.
The control
system
is formed
as as
a double
control
structure
the current
inner current
The control
system
is formed
a doubleclosed-loop
closed-loop control
structure
usingusing
the inner
loop
the outer
power
loop.
loop and
theand
outer
power
loop.
The current
inner current
is implementedininthe
the orthogonal
orthogonal αβαβ
frame.
Compared
with classical
The inner
looploop
is implemented
frame.
Compared
with classical
single-phase dq schemes, the current calculation of the proposed control method is simpler because
single-phase dq schemes, the current calculation of the proposed control method is simpler because no
no coordinate transformation, PLL, or conventional imaginary current construction is needed.
coordinate
transformation,
PLL, or conventional
current
construction
is needed.
However,
However,
the current references
i*sa1 and i*sa2 areimaginary
ac variables.
To track
the current references
with
*
*
the current
areand
ac variables.
To tracking
track the
currentwhen
references
zero error in
zero references
error in thei stationary
frame
achieve high
accuracy
the gridwith
frequency
sa1 and i sa2
fluctuates,
rather
relying
conventional
PI when
controllers
or afrequency
repetitive fluctuates,
controller [40],
the stationary
frame
and than
achieve
highon
tracking
accuracy
the grid
rather than
(PR) controllers
are utilized
in the current
relying proportional-plus-resonant
on conventional PI controllers
or a repetitive
controller
[40],loop.
proportional-plus-resonant (PR)
As for the outer power loop, a PI controller is used to adjust the total dc-link voltage udc_sum (udc1
controllers are
utilized in the current loop.
+ udc2). The active power p* is generated by multiplying the output of the PI controller by the total
Asdc-link
for thevoltage
outerudc_sum
power
loop, a PI controller is used to adjust the total dc-link voltage udc_sum
. Reactive power reference q* is given directly.
(udc1 + udc2 ).The
The
active
power
p* is generated
by and
multiplying
the output
the PI in
controller
detailed control topology
of the power
voltage control
module of
is shown
Figure 7. by the
*
*
*
total dc-link
voltage
udc_sum
power and
reference
q second
is given
directly.
Current
reference
i sa1 of. Reactive
the first H-bridge
i sa2 of the
H-bridge
are acquired through the
voltage
balance
controlofblock;
these current
references
are controlled
Thedc-link
detailed
control
topology
the power
and voltage
control
module isindependently.
shown in Figure 7.
*
Deviation
values
between
the
grid
current
i
sa* and the current references are input into the PR
Current reference i sa1 of the first H-bridge and i sa2 of the second H-bridge are acquired through the
regulators separately, and the modulation voltage signals u*a1 and u*a2 are generated for the first and
dc-link voltage balance control block; these current references are controlled independently. Deviation
second H-bridge. Carrier phase-shifted PWM (CPS-PWM) technology is adopted to generate
values between
grid achieving
current isamulti-level
and the current
references
are input
the PR
regulators
five-levelthe
voltage,
modulation.
Furthermore,
if theinto
reactive
power
referenceseparately,
q*
*
*
and theismodulation
voltage
u a1 can
andbeuachieved.
a2 are generated for the first and second H-bridge.
set to zero, then
a unitysignals
power factor
Carrier phase-shifted PWM (CPS-PWM) technology is adopted to generate five-level voltage, achieving
multi-level modulation. Furthermore, if the reactive power reference q* is set to zero, then a unity
Energies
2018,
11,be
x achieved.
7 of 19
power
factor
can
udc1 udc 2
us
usα
isα
isβ
us β
Figure
7. 7.Power
controlmodule.
module.
Figure
Powerand
and voltage
voltage control
2.5. Stability Analysis of the Power and Voltage Control Scheme
Assume that the parameters of the H-bridges are identical, such that the dc-link voltage udc1 =
udc2 = udc. The double-loop control diagram presented in Figure 6 can thus be transformed as
illustrated in Figure 8. In Figure 8, GV is the voltage gain of CHB, GPIV is the voltage PI regulator, K
Energies 2018, 11, 2435
7 of 18
Figure 7. Power and voltage control module.
2.5. Stability Analysis of the Power and Voltage Control Scheme
Assume that
that the
theparameters
parametersofofthethe
H-bridges
identical,
the dc-link
voltage
H-bridges
areare
identical,
suchsuch
that that
the dc-link
voltage
udc1 =
udc1
= udc2
= udc double-loop
. The double-loop
control
diagram
presented
in Figure
6 canthus
thusbe
be transformed
transformed as
dc2 =
dc. The
control
diagram
presented
in Figure
6 can
illustrated in Figure 8. In
In Figure
Figure 8,8,GGVVisisthe
thevoltage
voltagegain
gainofofCHB,
CHB,GG
voltage
regulator,
PIV
is is
thethe
voltage
PI PI
regulator,
K
PIV
K
conversion
coefficient
between
p* and
GqPR
the current
PR regulator,
GTPWM
is the
is is
thethe
conversion
coefficient
between
p* and
i*sa, Gi*qPR
the is
current
PR regulator,
GTPWM is
the transfer
sa , is
transfer
of the
PWM modulator,
is the transfer
of the to
voltage
tocurrent
output current
functionfunction
of the PWM
modulator,
GIV is theGIV
transfer
functionfunction
of the voltage
output
i*sa, and
*
iGsa
and
transfer function
of the to
current
tovoltage
output u
voltage
udc . G
GVIIVcan
andbe
GVI
can be deduced
VI, is
theGtransfer
of the current
output
dc. GIV and
deduced
from the
VI is the function
from
the small-signal
modelinshown
small-signal
model shown
Figurein
2. Figure 2.
uref + Δudc
−
GPIV
udc
p*
K
∗
isa
+
−
GqPR
GTPWM
+
us
isa
u dc
−
GIV
isa
1
K
p
1
udc
GVI
u dc
Figure 8. Basic double-loop controller structure diagram of the proposed power control.
control.
The closed-loop transfer function can be expressed
expressed as
as follows:
follows:
GGVV ==
GPIV
GqPR
GTPW
GIV
GVVII
G
PIV G
qPRG
TPWM
IV G
MG
11+
G qPRG
+G
GPIV
GTPW
MG IV
PIV GqPR
TPWM
IV GV
VII
(11)
(11)
One bridge of the CHB converter can be
be simplified
simplified according
according to
to Figure
Figure 99 per
per Thevenin
Thevenin law.
law.
However,
the
dc-link
voltage
unbalance
problem
in
CHB
remains
under
the
unbalanced
load
condition;
However, the dc-link voltage unbalance problem in CHB remains under the unbalanced load
therefore
voltagethe
balance
control
module
should
be added.
Figure
10 Figure
shows 10
theshows
Thevenin
condition;the
therefore
voltage
balance
control
module
should be
added.
the
equivalent
circuit withcircuit
the dc-link
balance
module,
wheremodule,
Z1 is the where
load impedance,
Thevenin equivalent
with voltage
the dc-link
voltage
balance
Z1 is the Zload
io is
the
impedance
between
the input
and output
of CHB,
is theofgain
of the
balance
control
impedance,
Zio is
the impedance
between
the input
andM
output
CHB,
M isvoltage
the gain
of the voltage
module,
G1 is themodule,
conversion
of power
to voltage,
iout to
is the
outputand
current.
case
balance control
G1 iscoefficient
the conversion
coefficient
of and
power
voltage,
iout is In
thethis
output
G
* ucase
).
current.
InPIV
this
G
1
=
1/(G
PIV
*
u
dc
).
1 = 1/(G
dc
Taking
Taking the
the first
first H-bridge
H-bridge as
as an
an example:
example:
uu dc1
G1 [ pp∗* ++ ((uurereff −
) M]]GGVV == ZZioio dc1
++uudc1
− udc1
dc 1 )
dc 1
ZZ1 1
(12)
(12)
GVGG
GG
M1 M
V1G
11
VG
VG
pp∗*+
udc1 =
udc1 =
+
uref ure f
Zio /Z
+
1
+
G
G
M
Z
/Z
+
1
+V G1VMG1 M
Z io 1/ Z1 + 1 + GVV G11 M
Z ioio / Z11+ 1 + G
(13)
(13)
Because Z1 >> Zio , GG1 M represents the gain in the basic double-loop controller with the dc-link
voltage balance module from Equation (13); the Bode plot is shown in Figure 11. The amplitude margin
is 12.7 dB, the cut-off frequency is 272 Hz, the phase margin is 105◦ , and the cross-over frequency is
78 Hz. All roots of (Zio /Z1 + 1 + GG1 M) are on the left half-complex plane, ensuring stability of the
system2018,
with11,the
Energies
x voltage balance control module.
8 of 19
Zio
uref
GV uref
iout
Z1
Thevenin equivalent circuit of the basic double-loop.
Figure 9. Thevenin
Z1
GV uref
Energies 2018, 11, 2435
Figure 9. Thevenin equivalent circuit of the basic double-loop.
8 of 18
Figure 10. Thevenin equivalent circuit with the voltage balance module controller.
Because Z1 >> Zio, GG1M represents the gain in the basic double-loop controller with the dc-link
voltage balance module from Equation (13); the Bode plot is shown in Figure 11. The amplitude
margin is 12.7 dB, the cut-off frequency is 272 Hz, the phase margin is 105°, and the cross-over
frequency is 78 Hz. All roots of (Zio/Z1 + 1 + GG1M) are on the left half-complex plane, ensuring
stability of the system with the voltage balance control module.
Figure10.
10.Thevenin
Theveninequivalent
equivalentcircuit
circuitwith
withthe
thevoltage
voltagebalance
balancemodule
modulecontroller.
controller.
Figure
Because Z1 >> Zio, GG1M represents the gain in the basic double-loop controller with the dc-link
voltage balance module from Equation (13); the Bode plot is shown in Figure 11. The amplitude
margin is 12.7 dB, the cut-off frequency is 272 Hz, the phase margin is 105°, and the cross-over
frequency is 78 Hz. All roots of (Zio/Z1 + 1 + GG1M) are on the left half-complex plane, ensuring
stability of the system with the voltage balance control module.
Figure 11.
11. Bode
Bode plot
plot of
of the
the basic
basic double-loop
double-loop controller
controller with
Figure
with the
the dc-link
dc-link voltage
voltage balance
balance module.
module.
3. Simulation Results
3. Simulation Results
The CHB converter system shown in Figure 1 was modelled in the MATLAB/Simulink R2015a
The CHB converter system shown in Figure 1 was modelled in the MATLAB/Simulink R2015a
(MATLAB/Simulink R2015a, MathWorks, Natick, MA, USA) software environment to verify the power
(MATLAB/Simulink R2015a, MathWorks, Natick, MA, USA) software environment to verify the
and voltage control scheme. The main system parameters used for simulation are shown in Table 1.
Tabledouble-loop
1. Parameters
Used For
Simulation.
Figure 11. Bode plot of the basic
controller
with
the dc-link voltage balance module.
Parameter
Symbol
Simulation Value
Grid voltage rms value
us
220 V
dc-link total voltage
dc-link capacitance
dc-link load resistance
Switching frequency
Inner current loop control parameters
Outer power loop control parameters
Udc
C1 , C2
R1 , R2
fsw
P, R, wc
P, I
400 V
4700 µF
10 Ω, 15 Ω
10 kHz
0.5, 100, 6.28
0.1, 8
3. Simulation Results
The CHB converterGrid
system
shown in Figure 1 was modelled
in the MATLAB/Simulink
R2015a
frequency
fg
50 Hz
Input inductance
L
3.0 mH
(MATLAB/Simulink R2015a,
MathWorks, Natick, MA, USA)
software environment
to verify the
Input
Inputinductance
inductance
dc-link
dc-linktotal
totalvoltage
voltage
dc-link
dc-linkcapacitance
capacitance
dc-link
dc-linkload
loadresistance
resistance
Switching
Switchingfrequency
frequency
Inner
Innercurrent
currentloop
loopcontrol
controlparameters
parameters
Energies 2018, 11, 2435
Outer
Outerpower
powerloop
loopcontrol
controlparameters
parameters
LL
U
Udcdc
CC11,,CC22
RR11,,RR22
ffswsw
P,
P,R,
R,wwcc
P,I
P,I
3.0
3.0mH
mH
400
400VV
4700
4700μF
μF
10
10Ω,
Ω,15
15Ω
Ω
10
10kHz
kHz
0.5,
0.5,100,
100,6.28
6.28
0.1,
0.1,88
9 of 18
3.1.
Proposed
Power
Control
Scheme
Simulation
3.1.
3.1.Proposed
ProposedPower
PowerControl
ControlScheme
SchemeSimulation
Simulation
Figures
with
unbalanced
loads,
where
R1 R
=
Ω
R2 R
=R2215
Ω.
Figures
12–14
show
the
simulation
results
with
unbalanced
loads,
where
== 10
Ω
== 15
Figures12–14
12–14show
showthe
thesimulation
simulationresults
results
with
unbalanced
loads,
where
R1110
10and
Ω and
and
15
Figure
12a
displays
the
grid
voltage
and
grid
current
waveform
in
the
steady
state,
revealing
that
the
Ω.
Ω. Figure
Figure 12a
12a displays
displays the
the grid
grid voltage
voltage and
and grid
grid current
current waveform
waveform in
in the
the steady
steady state,
state, revealing
revealing
unity
power
was
achieved.
that
unity
power
factor
was
thatthe
the
unityfactor
power
factor
wasachieved.
achieved.
(a)
(a)
(b)
(b)
Figure
Figure12.
12.Simulation
Simulationwaveforms
waveformsof
ofCHB
CHBconverter
converterin
insteady
steadystate:
state:(a)
(a)Grid
state:
(a)
Grid voltage
voltage and
and grid
grid current;
current;
(b)
waveform.
(b)Five-level
Five-levelvoltage
voltagestaircase
staircasewaveform.
waveform.
(a)
(a)
(b)
(b)
Figure
from
00var
1500
(a)
the
(b)
Figure13.
13.q*
q*changed
changed
fromfrom
var0to
tovar
1500tovar:
var:
(a)Dynamic
Dynamic
response
ofresponse
the grid
grid current;
current;
(b) Dynamic
Dynamic
Figure
q*
changed
1500
var:
(a) response
Dynamicof
of
the grid
current;
response
of
the
reactive
power.
response
of
the
reactive
power.
(b) Dynamic response of the reactive power.
(a)
(a)
(b)
(b)
Figure 14. q* changed from 0 var to −1500 var: (a) Dynamic response of the grid current;
(b) Dynamic response of the reactive power.
Figure 12b shows the ac side five-level staircase voltage. Dynamic responses of the proposed
method under sudden reactive power change conditions are shown in Figures 13 and 14. In these,
the active power reference p* is governed by the outer power loop, and the reactive power reference q*
is changed from 0 to −1500 var and 0 to 1500 var at 0.34 s.
3.2. Power-Based Voltage Balance Control Simulation
In this simulation, the initial loads of two H-bridges were 15 Ω resistors. At 1.0 s, the resistor of
the first H-bridge declined to 10 Ω. Two distinct cases were considered. In Figure 15a, the voltage
balance control module was not utilized, and the dc-link voltages became different after the load
change. The second H-bridge, whose resistor was unchanged, demonstrated higher dc-link voltage
Figure
12breference
shows the
side five-level
staircase
voltage.loop,
Dynamic
responses
the proposed
the active
power
p ac
is governed
by the
outer power
and the
reactiveofpower
reference
under
reactive
power
change
conditions
are shown in Figures 13 and 14. In these,
q* ismethod
changed
fromsudden
0 to −1500
var and
0 to
1500 var
at 0.34 s.
the active power reference p* is governed by the outer power loop, and the reactive power reference
* is changed from 0 to −1500 var and 0 to 1500 var at 0.34 s.
3.2.qPower-Based
Voltage Balance Control Simulation
InPower-Based
this simulation,
the
initialControl
loads of
two H-bridges were 15 Ω resistors. At 1.0 s, the resistor of
3.2.
Voltage
Balance
Simulation
Energies
2435
10 of 18
the2018,
first11,H-bridge
declined to 10 Ω. Two distinct cases were considered. In Figure 15a, the voltage
In this simulation, the initial loads of two H-bridges were 15 Ω resistors. At 1.0 s, the resistor of
balance control module was not utilized, and the dc-link voltages became different after the load
the first H-bridge declined to 10 Ω. Two distinct cases were considered. In Figure 15a, the voltage
change. The second H-bridge, whose resistor was unchanged, demonstrated higher dc-link voltage
balance
control module
was not
dc-linkvoltages
voltages became
different
afterbalance
the load control
than than
the
first
H-bridge.
Figure
15butilized,
showsand
thethe
dc-link
with the
voltage
the first H-bridge. Figure 15b shows the dc-link voltages with the voltage balance control
change.
The
second
H-bridge,
whosebalance
resistor was
unchanged,
demonstrated
higher
dc-linkreturned
voltage
method.
Using
the
proposed
voltage
control
module,
the
dc-link
voltages
method.
Using the proposed voltage balance control module, the dc-link voltages returned to theto the
than the first H-bridge. Figure 15b shows the dc-link voltages with the voltage balance control
initialinitial
value
(200(200
V).
value
method.
UsingV).
the proposed voltage balance control module, the dc-link voltages returned to the
initial value (200 V).
(a)
(b)
(a)
(b)
Figure
15. Simulated
responseofofdc-link
dc-link voltages
voltages when
(a) (a)
Without
voltage
balance
Figure
15. Simulated
response
whenload
loadchanged:
changed:
Without
voltage
balance
Figure 15. Simulated response of dc-link voltages when load changed: (a) Without voltage balance
control;
(b)
With
voltage
balance
control.
control;control;
(b) With
voltage
balance
control.
(b) With voltage balance control.
4. Experimental
Results
4. Experimental
Results
4. Experimental Results
4.1.4.1.
Experimental
Prototype
4.1. Experimental
Prototype
Experimental
Prototype
A single-phase
five-level
CHB
converter
experimental
platform
was
adopted
validate
A single-phase
five-level
CHB
converter
platform
was
adopted
to validate
A single-phase
five-level
CHB
converter experimental
experimental platform
was
adopted
totovalidate
thethe the
presented
power
and
voltage
control
scheme,
as
shown
in
Figure
16.
presented
and voltage
control
scheme,as
asshown
shown in
16.16.
presented
powerpower
and voltage
control
scheme,
inFigure
Figure
Figure
16.16.Platform
ofthe
theexperiments.
experiments.
Figure
Platform of
Figure 16. Platform of the experiments.
Two H-bridge converters with serially connected inputs formed the ac side of the experimental
setup. The dc output of each converter fed the loads. The converter was interfaced to the grid
through a coupling transformer and a voltage regulator to ensure safety during the experiments.
The secondary-side voltage of the regulator was set to 80 V (rms), while the dc-link voltage references
udc1 and udc2 were set to 50 V. The grid voltage, grid current, ac side voltage, and dc-link voltages were
measured using the outer high-performance hall sensors. A TMS320F28377D DSP processor board
was utilized to implement the control algorithm. Measured voltage and current signals were fed back
to the DSP processor board employing a built-in, 16-bit analog-digital conversion module. The power
factor and total harmonic distortion (THD) of the grid current were measured via a Fluke 435 power
quality analyzer.
4.2. Steady State
Figure 17 depicts the experimental waveforms of the grid voltage us (200 V/division), the grid
current isa (20 A/division), the dc-link voltage of the first H-bridge udc1 (20 V/division), and the ac
side voltage uc (100 V/division) for the proposed scheme in the steady state, where loads R1 and R2 in
Figure 1 are 10 Ω and 15 Ω, separately. When the reactive power reference q* was set to zero, the grid
conversion module. The power factor and total harmonic distortion (THD) of the grid current were
measured via a Fluke 435 power quality analyzer.
4.2. Steady State
Figure 17 depicts the experimental waveforms of the grid voltage us (200 V/division), the grid
11 of 18
current isa (20 A/division), the dc-link voltage of the first H-bridge udc1 (20 V/division), and the ac
side voltage uc (100 V/division) for the proposed scheme in the steady state, where loads R1 and R2
in Figure
are 10 with
Ω andthe
15 Ω,
separately.
reactive
power
reference
q* was setThe
to zero,
theof the
current
was in1 phase
grid
voltage, When
so thethe
unity
power
factor
was achieved.
THD
grid current was in phase with the grid voltage, so the unity power factor was achieved. The THD
grid current in the steady state was 4.3%, indicated in Figure 18. Moreover, this method was found
of the grid current in the steady state was 4.3%, indicated in Figure 18. Moreover, this method was
to compensate for the reactive power: CHB converters can generate or absorb reactive power to the
found to compensate for the reactive power: CHB converters can generate or absorb reactive power
power
whengrid
the reactive
is positive
or negative.
In Figure
19, the
gridgrid
current
to grid
the power
when thepower
reactivereference
power reference
is positive
or negative.
In Figure
19, the
was leading
the
grid
voltage;
thus,
the
CHB
converter
was
generating
reactive
power
to
the
system.
current was leading the grid voltage; thus, the CHB converter was generating reactive power to the
In Figure
20, In
theFigure
grid current
voltage,
CHB converter
was converter
absorbingwas
reactive
system.
20, thewas
gridlagging
currentthe
was
laggingand
thethe
voltage,
and the CHB
absorbing
power from the system.
power
from thereactive
system.
Energies 2018, 11, 2435
Energies 2018, 11, x
Energies 2018, 11, x
Figure
17.17.
Experimental
of CHB
CHBconverter
converter
steady
state.
Figure
Experimentalwaveforms
waveforms of
in in
steady
state.
Figure 18.THD
THD of grid
grid current
state.
Figure
currentin
insteady
steady
state.
Figure18.
18. THD of
of grid current
in
steady
state.
Figure
19.19.
Experimental
currentsofofCHB
CHBcapacitive
capacitive
mode.
Figure
Experimental grid
grid currents
mode.
Figure 19. Experimental grid currents of CHB capacitive mode.
12 of 19
12 of 19
Energies 2018, 11, 2435
12 of 18
Figure 19. Experimental grid currents of CHB capacitive mode.
Figure
20. Experimental
CHB
inductive
mode.
Figure
20. Experimentalgrid
grid currents
currents ofofCHB
inductive
mode.
4.3. Dynamic
Response
Compared
with
dqdq
Control
4.3. Dynamic
Response
Compared
with
Control
Currently,
the most
popular
controlmethod
method for
CHBCHB
converter
is dq control.
Currently,
the most
popular
control
forthe
thesingle-phase
single-phase
converter
is dq control.
Several
experiments
were
carried
out
tocompare
compare conventional
conventional dq dq
control
withwith
the proposed
control control
Several
experiments
were
carried
out
to
control
the
proposed
Energies 2018, 11, x
13 of 19
method. These experiments tested the dynamic responses of the systems under sudden power change
method.InThese
testeddc-link
the dynamic
of the
systems
sudden
power was
conditions.
theseexperiments
tests, the total
voltageresponses
udc_sum was
kept
at 100under
V, and
the system
change
conditions.
In
these
tests,
the
total
dc-link
voltage
u
dc_sum was kept at 100 V, and the system
connected to two resistive loads where R1 is 10 Ω and R2 is 15 Ω, respectively. The dynamic of the
connected
two resistive loads where R1 is 10 Ω and R2 is 15 Ω, respectively. The dynamic *of
d-axiswas
current
i* d intothe
dq control was managed by the outer voltage loop, and active power p in the
the d-axis current i*d in the dq control was managed by the outer voltage loop, and active power p* in
proposed scheme was controlled by the outer power loop. Therefore, only step changes in the reactive
the proposed scheme
was controlled by the outer power loop. Therefore, only step changes in the
current
reference i* in the dq control and reactive power reference q* in the proposed control were
reactive currentq reference i*q in the dq control and reactive power reference q* in the proposed
applied
to evaluate
the dynamic
control
of each.
Differences
the Differences
dynamic performance
control
were applied
to evaluate
theperformance
dynamic control
performance
of in
each.
in the
of thedynamic
dq control
scheme
and
the
proposed
control
method
are
illustrated
in
Figures
performance of the dq control scheme and the proposed control method are 21–28.
illustrated in
The
total
dc-link voltage udc_sum is 100 V; i* q and q* are given directly in each control method.
Figures
21–28.
The total
dc-link voltage
udc_sum
is 100
i*q and
directly
in each
method.
Reactive power
reference
q* equals
udc_sum
* i*V;
* i*qq*).are
Forgiven
instance,
when
the control
step change
of i* q is
q (100
*
*
*
*
*
*
*
Reactive
power reference
q equals
* ivar);
q (100when
* i q). For
when
i q ischange
5
5 A, the
step change
of q equals
100 * iudc_sum
the instance,
step change
ofthe
i q step
is −5change
A, theofstep
q (500
* equals 100 * i*q (500 var); when the step change of i*q is −5 A, the step change
*
*
A,
the
step
change
of
q
of q equals 100 * i q (−500 var).
of q* equals 100 * i*q (−500 var).
As
shown, the transient responses of the proposed power control method (less than 1 ms) were
As shown, the transient responses of the proposed power control method (less than 1 ms) were
faster than the dq control method (more than 5 ms). In the dq control method, a time delay of 1/4 in the
faster than the dq control method (more than 5 ms). In the dq control method, a time delay of 1/4 in
fundamental
period arose from classical imaginary current construction.
the fundamental period arose from classical imaginary current construction.
Grid Grid
current
and five-level
staircase
voltage
continuous
distortions
also
appeared
in in
thethe
dq control
current
and five-level
staircase
voltage
continuous
distortions
also
appeared
dq
method
duemethod
to conventional
imaginaryimaginary
current construction.
control
due to conventional
current construction.
Figure
21.21.
i* qi*changed
A to
to55AA(dq
(dqcontrol
control
method).
q changed from
Figure
from 00 A
method).
Energies 2018, 11, 2435
Energies 2018, 11, x
Energies 2018, 11, x
Figure 21. i*q changed from 0 A to 5 A (dq control method).
Figure 22.
22. qq**changed
changedfrom
from00var
varto
to500
500var
var(proposed
(proposed control
control method).
method).
Figure
Figure 23. i**q changed from 0 A to −5 A (dq control method).
Figure
changed from
A(dq
(dqcontrol
controlmethod).
method).
Figure23.
23.ii*qq changed
from 00 A
A to
to −
−55A
* changed from 0 var to −500 var (proposed control method).
Figure
Figure 24.
24. qq* changed
from 0 var to −500 var (proposed control method).
Figure 24. q* changed from 0 var to −500 var (proposed control method).
13 of 18
14 of 19
14 of 19
Energies 2018, 11, 2435
Energies 2018, 11, x
Energies 2018, 11, x
Figure 24. q* changed from 0 var to −500 var (proposed control method).
*
Figure
A (dq
(dq control
control method).
method).
Figure25.
25.i i*qq changed
changed from
from 55 A
A to
to −
−55 A
Figure 26. q** changed from 500 var to −500 var (proposed control method).
Figure
changed from
from 500
500 var
var to
to −500
−500var
var(proposed
(proposedcontrol
controlmethod).
method).
Figure 26.
26. qq* changed
*
Figure
Ato
to55A
A (dq
(dq control
control method).
method).
Figure27.
27.ii*qq changed
changed from
from −
−55A
Figure 27. i*q changed from −5 A to 5 A (dq control method).
14 of 18
15 of 19
15 of 19
Energies 2018, 11, 2435
15 of 18
Figure 27. i*q changed from −5 A to 5 A (dq control method).
Figure
28. q* changed from −500 var to 500 var (proposed control method).
Figure 28. q* changed from −500 var to 500 var (proposed control method).
4.4. Voltage Balance Control
Energies 2018, 11, x
16 of 19
Besides grid current control, balance control of the dc-link voltages is another important issue.
4.4. Voltage Balance Control
A dc-link
voltage balance control method based on power was adopted to render the proposed power
Besides
grid current
balance
controlunder
of the unbalanced
dc-link voltages
is another
important issue.
control strategy
applicable
to control,
the CHB
converter
load
conditions.
A dc-link voltage
balance control
method
on power
was adopted
to render the proposed
Unbalanced
load experimental
tests
werebased
conducted
to verify
the voltage-balancing
performance
power control strategy applicable to the CHB converter under unbalanced load conditions.
of the presented scheme. In these experiments, the load resistor of the first H-bridge R1 was stepped
Unbalanced load experimental tests were conducted to verify the voltage-balancing
from 15performance
Ω to 10 Ω of
whereas
that of
the second
R2the
was
15 H-bridge
Ω. In Figure
29a,
the presented
scheme.
In these H-bridge
experiments,
loadmaintained
resistor of theatfirst
R1
when the
resistors
were
thethat
dc-link
of the first
H-bridge
udc1at(10
V/division)
wasload
stepped
from 15
Ω tochanged,
10 Ω whereas
of thevoltage
second H-bridge
R2 was
maintained
15 Ω.
In
declinedFigure
from29a,
50 V
to 45
andresistors
that of were
the second
H-bridge
udc2
(10 V/division)
increased
from 50 V
when
theV,load
changed,
the dc-link
voltage
of the first H-bridge
udc1 (10
fromwhen
50 V the
to 45
V, andbalance
that of controller
the second was
H-bridge
udc2 (10
to 55 V. V/division)
Figure 29bdeclined
shows that
voltage
adopted,
theV/division)
dc-link voltages
increased
from
50
V
to
55
V.
Figure
29b
shows
that
when
the
voltage
balance
controller
could be controlled to 50 V when the load resistors were changed. Thus, the accuracy of thewas
presented
adopted, the dc-link voltages could be controlled to 50 V when the load resistors were changed.
dc-link voltage balance control method was confirmed.
Thus, the accuracy of the presented dc-link voltage balance control method was confirmed.
(a)
(b)
Figure
29. Experimental
response
of dc-link
voltages
when
load
changed:
Withoutvoltage
voltagebalance
Figure 29.
Experimental
response
of dc-link
voltages
when
load
changed:
(a)(a)Without
balance controller, (b) With voltage balance controller.
controller, (b) With voltage balance controller.
5. Discussion
5. Discussion
The proposed power and voltage control method offers many advantages including no
Thecoordinate
proposedtransformation,
power and voltage
control method offers many advantages including no coordinate
PLL, or conventional imaginary current construction. Moreover, it was
transformation,
PLL,
or
conventional
imaginary
current
construction.
Moreover,
it was dq
found to
found to exhibit faster transient responses
and lower
distortions
compared with
the conventional
exhibit control
faster transient
lower
distortions compared with the conventional dq control
method, asresponses
illustrated inand
Figures
21–28.
The natural frame
control21–28.
scheme presented in [23] also shows the advantages of no coordinate
method, as illustrated
in Figures
PLL,
or conventional
imaginary current
from the natural
frame
Thetransformation,
natural frame
control
scheme presented
in [23]construction.
also shows Differ
the advantages
of no
coordinate
control scheme, the proposed scheme connects power control with current control through the
transformation, PLL, or conventional imaginary current construction. Differ from the natural frame
instantaneous power theory. Besides, the proposed voltage balance control module is based on
power, in which the power compensation values are used to eliminate the uneven power in active
power p and reactive power q.
Even so, this control strategy has some limitations: First, although classical imaginary current
construction is not necessary, the creation of an imaginary voltage component cannot be avoided.
Therefore, an algorithm can be developed to reduce the time delay caused by imaginary voltage
Energies 2018, 11, 2435
16 of 18
control scheme, the proposed scheme connects power control with current control through the
instantaneous power theory. Besides, the proposed voltage balance control module is based on
power, in which the power compensation values are used to eliminate the uneven power in active
power p and reactive power q.
Even so, this control strategy has some limitations: First, although classical imaginary current
construction is not necessary, the creation of an imaginary voltage component cannot be avoided.
Therefore, an algorithm can be developed to reduce the time delay caused by imaginary voltage
construction. Second, only the steady grid voltage condition was considered here, although abnormal
operating states (e.g., grid voltage distortion) exist; thus, the control method should be optimized to
make it applicable to such states.
6. Conclusions
A power control method is introduced for the single-phase CHB multilevel converter in this paper.
A power-based dc-link voltage balance control module is also presented to eliminate the different
dc-link voltages caused by the unbalanced loads.
The proposed power and voltage control method is designed in a virtual αβ stationary reference
frame without coordinate transformation or phase-locked loop. So, the complicated calculation issue
can be avoided. What is more, conventional imaginary current construction is not necessary. Problems
like time delay can also be avoided. The inner loop current calculation is simplified compared with the
conventional dq control scheme. Stability of the proposed control scheme can be guaranteed through
the analysis based on small-signal model.
Simulation and experimental results were presented to verify the effectiveness of the proposed
control method. In the steady state, the proposed method can obtain the sinusoidal grid current and
unity power factor under unbalanced load conditions. Upon comparing the dynamic response of the
presented control strategy with that of the dq control scheme, the conducted experiments indicate that
the salient feature of the proposed scheme is as follows: the proposed scheme maintains a fast dynamic
response advantage over the conventional dq control method. This approach has been shown to be
useful for the single-phase CHB multilevel converter system. The proposed control scheme can also be
utilized with other multilevel converter systems.
Author Contributions: The individual contribution of each co-author with regards to the reported research and
writing of the paper is as follows. D.Y. conceived the idea, L.Y. carried out the experiments and analyzed the data,
and all authors wrote the paper.
Acknowledgments: This study is partly supported by the National Nature Science Foundation of China
(No. 61861003).
Conflicts of Interest: The authors declare no conflict of interest.
Nomenclature
CHB
PWM
DPC
DCC
P-DPC
PLL
DSP
MPC
SOGI
PI
PR
CPS-PWM
THD
Cascaded H-bridge
Pulse Width Modulation
Direct Power Control
Direct Current Control
Predictive DPC
Phase-Locked Loop
Digital Signal Processor
Model-Predictive Control
Second-Order Generalized Integrator
Proportional-Integral
Proportional-plus-Resonant
Carrier, Phase-Shifted PWM
Total Harmonic Distortion
Energies 2018, 11, 2435
17 of 18
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