Sana'a University
Faculty of Engineering
Department of Mechatronics
LOGIC SYSTEM DESIGN
Lab Manual
2015
Prepared by: Eng. Zakarya
EXPERIMENT 1
VERIFICATION AND INTERPRETATION OF TRUTH TABLES
Objective:
Verification and interpretation of truth tables for AND, OR, NOT, NAND,
NOR Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) Gates.
Theory:
Logic gates are electronic circuits which perform logical functions on one or more
inputs to produce one output. There are seven logic gates. When all the input
combinations of a logic gate are written in a series and their corresponding outputs
written along them, then this input/ output combination is called Truth Table.
Procedure:
1- Connect the inputs to the input switches.
2- Connect the output to the switches of O/P LEDs.
Apply various combinations of inputs according the truth tables.
 Inverter Gate (NOT Gate – 7404LS)
 2-Input AND Gate (7404LS)
 2-Input OR Gate (7432LS)
 2-Input NAND Gate (7400LS)
 2-Input NOR Gate (7402LS)
 2-Input EX-OR Gate (7486LS)
 3-Input NAND Gate (7410LS)
 2-Input NAND Gate (CD4011)
 2-Input NOR Gate (CD4001)
 4-Input NAND Gate (7420LS)
 2-Input EX-NOR (IC 74266)
EXPERIMENT 2
REALIZATION OF LOGIC FUNCTIONS
Objective:
Realization of logic functions with the help of universal gates-NAND Gate.
Theory:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT
gate. So its output is complement of the output of an AND gate.
This gate can have minimum two inputs, output is always one. By using only NAND
gates, we can realize all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So
this gate is also called universal gate.
NAND gates as NOT gate:
Y = (A.A)’
=>
Y = (A)’
NAND gates as AND gate:
Y = ((A.B)’)’
=>
Y = (A.B)
NAND gates as OR gate
From DeMorgan’s theorems: (A.B)’ = A’ + B’
NAND gates as NOR gate:
Y = (A + B)’
NOR gates as NOT gate:
Y = (A+A)’
=>
=>
(A’.B’)’ = A’’ + B’’ = A + B
Y = (A)’
NOR gates as OR gate:
Y = ((A+B)’)’
NOR gates as AND gate
From DeMorgan’s theorems: (A+B)’ = A’B’
NOR gates as X-OR gate:
NOR gates as NAND gate:
=>
=>
Y = A’B+ AB’
Y = (AB)’
Y = (A+B)
(A’+B’)’ = A’’B’’ = AB