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Hardware Lab 1

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EEE 120
Hardware Lab 1 Answer Sheet
Debugging a Half and Full Adder
Name: Bart Mistrot
Task 1-1: Build and Test the SUM & CRY of the 1-Bit Half-Adder
Follow the tesAng procedures outlined in the laboratory manual on your 1-bit half adder circuit and
record your results in Table 1:
Table 1
Input
(Logic Values)
Output
(Logic Values)
A
B
CRY
SUM
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
O1
Task 1-2: Debugging
As outlined in the lab manual debug your 1-bit half adder circuit aPer you or someone else has
introduced a random wiring error while you were not looking. Use the space provided below to describe
what steps you took to debug the circuit.
I randomly disconnected a wire and my logic table became:
Table 1
Input
(Logic Values)
Output
(Logic Values)
A
B
CRY
SUM
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
1
APer seeing the table output changed when both A and B were high inputs I decided to probe the
circuit while the inputs remained high from the output of the SUM all the way back to its input since
SUM should be “0”. APer probing with the voltmeter I noAced pin 6 on the 74LS32 had a 4.319 V high
output when it should have been low. APer inspecAng the inputs of the OR gate I detected a voltage of
1.91 V on the input of pin 5 for the 74LS32 which should have been low. This created an addiAonal high
input on pin 5 of 74LS08 that enabled the LED light for the SUM that should not have been there.
O2
Task 1-3: Build, Debug and Test a TTL 1-Bit Full Adder
Use the area below to draw a schemaAc of your SOP implementaAon of a 1-bit full adder. Feel free to
modify the figure in the lab manual if you want. Both Logisim schemaAc and hand-drawing are
acceptable. Be sure to idenAfy which pins of which TTL IC’s are used to implement each of the Boolean
gates in your design.
O3
Test your circuit using the control panel and record your results in Table 3.
Table 3
A
B
CRY
SUM
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
O
Task 1-4: Take a Photo of your Completed Circuit
Paste a photo of your completed 1-bit full adder in the space below:
O4
O5
HARDWARE LAB 1: LAB REPORT GRADE SHEET
Name:
Instructor Assessment
Grading Criteria
Max Points
Template
Neatness, Clarity, and Concision
2
DescripLon of Assigned Tasks, Work Performed & Outcomes Met
Task 1-1: Build and : Test the SUM & CRY of the 1-Bit Half-Adder
8
Task 1-2 Debugging
5
Task 1-3: Build, Debug and Test a TTL 1-Bit Full Adder
10
Self-Assessment Worksheet
(The content of the self-assessment worksheet will not be
graded. Full credit is given for including the completed worksheet.)
(2 extra
points)
Points Lost
Late Lab
Lab Score (25 total)
Lab Score
O6
Points
Lost
SELF-ASSESSMENT WORKSHEET
Put an ‘X’ in the table below indicaAng how strongly you agree or disagree that the outcomes of the
assigned tasks were achieved. Use ‘5’ to indicate that you ‘strongly agree’, ‘3’ to indicate that you are
'neutral', and ‘1’ to indicate that you ‘strongly disagree’. Use ‘NA’, ‘Not Applicable’, when the tasks you
performed did not elicit this outcome. Credit will be given for including this worksheet with your lab
report; however, your responses will not be graded. They are for your instructor’s informaAon only.
Table 4: Self-Assessment of Outcomes for Hardware Lab 1.
ASer compleLng the assigned tasks and report, I am
able to:
5
4
3
2
1
NA
Describe the truth tables that characterize the addiAon
X
of two single bit numbers.
Write the Boolean algebraic expressions that
characterize the sum and carry funcAons for the half
adder using both the product-of-sums and sum-ofproducts canonical forms.
X
Realize the sum and carry funcAons using TTL
hardware.
X
Debug TTL circuits using a Voltmeter as tesAng
instrument.
X
Write the Boolean algebraic expressions that
characterize the sum and carry funcAons for the full
adder.
X
Build and test a full adder.
X
Write below any suggestions you have for improving this laboratory exercise so that the stated learning outcomes
are achieved.
This was insanely fun :)
O7
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