Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic
CMOS Process
Chakravarthy Gopalan, Yi Ma, Tony Gallo, Janet Wang, Ed Runnion, Juan Saenz, Foroozan Koushan, and
Shane Hollmer
Adesto Technologies, 1225 Innsbruck Drive, Sunnyvale, CA. 94089, USA
Tel: (408) 400-0578, Chakku.Gopalan@adestotech.com
INTRODUCTION
RESULTS AND DISCUSSION
One of the promising technologies under development
for next generation non-volatile memory is the
Conductive Bridging Random Access Memory (CBRAM)
which utilizes the reversible switching of an electroresistive dielectric between two conductive states as
means of storing logical data [1-5]. In this paper, we
describe the successful integration of CBRAM
technology into an industry standard logic process.
Moreover, we show functional operation of such a
fully CMOS integrated CBRAM memory array and
highlight its specific fundamental low power
characteristics that make it suitable to be used in
scaled embedded application as well as discrete
devices.
The DC or quasi static current voltage characteristics in
Fig. 3 shows that as the voltage across the storage
resistor is swept, the device is initially at high
resistance state and switches on upon reaching a
certain threshold voltage. Here, a current compliance
of 10μA prevents the resistance to increase in a
runaway effect. When the voltage is swept back, the
storage dielectric is shown to be in the conductive
state. A dynamic range of 10,000 is shown in this
graph. This conductive state is a function of the
program current and can be controlled accurately
rendering multi-level cell possibility for this technology.
Figure 3b shows the dependence of resistance state
on programming current. This allows for potential use
of this technology in multi-level cell (MLC)
implementation. The threshold voltage can be tuned
by process and operational parameters to fit
seamlessly in a standard logic process. To erase the
cell, the voltage is swept back in the negative direction
and the high resistance state is recovered.
A critical aspects of a new technology,
especially when new materials are introduced is to
ascertain that there will not be negative effects on the
core CMOS technology. An integration scheme has
been developed to eliminate any impact on core
CMOS performance and especially impact on FEOL
devices. Such an integration scheme is essential in use
of this technology for embedded applications. Fig. 4
shows an example of core transistor characteristics
with and without CBRAM module. Another critical
elements for any new memory technology is a wide
margin of operation between data “1” and data “0”
states. A narrow margin will result extra burden on
design resources and also will be costly in terms of die
area (i.e, use of larger cells or differential cell
schemes). CBRAM technology offers a wide range of
operation and hence simplifies architectural and
design constraints. Fig. 5 shows low and high
resistance distributions achieved on one of the early
samples.
One of the unique and beneficial attributes of
the CBRAM technology is that the switching voltage
BACKGROUND AND EXPERIMENTS
CBRAM technology is known by other names such as
programmable metallization cell (PMC) solid
electrolyte memory, nano-ionic resistive memory,
electrochemical memory (ECM). The operational
principle of CBRAM technology is based on a
reversible creation of an electrochemically induced
nanoscale conductive link in a special dielectric acting
as a ion conducting solid-electrolyte. In its simplest
implementation, the basic storage element consists of
an access transistor and a programmable resistor
(similar to the DRAM one transistor and one capacitor
cell). We have successfully integrated this resistive
memory in 180nm with Aluminum back-end-of-line
(BEOL) as well as 130nm with Copper BEOL logic
processes (Fig. 1 & 2). Cross section image of a fully
integrated 1T1R cells are shown in these figures. The
programmable elements required only 2 non critical
masks at BEOL steps. In this paper, we present basic
characterization results on 180nm and 130nm logic
CMOS integrated CBRAM memory arrays. We explore
the operational capability of the core technology
including sub 100ns write, data sheet operation at 1V,
multi-level cell capability as well as retention and
reliability characteristics. Data was collected on single
cells as well as fully integrated decoded arrays.
978-1-4244-6721-1/10/$26.00 ©2010 IEEE
(SET voltage) is dependent on the voltage sweep rate
(Fig. 6). The fundamental reason behind this so called
“voltage-time dilemma” [6] is the complex dynamics
of three processes involved in the formation of the
conductive path: anodic dissolution, ion drift and
cathodic reduction at the opposite electrode. Current
understanding seem to indicate that the cathodic
reduction is the rate limiting process [6] however
other possible mechanisms are under investigation.
Empirically, this effect is very beneficial from the noise
immunity perspective since in real operation of a
memory cell in a device, the read and write switching
6
pulses have very high ramp rates exceeding 10 V/sec.
We show this effect in Fig. 7 where the quasi DC
switching of a cell occurs at 0.4V but in transient mode
operation the switching voltage for the same cell is
over 1.2V. This allows for better read disturb
immunity for real operating conditions We have
characterized the read disturb to an empirical model
showing that robust read operation for 10 years is
possible when read voltages are kept above below
230mV (Fig. 8). Cell structure, material and process
parameters will impact this voltage and hence careful
consideration is required to achieve robust disturb
immunity.
The endurance characteristics of CBRAM
technology is shown in Figures 9 and 10. Figure 9
shows number of pulses required to verify an ON state
and OFF state as a function of cycles. This data was
taken on fully decoded CMOS integrated arrays and
shows no degradation of the write operation. Figure
10 shows actual resistance distributions as measured
using a special test mode on the integrated decoded
arrays. Here we show that resistance distributions are
un-affected as a result of cycling.
Functional characteristics of the arrays were
also measured across temperature (Figure 11). It is
clear that the arrays show full functionality across 0C
to 100C. These results here show a typical result of
number of pulses needed for program or erase as well
as resistance distributions. Finally, we show standard
functionality of various standard patterns written in an
integrated CBRAM array in a standard logic process
(Fig. 12).
CONCLUSIONS
Today’s main stream NVM technologies
require operational conditions that are incompatible
with modern low voltage logic CMOS designs. This
characteristic results in complex integration issues as
well as costly process and array concept especially for
embedded NVM use models. Conductive bridging
memory cell (CBRAM) technology is an attractive
emerging memory technology that offers simple
integration and scalable operational conditions. These
unique features make CBRAM technology an ideal
candidate for embedded applications. In this paper,
we have shown successful integration of CBRAM into
Copper and Aluminum back end logic CMOS processes
with minimal number of added masks.
ACKNOWLEDGEMENT
The authors would like to thank technology
and engineering teams at Adesto Technologies as well
as Prof. Michael Kozicki of ASU for helpful discussions.
REFERENCES:
[1] M.N. Kozicki, et al, “Nanoscale Memory
Elements Based on Solid-State Electrolytes”,
IEEE Trans. Nanotechnology, vol. 4, p. 331,
2006.
[2] M. N. Kozicki, et al,” Programmable
Metallization Cell Memory Based on Ag-Ge-S
and Cu-Ge-S Solid Electrolytes”, IEEE NonVolatile Memory Techn. Symp. Tech. Dig., p.
89, 2005.
[3] M. Kund, et al, “Conductive bridging RAM
(CBRAM): An Emerging Non-Volatile Memory
Technology Scalable to Sub 20nm”, IEDM
Tech. Dig., 2005.
[4] R. Symanczyk, et al, “Conductive Bridging
RAM Development from Single Cells to 2Mb
Arrays”, IEEE Non-Volatile Memory Techn.
Symp. Tech. Dig., p. 70, 2007.
[5] R. Waser, et al, “Redix-Based Resistive
Switching Memories – Nanoionic Mechanisms,
Prospects, and Challenges”, Adv. Materials,
vol. 21, p. 2632, 2009
[6] C. Schindler, et al, “Electrode kinetics of Cu–
SiO2-based resistive switching cells:
Overcoming the voltage-time dilemma of
electrochemical metallization memories”,
Appl. Phys. Lett., vol. 94, 2009.
978-1-4244-6721-1/10/$26.00 ©2010 IEEE
Figure 1
CBRAM cell: schematic, integration in 180nm, integration in 130nm.
Dotted circle indicates the programmable resistor.
Figure 2
Top view of fully integrated CBRAM arrays
on standard CMOS logic process
VSL
BL
Storage
Dielectric
WL
Access
Transistor
180nm (Al BEOL)
Logic Process
130nm (Cu BEOL)
Logic Process
Figure 3
Quasi DC switching characteristics of a CBRAM programmable resistor.
384Kb Testchip
on standard
180nm (Al BEOL)
1Mb EEPROM/Flash
Macro on Standard Foundry
130nm (Cu BEOL)
Figure 4
Example of data showing integration of CBRAM in logic
process does not impact CMOS device characteristics
DC Current Voltage Characteristics of
2 Terminal CBRAM Cell (Current Compliance Set at 10uA)
1.0E-05
Low
8.0E-06
Current (A)
6.0E-06
4.0E-06
2.0E-06
0.0E+00
-2.0E-06
-4.0E-06
High
-6.0E-06
-8.0E-06
-1.0E-05
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Votlage (V)
(a)
Current Voltage
Characteristics
(b) Low resistance state
dependence on program current
With CBRAM
Without CBRAM
Figure 6
The fundamental characteristic of this technology is a dependence
of switching voltage on the actual voltage sweep rate. This is
shown in two different CBRAM technologies below.
Figure 5
Example of high resistance & low resistance distributions showing
wide distribution. Also, low resistance state allows larger
than 1uA read currents allowing fast random read operation.
(b) Cu/SiO2 CBRAM cell
(a) Ag/GexSy CBRAM cell;
(after Schindler, et al, App. Phys. Lett. (94), 2009).
This nature of the CBRAM technology allows better immunity to read disturb.
Figure 7
Data showing the difference in switching (SET) voltage between quasi
DC and actual AC operation. The same cell shows quasi DC switching
voltage of 0.4V while the actual operational voltage is over 1.2V.
Figure 8
Data showing time to disturb (erased cell) using an empirical fit
Data shows that due to the dynamic nature of switching threshold,
good noise immunity for read operation can be attained.
Case Voltage Stress Characteristics
ReadWorst
Disturb
Characteristics
Roff
~ 500KΩ
1.E+09
Time To Disturb (sec)
1.E+08
1.E+07
1.E+06
1.E+05
30ns x 1014 Read Cycles
1.E+04
1.E+03
1.E+02
~250mV
1.E+01
~230mV
1.E+00
1.E-01
1.E-02
0
5
10
15
20
25
30
35
40
45
50
Exp (1/Vr)
978-1-4244-6721-1/10/$26.00 ©2010 IEEE
55
60
65
70
75 80 85 90
y = 0.0042e0.3497x
R2 = 0.9869
Figure 9
100K Program and erase characteristics as a function
of cycling. Data shows the total number of pulses
needed to program verify the ON state to 50KΩ or
less and the OFF state to 800KΩ or more.
Figure 10
Data showing low and high resistance distributions measured as a function of
write cycles on 32Kb fully decoded arrays. Data shows robust window of
operation and no degradation as a result of cycling.
D0 (1)
Single Byte 10K Cycling (32K Arrays)
Sense Margin
D1 (1)
D0 (100)
D1 (100)
D0 (1000)
Resistance (MΩ )
10
D1 (1000)
D0 (10000)
D1 (10000)
1
OFF (DATA=0)
sense margin
0.1
ON (DATA=1)
0.01
0.001
0
1
2
3
4
5
DATA IO #
6
7
8
9
(a) shows measured resistance values
(b) shows actual resistance distributions on
on a byte vs. number of write cycles.
32Kb arrays as a function of write cycles.
Figure 11
Program and Erase across temperature.
T=0C
T=25C
T=100C
Pulse Count for
Program and Erase Verify
Resistance
Distributions
T=0C
T=25C
T=100C
Erased
Programmed
Resistance Bin (KΩ )
Figure 12
Bitmap capture of a demonstration of a fully functional CBRAM array integrated in a logic process. Data programmed include CHKB, revCHKBD,
Diagonal, ALL 1, ALL 0.
978-1-4244-6721-1/10/$26.00 ©2010 IEEE