Uploaded by shuddhodhan shetty

Digital Design Notes

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
Number system conversion:
o Any Radix system to Decimal:
 Ex1: Binary to Decimal: 101012 = 1*20 + 0*21 + 1*22 + 0*23 + 1*24 = 2110
 Here, the calculation is done from right to left (1*2 0 is the one which is there
at the LSB or right most side)
 Ex2: (110111.1011)2 = (?)10
o Here, it is bifurcated into 2 parts. One before the dot and after the
dot.
o Taking 110111 = 1*20 + 1*21 + 1*22 + 0*23 + 1*24 + 1*25 = 5510.
o Taking .1011, it goes from left to right:1*2-1 + 0*2-2 + 1*2-3 + 1*2-4
o This value is (0.6875)10
o So total value is (55.6875)10
o Calculation method is:
o
Decimal to any Radix:
 Done by successive division of whole decimal number by radix number
 Ex: 12510 = ?2
 Process: (Answer will be (1111101)2

o

For fraction decimal number: Ex2: (0.7) 10 = (?)2
 0.7*2 = (1).4
 0.4*2 = (0).8
 0.8*2 = (1).6
 0.6*2 = (1).2
 0.2*2 = (0).4
 0.4*2 = (0).8 -- Repeats. Stop here
 Answer: 0.1011002.
 Calculation is done from top to bottom
Binary to Octal & Hex & vice-versa:
 Ex1: (11011.011)2 = (?)8 = (?)16
 Group in 3s: 011 011 . 011 = (33.3)8
 Group in 4s: 0001 1011 . 0110 = (1B.6)16
 Working is:
 Ex2: (476.543)8 = (?)2 :
 Convert each digit to 3 bit binary form: (100 111 110 . 101 100 011) 2
 Ex3: (ADE.54C)16 = (?)2
 Convert each digit to 4 bit binary form: (1010 1101 1110 . 0101 0100 1100)
Signed Magnitude Representation:
o MSB of bit string is used as the sign bit & the lower bits contain the magnitude.
o 11112 = 15. This is an unsigned number
o 011112 = +15. This is a signed number.
o 111112 = -15. This is a signed number.
o Range of the ‘n’ bit signed magnitude integer is from : - (2n-1 – 1) to +(2n-1 – 1).
o In the above example, 4 bits are there, so range is -7 to +7.




Gates: (TT)
A
0
0
1
1
B
0
1
0
1
AND
0
0
0
1
NAND
1
1
1
0
OR
0
1
1
1
NOR
1
0
0
0
EX-OR
0
1
1
0
EX-NOR
1
0
0
1
Boolean Algebra:
o X+0=X
o X+1=1
o X+X=X
o X + X’ = 1
o X.X=X
o X . X’ = 0
o X + X.Y = X (Calculation is X(1+Y) => X.1
o X.Y +X.Y’ => X(Y+Y’) = X.1 = X
o (X + Y)(X + Z) => X + XZ + YX + YZ => X(1 + Z) + YX + YZ => X(1 + Y) +YZ => X +
YZ
o X.(X + Y) = X
o (X + Y) . (X +Y’) = X
o XY + YZ + X’Z => (Expand with x+x’, y+y’, z+z’ etc) = X’Z + XY
o (X + Y).(Y + Z).(X’ + Z) = (X + Y).(X’Y + Z)
o Demorgans Theorem:
 (A.B)’ = A’ + B’
 (A + B)’ = A’.B’
o Consensus Theorem:
 A.B + BC + A’C = A.B +A’C
Logic Minimization can be done using:
o Theorems
o Karnaugh maps
Karnaugh Maps Examples: (How Karnaugh reduction works)
o 5-bit Kmap:
o
Kmap with don’t cares:
o
Other Ex:

Combinational Circuits:
o Types of Adders:
 CLA (Carry Look Ahead)
 Cascaded carry look ahead
o Code Converters (B2G)

Sequential Circuits:
o Latches:
 SR Latch:
 If S=1, R=1 happens, Q/Q’ will toggle between 1 & 0 infinitely. This is
known as forbidden state or race condition.

o
Gated D Latch:
 When G is 1, Q=D; If G is 0, previous value is latched.
Flip-Flops:
 (Q+ is the next state)
 SR Flip-Flop:
S
R Q+
0
0
Q
0
1
0
1
0
1
1
1
Invalid

D Flip-Flop:
D
Q
0
0
1
1

J-K Flip-Flop:
 Is a modified version of SR F/F with an added layer of feedback.
 Feedback selectively enables one of the S/R inputs so that both cannot carry
active signal, thus eliminating invalid condition.
 Diagram:


(Q+ is
T Flip-Flop:
T
Q
0
Q
1
Q’
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