A
Project Report On
ROUTER
Submitted in partial fulfilment of the requirements for award of the degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
DIVYA SREE MADHA(14ND1A0478)
NAGA SUJATHA YARRAMSETTY(14ND1A04A0)
Under the guidance of
Mr. N.S. SHEKAR BABU
In charge, CED
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED
(A Government of India Enterprise)
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
ST.MARY’S WOMEN’S ENGINEERING COLLEGE
(Approved by AICTE,permitted by Govt.of A.P.,Affiliated to JNTUK)
Budampadu(v),Guntur Dist,A.P,India-522017.
A
Project report on
ROUTER
Submitted in partial fulfilment of the requirements for award of the degree of
BACHELOR OF TECHNOLOGY
In
ELECTRONICS AND COMMUNICATION ENGINEERING
By
MAMIDI SANGHAVI(15VE1A0433)
Under the guidance of
Mr. N.S. SHEKAR BABU
In charge, CED
Of
ECIL-ECIT
ELECTRONICS CORPORATION OF INDIA LIMITED
(A Government of India Enterprise)
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
SREYAS INSTITUTE OF ENGINEERING & TECHNOLOGY
(Approved by AICTE,New Delhi | Affiliated to JNTUH,Hyderabd)
Campus Address: Bside Indu Aranya, GSI, Bandlaguda,Nagol,HYD-500068)
.
2
DECLARATION
We hereby declare that the project entitled ―ROUTER” submitted in
partial fulfilment of the requirements for the award of degree of Bachelor of
Technology in Electronics and Communication Engineering. This
dissertation is our original work and the project has not formed the basis for the
award of any degree, associate ship, fellowship or any other similar titles and no
part of it has been published or sent for the publication at the time of
submission.
DIVYA SREE MADHA(14ND1A0478)
NAGA SUJATHA YARRAMSETTY(14ND1A04A0)
MAMIDI SANGHAVI(15VE1A0433)
3
ACKNOWLEDGEMENT
We wish to take this opportunity to express our deep gratitude to all those
who helped, encouraged, motivated and have extended their cooperation in
various ways during our project work. It is our pleasure to acknowledgement
the help of all those individuals who was responsible for foreseeing the
successful completion of our project.
We would like to thank Mr. N.S. SHEKAR BABU (In charge, CED) and
express our gratitude with great admiration and respect to our project guide
Mr. T. Naveen Kumar Reddy and Ms. K. SIVA RAMALAKSHMI for their
valuable advice and help throughout the development of this project by
providing us with required information without whose guidance, cooperation
and encouragement, this project couldn‘t have been materialized.
Last but not the least; we would like to thank the entire respondents for
extending their help in all circumstances.
DIVYA SREE MADHA(14ND1A0478)
NAGA SUJATHA YARRAMSETTY(14ND1A04A0)
MAMIDI SANGHAVI(15VE1A0433)
4
CONTENTS
Topic
Page no:
1. Introduction
01
1.1 Abstract
03
2. Organization profile
04
3. Using Xilinx
06
4. Router
19
4.1. Introduction
19
4.2. Applications of routers
20
4.3. Types of planes
21
4.4. Types of routers and features
22
5. Router 1x3 Architecture
33
6. Project Overview
35
6.1. Project modules
36
7. Definition, Acronyms, Abbreviations
37
8. System Design
38
8.1. Use case diagram
39
8.2. Class diagram
40
8.3. Sequence diagram
41
8.4. Activity diagram
41
9. Screen layout
42
10. Code
43
11. Conclusion
65
5
6
DESIGN OF VLSI BASED ROBUST ROUTER FOR NETWORK ON CHIP
Abstract
In this we attempt to give a networking solution by applying VLSI architecture
techniques to router design for networking systems to provide intelligent control over the
network. Networking routers today have limited input/output configurations, which we attempt
techniques we explore include the use of multiple protocols. we attempt to overcome the
security and latency issues with protocol switching technique embedded in the router engine
itself.
The approach is based on hardware coding to reduce the impact of latency issues as the
hardware itself is designed according to the need. We attempt to provide a multipurpose
networking router by means of Verilog code, thus we can maintain the same switching speed
with more security as we embed the packet storage buffer on chip and generate the code as a
self-independent VLSI based router. Our main focus is the implementation of hardware IP
router.
The approach enables the router to process multiple incoming IP packets with different
versions of protocols simultaneously, e.g. for IPv4 and IPv6. The approach will results in
increased switching speed of routing per packet for both current trend protocols ,which we
believe would result in considerable enhancement in networking systems.
Multiprocessor system on chip is emerging as a new trend for system on chip design but
the wire and power design constraints are forcing adoption of new design methodologies.
1
INTRODUCTION:
In this we attempt to give a networking solution by applying VLSI architecture
techniques to router design for networking systems to provide intelligent control over the
network. Networking routers today have limited input/output configurations, which we
attempt techniques we explore include the use of multiple protocols. we attempt to
overcome the security and latency issues with protocol switching technique embedded in
the router engine itself.
The approach is based on hardware coding to reduce the impact of latency issues
as the hardware itself is designed according to the need. We attempt to provide a
multipurpose networking router by means of Verilog code, thus we can maintain the
same switching speed with more security as we embed the packet storage buffer on chip
and generate the code as a self-independent VLSI based router. Our main focus is the
implementation of hardware IP router.
The approach enables the router to process multiple incoming IP packets with
different versions of protocols simultaneously, e.g. for IPv4 and IPv6. The approach will
results in increased switching speed of routing per packet for both current trend protocols
,which we believe would result in considerable enhancement in networking systems.
Multiprocessor system on chip is emerging as a new trend for system on chip
design but the wire and power design constraints are forcing adoption of new design
methodologies. Router architecture better supports the integration of SOC consists of on
chip packet switched network. Thus the idea is borrowed from large scale
multiprocessors and wide area network domain and envisions on chip routers based
network.cores access the network by means of proper interfaces and have their packets
forwarded to destination through multichip routing path.In order to implement a
competitive architecture,the router should be efficiently design. In this paper we
implement a parallel router which can support five requests simultaneously. Thus the
speed of communication can be increased after reducing communication bottleneck by
using simplest routing mechanism, flow mechanism and decoding logic.
2
This project helps one to understand the complete functional verification process
of complex ASICs and SOC‘s and it gives opportunity to try the latest verification
methodologies, and sophisticated EDA tools, for the high quality verification.
BLOCKDIAGRAM:
8
data
8
data_out_0
vld_out_0
read_enb_0
packet_valid
suspend_data
err
clock
reset
n
8
8
Router_1X3
data_out_1
vld_out_1
read_enb_1
data_out_2
vld_out_2
read_enb_2
ADVANTAGES:

General purpose router

Router hardware code is available

High switching speed with any no. of I/O pin connection

More secured

Robust router can handle all type of packets
APPLICATIONS:

Can be used as public internetworking router

Can be used as corporate router

Software company private router (client to client, developer to client)

Router for networking research

In other words one point networking solution
Languages:

Verilog HDL
Tools used:

modelsim for simulation

Xilinx ISE for synthesis
3
ORGANIZATION PROFILE
ECIL was setup under the department of Atomic Energy in the year 1967 with a view to
generate a strong indigenous capability in the field of professional grade electronic. The initial
accent was on self-reliance and ECIL was engaged in the Design Development Manufacture and
Marketing of several products emphasis on three technology lines viz. Computers, control
systems and communications. ECIL thus evolved as a multi-product company serving multiple
sectors of Indian economy with emphasis on import of country substitution and development of
products and services that are of economic and strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into collaboration with OSI
Systems Inc. (www.osi-systems.com) and set up a joint venture "ECIL_RAPSICAN LIMITED".
This Joint Venture manufacture the equipment‘s manufactured by RAPSICAN, U.K, U.S.A with
the same state of art Technology, Requisite Technology is supplied by RAPSICAN and the final
product is manufactured at ECIL facility.
Recognizing the need for generating quality IT professionals and to meet the growing
demand of IT industry, a separate division namely CED has been established to impart quality
and professional IT training under the brand name of ECIT. ECIT, the prestigious offshoot of
ECIL is an emerging winner and is at the fore front of IT education in the country.
Mission
ECIL‘s mission is to consolidate its status as a valued national asset in the area of
strategic electronics with specific focus on Atomic Energy, Defense, Security and such critical
sectors of strategic national importance.
Objectives

To continue services to the country‘s needs for the peaceful uses Atomic Energy. Special
and Strategic requirements of Defence and Space, Electronics Security System and
Support for Civil aviation sector.

To establish newer Technology products such as Container Scanning Systems and
Explosive Detectors.

To re-engineer the company to become nationally and internationally competitive by
paying particular attention to delivery, cost and quality in all its activities.
4

To explore new avenues of business and work for growth in strategic sectors in addition
to working realizing technological solutions for the benefit of society in areas like
Agriculture, Education, Health, Power, Transportation, Food, Disaster Management etc.
Divisions
The Company is organized into divisions serving various sectors, national and
Commercial Importance. They are Divisions serving nuclear sector like Control & Automation
Division (CAD), Instruments & Systems Division (ISD), Divisions Serving defence sector like
Communications Division (CND), Antenna Products Division (APD), Servo Systems Division
(SSD) etc., Divisions handling Commercial Products are Telecom Division (TCD), Customer
Support Division (CSD), Computer Education Division (CED).
Exports
ECIL is currently operating in major business EXPORT segments like Instruments and
systems design, Industrial/Nuclear, Servo Systems, Antenna Products, Communication, Control
and Automation and several other components.
Services
The company played a very significant role in the training and growth of high calibre
technical and managerial manpower especially in the fields of Computers and Information
Technology. Though the initial thrust was on meeting the Control & Instrumentation
requirements of the Nuclear Power Program, the expanded scope of self-reliance pursued by
ECIL enabled the company to develop various products to cater to the needs of Defence, Civil
Aviation, Information & Broadcasting, Tele communications, etc.
5
Using Xilinx Ise A Brief Tutorial:
ISE 13.2i Quick Start Tutorial
The ISE 13.2i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of the
basic design process using ISE 13.2i. After you have completed the tutorial, you will have an
understanding of how to create, verify, and implement a design.
Note: This tutorial is designed for ISE 13.2i on Windows.
This tutorial contains the following sections:
• ―Getting Started‖
• ―Create a New Project‖
• ―Create an HDL Source‖
• ―Design Simulation‖
• ―Create Timing Constraints‖
• ―Implement Design and Verify Constraints‖
• ―Reimplement Design and Verify Pin Locations‖
• ―Download Design to the Spartan™-3 Demo Board‖
For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the
Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/
Software Requirements:
To use this tutorial, you must install the following software:
• ISE 13.2i
6
For more information about installing Xilinx® software, see the ISE Release Notes and
Installation Guide at: http://www.xilinx.com/support/software_manuals.htm.
Hardware Requirements:
To use this tutorial, you must have the following hardware:
• Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board
Starting the ISE Software
To start ISE, double-click the desktop icon,
or start ISE from the Start menu by selecting:
Start → All Programs → Xilinx ISE → Project Navigator
Note: Your start-up path is set during the installation process and may differ from the one above.
Accessing Help
At any time during the tutorial, you can access online help for additional information
about the ISE software and related tools.
To open Help, do either of the following:
• Press F1 to view Help for the specific tool or function that you have selected or
Highlighted.
• Launch the ISE Help Contents from the Help menu. It contains information about
7
creating and maintaining your complete design flow in ISE.
Fig 4.1: ISE Help Topics
Create a New Project
Create a new ISE project which will target the FPGA device on the Spartan-3e Startup Kit demo
board.
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is
created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
8
♦ Product Category: All
♦ Family: Spartan3E
♦ Device: XC3S500E
♦ Package: FG320
♦ Speed Grade: -4
♦ Top-Level Module Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:
Fig 4.2: Project Device Properties
9
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the
end of the next section, your new project will be complete.
Create a Verilog HDL Source
In this section, I will create the a example top-level Verilog HDL file
Creating a Verilog Source
Create the top-level Verilog source file as follows:
1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name counter.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown
below:
10
Fig 4.3: Define Module
7. Click Next, then Finish in the New Source Information dialog box to complete the new source
file template.
8. Click Next, then Next, then Finish.
The source file containing the counter module displays in the Workspace, and the counter
displays in the Sources tab, as shown below:
Fig 4.4: New Project in ISE
Using Language Templates (Verilog)
The next step in creating the new source is to add the behavioral description for counter.
Use a simple counter code example from the ISE Language Templates and customize it for the
counter design.
1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
2. Open the Language Templates by selecting Edit → Language Templates…
11
Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.
3. Using the ―+‖ symbol, browse to the following code example:
Verilog → Synthesis Constructs → Coding Examples → Counter → Binary →
Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in File
toolbar button. This step copies the template into the counter source file.
5. Close the Language Templates.
Final Editing of the Verilog Source
1. To declare and initialize the register that stores the counter value, modify the
declaration statement in the first line of the template as follows:
replace: reg [<upper>:0] <reg_name>;
with: reg [3:0] count_int = 0;
2. Customize the template for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
♦ replace all occurrences of <clock> with CLOCK
♦ replace all occurrences of <up_down> with DIRECTION
♦ replace all occurrences of <reg_name> with count_int
3. Add the following line just above the endmodule statement to assign the register value to the
output port:
assign COUNT_OUT = count_int;
12
4. Save the file by selecting File → Save.
When you are finished, the code for the counter will look like the following:
module counter(CLOCK, DIRECTION, COUNT_OUT);
input CLOCK;
input DIRECTION;
output [3:0] COUNT_OUT;
reg [3:0] count_int = 0;
always @(posedge CLOCK)
if (DIRECTION)
count_int <= count_int + 1;
else
count_int <= count_int - 1;
assign COUNT_OUT = count_int;
endmodule
You have now created the Verilog source for the tutorial project.
Checking the Syntax of the New Counter Module
When the source files are complete, check the syntax of the design to find errors and typos.
1. Verify that Synthesis/Implementation is selected from the drop-down list in the
Sources window.
2. Select the counter design source in the Sources window to display the related
13
processes in the Processes window.
3. Click the ―+” next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in the
Console tab of the Transcript window. If you continue without valid syntax, you will not be able
to simulate or synthesize your design.
5. Close the HDL file.
Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
1.
Select
the
2. Create a new
counter HDL file in the Sources window.
test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Verilog test fixture as the source type, and type
counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform with the
source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays the
source directory, type and name. Click Finish.
14
15
16
Fig 4.5: Test Bench Waveform
7. Save the waveform.
8. Close the test bench waveform
17
ROUTER
INTRODUCTION
A router is a device that forwards data packets across computer networks. Routers
perform the data "traffic direction" functions on the Internet. A router is a microprocessorcontrolled device that is connected to two or more data lines from different networks. When a
data packet comes in on one of the lines, the router reads the address information in the packet to
determine its ultimate destination. Then, using information in its routing table, it directs the
packet to the next network on its journey. A data packet is typically passed from router to router
through the networks of the Internet until it gets to its destination computer. Routers also perform
other tasks such as translating the data transmission protocol of the packet to the appropriate
protocol of the next network.
The most familiar type of routers are home and small office routers that simply pass data,
such as web pages and email, between the home computers and the owner's cable or DSL
modem, which connects to the Internet (ISP) However more sophisticated routers range from
enterprise routers, which connect large business or ISP networks up to the powerful core routers
that forward data at high speed along the optical fiber lines of the Internet backbone.
Applications of Router
When multiple routers are used in interconnected networks, the routers exchange information
about destination addresses, using a dynamic routing protocol. Each router builds up a table
listing the preferred routes between any two systems on the interconnected networks. A router
has interfaces for different physical types of network connections, (such as copper cables, fiber
optic, or wireless transmission). It also contains firmware for different networking protocol
standards. Each network interface uses this specialized computer software to enable data packets
to be forwarded from one protocol transmission system to another.
18
Routers may also be used to connect two or more logical groups of computer devices
known as subnets, each with a different sub-network address. The subnets addresses recorded in
the router do not necessarily map directly to the physical interface connections.
A router has two stages of operation called planes:
1) Control plan
2) Forwarding plane
Control plane: A router records a routing table listing what route should be used to forward a
data packet, and through which physical interface connection. It does these using internal preconfigured addresses, called static routes.
A typical home or small office router showing the ADSL telephone line and ETHERNET
network cable connections.
Forwarding plane: The router forwards data packets between incoming and outgoing interface
connections. It routes it to the correct network type using information that the packet header
contains. It uses data recorded in the routing table control plane.
Routers may provide connectivity within enterprises, between enterprises and the
Internet, and between internet service providers (ISPs) networks. The largest routers (such as the
Cisco CRS-1 or Juniper T1600) interconnect the various ISPs, or may be used in large enterprise
networks.Smaller routers usually provide connectivity for typical home and office networks.
Other networking solutions may be provided by a backbone Wireless Distribution System
(WDS), which avoids the costs of introducing networking cables into buildings.
All sizes of routers may be found inside enterprises. The most powerful routers are
usually found in ISPs, academic and research facilities. Large businesses may also need more
powerful routers to cope with ever increasing demands of intranet data traffic. A three-layer
model is in common use, not all of which need be present in smaller networks.
Access routers
Linksys by Cisco WRT54GL SoHo Router
19
A screenshot of the LuCI web interface used by OpenWrt. Here it is being used to configure
Dynamic DNS.
Access routers, including 'small office/home office' (SOHO) models, are located at
customer sites such as branch offices that do not need hierarchical routing of their own.
Typically, they are optimized for low cost. Some SOHO routers are capable of running
alternative free Linux-based firmware‘s like Tomato, OpenWrt or DD-WRT.
Distribution
Distribution routers aggregate traffic from multiple access routers, either at the same site,
or to collect the data streams from multiple sites to a major enterprise location. Distribution
routers are often responsible for enforcing quality of service across a WAN, so they may have
considerable memory installed, multiple WAN interface connections, and substantial onboard
data processing routines. They may also provide connectivity to groups of file servers or other
external networks.
Security
External networks must be carefully considered as part of the overall security strategy.
Separate from the router may be a firewall or VPN handling device, or the router may include
these and other security functions. Many companies produced security-oriented routers,
including Cisco Systems' PIX and ASA5500 series, Juniper's Netscreen, Watchguard's Firebox,
Barracuda's variety of mail-oriented devices, and many others.
In enterprises, a core router may provide a "collapsed backbone" interconnecting the
distribution tier routers from multiple buildings of a campus, or large enterprise locations. They
tend to be optimized for high bandwidth.[8]
Routers for Internet connectivity and internal use
Routers intended for ISP and major enterprise connectivity usually exchange routing
information using the Border Gateway Protocol (BGP). RFC 4098[9] standard defines the types
of BGP-protocol routers according to the routers' functions:
Edge router: Also called a Provider Edge router, is placed at the edge of an ISP network. The
router uses External BGP to EBGP protocol routers in other ISPs, or a large enterprise
Autonomous System.
20
Subscriber edge router: Also called a Customer Edge router, is located at the edge of the
subscriber's network, it also uses EBGP protocol to its provider's Autonomous System. It is
typically used in an (enterprise) organization.
Inter-provider border router: Interconnecting ISPs, is a BGP-protocol router that maintains
BGP sessions with other BGP protocol routers in ISP Autonomous Systems.
Core router: A core router resides within an Autonomous System as a back bone to carry
traffic between edge routers.
Within an ISP: In the ISPs Autonomous System, a router uses internal BGP protocol to
communicate with other ISP edge routers, other intranet core routers, or the ISPs intranet
provider border routers.
"Internet backbone:" The Internet no longer has a clearly identifiable backbone, unlike its
predecessor networks. See default-free zone (DFZ). The major ISPs system routers make up
what could be considered to be the current Internet backbone core.[11] ISPs operate all four
types of the BGP-protocol routers described here. An ISP "core" router is used to interconnect its
edge and border routers. Core routers may also have specialized functions in virtual private
networks based on a combination of BGP and Multi-Protocol Label Switching protocols.
Port forwarding: Routers are also used for port forwarding between private internet
connected servers.
Voice/Data/Fax/Video Processing Routers: Commonly referred to as access servers or
gateways, these devices are used to route and process voice, data, video, and fax traffic on the
internet. Since 2005, most long-distance phone calls have been processed as IP traffic (VOIP)
through a voice gateway,. Voice traffic that the traditional cable networks once carried. Use of
access server type routers expanded with the advent of the internet, first with dial-up access, and
another resurgence with voice phone service.
Historical and technical information
The very first device that had fundamentally the same functionality as a router does
today, was the Interface Message Processor (IMP); IMPs were the devices that made up the
ARPANET, the first packet network. The idea for a router (called "gateways" at the time)
21
initially came about through an international group of computer networking researchers called
the International Network Working Group (INWG). Set up in 1972 as an informal group to
consider the technical issues involved in connecting different networks, later that year it became
a subcommittee of the International Federation for Information Processing.
These devices were different from most previous packet networks in two ways. First,
they connected dissimilar kinds of networks, such as serial lines and local area networks.
Second, they were connectionless devices, which had no role in assuring that traffic was
delivered reliably, leaving that entirely to the hosts (this particular idea had been previously
pioneered in the CYCLADES network).
The idea was explored in more detail, with the intention to produce a prototype system,
as part of two contemporaneous programs. One was the initial DARPA-initiated program, which
created the TCP/IP architecture in use today. The other was a program at Xerox PARC to
explore new networking technologies, which produced the PARC Universal Packet system, due
to corporate intellectual property concerns it received little attention outside Xerox for years.
Sometime after early 1974 the first Xerox routers became operational. The first true IP
router was developed by Virginia Strazisar at BBN, as part of that DARPA-initiated effort,
during 1975-1976. By the end of 1976, three PDP-11-based routers were in service in the
experimental prototype Internet.
The first multiprotocol routers were independently created by staff researchers at MIT
and Stanford in 1981; the Stanford router was done by William Yeager, and the MIT one by
Noel Chiappa; both were also based on PDP-11s.
Virtually all networking now uses TCP/IP, but multiprotocol routers are still
manufactured. They were important in the early stages of the growth of computer networking,
when protocols other than TCP/IP were in use. Modern Internet routers that handle both IPv4
and IPv6 are multiprotocol, but are simpler devices than routers processing AppleTalk, DECnet,
IP, and Xerox protocols.
From the mid-1970s and in the 1980s, general-purpose mini-computers served as routers.
Modern high-speed routers are highly specialized computers with extra hardware added to speed
22
both common routing functions, such as packet forwarding, and specialised functions such as
IPsec encryption.
There is substantial use of Linux and Unix software based machines, running open source
routing code, for research and other applications.
Cisco's operating system was independently designed. Major router operating systems,
such as those from Juniper Networks and Extreme Networks, are extensively modified versions
of Unix software.
Why Would I Need a Router?
For most home users, they may want to set-up a LAN (local Area Network) or
WLAN (wireless LAN) and connect all computers to the Internet without having to pay a full
broadband subscription service to their ISP for each computer on the network. In many instances,
an ISP will allow you to use a router and connect multiple computers to a single Internet
connection and pay a nominal fee for each additional computer sharing the connection. This is
when home users will want to look at smaller routers, often called broadband routers that enable
two or more computers to share an Internet connection. Within a business or organization, you
may need to connect multiple computers to the Internet, but also want to connect multiple private
networks
Not all routers are created equal since their job will differ slightly from network to network.
Additionally, you may look at a piece of hardware and not even realize it is a router. What
defines a router is not its shape, color, size or manufacturer, but its job function of routing data
packets between computers. A cable modem which routes data between your PC and your ISP
can be considered a router. In its most basic form, a router could simply be one of two computers
running the Windows 98 (or higher) operating system connected together using ICS (Internet
Connection Sharing). In this scenario, the computer that is connected to the Internet is acting as
the router for the second computer to obtain its Internet connection.
Going a step up from ICS, we have a category of hardware routers that are used to perform the
same basic task as ICS, albeit with more features and functions. Often called broadband or
Internet connection sharing routers, these routers allow you to share one Internet connection ple
23
computers.
Broadband or ICS routers will look a bit different depending on the manufacturer or brand, but
wired routers are generally a small box-shaped hardware device with ports on the front or back
into which you plug each computer, along with a port to plug in your broadband modem. These
connection ports allow the router to do its job of routing the data packets between each of the the
computers and the data going to and from the Internet.
Depending on the type of modem and Internet connection you have, you could also choose a
router with phone or fax machine ports. A wired Ethernet broadband router will typically have a
built-in Ethernet switch to allow for expansion. These routers also support NAT (network
address translation), which allows all of your computers to share a single IP address on the
Internet. Internet connection sharing routers will also provide users with much needed features
such as an SPI firewall or serve as a a DHCP Server.
Wired and Wireless Routers
Wireless broadband routers look much the same as a wired router, with the obvious exception of
the antenna on top, and the lack of cable running from the PCs to the router when it is all set up.
Creating a wireless network adds a bit more security concerns as opposed to wired networks, but
wireless broadband routers do have extra levels of embedded security.
Along with the features found in wired routers, wireless routers also provide features relevant to
wireless security such as Wi-Fi Protected Access (WPA) and wireless MAC address filtering.
Additionally, most wireless routers can be configured for "invisible mode" so that your wireless
network cannot be scanned by outside wireless clients. Wireless routers will often include ports
for Ethernet connections as well. For those unfamiliar with WiFi and how it works, it is
important to note that choosing a wireless router may mean you need to beef up your Wi-Fi
knowledge-base. After a wireless network is established, you may possibly need to spend more
time on monitoring and security than one would with a wired LAN.
24
Wired and wireless routers and the resulting network can claim pros and cons over each other,
but they are somewhat equal overall in terms of function and performance. Both wired and
wireless routers have high reliability and reasonably good security (without adding additional
products). However —and this bears repeating — as we mentioned you may need to invest time
in learning more about wireless security. Generally, going wired will be cheaper overall, but
setting up the router and cabling in the computers is a bit more difficult than setting up the
wireless network. Of course, mobility on a wired system is very limited while wireless offers
outstanding mobility features.
Are Routers Expensive?
Below is a sample price comparison of routers and expected features as well as current pricing in
U.S. dollars from online vendors found through PriceWatch in August 2009.
ROUTER
PORTS
Manufacturer Description / Features PRICE
NetGear WGR614 Wireless Cable/DSL Router
4
802.11g router offers wired and
wireless connections. Up to 54 Mbps of wireless throughput. Four RJ-45 Ethernet ports allow for
wired connections to the network. Includes a double firewall, WPA and 128-bit WEP encryption
$25
Linksys WRT110-RM Draft-N 802.11N Wireless Broadband Router
4
Internet-
sharing Router with 4-port switch and Wireless Access Point. Much faster than Wireless-G when
connected to Wireless-N, but also works great with Wireless-G and -B devices
Linksys EtherFast BEFSR81 Broadband Router
8
$30
Simply connect the Linksys BEF-
SR81 Wireless Router 8 Port 10/100 Switch to your DSL or Cable Modem and all the computers
in your home or office can share the Internet all at the same time. $80
D Link Systems NetDefend VPN Firewall
8
D-Link answers the need for a Broadband
VPN Router. The DIR-130 is a simple-to-deploy routing VPN and firewall solution designed
specifically for the Small Office / Home Office
$90
Today you can purchase a basic sub $90 broadband router that will enable you to share your
broadband Internet connection with multiple computers in your home or small office. Before
25
buying a router, however, you need to take into consideration the type of Internet connect you
have, and how many ports you will need for individual computers, and of course, make the
choice between wired or wireless. It is always a good idea to purchase a router with extra ports in
case you need to connect additional computers at a later date.
Forwarding plane:
For pure Internet Protocol (IP) forwarding function, a router is designed to minimize the
state information on individual packets. The main purpose of a router is to connect multiple
networks and forward packets destined either for its own networks or other networks. A router is
considered a Layer 3 device because its primary forwarding decision is based on the information
in the Layer 3 IP packet, specifically the destination IP address. This process is known as
routing. When each router receives a packet, it searches its routing table to find the best match
between the destination IP address of the packet and one of the network addresses in the routing
table. Once a match is found, the packet is encapsulated in the layer 2 data link frame for that
outgoing interface. A router does not look into the actual data contents that the packet carries, but
only at the layer 3 addresses to make a forwarding decision, plus optionally other information in
the header for hint on, for example, QoS. Once a packet is forwarded, the router does not retain
any historical information about the packet, but the forwarding action can be collected into the
statistical data, if so configured.
Forwarding decisions can involve decisions at layers other than the IP internetwork layer
or OSI layer 3. A function that forwards based on data link layer, or OSI layer 2, information, is
properly called a bridge or switch. This function is referred to as layer 2 switching, as the
addresses it uses to forward the traffic are layer 2 addresses in the OSI layer model.
Besides making decision as which interface a packet is forwarded to, which is handled
primarily via the routing table, a router also has to manage congestion, when packets arrive at a
rate higher than the router can process. Three policies commonly used in the Internet are tail
drop, random early detection, and weighted random early detection. Tail drop is the simplest and
most easily implemented;
26
the router simply drops packets once the length of the queue exceeds the size of the
buffers in the router. Random early detection (RED) probabilistically drops datagrams early
when the queue is exceeds a pre-configured size of the queue until a pre-configured max when it
becomes tail drop.
Weighted random early detection requires a weight on the average queue size to act upon
when the traffic is about to exceed the pre-configured size, so that short bursts will not trigger
random drops.
Another function a router performs is to decide which packet should be processed first
when multiple queues exist. This is managed through Quality of service (QoS), which is critical
when VoIP (Voice over IP) is deployed, so that delays between packets do not exceed 150ms to
maintain the quality of voice conversations.
Yet another function a router performs is called "policy based routing" where special
rules are constructed to override the rules derived from the routing table when a packet
forwarding decision is made.
These functions may be performed through the same internal paths that the packets travel
inside the router. Some of the functions may be performed through an application-specific
integrated circuit (ASIC) to avoid overhead caused by multiple CPU cycles, and others may have
to be performed through the CPU as these packets need special attention that cannot be handled
by an ASIC.
Router 1x3 Design
Router is a packet based protocol. Router drives the incoming packet which comes
from the input port to output ports based on the address contained in the packet.
The router has a one input port from which the packet enters. It has three output ports
where the packet is driven out. The router has an active low synchronous input resetn which
resets the router.
27
8
data
8
data_out_0
vld_out_0
read_enb_0
packet_valid
suspend_data
err
8
clock
reset
n
8
Router_1X3
data_out_1
vld_out_1
read_enb_1
data_out_2
vld_out_2
read_enb_2
Figure - Block Diagram of Router_1X3
Packet Format:
Packet contains 3 parts. They are Header, payload and parity.
Packet width is 8 bits and the length of the packet can be between 1 bytes to 63 bytes.
7 6
5 4 3 2 1 0
Length
data[0]
addr
byte 0
Header
byte 1
data[1]
Payload
data[N]
byte N+1
parity
byte N+2
Parity
Figure - Data Packet Format
Packet - Header:
Packet header contains two fields DA and length.
DA: Destination address of the packet is of 2 bits. The router drives the packet to respective ports
based on this destination address of the packets. Each output port has 2-bit unique port
address. If the destination address of the packet matches the port address, then router drives the
28
packet to the output port. The address ―3‖ is invalid.
Length: Length of the data is of 6 bits and from 1 to 63. It specifies the number of data
bytes.A packet can have a minimum data size of 1 byte and a maximum size of 63 bytes.
If Length = 1, it means data length is 1 bytes
If
If
Length
Length
=
=
2,
63,
it
it
means
means
data
data
length
length
bytes
and
is
is
2
63
bytes
bytes
Packet - Payload:
Data:
Data
should
be
in
terms
of
can
take
anything.
Packet - Parity:
Parity: This field contains the security check of the packet. It should be a byte of even, bitwise
parity, calculated over the header and data bytes of the packet.
Router Input Protocol:
clock
delay
reset
packet_valid
data
H
D
D
D
P
H
D
D
Suspend_data
err
sent packet
Packet 1 (addr = 0)
Packet 1 (addr =
0)
H = Header, D = Data, P = Parity
The characteristics of the DUV input protocol are as follows:
29
D
P
1 All input signals are active high and are synchronized to the falling edge of the clock.
This is because the DUV router is sensitive to the rising edge of clock. Therefore, driving
input signals on the falling edge ensures adequate setup and hold time, but the signals can
also be driven on the rising edge of the clock.
2 The packet_valid signal has to be asserted on the same clock as when the first byte of a
packet (the header byte), is driven onto the data bus.
3 Since the header byte contains the address, this tells the router to which output channel
the packet should be routed (data_out_0, data_out_1, or data_out_2).
4 Each subsequent byte of data should be driven on the data bus with each new
rising/falling clock.
5 After the last payload byte has been driven, on the next rising/falling clock, the
packet_valid signal must be deasserted , and the packet parity byte should be driven. This
signals packet completion.
6 The input data bus value cannot change while the suspend_data signal is active
(indicating a FIFO overflow). The packet driver should not send any more bytes and
should hold the value on the data bus. The width of suspend_data signal assertion should
not exceed 100 cycles.
The err signal asserts when a packet with bad parity is detected in the router, within 1 to 10
cycles of packet completion.
Router Output Protocol:
30
clock
reset
packet_valid
data
H
D
D
D
P
H
D
D
D
P
vld_out_0
response delay
read_enb
_0
data_out_0
received
H
D
D
D
P
Packet 1 (addr = 0)
packet
The characteristics of the output protocol are as follows:
1
2
3
4
5
6
7
8
All output signals are active high and can be synchronized to the rising/falling edge of the clock. Thus,
the packet receiver will drive sample data at the rising/falling edge of the clock. The router will drive
and sample data at the rising edge of clock.
Each output port data_out_X (data_out_0, data_out_1, data_out_2) is internally buffered by a FIFO of
1 byte width and 16 location depth.
The router asserts the vld_out_X (vlld_out_0, vld_out_1 or vld_out_2) signal when valid data appears
on the vld_out_X (data_out_0, data_out_1 or data_out_2) output bus. This is a signal to the packet
receiver that valid data is available on a particular router.
The packet receiver will then wait until it has enough space to hold the bytes of the packet and then
respond with the assertion of the read_enb_X (read_enb_0, read_enb1 or read_enb_2) signal that is an
input to the router.
The read_enb_X (read_enb0, read_enb_1 or read_enb_2) input signal can be asserted on the
rising/falling clock edge in which data are read from the data_out_X (data_out_0, data_out_1 or
data_out_2) bus.
As long as the read_enb_X (read_enb_0, read_enb_1 or read_enb_2) signal remains active, the
data_out_X (data_out_0, data_out_1 or data_out_2) bus drives a valid packet byte on each rising
clock edge.
The packet receiver cannot request the router to suspend data transmission in the middle of the packet.
Therefore, the packet receiver must assert the read_enb_X (read_enb_0, read_enb_1 or read_enb_2)
signal only after it ensures that there is adequate space to hold the entire packet.
The read_enb_X (read_enb_0, read_enb_1 or read_enb_2) must be asserted within 30 clock cycles of
the vld_out_X (vld_out_0, vld_out_1 or vld_out_2) being asserted. Otherwise, there is too much
congestion in the packet receiver.
31
9
The DUV data_out_X (data_out_0, data_out_1 or data_out_2) bus must not be tri-stated (high Z)
when the DUV signal vld_out_X (vld_out_0, vld_out_1or vld_out_2) is asserted (high) and the input
signal read_enb_X (read_enb_0, read_enb_1 or read_enb_2) is also asserted high.
32
ROUTER_1X3 ARCHITECTURE:
33






This design consists of 6 main blocks. Which are fsm_router, router_reg, ff_sync, and 3
fifo.
The fsm_router block provides the control signals to the fifo, and router_reg module.
The router_reg module contains the status, data and parity registers for the router_1x3.
These registers are latched to new status or input data through the control signals
provided by the fsm_router.
There are 3 fifo for each output port, which stores the data coming from input port based
on the control signals provided by fsm_router module.
The ff_sync module provides synchronization between fsm_router module and 3 fifo s ,
So that single input port can faithfully communicate with 3 output ports.
1. FIFO BLOCK
There are 3 fifos used in the router design. Each fifo is of 8 bit width and 16 bit depth.
The fifo works on system clock. It has synchronous input signal reset.
If resetn is low then full =0, empty = 1 and data_out = 0
Write operation:
The data from input data_in is sampled at rising edge of the clock when input write_enb is high
and fifo is not full.
Read Operation:
The data is read from output data_out at rising edge of the clock, when read_enb is high and
fifo is not empty.
34
Read and Write operation can be done simultaneously.
Full – it indicates that all the locations inside fifo has been written.
Empty – it indicates that all the locations of fifo are empty.
2. FF_SYNC BLOCK
This module provides synchronization between fsm and fifo modules. It provides faithful
communication between single input port and three output ports.
It will detect the address of channel and will latch it till packet_valid is asserted, address and
write_enb_sel will be used for latching the incoming data into the fifo of that particular channel.
A fifo_full output signal is generated, when the present fifo is full, and fifo_empty output
signal is generated by the present fifo when it is empty.
If data = 00 then fifo_empty = empty_0 and fifo_full = full_0
If data = 01 then fifo_empty = empty_1 and fifo_full = full_1
If data = 10 then fifo_empty = empty_2 and fifo_full = full_2
Else fifo_empty = 0 and fifo_full = 1.
35
The output vld_out signal is generated when empty of present fifo goes low, that means
present fifo is ready to read.
vld_out_0 = ~empty_0
vld_out_1 = ~empty_1
vld_out_2 = ~empty_2
The write_enb_reg signal which comes from the fsm is used to generate write_enb signal for
the present fifo which is selected by present address.
3. ROUTER_REG BLOCK
This module contains status, data and parity registers required by router.
All the registers in this module are latched on rising edge of the clock.
Data registers latches the data from data input based on state and status control signals, and this
latched data is sent to the fifo for storage. Apart from it, data is also latched into the parity registers
for parity calculation and it is compared with the parity byte of the packet. An error signal is
generated if packet parity is not equal to the calculated parity.
If resetn is low then output (dout, err, parity_done and low_packet_valid) are low.
36
The output parity_done is high


when the input ld_state is high and (fifo-full and packet_valid) is low
or when the input laf_state and output low_packet_valid both are high and the
previous value of parity_done is low. It is reseted to low value by reset_int_reg
signal.
The output low_packet_valid is high


when the input ld_state is high and packet_valid is low.
It is reseted to low by reset_int_reg signal.
First data byte i.e., header is latched inside the internal register first_byte when detect_add and
packet_valid signals are high, So that it can be latched to output dout when lfd_state signal goes
high.
Then the input data i.e., payload is latched to output dout if ld_state signal is high and fifo_full
is low.
Then the input data i.e., parity is latched to output dout if lp_state signal is high and fifo_full is
low.
The input data is latched to internal register full_state_byte when ld_state and fifo_full are
high; this full_state_byte data is latched inside the output dout when laf_state goes high.
Internal parity register stores the parity calculated for packet data, when packet is transmitted
fully, the internal calculated parity is compared with parity byte of the packet. An error signal is
generated if packet parity is not equal to the calculated parity.
37
4. f SM BLOCK
suspend_data
clock
write_enb_reg
resetn
detect_add
packet_valid
data
ld_state
8
lp_state
fifo_full
laf_state
fifo_empty
lfd_state
parity_done
low_packet_valid
full_state
fsm_router
reset_int_reg
The ‗fsm_router‘ module is the controller circuit for the router.
This module generates all the control signals when new packet is sent to router. These control
signals are used by other modules to send data at output, writing data into the fifo.
38
FSM State Diagram:
39
Functionality:
STATE - DECODE_ADDRESS
This is the default state. It waits for the packet_valid assertion, After packet_valid signal goes
high, if the address is valid and fifo for that address is empty (fifo_empty signal will be high), data
can be loaded, so, it goes to the next state LOAD_FIRST_DATA.
If fifo is not empty it goes to WAIT_TILL_EMPTY so that, new data couldn‘t be accepted till
fifo is ready.
The output signal detect_add is made high, so that ff_sync module can detect the address of
fifo to be used. detect_add signal is also used by router_reg module to latch the first byte in internal
register.
STATE - LOAD_FIRST_DATA
In this state lfd_state signal is generated, which indicates to the router_reg module that first
data byte can be latched.
At the same time suspend_data signal is made high so that first data byte can be faithfully
latched inside the output data register in router_reg module. In the next clock edge unconditionally
this state is changed to LOAD_DATA.
STATE - LOAD_DATA
In this state data is latched inside the data registers of router_reg module, for this ld_state
signal is generated for router_reg module. suspend_data signal is made low, so that router can
accept the new data from input simultaneously, latched data is sent to the fifo and
write_enb_reg is generated for writing into present fifo.
If fifo_full input goes high then no more data can be accepted by router so it goes to
FIFO_FULL_STATE.
Data is latched till the packet_valid signal is asserted, when it is de-asserted in LOAD_DATA
state, it goes to LOAD_PARITY state, where last parity byte is latched.
40
STATE – LOAD_PARITY
In this state last byte is latched which is parity byte. If fifo_full is high, data cannot be latched,
so, it goes to FIFO_FULL_STATE else if fifo_full is low, it goes to state
CHECK_PARITY_ERROR.
Signal lp_state is generated for router_reg module. suspend_data signal is made high so that
now router don‘t accepts any new data. write_enb_reg is made high for latching the last byte.
lp_state signal is generated for the router_reg module, so that last byte can be latched and the parity
bytes can be compared.
STATE – FIFO_FULL_STATE
In this state neither new data is accepted nor any data is latched. So suspend_data signal is
made high and write_enb_reg signal is made low.
Signal full_state is generated
for router_reg
LOAD_AFTER_FULL state when fifo_full becomes low.
module.
This
state
changes
to
STATE – LOAD_AFTER_FULL
In this state laf_state signal is generated for router_reg so that it can latch the data after
FIFO_FULL_STATE, no new data is accepted so suspend_data is kept high, last data is latched in
router_reg module for that write_enb_reg is made high.
It checks for parity_done register which if high shows that LOAD_PARITY state has passed,
if parity_done is high it goes to the last state CHECK_PARITY_ERROR.
Then it checks for low_packet_valid register, which if high shows that packet_valid for present
packet has been deasserted, if low_packet_valid is high it goes to LOAD_PARITY state otherwise it
goes back to the LOAD_DATA state.
STATE – WAIT_TILL_EMPTY
In this state neither new data is accepted nor data is latched by router_reg module, So
suspend_data signal is made high and write_enb_reg signal is made low. It waits for the fifo_empty
signal, when it goes high, it goes to the LOAD_FIRST_DATA state.
41
STATE – CHECK_PARITY_ERROR
In this state reset_int_reg signal is generated, which resets the status and parity registers inside
the router_reg module. Neither any data is latched nor any input data is accepted. Router_reg
compares the data parity from packet with calculated parity during this state.
This state changes to default state DECODE_ADDRESS with next clock edge.
42
CODE:
module router_fsm(clk,
resetn,
packet_valid,
data_in,
fifo_full1,
fifo_full2,
fifo_full3,
fifo_empty1,
fifo_empty2,
fifo_empty3,
suspend_data,
valid_chanel1,
valid_chanel2,
valid_chanel3,
we1,
we2,
we3,
data_out1,
data_out2,
data_out3,
err);
input clk,
resetn,
packet_valid,
fifo_full1,
fifo_full2,
fifo_full3,
fifo_empty1,
fifo_empty2,
fifo_empty3;
input [7:0] data_in;
output reg suspend_data,
err,
we1,
we2,
43
we3;
output
valid_chanel1,
valid_chanel2,
valid_chanel3;
output reg[7:0] data_out1,data_out2,data_out3;
reg [3:0] pre_state,next_state;
reg [7:0] parity1, parity2, parity3;
reg [7:0] parity;
parameter
dec_add = 4'b0000,
wt_till_emp = 4'b0001,
load_data0 = 4'b0010,
load_data1 = 4'b0011,
load_data2 = 4'b0100,
fifo_ful0 = 4'b0101,
fifo_ful1 = 4'b0110,
fifo_ful2 = 4'b0111,
ld_parity0 = 4'b1000,
ld_parity1 = 4'b1001,
ld_parity2 = 4'b1010,
chk_parity0 = 4'b1011,
chk_parity1 = 4'b1100,
chk_parity2 = 4'b1101;
// logic for present
always @ (posedge clk
begin
if (!resetn)
begin
pre_state
end
else
pre_state
end
state
or negedge resetn)
<= dec_add;
<= next_state;
// logic for next state
always @(*)
begin
case(pre_state)
44
dec_add : begin
if
((packet_valid
(fifo_empty1==1))
==
1)
&&
(data_in[1:0]==0)
&&
begin
next_state <= load_data0;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else if ((packet_valid
(fifo_empty2==1))
==
1)
&&
(data_in[1:0]==1)
next_state
parity1 <=
parity2 <=
parity3 <=
end
else if ((packet_valid
(fifo_empty3==1))
else if ((packet_valid
(fifo_empty1==0))
else if ((packet_valid
(fifo_empty2==0))
==
1)
&&
&&
begin
<= load_data1;
0;
0;
0;
(data_in[1:0]==2)
&&
begin
next_state <= load_data2;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
== 1) && (data_in[1:0]==0)
&&
begin
next_state <= wt_till_emp;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
== 1) && (data_in[1:0]==1)
&&
next_state
parity1 <=
parity2 <=
parity3 <=
45
begin
<= wt_till_emp;
0;
0;
0;
end
else if ((packet_valid
(fifo_empty3==0))
==
1)
&&
(data_in[1:0]==2)
next_state
parity1 <=
parity2 <=
parity3 <=
&&
begin
<= wt_till_emp;
0;
0;
0;
end
else
begin
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
next_state <= dec_add;
end
end
wt_till_emp : begin
if
((packet_valid
(fifo_empty1== 1))
==
1)
&&
(data_in[1:0]==0)
next_state
parity1 <=
parity2 <=
parity3 <=
else if ((packet_valid
(fifo_empty2==1))
else if ((packet_valid
(fifo_empty3==1))
==
1)
&&
&&
begin
<= load_data0;
0;
0;
0;
end
(data_in[1:0]==1) &&
begin
next_state <= load_data1;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
== 1) && (data_in[1:0]==2)
&&
begin
next_state <= load_data2;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
46
else
begin
parity1
parity2
parity3
next_state <=
<= 0;
<= 0;
<= 0;
wt_till_emp;
end
end
load_data0 : begin
if ((fifo_full1 == 1) && (packet_valid == 1))
begin
next_state <=
parity1
parity2
parity3
fifo_ful0;
<= 0;
<= 0;
<= 0;
end
else if ((packet_valid == 0) && (fifo_full1 == 0))
begin
next_state <= ld_parity0;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else
begin
parity1 <=
parity2 <=
parity3 <=
next_state
0;
0;
0;
<= load_data0;
end
end
load_data1 : begin
if ((fifo_full2 == 1) && (packet_valid == 1))
begin
next_state <= fifo_ful1;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
47
else if ((packet_valid == 0) && (fifo_full2 == 0))
begin
next_state <= ld_parity1;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else
parity1 <=
parity2 <=
parity3 <=
next_state
end
end
begin
0;
0;
0;
<= load_data1;
load_data2 : begin
if ((fifo_full3 == 1) && (packet_valid == 1))
begin
next_state <= fifo_ful2;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else if ((packet_valid == 0) && (fifo_full3 == 0))
begin
next_state<= ld_parity2;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else
begin
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
next_state <= load_data2;
end
end
fifo_ful0 : begin
48
if ((packet_valid == 1) && (fifo_full1 == 0))
begin
next_state <= load_data0;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else if ((packet_valid == 0) && (fifo_full1 == 0))
begin
next_state <= ld_parity0;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else
parity1 <=
parity2 <=
parity3 <=
next_state
begin
0;
0;
0;
<= fifo_ful0;
end
end
fifo_ful1 : begin
if ((packet_valid == 1) && (fifo_full2 == 0))
begin
next_state <= load_data1;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else if ((packet_valid == 0) && (fifo_full2 == 0))
begin
next_state <= ld_parity1;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else
begin
parity1 <= 0;
parity2 <= 0;
49
parity3 <= 0;
next_state <= fifo_ful1;
end
end
fifo_ful2 : begin
if ((packet_valid == 1) && (fifo_full3 == 0))
begin
next_state <= load_data2;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else if ((packet_valid == 0) && (fifo_full3 == 0))
begin
next_state <= ld_parity2;
parity1 <= 0;
parity2 <= 0;
parity3 <= 0;
end
else
parity1 <=
parity2 <=
parity3 <=
next_state
begin
0;
0;
0;
<= fifo_ful2;
end
end
ld_parity0 : begin
parity1 <= data_in;
parity2 <= 0;
parity3 <= 0;
next_state <= chk_parity0;
end
ld_parity1 : begin
parity1 <= 0;
parity2 <= data_in;
parity3 <= 0;
next_state <= chk_parity1;
end
50
ld_parity2 : begin
parity1 <=
parity2 <=
parity3 <=
next_state
0;
0;
data_in;
<= chk_parity2;
end
chk_parity0 : begin
next_state <= dec_add;
end
chk_parity1 : begin
next_state <= dec_add;
end
chk_parity2 : begin
next_state <= dec_add;
end
endcase
end
//output logic
always @ (*)
begin
if (!resetn)
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else if ((pre_state == dec_add) && (data_in[1:0] == 0))
begin
suspend_data <= 0;
data_out1 <= data_in;
data_out2 <= 0;
data_out3 <= 0;
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err
we1
we2
we3
<=
<=
<=
<=
0;
1;
0;
0;
end
else if ((pre_state == dec_add) && (data_in[1:0] == 1))
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= data_in;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 1;
we3 <= 0;
end
else if ((pre_state == dec_add) && (data_in[1:0] == 2))
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= data_in;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 1;
end
else if (pre_state == dec_add)
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
52
else if (pre_state == wt_till_emp)
begin
suspend_data <= 1;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else if (pre_state == fifo_ful0)
begin
suspend_data <= 1;
data_out1 <= data_out1;
data_out2 <= data_out2;
data_out3 <= data_out3;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else if (pre_state == fifo_ful1)
begin
suspend_data <= 1;
data_out1 <= data_out1;
data_out2 <= data_out2;
data_out3 <= data_out3;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else if (pre_state == fifo_ful2)
begin
suspend_data <= 1;
data_out1 <= data_out1;
data_out2 <= data_out2;
data_out3 <= data_out3;
err <= 0;
53
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else if (pre_state ==load_data0)
begin
suspend_data <= 0;
data_out1 <= data_in;
data_out2 <= 0;
data_out3 <= 0;
err <= 0;
we1 <= 1;
we2 <= 0;
we3 <= 0;
end
else if (pre_state ==load_data1)
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= data_in;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 1;
we3 <= 0;
end
else if (pre_state ==load_data2)
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= data_in;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 1;
end
54
else if (pre_state == ld_parity0)
begin
suspend_data <= 0;
data_out1 <= data_in;
data_out2 <= 0;
data_out3 <= 0;
err <= 0;
we1 <= 1;
we2 <= 0;
we3 <= 0;
end
else if (pre_state == ld_parity1)
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= data_in;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 1;
we3 <= 0;
end
else if (pre_state == ld_parity2)
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= data_in;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 1;
end
else if (pre_state == chk_parity0)
begin
suspend_data <= 1;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
55
err
we1
we2
we3
<=
<=
<=
<=
(parity == parity1)?0:1;
0;
0;
0;
end
else if (pre_state == chk_parity1)
begin
suspend_data <= 1;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
err <= (parity == parity2)?0:1;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else if (pre_state == chk_parity2)
begin
suspend_data <= 1;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
err <= (parity == parity3)?0:1;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
else
begin
suspend_data <= 0;
data_out1 <= 0;
data_out2 <= 0;
data_out3 <= 0;
err <= 0;
we1 <= 0;
we2 <= 0;
we3 <= 0;
end
end
56
always @(posedge clk or negedge resetn)
begin
if(!resetn)
parity <= 0;
else if (pre_state == dec_add)
parity <= data_in;
else if (packet_valid && !fifo_full1 && !fifo_full2
&& !fifo_full3 && !suspend_data )
parity <= parity ^ data_in;
end
assign valid_chanel1 = ((~fifo_empty1))?1:0;
assign valid_chanel2 = ((~fifo_empty2))?1:0;
assign valid_chanel3 = ((~fifo_empty3))?1:0;
endmodule
module fifo(clk,
resetn,
data_in,
we,
re,
data_out,
fifo_full,
fifo_empty);
input
clk,
resetn,
we,
re;
input[7:0] data_in;
output[7:0] data_out;
output
fifo_full,
fifo_empty;
reg [3:0] read_pointer,write_pointer;
reg [7:0] data_out;
wire fifo_full;
57
wire fifo_empty;
reg [7:0] mem[15:0];
always@(posedge clk)
begin
if(we && !fifo_full)
mem[write_pointer] <= data_in ;
if(re && !fifo_empty)
data_out <= mem[read_pointer] ;
end
always @ (posedge clk)
begin
if (!resetn)
begin
read_pointer <= 4'b0000;
write_pointer <= 4'b0000;
end
else
begin
if(we && !fifo_full)
begin
if(write_pointer == 15)
write_pointer <= 0;
else
write_pointer <= write_pointer + 1;
end
if(re && !fifo_empty)
begin
if(read_pointer == 15)
read_pointer <= 0;
else
read_pointer<=read_pointer+1;
end
end
end
assign
fifo_full
=
((write_pointer)
==
(read_pointer+4'b1111))?1:0 ;
assign fifo_empty = (write_pointer == read_pointer)?1:0 ;
58
endmodule
module router_top (clk,
resetn,
packet_valid,
re1,
re2,
re3,
data_in,
suspend_data,
err,
valid_chanel1,
valid_chanel2,
valid_chanel3,
ch_out1,
ch_out2,
ch_out3);
input clk,
resetn,
packet_valid,
re1,
re2,
re3;
input [7:0]data_in;
output suspend_data,
err,
valid_chanel1,
valid_chanel2,
valid_chanel3;
output [7:0] ch_out1,
ch_out2,
ch_out3;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
wire [7:0] w10,w11,w12;
router_fsm
fsm1(.clk(clk),
59
.resetn(resetn),
.packet_valid(packet_valid),
.data_in(data_in),
.fifo_full1(w1),
.fifo_full2(w2),
.fifo_full3(w3),
.fifo_empty1(w4),
.fifo_empty2(w5),
.fifo_empty3(w6),
.suspend_data(suspend_data),
.valid_chanel1(valid_chanel1),
.valid_chanel2(valid_chanel2),
.valid_chanel3(valid_chanel3),
.we1(w7),
.we2(w8),
.we3(w9),
.data_out1(w10),
.data_out2(w11),
.data_out3(w12),
.err(err));
fifo f1(.clk(clk),
.resetn(resetn),
.data_in(w10),
.we(w7),
.re(re1),
.data_out(ch_out1),
.fifo_full(w1),
.fifo_empty(w4));
fifo f2(.clk(clk),
.resetn(resetn),
.data_in(w11),
.we(w8),
.re(re2),
.data_out(ch_out2),
.fifo_full(w2),
60
.fifo_empty(w5));
fifo f3(.clk(clk),
.resetn(resetn),
.data_in(w12),
.we(w9),
.re(re3),
.data_out(ch_out3),
.fifo_full(w3),
.fifo_empty(w6));
endmodule
module router_fsm_tb();
reg
clk,
resetn,
packet_valid,
fifo_full1,
fifo_full2,
fifo_full3,
fifo_empty1,
fifo_empty2,
fifo_empty3;
reg [7:0] data_in;
wire suspend_data,
valid_chanel1,
valid_chanel2,
valid_chanel3,
we1,
we2,
we3,
err;
wire [7:0] data_out1,
data_out2,
data_out3;
router_fsm f1(clk,
resetn,
61
packet_valid,
data_in,
fifo_full1,
fifo_full2,
fifo_full3,
fifo_empty1,
fifo_empty2,
fifo_empty3,
suspend_data,
valid_chanel1,
valid_chanel2,
valid_chanel3,
we1,
we2,
we3,
data_out1,
data_out2,
data_out3,
err);
task initialize();
begin
packet_valid = 0;
data_in = 8'b00000000;
fifo_full1 = 0;
fifo_full2 = 0;
fifo_full3 = 0;
fifo_empty1 = 0;
fifo_empty2 = 0;
fifo_empty3 = 0;
end
endtask
task reset();
begin
resetn=1'b0;
#10 resetn =~resetn;
end
endtask
task fifo_full(input i,j,k);
begin
62
fifo_full1 = i;
fifo_full2 = j;
fifo_full3 = k;
end
endtask
task fifo_empty (input m,n,o);
begin
fifo_empty1 = m;
fifo_empty2 = n;
fifo_empty3 = o;
end
endtask
initial
clk=1'b0;
always
# 5 clk= ~clk;
initial
begin
reset;
@(negedge clk);
//initialize;
packet_valid = 1'b1;
fifo_full (0,0,0);
fifo_empty (1,1,1);
wait(!suspend_data);
@(negedge clk);
data_in = 8'b00001000;
#10;
wait(!suspend_data);
@(negedge clk);
data_in = 8'b00101010;
#10;
wait(!suspend_data);
fifo_empty (0,1,1);
@(negedge clk);
data_in = 8'b01001010;
#10;
fifo_full (1,1,1);
63
#30;
fifo_full (0,0,0);
wait(!suspend_data);
@(negedge clk);
data_in = 8'b10001010;
#10;
packet_valid = 1'b0;
wait(!suspend_data);
@(negedge clk);
data_in = 8'b11100010;
@(negedge clk);
@(negedge clk);
data_in = 8'hxx;
#100;
$finish;
end
endmodule
64
CONCLUSION
As the functional verification is decides the quality of silicon, we speed 60% of the design
cycle time only for the verification/simulation. In order to avoid the delay and meet the TTM, we
use the latest verification methodologies and technologies and accelerate the verification process.
This project helps one to understand the complete functional verification process of complex
ASICs and SoC‘s and it gives opportunity to try the latest verification methodologies ,
programing concepts like object oriented programming of hardware verification languages and
sophisticated EDA tools, for the high quality verification.
In this four Port Router project I design and verified the functionality of router with the latest
verification methodology i.e., system Verilog and observed the code coverage and functional
coverage of router by using cover points , cross and different test cases I improved the functional
coverage of router . In this I used one master and eight slaves to monitor the router. Thus the
functional coverage of router was improved.
The results shows that system Verilog methodology can be used to make reusable test benches
successfully .Large part of test bench is made reusable over multiple projects . Even though this
reusability is limited to the interfaces. A large class of devices that are build on these interfaces
can be verifies successfully. Ones these components are made the amount of time required to
build test benches for other projects reduced a lot .
FUTURE WORK:
This project used system Verilog i.e., the technology used is direct test cases , randomized test
cases , OVM for verification even though the coverage is 100% there may be some errors which
cannot be show so in order to overcome this new technology of system verilog i.e., OVM and
UVM . In the coming future the router can be done by using OVM and UVM.
65
REFERENCES :

Open cores project site http://www.opencores.org..

NORTEL ISP Router design document.

www.testbench.in

Verilog HDL-Digital Design and Synthesis, by Samir palnitkar

www.google.in
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