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Assignment 5

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National University
Of
Computer
&
Emerging
Sciences
Faisalabad -Chiniot
Campus
Department of Computer Science
EE 204 – Computer Architecture
Assignment-05
Course Instructor: Asra Ashraf
Total Marks: 50
Section: A
Due Date: 01/08/2019, 12:00pm
1. For a direct-mapped cache design with a 32-bit address and byte-addressable memory, the following bits of
the address are used to access the cache:
1.1
Tag Index Offset
31-10 9-5 4-0
1.1.1 What is the cache line size (in words)?
1.1.2 How many entries (cache lines or blocks) does the cache have?
1.2
Tag Index Offset
31-12 11-6 5-0
1.2.1 What is the cache line size (in words)?
1.2.2 How many entries (cache lines) does the cache have?
2. Both your L1 instruction and data caches separate a 32-bit address as follows:
bits 0 - 3 = offset bits
4 - 14 = index bits
15 - 31 = tag
What is the size of each cache? How much space is required to store the tags for the L1 instruction cache?
3. You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. Writing and reading data to
L2 takes 10 cycles. You get the following sequence of writes to the cache – each is a 32-bit address
in hexadecimal:
0x1000
0x1004
0x1010
0x11c0
0x2000
0x21c0
0x3400
0x3404
0x3f00
0x2004
0x1004
National University
Of
Computer
&
Emerging
Sciences
Address Index Tag
Faisalabad -Chiniot
Campus
Access Type
3.1 How many cache misses occur with an LRU policy?
3.2 How many cache misses occur with a most-recently used policy?
3.3 Would the miss-rate increase or decrease if the cache was the same size, but direct-mapped? Explain.
4. Consider three processors with three cache configurations:
Processor 1:
Direct-mapped i-cache and d-cache with one-word blocks Instruction miss-rate
= 4%, data miss-rate = 6%
Processor 2:
Direct-mapped i-cache and d-cache with four-word blocks Instruction miss-rate
= 2%, data miss-rate = 4%
Processor 3:
Two-way set associative i-cache and d-cache with four-word blocks Instruction
miss-rate = 2%, data miss-rate = 3%
For these processors, 50% of the instructions contain a data reference. Assume that the cache penalty is 6 +
Block size in words. Determine which processor spends the most cycles on cache misses.
5. Given the following sequence of address references in decimal:
20000, 20004, 20008, 20016, 24108, 24112, 24116, 24120
Starting with an empty cache, show the index and tag for each address and indicate whether a hit or a miss.
Address
Decimal=Hexadecimal
Cache Index (7 bits)
Tag
Offset (5 bits)
Hit/Miss
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