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# Mod2 - PG

advertisement ```Discrete and Continous


Discrete – sampling is required in time domain. Should
follow Nyquist criteria
i.e. Clock rate >> 2* BWsignal; to reduce the
requirements of an anti-aliasing filter. As a result,
switched-capacitor filters are limited in their ability to
process high-frequency signals.
Continous Time filter
Advantage
 Signals remain
continuous in time
and have analog
signal levels.
 No sampling increased speed
Disadvantage:
 need tuning circuitry
 poor linearity and
noise performance.
Continous Time filter
Integrators, summers, and gain stages are
the fundamental building blocks of analog
filters.
 Realize any rational function TF
 Any rational function with real valued
coefficient may be factored into first- and
second-order terms

First-Order Filters
First-Order Filters
•
•
•
•
•
the number of
integrators = order of
the desired TF
real pole at a freq = 0.
The pole to lie in the
LHS of the s-plane, the
value of 0 must be
positive.
DC gain, H(0) = ko/ 0
Gain at very high
frequencies = H()=
K1.
Second-Order Filters / biquadratic filters /
biquads
INTRODUCTION TO Gm-C FILTERS –
Integrators & Summers
s
V0 = integration of differential input voltage multiplied by
integrator unity gain frequency 0.
Fully differential Integrator
IC applications signals are kept differential
 Better noise immunity and distortion
properties.

Single Vs Two capacitor Diff. Ckt
Single Capacitor – Parasitic Effect
First Order Filter
First Order Filter
First Order Filter
0<k<1
 Cant use in high
frequency gain ckt

Fully differential first order Gm-C
filter
TRANSCONDUCTORS USING FIXED RESISTORS


Objective : linearize the relationship between differential
input voltage and output current of a differential pair of
transistors
input voltage,Vi, appears across the two Rs/2 resistors
and Rs
If VGS=0
If Vi=0
Bias Current I1 exist through Rs/2
 Vi will be closer to ground- undesired

Extend of relation stands to the value
upto which gm can equal 1/Rs, ensuring
linear realtion b/w io and Vi even with
varying Vbe
 For linearity , bias current should be large
and input signal should be small (to keep
gm small)

Alternative - Use opamp
Using current mirrors – constant
current through Q1, Q2
Transconductance using triode
transistor
Transconductance using triode
transistor

For n channel transistor in triode region,
Transconductors Using a Fixed-Bias Triode
Transistor

VDS=0 ; ID  VDS
Transconductors Using a Fixed-Bias Triode
Transistor
Transconductors Using a Fixed-Bias Triode
Transistor
Constsnat current flow through
transistors Q1 and Q2 so that VGS is
constant
 Gm = 1/ rds of Q9

Transconductors Using a Variable-Bias
Triode Transistor

To ensure Q3 and Q4 lie in triode region V1=V2

ie Vx = Vy = Vi-VGS1 = V1- (Veff1+Vtn)

ie for Q3, Q4 ,

VGS of Q3 & Q4 = VGS of Q1 & Q2 ensuring Q3 ,
Q4 is in triode region
VDS = 0
To find the Gm
ID in saturation
Gm is not linear wrt I1
 Gm can be tuned by changing I1

Transconductors Using Constant Drain-Source
Voltages
Transconductors Using Constant DrainSource Voltages


Gm depends on constant VDS only
Bias current I1 also depends on constant VDS if small VDS
CMOS TRANSCONDUCTORS USING
ACTIVE TRANSISTORS
worse linearity performance - moderate
(around 30 to 50 dB) –based on square
law for ID
 have improved speed performance

Methods

Constant Sum of Gate-Source Voltages

Bias offset Cross coupled differential Pair
I. Constant Sum of Gate-Source Voltages
To maintain Constant Gate Source Voltage



Source-Connected Differential Pair
Inverter Based
Differential-Pair with Floating Voltage Sources
Source-Connected Differential Pair
Source-Connected Differential Pair






Input signal varies symmetrically around a
common mode voltage
Linearity limited due to square-law model being
inaccurate
Even-order harmonics occur if the difference
between two drain currents not exact.
Limited to less than 50 dB linearity
Adjust Gm by varying VCM
In a short channel process, velocity saturation
limits transconductance variation
CMOS Pair – Two transistor Circuit
Two transistors in
active region
 Eqvt to a single
transistor
 Vt-eq – Eqvt.
Threshold voltage
 Keq - Eqvt.
parameter

Inverter Based
; Io=???
If
Gm = 4Keq(VC1 – Vt-eq)
 Transconductance value can be varied by
changing the control voltages, VC1 and VC2
 Matching should occur only for transistors of
the same type. ie, the n-channel transistors
should match and the p-channel transistors
should match.
 But there is no need to match n- and p-channel
transistors to each other.

Differential-Pair with Floating Voltage Sources
Differential-Pair with Floating Voltage Sources
VGS1 – (Vx + Vtn)+ VGS2 –(Vx + Vtn) = 0
VGS1+ VGS2 = 2(Vx + Vtn)
ie. circuit maintains a constant sum of gate-source
voltages even if the applied differential signal is not
balanced.
V1 – VGS1 + Vx + Vtn = V2
V2 – VGS2 + Vx + Vtn = V1
VGS1 - VGS2 = 2(V1 – V2)
ie. the difference between the input voltages =1/2 ( the
difference between the gate-source voltages)
Differential-Pair with Floating Voltage Sources

We know,
(iD1 – iD2) = K (VGS1+ VGS2 – 2Vtn)(VGS1 - VGS2 )

(iD1 – iD2) = 4KVx(V1 – V2)

ie, Gm = 4KVx
II. Bias-Offset Cross-Coupled Differential Pairs
Bias-Offset Cross-Coupled Differential Pairs
Bias-Offset Cross-Coupled Differential Pairs


O/p differential current is linear wrt the differential i/p
voltage
Gm  VB.
Bias currents through Q5,Q6,Q7 and Q8 are all square-law
related to VB
 So,
1) Gm of Q5,Q6,Q7 and Q8  square root of the changing bias
current
2) Bias current, Iss , doesn’t affect Gm but determine the
maximum (or minimum) output current available.

BIPOLAR TRANSCONDUCTORS
1.Fixed Transconductor with
Gain Cell
Fixed Transconductor – a
differential pair linearized
through resistor
degeneration.
Gain cell - allows scaling of the
output current by varying the
ratio of two current sources.
• Larger input range, lower
transconductance
• Create a transconductor with
a fixed value using a resistor
• Tune the transconductance
using a gain cell
2. Multiple Differential
Pairs
• Smaller input range, higher
transconductance
• Use 2 diff pairs to extend
linear input range
• Tuning done by adjusting
bias current
• More linearity is offered
Gain Cell Transconductors - Gain Cell

To execute variable
transconductance, gain
cell is used

In a gain cell, the output
current is equal to a
scaled version of the
input current

The scaling factor is
determined by the ratio
of two dc bias currents.

Also, the circuit is highly
linear.
Gain Cell Transconductors
io1 = Vi / RS
io = (I2/I1) io1

Gm 
Gain cell below the input differential pair,
Gain cell below the input differential pair,

2re vs 4re in series with the degeneration resistor, RE,
which might affect the distortion performance.

The gain cell shown has less distortion due to finite
effects and has therefore been referred to as a betaimmune type-A cell
Transconductors Using Multiple Differential
Pairs – Differential Pair




Gm  I1
Limited input range when used as a linear
transconductor.
when Vi > 32mVpp, the total harmonic distortion of the
output current > 1%
use parallel differential pairs to increase the linear input
range
currents of the right side transistors in each
transistor pair.
 If the dc offset voltages,V1 , are chosen carefully, then
the two current curves will partially linearize each
other when they are added together,
 In this case,V1 is chosen to be equal to 1.317 VT to
maximize the linear input range
 Thus the input range can now be approximately
three times that of the original differential pair or,
equivalently, 96mVpp and achieve the same
distortion performance.

To simplify the circuit
Eliminate d source by approx. sizing the
differential pair of transistors
 Let Vi=0, V1= 1.317VT, Ic of Q2 and Q4


If a two-transistor differential pair has unequal-sized
transistors such that the same two currents occur for
Vi=0 , then this unequal-sized differential pair will
behave the same as that of an equal-sized differential
pair with a dc offset applied.
Size of unequal transistors
k= ratio of area of Base – emitter of Q1
to Q2.
 If Vi=0,


Q1 3.73 times larger than Q2, and similarily Q4 should
be 3.73 times larger than Q3.

Such transistor sizing achieves the same result as the dc
offset voltages.

The ratio of the two currents be 0.7887/ .2113 when
their VBE are equal resulting in the area ratio.

Area ratio is set to 4 for practical reasons.
The final linearized transconductor

For this circuit with Vi=0 , the currents through Q1 and Q2
are and 0.8 I1 , 0.2I1 resp.
Active RC filter & MOSFET C Filter

To realize Analog integrated filters


Principle (Miller integration) : integration of current is
performed upon capacitors connected in feedback around
a high-gain amplifier.
Miller compensation capacitor in a two-stage opamp

Gm-C filters, use grounded capacitors to integrate current.

Miller integration:
- improves linearity
- need high gain-bandwidth product in the amplifier making
active RC and MOSFET-C filters slower than Gm-C filters.

Opamps are capable of driving resistive loads are required
in active RC and MOSFET-C filters reducing speed vs the
capacitive loads in Gm-C filters.


But used in BiCMOS technologies where hightransconductance opamps are available.
Active RC filter

Vx - the two input voltages of the opamp
equal due to –ve feedback

If components during +ve and –ve half cycles
are equal,
Vdiff = positive integration of the two input
differential signals.
 Negative integration??

MOSFET-C filters

Similar to fully differential active-RC filters, but resistors
are replaced with equivalent MOS transistors in triode.

Variations of MOSFET-C filters —
Two-transistor integrators
Four-transistor integrators
R-MOSFET-C filters.
MOSFET Two-Transistor Integrators
Vx determine the small-signal resistance of the
transistors.
 Vc – for tuning

Vp1, Vp2, Vn1, Vn2 are balanced around VCM,
 Making o/p also balanced
 Vpo, Vno, is linear.


Since the circuit is fully differential, even order
distortion products cancel and two-transistor
MOSFET-C integrators realize filters with around a
50 dB linearity.
Four Transistor Integrator - A single-input fourtransistor MOSFET-C integrator.



Improve linearity
The small-signal analysis of this four-transistor
integrator treat one-input integrator as a two-input
integrator in which the two input signals are Vpi - Vni
and the inverted signal is Vni - Vpi
Effective resistance is determined by control voltage

4 transistor ckt can cancel both even and odd distortion
products if the nonlinear terms are not dependent on
the control signals

In long channel transistors, non linear distortion terms in
IDS is independent of control voltages


Linear term depends on controlling gate voltage,
But, all distortion terms of the ID remain equal in the pair
Qp1, Qp2 & Qn1, Qn2 as VDS is equal in each pair.

Due to the cross-coupling connection, both the even and
odd distortion terms cancel.


Not available in short-channel devices.
Also, transistor mismatch limits the achievable
distortion performance. ie a 10-dB linearity
improvement using this technique over the twotransistor MOSFET-C integrator.
R-MOSFET-C Filters - Use additional linear resistors





Rq1,Rq2 - small-signal drain-source resistances of Q1, Q2
DC gain of this first-order filter is not adjustable, but
can be set precisely since it is determined by the ratio
of two resistors.
Time constant = R2C1 can be changed by changing the
values of Rq1,Rq2 by varying the control voltages.
Low freq – R2 set Vx to VG – increase linearity (-90db)
High freq – dec in linearity to -70db
TUNING CIRCUITRY
CTF - requirem of additional tuning circuitry.
 Why
- large time-constant fluctuations due to
process variations. Eg: IC, R, Gm
 Time constant RC or Gm-C variation???
- temperature variations

Abs. component value vs relative component
value
Abs. vs relative value of transcondcutoance

Let (i) Gmi = Kmi x Gm1.
(ii) CX + CB = kXBCA

Kmi – appropriate transistor, resistor, or bias-current
scaling.
KXB - ratio of capacitance values.
KX = CX / CA


Gm1 / CA… and extends to all transconductors
 indirect frequency tuning


To tune a continuous-time integrated filter, an extra
transconductor that is tuned is used and the resulting tuning
signal to control the filter Transconductors
Such an approach is commonly referred to as indirect
frequency tuning.

This tuning is indirect as matching between the filter
transconductors and the extra transconductor is focussed .
ie the filter is not directly tuned by looking at its output
signal.

Constant Transconductance
No tuning – 30%tolearnce in abs. value for Gm/C.
 Tune Gm only if ??
 Else…
 How – Employ ext. resistors
 Use a known value of external resistance and
measure the step response of the filter

determine the C value from step-response result
 Proper resistance is calculated.


Use f/b ckt to set Gm = 1/ ext. resistance
Frequency Tuning – Approach 1
Frequency Tuning
Req = 1/(fclkCM)
 Gm/C A = (fclkCM)/ C A
 Precise frequency tuning can be achieved
without any external components.

Problem-1

Requires large transconductance ratios leading to poorer
matching if high-frequency filters are desired.

Solution - reducing fclk by increasing CM. But ..
Set a smaller transconductance value for tuning circuit –
need proportiante increase in fclk in filter transconductor
Leads to poor matching between the filter and the tuning
circuitry, resulting in a less accurate frequency setting for
the filter


Approach 2 – Using two scaled current sources




Req = - 1/(fclkCM)
diode-connected transconductor is equivalent to a
resistor =1/Gm.
When the average current into the integrator is zero,
Gm = N fclkCM .
ie the clock frequency of this circuit is N times lower
than previous circuit
Approach 3 – Using PLL




Two continuous-time integrators are placed in a loop to
realize VCO that is placed into PLL.
Once ON, the negative feedback of the PLL causes the
VCO frequency and phase to lock to the external
reference clock.
Once the VCO output is locked to an external reference
signal, the Gm /C ratio of the VCO is set to a desired
value, and the
control voltage,Vcntl, can be used to tune the integrated
filter.
Q Factor tuning



Q-factors of the poles of the integrated filter are tuned
due to high-speed or highly-selective filtering, non ideal integrator effects and parasitic components
By tuning a single time constant, can set all coefficients
of an integrated filter with around 1% accuracy
But if Q>1, even small errors in the Q-factor can result
in large errors in the filter frequency and step response.
Hence, in some applications additional tuning is needed
to precisely set the Q-factors.
Method -1



Tune the phase of the filter’s integrators to a 90-degree
phase lag near the filter’s passband edge.
Done by using tunable resistor in series with integrating
capacitor
The control voltage for this tunable resistance,VQ, is
generated by a Q-factor tuning circuit and passed to all
the filter integrators.

If integrated filter is second order, the pole Q can be
adjusted by changing the transconductance of the
damping transconductor in the filter.
Tuning Methods Based on Adaptive
Filtering

used in DSP applications such as model matching,
channel equalization, and noise (or echo) cancellation.
Adaptive-filter tuning method intended for highspeed data transmission over a twisted-wire pair
pulse-shaping filter - to ensure that not too much highfrequency power is radiated from the twisted-wire channel.
 frequency and Q-factor loops rely on the fact that the input
to the filter is a series of steps ie tune to step response of
the filter
 Frequency tuning is done by ensuring that the zero crossing
of the filter’s low-pass output occurs at the correct time
period after a data transition.
 Q-factor tuning is performed by comparing the peak in the
filter’s bandpass output with a known voltage.
 The peak in the bandpass output occurs at approximately
the same time as the zero crossing, so both detectors can
be realized through the use of two clocked comparators,
which are triggered at a set time after a data transition.



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
Frequency tuning is done by ensuring that the zero
crossing of the filter’s low-pass output occurs at the
correct time period after a data transition.
Q-factor tuning is performed by comparing the peak in
the filter’s bandpass output with a known voltage.
The peak in the bandpass output occurs at
approximately the same time as the zero crossing, so
both detectors can be realized through the use of two
clocked comparators, which are triggered at a set time
after a data transition.
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