SIGNAL INTEGRITY
Dr.Lynne Green
Duet Technologies Inc.
boards and ICs, so what is learned in one
area may be useful in the other.
For designers, signal integrity means clean
data, and in any high-speed circuit design,
signal integrity is a major concem. In the
early days, signal integrity was primarily an
issue in RF board design. Today, it is an
issue for both high-speed boards and for
deep-submicron (below 0.35 um) ICs.
For the I/O pad design group at Duet
Technologies' IP Infrastructure Business
group, signal integrity has proven to be an
ongoing issue in library design. Our silicon
library design tools must be able to meet
the
requirements
for
simultaneous
switching outputs (SSOs), because a user
may switch 16 or more 4-mA pads sharing
a single Vdd and ground pad set, depending
on switching speed and signal integrity
requirements. Deep-submicron ICs deliver
the speed, but higher processing speeds lead
to higher edge rates at the chip boundary,
so overcoming signal interference is always
a primary concern.
As circuit design continues to migrate to
deep-submicron integrated and fine-line
multi-layer boards, maintaining signal
integrity becomes a greater challenge.
Increasing clock rates are forcjing designers
to reexamine design practices. Designers
need to locate sources of signal interference
early in the design cycle. That is becoming
easier as design tools improve.
Historically, designers have: used two
approaches in solving signal integrity
problems: the RF solution, which has
focused on transmission lines, and the
digital solution, which has focused on
package selection and ground planes.
Those two options, however,, have fallen
short addressing signal integrity problems
in deep-submicron IC design.
The issue of signal integrity
In practice, signal integrity problems often
show up as pattem-dependent, or soft,
errors, which are not repeatable and
therefore difficult to isolate. Another way
of looking at such problems is that signal
integrity
failures
introduce
"free"
transitions, leading to either "bad" data
being captured into a latch or a "bad clock
edge that causes data to be captured at the
wrong time.
, To
ensure signal integrity, designers need
to consider circuit design, placement and
routing, and circuit simulation. In circuit
and system design, designers can designate
the number of maximum simultaneous
switching outputs. When it comes to
correcting interference through placement
and routing, however, the designers' task
becomes more difficult. The necessary
tools are still in their infancy; the best
option is to be careful and methodical
during circuit simulation. Fortunately, the
same fundamental concepts apply to both
0-7803-5075-8/98/$10.0001998 IEEE.
The origins of signal integrity problems lie
in the circuit interconnections (wires,
substrates, and wells). After all, a wire
serves not only as a conductor of electrons,
but also as a resistor (at low frequencies), a
capacitor (at midrange frequencies), an
inductor (at high frequencies), and an
antenna (at very high frequencies), all of
which can affect signal integrity. The
challenge for designers is to isolate sources
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a clock input. The quiescent signal also
must not cross either VOH or VOL in order
to keep it in a known digital state.
of possible interference and eliminate them
before they cause problems within a design.
For example, when thinking of a wire
functioning as an inductor or antenna at
high frequencies, the question becomes
how high is "high"? One way of estimating
which effects are dominant is to took at the
wire's impedance at various frequencies.
Consider a package interconnect having 5
ohms + 50 pFd + 10 nH: at a frequency of
100 MHz, the corresponding impedances
are [5, -i32, +j6]. All three terms are
comparable in magnitude. As a general
rule, the larger the series (R and L) terms
and the smaller the shunt (C) term, the
more significant each term becomes. For
digital switching edges, the frequency used
in this calculation is typically lO/tr, where
tr is the signal rise time.
That's just one example of the challenge
that signal integrity poses to designers. The
secret to maintaining signal integrity is
applying a combination of better design
tools and better design techniques.
Origins of RLC effects
As ICs and boards move to finer line
widths, signal integrity becomes more of a
challenge, primarily because of the faster
rise times and the unavoidable physics of
routing structures. Also, at these speeds,
ground bounce increases as faster signal
rise times interact with board and package
parasitics.
When looking at signal integrity, one has to
consider a fundamental problem. A lack of
signal integrity causes a signal to violate a
voltage constraint.
In the simulated
switching waveforms in Figure 1, note that
both the quiescent and switching lines ring.
The ringing frequency is set by the load
capacitance and the package inductance.
The switching waveform exhibits both
overshoot and undershoot, and the
quiescent waveform exhibits ringing. An
1/0 driver must be designed so that the
quiescent waveform does not cross VOL or
VOH during SSO operation, where VOH
and VOL are the output-high and outputlow voltages for the 1/0 interface
specification (VOH = 2.4 V and VOL = 0.4
V for TT'L).
In any design, resistance is caused by the
interaction of the current-carrying electrons
with the atoms and crystalline grains in the
metal.
Silicon foundries and board
developers are addressing the problem by
changing the metallization, incorporating
new metals that minimize resistance.
Another factor affecting signal integrity in
chip design is capacitance. Capacitance is
the result of the closeness of structures with
independent voltages.
A reduction in
design rules has two effects: first, as wires
become smaller, capacitance becomes
dominated by wire spacing dimensions.
Second, as the spacing between wires
decreases, capacitance increases.
For
example, in the domain of deep-submicron
design, wiring capacitance is dominated by
fringing instead of area.
The switching signal must not cross VOL
or VOH more than once, or multiple
transitions may be observed by the next
latch or gate. The integrity of the switching
signal is particularly critical if the signal is
As silicon foundries move to six layers of
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9
* ......... ...................................................................
nmc
Figure 1: Simulated switching and quiescent signals.
with crosstalk is to use a 3D extractor and
metal, and boards move to a dozen or more,
then to perform circuit simulation.
capacitance calculations become more
complex. It is no longer sufficient to
The rule of thumb when dealing with
calculate capacitances to the substrate or
crosstalk is that below 10 MHz on boards
ground plane. Today, designers can use 2D
and 100 MHz on chips, it isn't a major
or, better yet, 3D field solvers to extract
issue, but above 100 MHz on boards and
net-to-net capacitances.
1,000 MHz on chips, it is significant. For
anything in between, crosstalk is a definite
Inductance remains a concern primarily at
risk, especially at the I/O interface, because
the package and board levels and is dictated
that's where you see board-level as well as
by both the size of the wire and the distance
chip-level effects. As sizes scale down,
though, such rules of thumb lose their
to the retum path (usually another wire
validity.
nearby or a ground plane). Inductances of
even a few nanohenries can be a problem,
when high switching currents in the power
A new strategy
rails can produce Vdd and ground noise
that can be coupled into logic. When two
wires run in parallel, there's also a mutual
There is a silver lining to the cloudy issues
inductance, which can couple noise onto a
surrounding signal integrity and circuit
quiescent line.
design. Since larger R, L, and C values are
found on printed circuit boards, there's a
Crosstalk is a signal integrity problem that
long list of available solutions. These
grows with both increasing chip clock
solutions stretch from those used for early
speeds and decreasing design rules.
FW boards to those employed on today's
Crosstalk is the result of capacitive and
multilayer digital boards. IC designers,
inductive coupling between adjacent wires,
particularly those designing 1/0cells, have
which causes each wire to act as an
been modeling package parasitics more
antenna. Crosstalk is typically observed as
than a decade, and IBIS users have worked
a fast dV/dt in one wire, which causes a
hard to develop models for packages and
second wire to respond. At moderate
1/0cells.
speeds, crosstalk can be adequately
modeled as pure Capacitive coupling
Traditionally, two approaches have been
(displacement current). However, at higher
used to solve the problems of signal
speeds or smaller dimensions, inductive
integrity for chip and multichip module
coupling becomes significant as well. That
designers. The RF solution has tended to
means that the best strategy for dealing
emphasize transmission lines, using
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extraction, integrated with a signal integrity
tool that would rip up and reroute if signal
integrity fell below the desired threshold.
impedance matching at ,the package
boundaries.
The digital (broadband)
solution has emphasized care in package
selection, limiting the number of
simultaneously switching outputs and/or
switching speeds, and using high-frequency
decoupling capacitors between Vdd and
ground package pins.
The third and most obvious solution
designers can apply is to simulate circuits
with care. If there's no accurate parasitic
extractor, then it's up to the designers to
estimate the correction factors.
For
example, in one study we conducted, we
found that quasi-3D capacitances were
about twice the value obtained using areato-substrate-only effects. Therefore, during
simulation all capacitances should be
modeled as intemodal, rather than as
capacitances to ground. That will allow
observation of crosstalk effects on
quiescent nodes, as well as give more
accurate delay and slew rate predictions.
As designers address the problem of signal
integrity in deep-submicron designs,
they've found that those solutions are no
longer adequate. For example, lirriiting
Wdt, though greatly improving ground
bounce and crosstalk, limits the clock
speed. That means new approaches must
be adapted for deep-submicron design.
Addressing signal integrity in design
Finally, simulation must be done on the
circuit in its package environment. As clock
speeds increase, that becomes one of the
critical validation or verification steps. As
dimensions continue to scale down and
more layers of metal routing are used,
maintaining signal integrity presents more
of a challenge for circuit designers. Since
signal integrity problems often appear as
unrepeatable errors, it becomes more
important to fix problems before silicon is
fabricated or a board is built. That means
that designers will be required to spend
more time on issues such as simultaneous
switching control, simulation, and
packaging before chip fabrication.
The signal integrity problem can be
addressed in three ways: circuit design,
placement and routing, and simulation. In
circuit design, designers have more choices
and can control signal integrity by
designating the number of simultaneous
switching outputs, the maximum dI/dt and
dV/dt of each block, and so on. Designers
may also choose to use differential signals
for high-fanout blocks, such as clock
drivers. The most common example is
positive-ECL signals for clocks, or fullswing differential. Both can be used onchip as well as off-chip.
In placement and routing, the choices are
more difficult. For example, crosstalk can
be improved by routing sensitive nets
perpendicular to noisy nets, but how does
one do placement and routing to achieve
the desired signal integrity? Rule-driven
routers have recently become available for
printed circuit boards, and are becoming
available for ICs. At the same time, the
place-and-route tools must incorporate full
parasitic extraction (preferably near-3D) to
allow accurate prediction of slew rates
(since it's slew rates that drive signal
integrity) as well as delays. The ultimate
router would incorporate accurate parasitic
As circuits continue to shrink and clock
speeds increase, simulation will no longer
be sufficient to validate signal integrity. A
prototype will be required. Signal integrity
data must appear on data sheets from IC
vendors, and the signal integrity
characteristics must incorporate package
information to be useful to the user
community.
Although we have a long way to go before
the EDA industry integrates placement,
routing, and signal integrity checking
design tools, formal signal integrity
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verification strategies, and databook
information formats required to address the
challenges of signal integrity in deepsubmicron design, significant progress has
already been made. The proliferation of
parasitic extractors (both 2D and 3D) is an
indication of the willingness of EDA
vendors to respond to industry needs. Over
the next two or three years, the industry
should see interesting developments in the
evolution of cell design, place-and-route
tools, and verification tools. The improved
information will in turn be of great use to
board designers.
Lynne Green is CMOS circuit analysis and
development engineer for the IP
Infrastructure Business Group of Duet
Technologies, Inc. in Bellevue, Wash.
Previously, she served as president of
Green Streak Programs, a consulting
company specializing in Spice modeling
and circuit simulation, and as a staff
engineer doing CMOS modeling and
simulation at IBM.
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