Delta Modulator and Demodulator
Objectives:
1. To understand the operation theory of delta modulation (DM).
2. To understand the signal waveforms of DM modulation.
3. Design and implementation of DM modulator.
4. Measurement and adjustment of DM modulator.
Components Required:
1. ICs: 393(Comparator)
4. LM741
7. 7474 (D Flip Flop IC)
2. Capacitor
5. Connecting wires 8. Breadboard
3. DSO Probe
6. Function Generator
10. Resistance
11. DC power supply
9. Digital signal oscilloscope
Theory:
Delta Modulation (DM) is a simplified PCM. In some type of signals (ex. Speech signal),
the neighboring samples are closely correlated with each other. Therefore, once a sample value is
known this enables the prediction of next sample value accurately. Thus, instead of sending the real
value of every sample at each time, differences (variances) between the present and the previous
samples are sent in DM. Same principle is also used in DPCM too.
In DM, two-level quantizer and one-bit coding is used. Transmitted code pulses do not carry
the data related to the message signal itself; instead they carry data regarding the differentials (Δ) of
the message function. The output of a delta modulator is a bit stream of samples at a relatively high
rate, the value of each bit being determined according to whether the input message sample
amplitude has increased or decreased relative to the previous sample.
Block Diagram of Delta Modulation and Demodulation
Figure 1: Delta Modulation
Figure 2: Delta Demodulation
Circuit Diagram:
Comparator
Sampler
Integrator
Figure 3: Circuit Diagram of Delta Modulator
Figure 4: Circuit Diagram of Delta Demodulator
Condition to Avoid Slope Overload:
This occurs when the sawtooth approximation cannot keep up with the rate-of-change of the input
signal in the regions of greatest slope. The step size is reasonable for those sections of the sampled
waveform of small slope, but the approximation is poor elsewhere. This is ‘slope overload’, due to
too small a step. Slope overload is illustrated in Figure 5(a).


To reduce the possibility of slope overload the step size can be increased (for the same
sampling rate).This is illustrated in Figure 5(b). The sawtooth is able to match the message
better in the regions of steep slope.
An alternative method of slope overload reduction is to increase the sampling rate. This is
illustrated in Figure 5(c), where the rate has been increased by a factor of 2.4 times, but the
step is the same size as in Figure 5(a). Bandwidth increases in this method.
Figure 5(a):Slope Overload
Figure 6(b):Slope Overload
Figure 7(c):Slope Overload
Procedure:
1. Connect the circuit as given in Figure 3.
2. Give a sinusoidal message signal of 1 Vpp and 400 Hz at the input of comparator as shown
in Figure.
3. Give a TTL clock of 32 KHz at the clock input of D filp flop.
4. Connect the inverting and non-inverting input of comparator to the different channels of
DSO.
Make voltage levels of both signal comparable by adjusting potentiometer of amplifier.
(Why
we
did that?)
5. Observe output after each stage of Figure 3 and draw it in your copy with proper
specification.
6. Step size of delta modulator circuit can be calculated by observing the change in amplitude
of unipolar to bipolar output in the sampling duration (Why?).
7. Now Fix sampling frequency to 32KHz. Increase the frequency of message signal by
varying
the
frequency of sinusoid and record the maximum frequency at which the integrator’s output
ceases
to follow the message signal on DSO. This condition is called slope overloading. Now
restore
the
frequency and start increasing the amplitude of message signal. Note the amplitude at which
slope
overloading occurs.
8. The estimated message signal from unipolar to bipolar output is passed through a low pass
filter as shown in Figure 4. Low pass filter will recover the message signal.
Results:
Input Sine
Wave
Modulated Signal
with Equal Step
changes
Step Size
Figure 8: DSO Output
U1(V+)
U1(POS IP)
A
7
U1
B
U4:A
3
6
1
C
2
2
D
4
1
5
74LS14
UA741
U1(V-)
U2(V-)
R1
10K
C1
4
U3:A
U3:A(CLK)
2
Q
5
1
4
U2
R
8n
6
1
Q
S
CLK
R2
2
D
3
5
10K
6
3
7
4013
UA741
U2(V+)
Figure 9: Full Circuit Connection in Proteus for Simulation (Modulator)
C2
10n
Encoded Modulated Signal
R3
R4
4k7
4k7
C1
BAT1
10n
12V
7
U1
Demodulated/Reconstructed Signal
3
6
4
1
5
2
741
BAT2
R1
12V
10k
R2
10k
Figure 8: Full Circuit Connection in Proteus for Simulation (DeModulator)
Results:
Delta Modulation and Demodulation are verified in both hardware and simulation (in
PROTEUS).Its waveforms are studied.
Precaution:
1. Check the connections before switching on the kit.
2. Connections should be done properly.
3. Observation should be taken properly.
Outcome:
A video (with loud audio) to be prepared by students.
1. Detailed explanation of the objective and delta modulation with circuit diagram.
2. Detailed explanation of procedure and results obtained.
3. Detailed explanation of the components on the installation board.
4. The final waveform at each nodes with proper analysis and explanation.
5. Future scope and improvement.
Viva Questions
1. If the signal of CLK is not TTL signal, then describe what the output signal will be.
2. What is a delta modulator and demodulator?
3. What are the advantages of DM over PCM?
4. What are the applications of Delta Modulation?
5. What is ADM in digital communication?
6. What are the advantages of Delta Modulation?
7. What is granular noise in Delta Modulation?
8. What is slope overload? Explain with circuit diagram?
9. What is quantization noise?
10. What is quantization and sampling?
11. What is quantization distortion?
12. What is slope over distortion?
13. In Delta modulation,
a) One bit per sample is transmitted
b) All the coded bits used for sampling are transmitted
c) The step size is fixed
d) Both a) and c) are correct
14. In digital transmission, the modulation technique that requires minimum bandwidth is
a) Delta modulation
b) PCM
c) DPCM
d) PAM
15. In Delta Modulation, the bit rate is
a) N times the sampling frequency
b) N times the modulating frequency
c) N times the Nyquist criteria
d) None of the above