Alexandria University
Faculty of Engineering
Computer and Systems Engineering Dept.
Third Year
Computer Architecture
Spring 2019
Sheet 1
Assigned: 16th February 2019
Due: 21st February 2019
A Single-Cycle Implementation for MIPS
1) Describe the effect that a signal stuck-at-0 fault (i.e. regardless of what it should be, the signal is
always 0) would have for the signals shown below, in the single-cycle data-path described in the
lectures. Which instructions, if any, will not work correctly? Explain why.
a. RegWrite
b. RegDst
c. ALUScr
d. MemtoReg
e. Branch
2) Repeat the previous question, but this time consider stuck-at-1 faults (the signal is always 1).
3)
4
For questions 4 and 5, assume that you can add any additional components you may need to
implement the new instructions.
4) We wish to add the instruction jr (jump register) to the single-cycle data-path. Add any
necessary data-paths and control signals to the single-cycle data-path of Figure 4.17 and show
the necessary additions to Figure 4.18. You can photocopy these figures to make it faster to
show the additions. You can find the jr instruction format in page A-64 in appendix A of the
reference Computer Organization and Design, 5th Ed. - Hennessy & Patterson.
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5) It is required to add a variant of the lw (load word) instruction, which increments the index
register after loading word from memory. This instruction (l_inc) corresponds to the following
two instructions:
Lw $rt, L($rs)
Addi $rs,$rs,1
Mention the modifications required in any component to implement such instruction. Add any
necessary data-paths and control signals to the single-cycle data-path of Figure 4.17 and show
the necessary additions to the table in Figure 4.18.
6) Assume that the logic blocks used to implement the data-path have the following latencies:
a. To avoid lengthening the critical path of the data-path shown in Figure 4.24, how much time
can the control unit take to generate the MemWrite signal?
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