See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/4166466
Advanced failure analysis of circuit-under-pad (CUP) structures in Cu/FSG and
Cu/low K technologies
Conference Paper · February 2005
DOI: 10.1109/RELPHY.2005.1493100 · Source: IEEE Xplore
CITATION
READS
1
487
11 authors, including:
Sailesh Merchant
Jim Cargo
Broadcom Limited
Broadcom Corporation
42 PUBLICATIONS 301 CITATIONS
17 PUBLICATIONS 87 CITATIONS
SEE PROFILE
John Osenbach
LSI Corporation
43 PUBLICATIONS 414 CITATIONS
SEE PROFILE
Some of the authors of this publication are also working on these related projects:
proton‐exchanged lithium niobate View project
Cu/Low-k Technology Analysis View project
All content following this page was uploaded by Sailesh Merchant on 23 February 2016.
The user has requested enhancement of the downloaded file.
SEE PROFILE
Advanced Failure Analysis, Failure Modes and
Reliability Study on Circuit-Under-Pad (CUP)
Structures with Copper Technologies
Huixian Wu 1, 2, Vance Archer 1, Sailesh M. Merchant 1, James Cargo 1, Daniel Chesire 1,
Joze Antol 1, Rafe Mengel 1, John Osenbach 1, Steve Horvat 1, Carl Peridier 1 , Marvin White 2
1
Agere Systems, Room: 20E-229A, 555 Union Blvd., Allentown, PA 18109
Phone: 610-712-5998, Email: hwu7@agere.com
2
Lehigh University, Dept. of Electrical & Computer Engineering
Abstract: In this paper, new failure modes for
CUP devices of copper technology, and Failure
Analysis (FA) challenges will be presented.
Fabrication processing and assembly/package
related reliability issues on Cu/low k technology
will also be addressed. Failure analysis
techniques for CUP devices of copper technology
have been developed and will be discussed.
Several backside FA deprocessing and crosssection techniques for CUP devices including:
reactive ion etching (RIE), parallel polishing, wet
chemical etching, chemical mechanical polishing
(CMP), Focus Ion Beam (FIB), SEM, TEM and a
combination of these techniques will be
addressed. Finally some case studies on CUP
structures with Cu/FSG, Cu/low k technologies
will be presented.
1. Introduction
Copper interconnects and low k dielectrics have
been introduced in advanced IC technology to
reduce the interconnect resistance, improve the
resistance to electromigration and reduce RC
delay and cross talk effects. The introduction of
new materials in integrated circuits makes
physical failure analysis more challenging.
Moreover, as technology shrinks, defects can be
smaller and more subtle, which generates
additional challenges for defect localization and
physical failure analysis. It is increasingly
important to understand new failure modes and
reliability issues related to Cu/low k technology
and develop FA techniques accordingly.
CUP structures with Cu/low k technology are
introduced.
Some
fabrication
and
assembly/package related reliability issues on
Cu/low k technology will be discussed. Some
advanced FA techniques will be presented.
Conventional front side defect localization in IC
devices has become less and less effective with
an increase in the number of metallic layers for
Photon Emission Microscopy (PEM), as
technology continually scales down to subquarter micron. Electrical defect localization in
devices with CUP structures, devices with a high
number of metallization levels and Flip-Chip Ball
Grid Array (FCBGA) packages, can more easily
be carried out from the backside of the die.
Development of backside failure analysis
techniques is increasingly important. In the work,
for CUP structures with eight metal layers of
Cu/low k technology, front side defect
localization is even impossible. Backside failure
analysis for CUP structures of Cu/low k
technology becomes necessary and critical. Three
major steps are involved in the backside FA
process: backside sample preparation, backside
defect localization, and backside physical
analysis.
For physical analysis, several backside FA
deprocessing techniques for CUP structures will
be presented.
The deprocessing techniques
include wet chemical etching, RIE, parallel
polishing, chemical mechanical polishing (CMP),
FIB, SEM, TEM and a combination of these
techniques. Some characterization results of FA
deprocessing will be presented for CUP devices
1
of Cu/low k devices. Finally, some case studies
and reliability analysis, and failure mode study
will be provided.
2. CUP Structures with Cu/low k
Technology
Following the fabrication of the semiconductor
devices on a wafer, each of the devices (also
known as chips or die) is tested for functionality,
or the wafers are “sorted”. Electrical probes from
a tester contact bonding pads formed on each of
the devices to determine if individual devices are
functional. After electrical testing, the wafer is
cut and the devices are separated from one
another. The devices are then assembled onto a
substrate using procedures known as die attach or
die bonding. Subsequent to the attachment of the
devices to package substrates, electrical
connections are made between the bonding pads
on the devices and the electrical leads on the
package. The electrical connections are made
using different techniques including wire
bonding, flip-chip bonding and tape-automated
bonding. At least with respect to wire bonding, a
bonding pad is subjected to a force applied
directly to the bond that may damage underlying
layers, materials, or components of a device.
After the die attachment and wire bonding
operations are completed, the device is then
“packaged” into a plastic molded package or a
ceramic package, depending upon the die size,
package application and end-use.
These devices are subjected to thermal and
mechanical stresses during electrical testing,
during wafer test and subsequent assembly
procedures. Damage to the device may be caused
during electrical testing, when the test probes are
pressed against the bonding pad. During the
probing operation, bond pad metal may be
deformed, thus preventing a reliable electrical
connection during subsequent wire bonding
between the bond pad and the package pad.
Moreover, the nature of the bond may be
mechanically and metallurgically weak, leading
to wire lift-off or a “non-stick” (no adherence)
situation. This problem is exacerbated by the
ever decreasing sizes of bond pad on which
smaller wire bonds are formed, leaving very
small regions where a sound wire bond is
possible. Furthermore, during the wire bond
operations, dielectric cracking can occur and
cracks can propagate through the layers to device
components, which may be damaged.
For
reasons outlined above, the industry has opted to
preclude the use of the area under the bond pads
for device layout, thereby decreasing the
efficiency of substrate utilization for active
circuitry. Input and output buffers are thus
located on the periphery of the device and
between bond pads to avoid placement of such
components under the bond pad. Therefore, the
spacing between the bond pads must be increased
to accommodate these buffers or other similar
devices.
In order to save valuable space on the device,
thereby decreasing the overall chip dimensions,
Agere Systems has begun placing active circuitry
underneath the pads [1]. The circuit under pad
(CUP) concept uses a variety of support
structures that contain metals, dielectrics and
combinations thereof. These CUP bonding pad
support structures are designed to protect device
components that are disposed within the device
directly under the pad in conjunction with
minimizing the damage caused by probe testing
and subsequent assembly.
Such a support
structure will also inhibit bond pad peeling that
may result from underlying layer damage.
In this study tester devices, containing a variety
of CUP support structure designs and
configurations, were fabricated to better
understand the interactions between probe
testing, wire bonding and subsequent assembly
operations on active circuitry under the pad. A
series of damage and crack detection circuits
were specifically designed and placed under the
bond pads to quantify this damage. Many of the
test structures were fabricated without any
protection from electrical over-stress (EOS) or
electro-static discharge (ESD).
This study
reports the effects of electrical over-stress on the
behavior of these unique test structures and
methods of analyzing failures of these test
structures under electrical over-stress.
2
After subjecting the test devices to routine sort
and assembly processes, typical accelerated
reliability tests were performed to assess the
degree of damage, if any, from these operations
to the integrity of the specially designed damage
testers placed underneath the pads. Moreover,
the performance of conventional device circuitry,
underneath the CUP support structures, was also
determined and compared with devices fabricated
without CUP support structures.
This report outlines the various techniques used
to determine the degree of mechanical and
metallurgical damage (if any) created to devices
fabricated
with
multilevel
copper/low-k
interconnects at the 130nm technology node.
3. Process and Packaging Effects on
Reliability of CUP Structures with Cu/low
k Technology
A. Process Issues:
Copper CMP process has a critical effect on the
low k dielectric delamination. Low polishing
shear force is preferred. Shear force depends not
only on process parameters, but also on pad
materials, slurry type, and the accumulation of
polish by-products [2].
CMP solution plays an important role on the rate
of chemically assisted crack growth in low k
dielectric [3]. Adhesion energies of Cu – low k
dielectric interfaces measured with the technique
of four-point bending, show a correlation to
chemical mechanical polish result. The interfaces
with adhesion energy below a critical value
exhibit delamination and cracking [4].
The etching and CMP processes have a major
influence on the dielectric breakdown. The
composition of the dielectric diffusion barrier and
pretreatment of the low k surface also affect the
integrity of the barrier/low-k interface [5] [6].
Slight changes in the interfacial chemistry result
in dramatic change in interface adhesion [6].
Barrier/dielectric
interface
with
copper
technology has found to be susceptible to
subcritical debonding similar to stress-corrosion
cracking. It is also found moisture has a larger
effect on reducing the interface adhesion than
temperature [7].
Due to weak mechanical properties and weak
adhesion of low k material, cracks and interface
delamination is contributing to inter-level
dielectric (ILD) failures. The primary failure
mode in structures with high breakdown field
was mechanical cracking of the dielectric barrier
or delamination at the barrier/ILD interface. The
type of the failure mode was strongly related to
processing conditions and is not necessary a
function of stress condition during the test [5].
B. Packaging Issues
Packaging assembly can significantly impact
wafer-level reliability causing interfacial
delamination, which is a serious reliability
concern for Cu/low k technology [8]. Key
assembly processes that impact interfacial
reliability include: wafer dicing, wire bonding,
flip chip bumping, molding, or under-filling [9].
At package level, the crack driving force is not
only residual stresses and thermal mismatch
stresses, but also the global thermal mismatch of
the package [10].
Delamination and cracking can occur as
mechanical and thermal stress are introduced
during fabrication processing such as CMP,
pretreatment, high temperature curing steps, and
so on. Delamination and cracking can also occur
during assembly/package processing due to the
large difference in thermal expansion coefficients
between the die and package substrates. Defects
or failures can be exaggerated during reliability
stress tests (HTOB, HTS, THB, TC).
The effect of packaging on the energy release
rate driving interface delamination and its impact
on reliability for Cu/low k. Interface
delamination is commonly observed in low k
3
interconnects after assembling the die into a flipchip package [11].
polishing, wet chemical etching, CMP and RIE
have been developed for Cu/low k technology.
Dicing or sawing is the first step in the packaging
process. Low k material has weak mechanical
properties, low adhesion strength, which
introduce more challenges on packaging and
assembly processing. Good seal ring design is
important in protecting the dies from the sawing
process [12].
Traditional front side defect localization is not
effective for CUP structures due to the gold balls
on top of bond pads blocking the thermal and
light emission from defect sites. Backside defect
localization from backside of the die is necessary
for CUP structures.
Wire bonding in Cu/low k technology presents
challenges. A major problem encountered in
bonding to Cu/low k chips results from the
oxidation of the copper during handling, wafer
sawing, die attaching curing and thermo-sonic
bonding [13].
C. Reliability Accelerated Testing
This section will be discussed late.
4. Failure Modes and FA Challenges for
CUP Structures of Cu/low k Technology
FA challenges will result from new failure modes
and reliability issues associated with the
integration of Cu and low k dielectrics. CUP
structure brings additional challenges for
electrical defect localization and physical failure
analysis:
Deprocessing copper and low k materials present
challenges. Delayering copper presents several
challenges, such as global uniformity problems,
dishing of metal interconnect, copper smearing,
and erosion of copper and dielectrics. For
delayering low k dielectrics, parallel polishing
has limitations due to its non-uniform process
and low removal rate. The conventional wet
chemicals used for ILD etching are not suitable
for some low k dielectrics. RIE may be an
alternative due to certain advantages. However,
there are still some challenges for RIE of low k
materials including etch selectivity, RIE grass,
surface roughness, and optimization of the
process parameters. In this work, several
deprocessing techniques such as parallel
More challenges may also be introduced during
front side physical deprocessing on CUP devices.
Traditional wet chemicals used for gold ball
removal don’t work for CUP devices with
Cu/low k technologies due to the wet chemicals
etching away copper and breaking through the
barrier layers. Parallel polishing of gold balls
may introduce mechanical stress, causing cracks
or delamination, which is also not a proper
method. Backside physical analysis and
deprocessing may be an alternative, especially
for CUP devices.
5. Failure Analysis Development for CUP
Devices
A. Backside sample Preparation for CUP
devices
A combination of mechanical milling (ChipUnzip TM) and RIE techniques has been employed
for silicon thinning, which is a critical step in the
backside sample preparation process [14]. In this
process, RIE can be used for final silicon
thinning after mechanical milling to achieve
more precise control of thickness of the
remaining silicon die while still preserving the
electrical integrity of the device. Figure 1 shows
a low power optical image of the backside PBGA
package during the backside sample preparation
process. The thickness of the remaining silicon
material is approximately 100 microns.
4
Figure 1. Low power image of package after
backside silicon thinning and final polishing
B. Backside Defect Localization for CUP
devices
Several backside defect localization techniques
and tools have been used in the industry, such as
Light-Induced Voltage Alteration (LIVA),
Thermally-Induced Voltage Alteration (TIVA),
Optical Beam Induced Resistance Change
(OBIRCH), Picosecond Imaging Circuit Analysis
(PICA), Laser Voltage Probing (LVP),
Fluorescent Microthermal Imaging (FMI), and
Photo Emission Microscopy (PEM).
In this work, backside FMI techniques were
performed to localize the defect site. Device was
analyzed under FMI through the backside during
unpowered curve trace. Thermal emissions were
detected at the failed pin during pin-to-pin curve
tracing of the device. No light emission was
detected. The same thermal emission was also
detectable using Liquid crystal analysis through
the backside. Figure 2 show backside FMI
images of the thermal emission for defect
localization.
Figure 2 FMI images of the thermal emission for
defect localization
C. Backside Physical Analysis
After backside sample preparation and backside
defect localization, backside physical failure
analysis becomes increasingly critical to find the
root cause of the failure.
Silicon removal, expose active circuitry from
Backside
In certain package types other than flip-chip
BGA packages, after the backside sample
preparation process, there is a cavity in the
backside of the package containing the die.
Deprocessing the whole package from the
backside is time consuming. Moreover, some
artifacts and defects could be introduced during
deprocessing of the entire package. There are
several ways to separate the die from the rest of
the package. One way is mechanical sawing, and
the other is wet chemical etching [15].
Combination of RIE and parallel polishing can be
used to remove the silicon material until the
remaining silicon thickness was approximately
five microns. RIE characterization of the silicon
5
substrate for backside FA has been performed in
our previous work [14].
TMAH wet chemical etching was used to
selectively remove silicon material over gate
oxide due to its high Si/SiO2 etch selectivity.
The advantages of TMAH over mechanical
polishing for removing the silicon substrate are
as follows: removing silicon without damage to
gate oxide, better uniformity across the die, and
better control of backside deprocessing.
The etch rate of silicon, gate oxide, and Si/SiO2
etch selectivity have been characterized at
different temperatures and at different TMAH
concentrations in our previous work [15].
Si/SiO2 etching selectivity decreases with an
increase in temperature. In this work, 20%
TMAH was used to remove silicon material at
temperature of 70 degree C.
Backside physical site analysis – gate level
analysis
Gate level failure modes could be breakdown of
the gate dielectrics, soft breakdown (SBD), stress
induced leakage current (SILC), direct tunneling,
hot carrier injection (HCI), trap assisted
tunneling (TAP), negative bias temperature
instability (NBTI), and interface instability.
The ability to perform physical FA at the gate
level has become increasingly important with
increased potential gate level defects, such as soft
breakdown of ultra thin gate oxide, SILC, TAT
and so on. In this paper, Backside gate level
deprocessing techniques will be presented.
To detect physical gate defects and study gate
dielectric integrity, Silicon etch process to expose
the gate dielectric is important and critical.
Figure 3 shows the SEM image at the gate level
from backside of the die.
Figure 3. SEM image at the gate level
More will be discussed later on.
Backside physical site analysis – combination of
CMP and RIE for metal level deprocessing
A combination of CMP and RIE was used to
deprocess the device layer and layer at the
metallization levels during backside FA. The
CMP method used for backside FA is similar to
the one for front-side FA.
Deprocessing of copper by CMP presents several
challenges to the FA analyst. Especially for CUP
structure, which is in the edge or corner of the
die, more challenges are introduced during the
deprocessing and physical analysis of CUP
structures.
Patterned wafers have been used for
characterization of the CMP process in our
previous work [16]. The polishing parameters
investigated include slurry chemistry, polishing
pad type, pressure, and pad rotation speed. We
found that multi-step CMP techniques with
different polishing conditions can be extremely
useful for deprocessing copper layers. Lower
pressure and lower pad rotation speed are used in
the final step to avoid over-polish of copper.
The characterization of RIE process of low k
dielectrics has been performed in our previous
work [17]. With the optimization of the RIE
process, high etch selectivity, low damage, and a
clean surface free of RIE grass can be achieved.
Figure 4 shows the SEM image of exposed
6
comb/meander structure by using CMP of copper
and RIE of low k material.
Figure 5. Backside optical image – M5 layer
Figure 4. SEM image of exposed comb/meander
structure underneath the bond pad
Backside Cross Section Analysis- Focus Ion
Beam (FIB)
FIB cross-section analysis can used to study the
integrity of the copper/barrier/low k interface.
SEM analysis was then performed at the
damaged area. A dielectric crack, copper
migration along the crack and thermally induced
damage in dielectric was observed. The damage
appeared to be caused by electrical overstress,
resulting in thermal effects.
Figure 6. Backside optical image – M6 layer
SEM analysis of the observed anomaly was
performed at M6 layer. Metal cracks were
observed, which is shown in Figure 7 and 8.
6. Failure Analysis Case Studies on CUP
Devices with Cu/low k Technology
Case Study 1:
An anomaly was observed at thermal emission
site when deprocessing the device down to M5
layer and M6 layer, which are shown in Figure 5
and Figure 6.
7
Figure 7. SEM image of the observed anomaly –
metal cracks at M6 layer
Figure10. Backside optical image – M5 layer
Figure 8. SEM image of the observed anomaly –
thermal damage at M7 layer
Case Study 2: (CMP & RIE)
In this case, a combination of CMP and wet
chemical etching was performed to deprocess the
device from backside of die. Figure 9 and Figure
10 showed an optical image of an anomaly at M4
and M5 layer, respectively.
Case Study 3: (CMP & Wet chemical Etching)
In this case, a combination of CMP and wet
chemical etching was performed to deprocess the
device from backside of die layer by layer.
Figure 11 shows the optical image of the
observed defects. Figure 12 shows the SEM
image of the defect after exposed M5 copper
runner.
Figure11. Backside optical image – M5 layer
Figure 9. Backside optical image – M4 layer
8
Figure12. SEM image of M5 layer
Figure 13. Optical image of the defects at M4,
M5 layers
Figure 11 and 12 show the anomalies at the edge
of the meander/comb structure. Dielectric cracks,
copper extrusion, copper voids were observed at the
damaged areas, which were believed to be caused by
electrical overstress.
Case Study 4: (CMP & FIB)
During backside physical failure analysis, a
combination of CMP and RIE was used to
deprocess the device layer and layer down to
Metal 5 (M5) layer. High power optical
inspection was performed and a damaged area
was observed at edge of the meander structure at
M5 layer, shown in Figure 13.
Further FIB cross-section analysis was performed
at the damaged area. SEM analysis was then
performed at the damaged area. A dielectric
crack, copper migration along the crack and
thermally induced damage in dielectric was
observed in Figure 14 and 15. The damage
appeared to be caused by electrical overstress
induced thermal effects.
Figure 14. FIB image of the defects
9
7. Conclusion
Figure 15. FIB image of the defects
Case Study 5: - Study of gate level defect
To detect physical gate defects and study gate
dielectric integrity, Silicon etch process to expose
the gate dielectric is important and critical.
Figure 16. SEM image at the gate level
Reliability analysis and technical discussion on
failure modes on CUP structures
This section will be provided later
CUP structures have been developed and
introduced. Various process and package related
reliability issues on Cu/low k technology have
been discussed. Several FA techniques including
deprocessing and cross section techniques for
CUP structures of Cu/low k technology have
been presented: reactive ion etching (RIE),
parallel polishing, chemical mechanical polishing
(CMP), FIB cross-section and combinations of
these techniques. We found the combination of
RIE and CMP techniques works well for
deprocessing copper and low k ILD layers.
Various FA challenges for CUP structures of
Cu/low k technology were also addressed.
Finally some FA case studies were discussed.
Reference:
[1] S. Chittipeddi et al., US Patent 5,751,065.
[2] Stan Tsai and et al., pp. 102-104, 2002 IEEE
[3] Eric P. Guyer and R.H. Dauskardt, pp. 89-91,
2003 IEEE
[4] T. Scherban and et al., pp. 257-259, 2001
IEEE
[5] Glenn B. Alers, K. Jow and et al., pp. 148152, IEEE Transactions on Device and
materials Reliability, Vol. 4, No. 2, June
2004
[6] M. Lane, N. Krishna, I. Hashim, and R.H.
Dauskardt, J. Mater. Res., Vol. 15, No. 1, pp.
203-211, 2000
[7] M. Lane, X. Liu, and T.M. Shaw, IEEE
Transactions on Device and Materials
Reliability, Vol. 4, No. 2, pp. 142-147, 2004
[8] Guotao Wang, Steven Groothuis, and Paul S.
Ho, pp. 28-30, 2004 IEEE
[9] Cheryl D. Hartfield, Ennis T. Ogawa and et
al., pp. 1-15, IEEE Transactions on Device
and materials Reliability, Vol. 4, No. 2, June
2004
[10] Lei Mercado, Cindy Goldberg, and ShunMeen Kuo, pp. 119-121, 2002 IEEE
[11] Guotao Wang, Steven Groothuis, and Paul
S. Ho, pp. 727-732, 2003 Electronic
Components and Technology Conference
[12] Hanxie Zhao and Dianne Shi, pp. 401-407,
2003 IEEE Int’l Electronics Manufacturing
Technology Symposium
10
[13] George G. Harman and Christian E.
Johnson, pp. 677-683, IEEE Transactions on
Component and packageing Technologies,
Vol. 25, No. 4, Dec. 2002
[14] Huixian Wu and James Cargo,
“Characterization of reactive ion etching of
silicon substrate for backside failure mode
analysis”, ISTFA 2002
[15] Huixian Wu, James Cargo, “Backside
failure analysis and case studies for Cu/low k
technology”, 2004 IPFA
[16] Huixian Wu, James Cargo, Barry Dutt and
et al., “Interconnect and Gate Level
Delayering Techniques for Cu/Low k
Technology Failure Analysis”, ISTFA 2003
[17] Huixian Wu, James Cargo, Carl Peridier
and Joe Serpiello, “Reliability issues and
advanced failure analysis deprocessing
techniques for copper/low k technology”, pp.
536-544, 2003 IRPS
11
View publication stats