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Topic 3 - CMOS Fab Process (1up)

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Topic 3
CMOS Fabrication Process
Peter Cheung
Department of Electrical & Electronic Engineering
Imperial College London
URL: www.ee.ic.ac.uk/pcheung/
E-mail: [email protected]
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 1
Layout of a Inverter
VDD
Qp
vo
vi
Qn
GND
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 2
The CMOS Process - photolithography (1)
(a) Bare silicon wafer
Silicon Wafer
(b) Grow Oxide layer
SiO2 ~ 1µm
Silicon Wafer
(c) Spin on photoresist
photoresist
Silicon Wafer
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 3
The CMOS Process - photolithography (2)
(d) Expose resist to UV light
through a MASK
(f) Etch away oxide
Silicon Wafer
(g) Remove remaining resist
Silicon Wafer
(e) Remove unexposed resist
Silicon Wafer
Silicon Wafer
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 4
Mask 1: N-well Diffusion
• SiO2 is etched using
Mask 1.
Phosphorous Diffusion
SiO2
p-substrate
• Phosphorous is
diffused into the
unmasked regions of
silicon creating an nwell for the fabrication
of p-channel devices
PYKC Oct-18-10
n-well
p-substrate
E4.20 Digital IC Design
Lecture 3 - 5
Mask 2: Define Active Regions
• Mask 2 creates the
active regions where
the MOSFETs will be
placed
Photoresist
SiO2
Photoresist
n-well
p-substrate
A thick field oxide is grown using a
contruction technique called Local Oxidation
Of Silicon (LOCOS).
SiO2
• The thick oxide regions
provides isolation
between the MOSFETs
PYKC Oct-18-10
n-well
p-substrate
E4.20 Digital IC Design
Lecture 3 - 6
Mask 3: Polysilicon Gate
• A high quality thin oxide
is grown in the active
area (~100A->300A)
• Mask 3 is used to
deposit the polysilicon
gate (most critical step)
Thin Oxide
SiO2
n-well
p-substrate
The polysilicon layer is usually arsenic doped
(n-type). The photolithography in this step is the
most demanding since it requires the finest
resolution to create the narrow MOS channels.
SiO2
n-well
p-substrate
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 7
Mask 4: n+ Diffusion
• Mask 4 is used to
control a heavy arsenic
implant and create the
source and drain of the
n-channel devices.
• This is a self-aligned
structure.
Arsenic Implant
SiO2
Photoresist
n-well
p-substrate
The polysilicon gate acts like a barrier for this
implant to protect the channel region.
n+
n+
SiO2
n+
n-well
p-substrate
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 8
Mask 5: p+ Diffusion
• Mask 5 is used to
control a heavy Boron
implant and create the
source and drain of the
n-channel devices.
• This is a self-aligned
structure.
Boron Implant
Photoresist
SiO2
n-well
p-substrate
The polysilicon gate acts like a barrier for this
implant to protect the channel region.
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 9
Mask 6: Contact Holes
• A thin layer of oxide is
deposited over the entire
wafer
• Mask 6 is used to pattern
the contact holes
• Etching opens the holes.
oxide
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
Etched contact holes
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 10
Mask 7: Metalization
• A thin layer of aluminum
is evaporated or
sputtered onto the wafer.
• Mask 7 is used to
pattern the
interconnection.
p+
n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
Aluminum Interconnection
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 11
Cross section of a CMOS Inverter
vi
vo
VDD
p+
n+
Qn
n+
p+
n+
Qp
n-well
Source-Body
Connection
p-substrate
PYKC Oct-18-10
p+
E4.20 Digital IC Design
Source-Body
Connection
Lecture 3 - 12
Physical Layout of an Inverter
n-well
PMOS active region
VDD
Qp
NMOS active region
n+ diffusion
p+ diffusion
vo
vi
Poly 1 (poly-Si gate)
Qn
Contact Hole
Metal 1
PYKC Oct-18-10
GND
E4.20 Digital IC Design
Lecture 3 - 13
Dimension of transistors
L
n+
W
Poly
L
n+
W
Gate
n-well
n-channel MOSFET
PYKC Oct-18-10
Poly
p+
Drain
Source
Drain
Source
p+
Gate
p-channel MOSFET
E4.20 Digital IC Design
Lecture 3 - 14
Photo cross-section of a transistor
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 15
Advanced metalization with polishing
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 16
Latch-up problem (1)



As shown above, the p+ region of the p-transistor, the n-well and the p- substrate form a
parasitic pnp transistor T1.
The n- well, the p- substrate and the p+ source of the n-transistor forms another parasitic
npn transistor T2.
There exists two resistors Rw and Rs due to the resistive drop in the well area and the
substrate area.
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 17
Latch-up (con’t)





T1 and T2 form a thyristor circuit.
If Rw and/or Rs are not 0, and for some
reason (power-up, current spike etc), T1 or
T2 are forced to conduct, Vdd will be
shorted to Gnd through the small
resistances and the transistors.
Once the circuit is 'fired', both transistors
will remain conducting due to the voltage
drop across Rw and Rs. The only way to
get out of this mode is to turn the power
off.
This condition is known as latch-up.
To avoid latch-up, substrate-taps (tied to
Gnd) and well-taps (tied to Vdd) are
inserted as frequently as possible. This
has the effect of shorting out Rw and Rs.
PYKC Oct-18-10
E4.20 Digital IC Design
Lecture 3 - 18
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