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Course Code and Title: CT
PL3002 PLCs and Microcontrollers
Programme:
BASc Utilities Engineering
Exercise 2: The Condition Code Register, Relative Addresses, Branching, Extended Addressing,
Multiple Precision and Signed Addition
OBJECTIVES
1) To be able to use the Line Assembler (ASM) command to enter programs using mnemonics;
2) To be able to use the Breakpoint (B) command to set breakpoints to interrupt a program at
selected places;
3) To use the following new Monitor commands:
Fill (F) command to fill a set of locations with a specified byte;
Move (MOVE) command to relocate the contents of a set of locations;
4) To become familiar with the Condition Code Register and, in particular, the N, Z, V, and C
flags;
5) To be able to determine relative addresses;
6) To demonstrate the characteristics and use of the relative and extended addressing modes of
the 68HC12;
7) To be able to interpret the addition of signed numbers
8) To be able to add multiple precision numbers;
9) To write a program using extended addressing; and
10) To use the following new instructions of the 68HC12 instruction set:
BRA, BEQ,
CLC, CLV, SEC, SEV,
ADCA.
Introduction
In this exercise there are several main points:
1) the Relative Addressing Mode,
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2) the Condition Code Register.
3) branch instructions,
4) multiple precision operations, and
5) the Extended Addressing Mode.
The Relative Addressing Mode
Branch instructions, which are introduced in this exercise, use the relative addressing mode. A
relative address gives the location, or offset, of a byte in memory relative to a base location.
This is illustrated in Figure 2-1. The offsets shown are relative to the base location (which has
the relative address $00).
Figure 2-1 Relative Addresses
Since a relative address is a single byte and is signed, the address is forward (increasing memory
locations) relative to the base location if the most significant bit of the relative address is '0',
and backward (decreasing memory locations) if the most significant bit is ‘1’. Hence, a relative
address is between 8016 (-12810) and 7F16 (+12710) relative to the base location.
To determine the relative address, call the base location address $00 and count up (in hex)
increasing locations, and count backwards ($FF, $FE, $FD,...) for decreasing locations.
Alternatively, you can count up for decreasing locations and take the two's complement of the
count if you find counting backwards in hex a nuisance.)
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The Condition Code Register
The programs in Exercise 1 (not counting the sessions) were straight line programs where a
sequence of instructions was executed in order. Such programs are very limited. The capability
of branching to other places, depending on certain conditions, is necessary to make programs
useful to any extent.
The conditions that cause branching depend on an 8-bit register called the Condition Code
Register (CCR). Generally instructions affect these bits when they are executed. The 68HC12
instruction set sheets show the effect of every instruction on each of the bits in this register.
For example, the COMA (1's complement accumulator A) instruction has the following notation
in regard to the bits in the CCR
A '.’ means the particular bit is not changed by the instruction. A '0' or '1' means the bit is
unconditionally set to a '0' or '1' when the instruction is executed, and an up-down arrow
means the instruction may set the bit either to a '0' or '1' depending on the result of the
instruction.
The bits in the CCR are named S. X, H, I, N, Z, V. C. 'S' is the STOP instruction disable flag, and 'X'
and 'I' are interrupt masks. The remaining 5 bits are status flags related to the results of
arithmetic and other operations. The least significant 4 bits (N, Z, V. and C) are of interest in this
exercise.
A memory aid for remembering the names of the last 6 bits is the response to this question,
"Hello. What's the temperature?" which is "HI, Not Zero, but Very Cold."
Branch Instructions
The 68HC12 contains approximately 20 branch instructions whose action generally depends on
logical functions of the state of the status flags N, Z, V, and C in the Condition Code Register at
the time the branch instruction is executed. For example, the 'Branch If = Zero' (BEQ)
instruction branches if the Z flag is '1'; otherwise the program continues with the next
instruction following the branch instruction.
The 'Branch If> Zero' (BGT) instruction branches if the function Z + (N≈ V) =0 where Z, N, and V
are the states of the zero, negative, and overflow flags. '+' is the logical or operator and '≈' is
the logical exclusive or operator. If Z + (N≈ V) = 1, then the program continues with the next
instruction following the branch.
The 'Branch Always' (BRA) instruction branches unconditionally regardless of the state of the
flags. For completeness, the instruction set even contains a 'Branch Never' (BRN) instruction.
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Where the branch instruction branches to is determined by its single byte operand which is a
relative address. The base location for the relative address is the location of the first byte of the
instruction following the branch instruction. The reason for this is that the program counter is
pointing to the next instruction after the branch instruction is fetched. If the logical test
determines that the branch should occur, the relative address is simply added to the program
counter.
Figure 2-2 shows the technique for determining the relative address for a branch instruction.
Note that the relative address is determined by counting bytes, not instructions.
Figure 2-2 Determining the Relative Address for Branch Instructions
Multiple Precision Operations
Another topic considered in this exercise involves arithmetic operations on values which
require more than one byte for their representation. In particular, addition of multiple precision
numbers is introduced. This topic will be expanded in Exercise 3.
The Extended Addressing Mode
The Extended Addressing Mode, which is introduced in this exercise, is very simple and allows
instructions to refer to the contents of any address in the 64K memory space of the
microprocessor. It is much like the Direct Addressing Mode that we have already used except
that the operand requires two bytes rather than one.
PREPARATION
There are 10 preparation problems below which you should complete before performing the
exercise.
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PREPARATION 2-1 simply asks you to write the 16 hex digits in binary. These will be useful for
interpreting the behavior of the program below it.
PREPARATION 2-2 requires you to look up 6 instructions which act directly on the Condition
Code Register.
PREPARATION 2-3 asks you to "walk through" an algorithm for adding the integers from 1 to N
where N can be specified. "Walking through" is a way of checking an algorithm. You essentially
play computer and execute all the instructions, one at a time, while keeping track of their
effects, just as a computer would.
PREPARATION 2-4 asks you to determine a relative address for a branch instruction in the given
listing and to study the listing to convince yourself that it performs the specified task.
PREPARATION 2-5 asks you to find the sum of the integers from 1 to 10 ($0A).
PREPARATION 2-6 requires you to add three instructions to the program for adding consecutive
integers so that it adds only the even integers.
PREPARATION 2-7 asks you to add sets of single byte numbers, determine how the CCR flags get
set, and interpret the correctness of the additions in terms of the flags.
PREPARATION 2-8 simply requires you to add two 6-digit numbers in hexadecimal.
PREPARATION 2-9 asks you to perform 3 subtraction problems involving 2-byte hexadecimal
numbers.
PREPARATION 2-10 asks you to modify a previous program so that it uses extended mode
addressing rather than direct mode addressing. The relative addresses you have to determine
are different from the previous program since extended addresses require 2 bytes rather than
the 1 byte for direct addressing.
PROCEDURE
1. Some More Monitor Commands
Do Session 3: Using the Monitor Line Assembler Breakpoints,
Do Session 4: Some Other Monitor Commands.
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2. The Condition Code Register
The following program does a number of operations on accumulator A which affects condition
code register in various ways:
1000 87
CLRA
1001 86 01 LDAA #$01
1003 4 3 DECA
1004 4 3 DECA
1005 4 2 INCA
1006 4 2 INCA
1007 86 40 LDAA #$40
1009 8B 3A ADDA #$3A
100B
86 40
LDAA #$40
100D
8B 4A
ADDA #$4A
100F
86 80
LDAA #$80
1011
8B 7A
ADDA #$7A
1013 86 80 LDAA #$80
1015 8B 80 ADDA #$80
1017 86 80 LDAA #$80
1019 8B 8A ADDA #$8A
101B 86 7A LDAA #$7A
101D
8B 80
ADDA #$80
101F 86 7A LDAA #$7A
1021
8B 90
ADDA #$90
1023
20 FE
BRA
$1023
Enter the program using the Line Assembler (ASM) command as shown below. Note that the '$'
appearing in the listing above are not entered since all numerical values are assumed to be
hexadecimal when using the Line Assembler.
> ASM 1000 <cr>
1000 xxxxxxxx (This instruction may be anything.)
CLRA <cr>
1001 xxxxxxxx
LDAA #01 <cr> (The ‘$’ in the listing above is omitted!)
1003 xxxxxxxx
DECA <cr>
(Continue entering the rest of the instructions.)
:
:
1023 xxxxxxxx
BRA $1023 <cr> <.>
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>
Check that the program is correct using the ASM command:
> ASM 1000 <cr>
1000 87
CLRA
1001 86 01 LDAA #$01
1003 4 3 DECA
:
:
1023 20 FE BRA $1023
We are going to trace through the program and record the contents of accumulator A and the
Condition Code Register C in the table of Figure 2-3 after each instruction is executed.
First set the program counter with the Register Examine and Modify command as follows:
> RM
PC-xxxx CC-xx <Sxxxxxxx> B-xx A-xx X-xxxx Y-xxxx SP-xxxx
PC-xxxx 1000 <cr> <.>
>T 20
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1001 3C00 0004 0001 00:00
1000 0100
xx:1001 8601
LDAA #$01
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1003 3C00 0004 0001 01:00
1000 0000
xx:1003 43
DECA
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1004 3C00 0004 0001 00:00
1000 0100
xx:1004 43
DECA
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1005 3C00 0004 0001 FF:00
1000 1000
xx:1005 42
INCA
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1006 3C00 0004 0001 00:00
1000 0100
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xx:1006 42
INCA
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1007 3C00 0004 0001 01:00
1000 0000
xx:1007 8640
LDAA #$40
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1009 3C00 0004 0001 40:00
1000 0000
xx:1009 8B3A
ADDA #$3A
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 100B 3C00 0004 0001 7A:00
1000 0000
xx:100B 8640
LDAA #$40
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 100D 3C00 0004 0001 40:00
1000 0000
xx:100D 8B4A
ADDA #$4A
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 100F 3C00 0004 0001 8A:00
1000 1010
xx:100F 8680
LDAA #$80
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1011 3C00 0004 0001 80:00
1000 1000
xx:1011 8B7A
ADDA #$7A
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1013 3C00 0004 0001 FA:00
1000 1000
xx:1013 8680
LDAA #$80
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1015 3C00 0004 0001 80:00
1000 1000
xx:1015 8B80
ADDA #$80
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PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1017 3C00 0004 0001 00:00
1000 0111
xx:1017 8680
LDAA #$80
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1019 3C00 0004 0001 80:00
1000 1001
xx:1019 8B8A
ADDA #$8A
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 101B 3C00 0004 0001 0A:00
1000 0011
xx:101B 867A
LDAA #$7A
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 101D 3C00 0004 0001 7A:00
1000 0001
xx:101D 8B80
ADDA #$80
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 101F 3C00 0004 0001 FA:00
1000 1000
xx:101F 867A
LDAA #$7A
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1021 3C00 0004 0001 7A:00
1000 0000
xx:1021 8B90
ADDA #$90
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1023 3C00 0004 0001 0A:00
1000 0001
xx:1023 20FE
BRA $1023
PP PC SP X Y D = A:B CCR = SXHI NZVC
38 1023 3C00 0004 0001 0A:00
1000 0001
xx:1023 20FE
BRA $1023
>
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Note the value of accumulator A and the Condition Code Register CCR. Record the values you
read in the table of Figure 2-3. Enter the accumulator A value in hexadecimal and the values of
the NZVC flags as binary digits. The table you generated in PREPARATION 2-1 should help you
with this.
PREPARATION 2-1: Write the binary digits corresponding to the least significant digit in the
hexadecimal values given. (The bits denoted by ‘x' corresponding to the S, X, H, and I flags are
not of concern here.)
Hex S X H I N Z V C
X0
xxxx 0000
X1
xxxx
X2
xxxx
X3
xxxx
X4
xxxx
X5
xxxx
X6
xxxx
X7
xxxx
X8
xxxx
X9
xxxx
XA
xxxx
XB
xxxx
XC
xxxx
XD
xxxx
XE
xxxx
XF
xxxx
A
N Z V C
Initial value of A and CC:
1000 87
CLRA
1001 86 01 LDAA #$01
1003 4 3 DECA
1004 4 3 DECA
1005 4 2 INCA
1006 4 2 INCA
1007 86 40 LDAA #$40
1009 8B 3A ADDA #$3A
100B 86 40 LDAA #$40
100D 8B 4A ADDA #$4A
100F 86 80 LDAA #$80
1001 8B 7A ADDA #$7A
1013 86 80 LDAA #$80
1015 8B 80 ADDA #$80
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1017 86 80 LDAA #$80
1019 8B 8A ADDA #$8A
101B 86 7A LDAA #$7A
101D 8B 80 ADDA #$80
101F 86 7A LDAA #$7A
1021 8B 90 ADDA #$90
1023 20 FE BRA
$1023
Figure 2-3. Tabular Results of Condition Code Register Study
Figure 2-4 shows the behavior of the condition code flags for each of the instructions used in
the program above. This figure has been compiled using information from the 68HC12
instruction set sheets.
Figure 2-4. Effect of Some 68HC12 instructions on Condition Code Flags
A dot (.) indicates that the particular flag is not affected by the instruction;
A '0' or '1' indicates that the flag is unconditionally set to that value by the instruction;
An up-down arrow indicates that the flag is set according to the result in accumulator A after
the instruction is executed according to the following rules:
N
Negative flag - set to '1' if result is negative (Most Significant Bit = 1), set to '0' if result is
positive (Most Significant Bit = 0);
Z
Zero flag - set to '1' if all bits of result are '0', set to '0' otherwise;
V
Overflow flag - set to '1' if an overflow occurs as a result of the operation
This flag is generally used when signed arithmetic is intended. For example, if the sum of two
positive numbers produces a negative number, or the sum of two negative numbers produces a
positive number, the overflow flag is set to 1 to indicate an overflow has occurred. If a positive
and negative number are added, an overflow can't occur, and hence the overflow flag will be
set to 0; it is set to '1' otherwise.
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C
carry/borrow flag - set to '1' if carry is generated as a result of an addition or if a
borrow is necessary as a result of a subtraction; it is set to '0' otherwise.
Carefully check that the results that you have written in Figure 2-3 are consistent with these
rules.
Why is the carry bit '1' after the LDAA #$80 instruction at location $1017 is executed?
3. Some Instructions which Manipulate Bits in the Condition Code Register
PREPARATION 2-2: Look up the following instructions in the M68HC12 Reference Manual and
write a brief description of what they do:
CLC
CLV
SEC
SEV
TAP
TPA
Enter the program shown in Figure 2-5 with the Line Assembler (ASM) command. Check the
program after you have entered it with the ASM command.
Set the program counter to $1000 with the Register Examine and Modify (RM) command and
execute the program one instruction at a time with the next step (N) command. Record the
value of accumulator A in hexadecimal and the NZVC flags as binary digits in the spaces
provided.
A
N Z V C
1000 87
CLRA
1001 14
01
SEC
1003 14
02
SEV
1005 B 7 20 TPA
1007 1 0 FE CLC
1009 10 FD
CLV
100B 20 FE BRA 1006
Figure 2-5. Tabular Results of Instructions which Modify CCR Study
Are the results consistent with the descriptions you wrote in PREPARATION 2-2?
4. Program Branches - The Sum of Consecutive Numbers from 1 to N
The algorithm shown in the flow chart in Figure 2-6 adds consecutive numbers from 1 to N
where $01 ≤N≤ $FF. The algorithm uses three memory locations on page $11. The location
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'term' contains the next term to be added to the sum; it is initialized to ‘N’. Two other bytes,
'sum', contain the accumulation of the terms, and, when the algorithm ends, 'sum' will contain
the desired result.
Each time around the loop, 'term' is decremented by 1, and the algorithm ends when 'term'
becomes 0.
Figure 2-6. Algorithm to Add Consecutive Numbers from 1 to N
PREPARATION 2-3. Convince yourself that the routine in Figure 2-6 works by 'walking through
the algorithm' assuming the value initially stored in 'term' is $04.
The program in Figure 2-7 implements the algorithm in Figure 2-6. It is assumed that 'term' is
stored in location $1100, and the 2 byte 'sum' is stored in locations $1101 and $1102.
1000 79 11 01
clr $1101
1003 79 11 02
clr $1102
1006 87
clra
1007 f6 11 00
ldab $1100
100a f3 11 01
addd $1101
100d 7c 11 01
std $1101
1010 73 11 00
dec $1100
1013 26
bne
$1006
1015 27 fe
beq $1015
Figure 2-7. Program to Add Consecutive Numbers from 1 to N
PREPARATION 2-4: Determine the relative address (2 hexadecimal digits) for the BNE
instruction at location $1013. Also convince yourself that the program implements the
algorithm shown in Figure 2-6.
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The addresses of the two CLR instructions at the beginning of the program and the address of
the DEC instruction at location $101D are 2-byte addresses. Besides being able to clear and
decrement accumulator contents, the CLR and DEC instructions can also operate directly on
memory locations. However, they do not have a direct addressing mode. The 2-byte addresses
are called extended addresses.
Enter the program in Figure 2-7 using the Line Assembler (A) command as show below. Recall
that the '$' signs appearing in the listing are not typed with the Line Assembler since all values
are taken to be hexadecimal.
>ASM 1000
1000 xxxxxxxx
CLR 1001 <cr> (The Line Assembler will recognize that CLR takes a 2-byte address.)
1001 xxxxxxxx
CLR 1002 <cr> (The '$' is omitted in Line Assembler values!)
1003 xxxxxxxx
CLRA <cr>
(Continue entering the rest of the instructions.)
:
:
1015 BEQ $1015 <cr>
Check that the program is correct using the ASM command. Check the machine code
hexadecimal values using the Memory Examine and Modify command (> MM 1000).
First we will find the sum $01 + $02 + ... + $0A. Load the value $0A in location $1100 using the
Memory Examine and Modify (MM) command as follows:
> MM 1100
1100 xx 0A <cr> (.)
Set the program counter to 1000 with the Register Examine and Modify (RM) command and
single-step through the program using the (T) command. The program will get into the infinite
loop, so you will have to reset the EVB by pressing the reset button. Check the values in
locations $1100, $1101, and $1102 using the Memory Examine and Modify command (> MM
1100).
Note that the byte at location $1100 has been decremented to zero. The sum of the
consecutive values are in the next two bytes at locations $1101 and $1102. Does your result
agree with PREPARATION 2-5?
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PREPARATION 2-5: Find the sum $01 + $02 +...+ $0A in hexadecimal. -------Repeat the above procedure to find the sum $01 + $02 +... + $FF by entering $FF at location
$1100. Instead of single-stepping, run the program using the Go (G) command (> G 1000).
Press the reset button and inspect locations $1101 and $1102. They should contain $7F80.
PREPARATION 2-6: The program to add consecutive integers between 1 and N is to be modified
to add only the even numbers between 1 and N. This can be done by adding three instructions
to the original program as indicated in the flow chart below in Figure 2.8.
Convince yourself that this performs the required function, and complete the program outlined
below.
1000 79 1101
CLR $1101
1003 79 1102
CLR $1102
The program to add consecutive integers will now be modified to add consecutive even
integers between 1 and N.
Reenter the addition program with the additional 3 instructions you devised in PREPARATION 26 using the Line Assembler (ASM).
Enter the value $FF at location $1100 and run the program with the GO (G) command. Press the
reset button and record the value you find at location $1101-$1102-----Modify the program (by changing only one statement) so that it adds consecutive odd integers
between 1 and N.
Enter the value $FF at location $1100 and rerun the program and record the value you now find
at location $1101-$1102---Do these two values sum to $7F80? They should.
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Figure 2.8 Flowchart for Adding Consecutive Even Numbers
5. Signed Addition
Enter and check the program listed in Figure 2-9 using the Line Assembler (A) command. The
hexadecimal values correspond to the base 10 numbers given in PREPARATION 2-7.
Execute the program one instruction at a time. First set the program counter to $1000 with the
Register Examine and Modify (R) command, then use the next step (N) command. As you step
through the program, write the value of accumulator A and the NZVC flags in the spaces
provided.
A
N Z V C
1000 86 43 LDAA #$43
1002 8B 19 ADDA #$19
1004 86 BD LDAA #$BD
1006 8B E7 ADDA #$E7
1008 86 BD LDAA #$BD
100A 8B 19 ADDA #$19
100C 86 43 LDAA #$43
100E 8B 41 ADDA #$41
1010 86 BD LDAA #$BD
1012 8B BF ADDA #$BF
1014 86 43 LDAA #$43
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1016 8B E7 ADDA #$E7
1018 20 FE BRA $1018
Figure 2-9. Tabular Results of Instructions which Modify CCR Study
Use this to confirm the results of PREPARATION 2-7.
PREPARATION 2-7. When the 68HC12 executes an add instruction, it adds two numbers as if
they were unsigned. If the programmer intends the numbers to be signed, then he is obliged to
check the results and take whatever action is necessary if the result is not correct.
The Condition Code Register, especially the V flag, is necessary to make this decision.
Below are 6 addition problems. If either or both of the numbers to be added can be taken as
negative (the most significant bit is 1) two additions are given.
Carry out the additions in binary, and write what the NZVC flags would be immediately after the
microprocessor adds them. You will find the discussion in Part 2 of this exercise useful in
determining the flag settings.
4316 01000011
1916 00011001
----- -----------------------16
16
NZVC
or
or
16
NZVC
4316
4116
-----
BD16
E716
-----
-4316 10111101
-1916 11100111
----- -----------16
BD16 or -4316
1916
1916
---------16
16
NZVC
01000011
01000001
------------
BD16
BF16
----16
10111101
00011001
-------------------
NZVC
or
or
-4316 10111101
-4116 10111111
----- -----------16
NZVC
4316 or 4316
E716 or -1916
---------16
01000011
11100111
------------
16
NZVC
Check that the following statements are true:
1. FOR UNSIGNED ADDITION, the result is correct provided the carry bit is taken as the 9th bit of
the sum.
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2. FOR SIGNED ADDITION:
i) If the two operands are both positive, then the result will be correct only if the sum is
between 0 and +127. The V-flag indicates when the result is incorrect.
ii) If the two operands are both negative, then the result will be correct only if the sum is
between -128 and -1. The V-flag indicates when the result is incorrect. If the two operands are
both negative, there is always a carry which should be neglected in determining the sum.
iii) If the operands are of opposite sign, the result will always be correct. The V-flag will always
be '0'. If the result is positive, the C-flag will be 1; if the result is negative, the C-flag will be 0.
The C-flag should be disregarded in interpreting the sum.
6. Multiple Precision Addition
PREPARATION 2-8. Perform the following addition. The values are hexadecimal.
A67295
+ 71638A
The following program illustrates the use of the Add With Carry instruction to perform multiple
precision addition. In particular, it adds two 3-byte hexadecimal values, storing the sum in
memory:
1000 b6 11 02
LDAA
$1102
1003 bb 11 05
ADDA
$1105
1006 7a 11 09
STAA
$1109
1009 b6 11 01
LDAA
$1101
100c b9 11 04
ADCA
$1104
100f 7a 11 08
STAA
$1108
1012 b6 11 00
LDAA
$1100
1015 b9 11 03
ADCA
$1103
1018 7a 11 07
STAA
$1107
101b 86 00
LDAA
#$00 (note immediate
101d 89 00
ADCA
#$00 mode addressing)
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101f 7a 11 06
1022 20 fe
STAA
BRA
$1106
$1022
Enter the program and check it using the Line Assembler (A) command.
Enter the two numbers to be added with the Memory Examine and Modify (MM) command as
follows:
> MM 1100
1100 xx A6 xx 72 xx 95 xx 71 xx 63 xx 8A xx <cr> <.>
Execute the program using the Go (G) command.
Press reset and use Memory Examine and Modify (MM) command (> MM 1100) to check your
results.
Do your results agree with PREPARAT1ON 2-8?
7. Multiple Precision Subtraction
PREPARATION 2-9. Perform the following subtractions. The values are hexadecimal.
A73B
A73B
A73B
-212A
-295A
-321A
The following program illustrates the use of the Subtract and Subtract With Carry (Borrow)
instructions to perform multiple precision subtraction. It subtracts two 2-byte hexadecimal
values, storing the difference in memory:
1000 b6 11 01
LDAA
$1101
1003 b0 11 03
SUBA
$1103
1006 7a 11 05
STAA
$1105
1009 b6 11 00
LDAA
$1100
100c b2 11 02
SBCA
$1102
100f 7a 11 04
STAA
$1104
1012 20 fe
BRA
$1012
Enter the program and check it using the Line Assembler (ASM) command.
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Place a breakpoint at location $1012.
Enter the two first two numbers to be subtracted in PREPARATION 2-9 ($A73B and $212A) with
the Memory Examine and Modify (MM) command.
Execute the program using the Go (G) command.
What is the value of the carry flag when the program displays the register contents?
Use the Memory Examine and Modify (MM) command (> MM 1000) to check the results.
Do your results agree with PREPARATION 2-9?
Enter the two numbers for the next subtraction in PREPARATION 2-9 with the Memory Examine
and Modify (MM) command, and execute the program.
What is the value of the carry flag now?
Do this for the two numbers for the last subtraction in PREPARATION 2-9.
What is the value of the carry flag now? How come?
REFLECTIONS
1. Classification of the branch instructions
The branch instructions fall roughly into four classes:
i) unconditional branches,
ii) branch instructions depending on a single flag in the CCR,
iii) branch instructions depending on the relation between unsigned values,
iv) branch instructions depending on the relation between signed values.
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The unconditional branches are BRA (Branch Always) and BRN (Branch Never). Why should a
Branch Never (which does nothing) be included in the instruction set?
Branch instructions depending on a single CCR flag are:
Flag N
Z
V
C
0
BPL
BNE BVC BCC
1
BMI BEQ BVS BCS
Branch instructions depending on the relation between values are summarized in the following
table. The top row is for unsigned integers, and the bottom row is for signed integers.
Branching for the given branch instructions would occur if the relations are those following, for
example, this sequence of instructions:
LDAA #YY
CMPA #XX
Bxx
…
Unsigned
Signed
BLO
BLT
BLS
BLE
BEQ
BEQ
BNE
BNE
BHS
BGE
BHI
BGT
Convince yourself that these are true by working out some typical examples using actual
numerical values and checking the resulting CCR flag settings with branching conditions of the
various branch instructions.
Note that the BEQ and BNE instructions are in both the branch instructions depending on a
single flag and in the branch instructions depending on the relation between two values. Also,
even though the mnemonics are different, the BLO and BCS are equivalent instructions since
they each branch if and only if the carry is set. The same is true for the BHS and the BCC
instructions. They each branch if and only if the carry is clear.
2. Branching Further than Relative Addressing Allows
The branch instructions can be arranged in pairs such that they branch on inverse conditions as
demonstrated by the following table.
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Suppose you wanted to do a relative branch to an instruction which is located more than 127 or
so bytes possible with a relative address. It could be done by using a JMP instruction and the
inverse condition. For example, the following two code segments do the same thing (except
that the instruction with label "HERE" can be anywhere in memory in the second case).
BNE HERE
CLRB
:
HERE LDAA
OVER
HERE
BEQ OVER
JMP HERE
CLRB
:
LDAA...
Convince yourself that the above works.
How could you branch more than 127 bytes just using relative branch instructions (without the
JMP)?
3. Caution
The multiple precision addition program in Part 8 won't work properly if the LDAA #$00
instruction at location $101B is replaced with CLRA.
Why not? After all, both instructions do the same thing (put $00 in accumulator A). What's the
moral?
4. Negating a Multiple Precision Number
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The sign of a single byte hexadecimal value can be changed by using the NEG instruction which
takes the 2's complement of a number.
Suppose there is a multiple precision number in memory stored in 3 consecutive bytes, msb
first (as in Part 8 of this exercise). Write a sequence of instructions that generates the negative
of this 3-byte number.
What would you get if you negate the byte 00000516?
FFFFFF16?
00000016?
5. How the Microprocessor Executes Extended Addressing Mode Instructions
Study the contents of chapter 3 (The Central Processing Unit) in the recommended textbook; in
particular study the sequences of the sample program which show how the microprocessor
adds two bytes in memory and stores the sum using extend addressing, and note how the
address bus is used to access data stored in memory.
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