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# © 2018 Synopsys, Inc. All rights reserved. # # This script is proprietary and confidential information of Synopsys, Inc. and may be used and # # disclosed only as authorized per your agreement with Synopsys, Inc. controlling such use and disclosure. #######################################################################################################################
# # Synopsys Customer Education Services
# # Synthesis : Certification Program # # Version 1.0, 2018
# # Developed by DG Team #######################################################################################################################
DESIGN COMPILER LAB
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Folder: LAB1_DC_synthesis_flow
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Description:
In this folder you will be analyzing the existing Synthesis run results on Leon3mp design targetted at 200MHz
It contains the following files and folders.
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rm_setup/common_setup.tcl: This script contains common design setup variables for the reference methodologies rm_setup/dc_setup.tcl : This script contains library and variable setup for Design Compiler Reference Methodology
rm_setup/dc_setup_filenames.tcl : This script contains pointers to all file names needed to run Design Compiler
rm_dc_scripts/load_compiled_design.tcl : This script is used to load the compiled ddc file and run the task1
README : This file contains the instructions required to execute placement stage.
clean.tcl : This file has the shell "remove" command to delete the unneccessary files before the start of this stage
run.tcl: This file contains the activities needed to complete task1. ========================================================================================================================
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Learning Objective:
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The purpose of this lab is to Analyze a compiled design and results on Leon3mp design targetted at 200MHz
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Steps for completing this lab
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1. Open a DC session with preloaded design using DC version 2016.12-SP2:
In DC shell
dc_shell -topo> source ./rm_dc_scripts/load_compiled_design.tcl | tee -i analysis.log
From Unix shell
%> dc_shell -topo -f ./rm_dc_scripts/load_compiled_design.tcl | tee -i analysis.log 2. Complete the tasks provided by filling the appropriate options in run.tcl