Chapter 11
Analog and Mixed-Signal Testing
EE141
VLSI
Test Principles and Architectures
1
Chap. 11 - Analog and Mixed-Signal Testing - P.1
What is this chapter about?
 Introduces AMS
circuits, failure modes
and fault models.
 Addresses
analog testing, including DC
and AC parametric testing.
 Discusses
mixed-signal circuits, ADC
and DAC, and their testing approaches.
 Studies
IEEE Std. 1149.4, the standard
for mixed-signal test buses
EE141
VLSI
Test Principles and Architectures
2
Chap. 11 - Analog and Mixed-Signal Testing - P.2
Chapter 11
Analog and Mixed-Signal Testing
 Introduction
 Analog
Circuit Testing
 Mixed-Signal Testing
 IEEE Std. 1149.4 Standard for MixedSignal Test Bus
 Concluding Remarks
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Test Principles and Architectures
3
Chap. 11 - Analog and Mixed-Signal Testing - P.3
11.1 Introduction
 Analog
Circuit Properties
 Analog Defect Mechanism and Fault
Models
EE141
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4
Chap. 11 - Analog and Mixed-Signal Testing - P.4
Analog, Digital, and Mixed-Signal Signals
1
0
Analog
Mixed-Signal
EE141
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Digital
5
Chap. 11 - Analog and Mixed-Signal Testing - P.5
Analog Circuit Properties
 Continuous
Signal
 Large Range of Circuits
 Nonlinear Characteristics
 Feedback Ambiguity
 Complicated Cause-Effect Relationship
 Absence of Suitable Fault Model
 Accurate Measurements Required
EE141
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6
Chap. 11 - Analog and Mixed-Signal Testing - P.6
Properties - Continuous Signal
Digital Signal
Analog Signal
VOV
VH
SR
VA
VL
tLH
tHL
• Logic 1, Logic 0
• VIH, VIL, VOH, VOL
• Rise Time, Fall Time
• Propagation Delay H-L/L-H
• Noise Margin High/Low
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tSettle
• Voltage/Current
• Slew Rate
• Overshoot
• Damping Factor
• Frequency
• Bandwidth
7
Chap. 11 - Analog and Mixed-Signal Testing - P.7
Properties - Large Ranges of Circuits
Digital Circuits
• Operation
• Static Logic
• Dynamic Logic
• Structure
• Gates
• PLA
• Memory
EE141
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Analog Circuits
• Operation
• Current Mode
• Voltage Mode
• Switching Cap
• Structure
• Amplifier
• Multiplier
• Rectifier
• Resonator
8
Chap. 11 - Analog and Mixed-Signal Testing - P.8
Properties- Nonlinear Characteristics
 Analog
circuits are nonlinear in nature
 Nonlinear
cause effect
V D / nVT
ID  Is  e
ID 
1
W
Cox (Vgs  Vt )2
2
L
ID
VD
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Test Principles and Architectures
9
Chap. 11 - Analog and Mixed-Signal Testing - P.9
Properties- Feedback Ambiguities
 Feedback
puts circuit parameters together
 Difficult to identify fault location
+
+
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10
Chap. 11 - Analog and Mixed-Signal Testing - P.10
Properties- Complicated Cause-Effect Relationship
 Difficult
to determine the cause of error.
V0
R2
AV 

Vi
R1
V0
A
A 

A
Vi
(1  ) R1
R2
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11
Chap. 11 - Analog and Mixed-Signal Testing - P.11
Properties – Absence of Suitable Fault Models
Digital Faults
• Good Logic Fault Model
• Generally Accepted
• Stuck-at-1, Stuck-at-0
• Stuck-Open, Stuck-On
• Short. Open
• Memory Faults
• PLA Faults
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Chap. 11 - Analog and Mixed-Signal Testing - P.12
Properties - Absence of Suitable Fault Models
Analog Faults
• No Good Fault Model
• Not Generally Accepted
• Open Short
• Missing/Extra Devices
• Parameter Variation
• Performance Deviation
• Circuit Structure Related
• Functional Faults
• ???????????
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13
Chap. 11 - Analog and Mixed-Signal Testing - P.13
Properties – Accurate Measurements Required
Digital Instrument
• Oscilloscope
• Function Generator
• Logic Analyzer
• Frequency Counter
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Chap. 11 - Analog and Mixed-Signal Testing - P.14
Analog Instrument
Properties – Accurate Measurements Required
•
•
•
•
•
•
•
•
•
•
•
EE141
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Test Principles and Architectures
Oscilloscope
Function Gen
Freq. Counter
Spectrum Analyzer
Network Analyzer
Impedance Analyzer
Timing Analyzer
Communication Analyzer
RF Instrument
Optical Instrument
Microwave Instrument
15
Chap. 11 - Analog and Mixed-Signal Testing - P.15
11.1 Introduction
 Analog
Circuit Properties
 Analog Defect Mechanism and Fault
Models
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Chap. 11 - Analog and Mixed-Signal Testing - P.16
Defect Mechanisms (1)
 Material




Defects
cracks
crystal imperfection
surface impurities
ion migration
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Test Principles and Architectures
 Processing
Faults






oxide thickness
mobility change
impurity density
diffusion depth
dielectric constants
metal sheet
resistance
 missing contacts
 dust
17
Chap. 11 - Analog and Mixed-Signal Testing - P.17
Defect Mechanisms (2)
 Time-Dependent
Failures
 dielectric breakdown
 electron migration
 Packaging
Failures
 contact degradation
 seal leakage
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Chap. 11 - Analog and Mixed-Signal Testing - P.18
Analog Fault Model
Defects/Failure
Hard Faults Soft Faults
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Chap. 11 - Analog and Mixed-Signal Testing - P.19
Analog Faults - Defect
• Defects
• Extra Defects
• Etching Defects
• Source
• Dust
• Lithography
• Layout Oriented
• Statistical Model
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Chap. 11 - Analog and Mixed-Signal Testing - P.20
Analog Faults - Hard Faults
• Fault Models
• Open
• Short
• Missing Device
• Extra Devices
• Faulty Effects
• Catastrophic Error
• Module Malfunction
• System Failure
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Chap. 11 - Analog and Mixed-Signal Testing - P.21
Analog Faults - Soft Faults
• Parametric Faults
• Io: 100uA -> 50uA
• W: 20um -> 10um
• Deviation Faults
• fo: 10MHz -> 5MHz
• Gain: 10000 -> 2000
• Sources
• Mobility
• Oxide Thickness
• Impurity Density
• Defusion Depth
• Dielectric Constants
• Metal Sheet Resistance
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Chap. 11 - Analog and Mixed-Signal Testing - P.22
Analog Fault - Model Mapping
Functional Level
Circuit Level
Layout Level
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 Deviation
Faults
 Parametric
Faults
 Extra
Defects
 Etching Defects
23
Chap. 11 - Analog and Mixed-Signal Testing - P.23
Analog Faults - Model Mapping
Layout to Parametric
• Defect Statistics
– Randomly insert dusts of
random size.
• Parameter Statistics
– Simulate the effect of dust on
transistor parameters
W
K  C ox
L
Ko
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Test Principles and Architectures
24
Chap. 11 - Analog and Mixed-Signal Testing - P.24
Analog Faults - Model Mapping
Parametric to Deviation
• Use SPICE simulation
and statistics to derive
the performance
deviation.
W
K  C ox
L
Ko
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Fto
25
Chap. 11 - Analog and Mixed-Signal Testing - P.25
11.1 Summary

Studied the analog test properties
 Nonlinearity, Feedback Ambiguity
 No good fault model

Overview the analog test plan
 Test Code, Binning, Sequence Control
 Focused Calibrations, DIB Checkers
 Characterization and Simulation Code

Analog Fault Model
 Extra and Etching Defects
 Parametric and Deviation faults
 Model Mapping
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Test Principles and Architectures
26
Chap. 11 - Analog and Mixed-Signal Testing - P.26
11.2 Analog Circuit Testing
 Analog
Test Approaches
 Analog Test Waveforms
 DC Parametric Testing
 AC Parametric Testing
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Chap. 11 - Analog and Mixed-Signal Testing - P.27
Analog Testing
Spec
Oriented
Waveform
Oriented
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Chap. 11 - Analog and Mixed-Signal Testing - P.28
Specification Oriented Test
Analog Devices, Inc.TM
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Chap. 11 - Analog and Mixed-Signal Testing - P.29
Specification Oriented Test
 Specification Oriented Test
Check whether all the specs are met
Tedious and inflexible
 Example: Operational Amplifier
DC Specifications
–Input Offset Voltage
–Input Bias Offset Current
–Open-Loop Gain
–Noise
–Common Rejection Ratio
–Temperature Drift
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 AC Specifications
– Bandwidth
– Harmonic Distortion
– Slew Rate
– Settling Time
– Noise
30
Chap. 11 - Analog and Mixed-Signal Testing - P.30
Waveform Oriented Test
 Waveform
Oriented Test
 Compare waveform to the simulated ones
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Chap. 11 - Analog and Mixed-Signal Testing - P.31
Waveform Oriented Test
C
B
D
A
A
B
C
D
DC Bias, Input Offset
Slew Rate, Damping Factor
Overshoot, Damping Factor, Bandwidth
Settling Time, DC Gain
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Chap. 11 - Analog and Mixed-Signal Testing - P.32
Analog Testing - Comparison
 Specification




Require more test runs and time
Require accurate instrument
Specifications are guaranteed
Low defect level
 Waveform




Oriented Test
Oriented Test
Less test runs and test time
More forgiving on instrument
Specifications are not guaranteed
Low cost
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.33
11.2 Analog Circuit Testing
 Analog
Test Approaches
 Analog Test Waveforms
 DC Parametric Testing
 AC Parametric Testing
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Test Principles and Architectures
34
Chap. 11 - Analog and Mixed-Signal Testing - P.34
Analog Test Waveforms
Sine
Square (Step)
Ramp
Chirp (Sweep Sine) Arbitrary
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Triangular
Modulated
35
Chap. 11 - Analog and Mixed-Signal Testing - P.35
Waveform - Step
 For
transient response testing
 Application: Filter, OPs, VCO, etc
 Difficult to generate good steps
Tr
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Test Principles and Architectures
  45o ~ 60 o
1
f 
( 4 ~ 3)Tr
1
f 
3.5Tr
36
Chap. 11 - Analog and Mixed-Signal Testing - P.36
Waveform - Step
 Step
change in voltage: Transient testing
 Step change in frequency: PLL testing
 Step change in amplitude: AGC testing
Voltage Step
Frequency Step
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Amplitude Step
37
Chap. 11 - Analog and Mixed-Signal Testing - P.37
Waveform - Ramp
 Triangular
Wave Generation
+
 Sawtooth
Wave Generation
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Chap. 11 - Analog and Mixed-Signal Testing - P.38
Waveform - Chirp
 Also
called Sweep Sine
 Generation: Triangular to VCO
 Application: Frequency response plotting
VCO
Chirp
+
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.39
Waveform - Chirp
 Application:
Frequency response plotting
VCO
+
-
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Test Principles and Architectures
CUT
Filter
LPF
40
Chap. 11 - Analog and Mixed-Signal Testing - P.40
Waveform - Arbitrary
 Synthesized
by DACs
 Combinations of all kinds of waveform
DAC
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LPF
41
Chap. 11 - Analog and Mixed-Signal Testing - P.41
Waveform - Modulated/Synthesized
 Modulated/Synthesized
Waveforms
 Communication System Testing
–GSM, CDMA, 1394, USB2, etc.
 Modulation
–AM, FM, PCM, PWM, QAM, PSK, QPSK
 Generated
by dedicated instrument
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42
Chap. 11 - Analog and Mixed-Signal Testing - P.42
11.2 Analog Circuit Testing
 Analog
Test Approaches
 Analog Test Waveforms
 DC
 AC
Parametric Testing
Parametric Testing
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Chap. 11 - Analog and Mixed-Signal Testing - P.43
DC Parametric Testing
Rated output current
Open-loop gain
Unity gain full power
response
Overload recovery
Input offset voltage
Rated output voltage
Slewing rate
Unity gain small signal
response
Input bias current
Input offset current
Input noise
Supply voltage sensitivity
Maximum voltage between
inputs
Temperature drift
Input impedance
Common mode rejection
Maximum common mode
voltage
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Source: [Sata 1967]
44
Chap. 11 - Analog and Mixed-Signal Testing - P.44
DC Test – Open-Loop Gain Measurement
f 3dB
Vx
Ao  101 
V y
Ao  101 
80
60
40
10K
10K
Ao
20
101
V x
V y
 6dB / Octave
102
103
104
ft
105
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106
100
Vi
Vy
Vx
10K
100
Vo
RL 
Io
45
Chap. 11 - Analog and Mixed-Signal Testing - P.45
DC Test – Unit Gain Bandwidth Measurement
f t  Ao  f 3dB
Vy
SR
Vi 
2ft
Vy
Vx
V
Rf  o
Io
100
Rf
SR
Vi 
2f t
Inverting Configuration
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Vx
100
1k
SR
Vi 
2f t
V
RL  o
Io
Noninverting Configuration
46
Chap. 11 - Analog and Mixed-Signal Testing - P.46
DC Test – Common Mode Rejection Ratio
VCM
Vo
100
R2
R1
VCM
R1
R2
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VCM i
Vo
R2

 Vo /
Ao
R1
Vo
CMRR  20 log( Ao /
)
VCM
47
Chap. 11 - Analog and Mixed-Signal Testing - P.47
DC Test – Power Supply Rejection Ratio
Vo
PSRR  20 log( Ao /
)
VDD
VDD
Vo
VDD
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Test Principles and Architectures
48
Chap. 11 - Analog and Mixed-Signal Testing - P.48
11.2 Analog Circuit Testing
 Analog
Test Approaches
 Analog Test Waveforms
 DC Parametric Testing
 AC Parametric Testing
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49
Chap. 11 - Analog and Mixed-Signal Testing - P.49
Analog AC Testing
 Test





Types
Gain
Phase
Distortion
Signal Rejection
Noise
 Test
AWG
CUT
Digitizer
DSP
Setup
 AGW: Arbitrary Waveform Generator (DAC)
 Digitizer: Sample and convert to digital (ADC)
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Chap. 11 - Analog and Mixed-Signal Testing - P.50
AC – Maximal Output Amplitude
Input sine wave (1KHz) with fixed amplitude
 Digitize the output waveform
 DSP (FFT) to eliminate distortion and noise.
 Check the fundamental amplitude.
 Detect first order defects in a circuit.
 Voltage in dBV or dBm

AWG
DUT
Digitizer
DSP
Clipped
VPP
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.51
AC - Frequency Response
LPF
Low Pass Filter
BPF
Band Pass Filter
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HPF
High Pass Filter
BRF
Band Reject Filter
52
Chap. 11 - Analog and Mixed-Signal Testing - P.52
AC - Frequency Response
40
Bode Plot
10 (1 
2
A( jw ) 
(1 
jw
10
2
)(1 
-20dB/dec
20
jw
10
A (dB)
)
6
0
jw
10
4
-20
-40dB/dec
-40
101 102 103 104 105 106 107
)
0
• Open Loop Gain
102
• Pole 1: 102
• Pole 2: 104
• Zero: 106
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Phase
-20dB/dec
-45
-90
-45/dec
-135
45/dec
-180
53
Chap. 11 - Analog and Mixed-Signal Testing - P.53
AC - Frequency Response
A(dB)
Pass Band Ripple
Stop Band
Rejection
Stop Band
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Stop Band
Rejection
Pass Band
Stop Band
54
F
Chap. 11 - Analog and Mixed-Signal Testing - P.54
AC - Frequency Response
A(dB)
Upper Limit
Mask
Lower Limit
Mask
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F
Chap. 11 - Analog and Mixed-Signal Testing - P.55
AC - Frequency Response
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Frequencies of
special interests
56
Chap. 11 - Analog and Mixed-Signal Testing - P.56
AC - Frequency Response
• Multi-tone Test Waveform
i k
A(t )   Ai sin(  i t  i )
i 1
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.57
AC - Frequency Response
• Multi-tone Test Waveform
i k
A(t )   Ai sin(  i t  i )
i 1
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.58
AC – Noise and Distortion
• Distortion
• Harmonic Distortion
• Intermodulation Distortion
• Crossover
• Cause
• Nonlinearity of the circuit
• Clip (saturation)
• Mismatch of the devices
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.59
AC – Noise and Distortion
• Apply sinusoidal waveform
• Do Fourier transform on response waveform
• Obtain F domain properties mathematically.
Filter
dB
FFT
Analysis
Fundamental
Offset
Peak Harm.
Noise Flour
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.60
AC – Noise and Distortion
THD  10 log
F2
2
 Hi
 100 
F2
2
 Hi
%
SNR  10 log
F2
SNDR  10 log
dB
Fundamental
F
Noise
2
 Ni
F2
2
2
 H i   Ni
Harmonics
DC
Offset
Ni
H2
H3
H4
H5
F
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.61
AC – Intermodulation Distortion
v(t )  A1 sin 2f1t  A2 sin 2f 2t
f1 f2
f1 f2
7 8
f2 – f1
0
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Test Principles and Architectures
2
4
6
f1 + f2
2f 2 – f 1
2f 1 – f 2
8
10
12
2f 1
2f 2
14
16
3f 1
18
20
3f 2
22
62
24
Chap. 11 - Analog and Mixed-Signal Testing - P.62
11.2 Summary
 Studied
the analog test approaches
 Specification oriented testing
 Waveform oriented testing
 Outlined
the analog test waveforms
 Sine, step, triangular, chirp, arbitrary, modulated
 Discussed
DC parametric testing
 Open-loop gain, unit gain bandwidth
 CMRR, PSRR
 Discussed AC
parametric testing
 Use AWG, Digitizer, and DSP
 Frequency response, Noise, and Distortion
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.63
11.3 Mixed-Signal Testing
 Introduction
to Analog-Digital Conversion
 ADC and DAC Circuit Structure
 ADC/DAC Specification and Fault Models
 IEEE Std. 1057
 Time-Domain ADC Testing
 Frequency-Domain ADC Testing
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.64
AD Model - Quantization
12
11
10
9
8
7
6
5
4
3
2
1
0
X out LSBs
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4
3
2
1
1
X in
2
3
4
X in
Chap. 11 - Analog and Mixed-Signal Testing - P.65
Quantizatoin – Noise Model
• Quantization error is sawtooth-like.
• Uniform distribute between (-q/2, q/2) (q=LSB).
x( t )
Original signal
Quantized signal
q
t
nq ( t )
Quantization error
q/2
q / 2
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Test Principles and Architectures
t
66
Chap. 11 - Analog and Mixed-Signal Testing - P.66
Quantizatoin – Noise Model
• The error contains a lot of jumps.
• Error spectral is much wider than the original signal.
• The bandwidth of the quantization is proportional to
the slop of the signal and inversely proportional to
the quantum size q.
nq ( t )
Quantization error
q/2
t
q / 2
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Chap. 11 - Analog and Mixed-Signal Testing - P.67
Quantization - Noise Model
 A sine
wave is quantized by a B-bit ADC.
How large is the SNR.
Original signal
2V p  2 q
n
Quantized signal
x( t )
q
PS 
V p2
t
2
q
 2
PN  
 3

2


q2
 
12


nq ( t )
Quantization error
q/2
q / 2
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t
68
Chap. 11 - Analog and Mixed-Signal Testing - P.68
Quantization - Noise Model
 V p2



Ps
SNR  10 log
 10 log 2 2   10 log( 6  4n 1)
PN
q


12 

SNR  (1.76  6n)dB
For n=10,
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SNR  61 .8dB
69
Chap. 11 - Analog and Mixed-Signal Testing - P.69
11.3 Mixed-Signal Testing
 Introduction
to Analog-Digital Conversion
 ADC and DAC Circuit Structure
 ADC/DAC Specification and Fault Models
 IEEE Std. 1057
 Time-Domain ADC Testing
 Frequency-Domain ADC Testing
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Test Principles and Architectures
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Chap. 11 - Analog and Mixed-Signal Testing - P.70
ADC Architecture - Gain Stage
Gain
Filter
MUX
S/H
A
D
C
Gain: Provide offset and full scale conversion
 Filter: Reject off-band noise (anti-aliasing filter)
 MUX: Provide multiple channel access
 S/H: Provide steady signal for A-to-D conversion
 ADC: Actual analog to digital conversion

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Chap. 11 - Analog and Mixed-Signal Testing - P.71
ADC Architecture - Gain Stage
Gain
Filter
MUX
S/H
A
D
C
Function: Provides gain and offset
 Achieve the maximal A/D resolution by scaling the
input signal to match the full A/D input range.
 Drawbacks:

 Introduces noise, nonlinearity, drift
 Expense of tight-tolerance
 Require calibration
EE141
VLSI
Test Principles and Architectures
72
Chap. 11 - Analog and Mixed-Signal Testing - P.72
ADC Architecture - Filter Stage
Gain
Filter
MUX
S/H
A
D
C
Function: Attenuate the out-of-band noise to
prevent aliasing
 Filter Position

 Before the MUX (1 per channel) : maximize speed in
switching channels.
 After the MUX: minimize mismatching among channels.
EE141
VLSI
Test Principles and Architectures
73
Chap. 11 - Analog and Mixed-Signal Testing - P.73
ADC Architecture - Filter Stage
 Anti-Aliasing
A(w)
Signal
Spectrum
Filter
A(w) Anti Aliasing Filter
Nyquist Rate
Sampling
EE141
VLSI
Test Principles and Architectures
A(w)
Anti Aliasing Filter
4X Over
Sampling
74
Chap. 11 - Analog and Mixed-Signal Testing - P.74
ADC Architecture - MUX Stage
Gain
Filter
MUX
S/H
A
D
C
Function: Provides multiple access
 Crosstalk:

 The most severe problem
 Frequency dependent
 Can be minimized by placing amplifier before the MUX.

Load Issues
 Avoid too many fanins.
 Use hierarchical structure.
EE141
VLSI
Test Principles and Architectures
75
Chap. 11 - Analog and Mixed-Signal Testing - P.75
ADC Architecture - S/H Stage
Gain

Filter
MUX
Function:
S/H position:
S/H
S/H
 After the MUX for cost reason
 Before MUX for synchronization
and crosstalk reduction.
EE141
VLSI
Test Principles and Architectures
S/H
S/H
 Provides steady signal
 Provides signal synchronization,

A
D
C
M
U
X
S/H
76
Chap. 11 - Analog and Mixed-Signal Testing - P.76
ADC Architecture - S/H Check List
Aperture Time: The time aperture (t3)
 Acquisition Time: The total time for the S/H to
acquire a full-scale step input signal. (t3 - t1)
 Aperture Jitter: The uncertainty of aperture time due to
noise or jitter in clock. (t4-t2)

S
Vin
R
I leak
Vdroop 
CH
Vc
Vc  X %  LSB
CH
EE141
VLSI
Test Principles and Architectures
t1
t 2 t3 t 4
Sample
Hold
77
Chap. 11 - Analog and Mixed-Signal Testing - P.77
ADC Architecture - ADC Stage
Gain
Filter
MUX
S/H
A
D
C
Executes
analog to digital conversion
Check List:




Bit length
Accuracy
Conversion Rate
System Error Budget
EE141
VLSI
Test Principles and Architectures
▪
▪
▪
▪
Input Signal Range
Total System Cost Target
Input Impedance
AC or DC Inputs BW
78
Chap. 11 - Analog and Mixed-Signal Testing - P.78
DAC Example - R-2R Ladder
R
R
R
R
R
2R
2R
2R
2R
2R
2R
Vref
2R
S1
Vo  S5 
Vref
1
2
5
S2
 S4 
S3
Vref
2
2
4
S4
 S3 
3
S5
Vref
2
3
Rf=R
+
S6
 S2 
2
Vref
2
 S1 
4
1
Vref
Vout
5
 S0 
0
Vref
2
 ( S5  2  S 4  2  S3  2  S 2  2  S1  2  S0  2 ) 
EE141
VLSI
Test Principles and Architectures
Vref
26
26
79
Chap. 11 - Analog and Mixed-Signal Testing - P.79
ADC Example – Pipelined ADC
S/H
Vi
s1
ADC
X4
S/H
da1
DAC
s2
ADC
3 bits
3 bits
X4
X4
S/H
da2
DAC
S/H
s4
da3
s3
ADC
DAC
ADC
2 bits
3 bits
Calibration and Correction Circuit
d0
EE141
VLSI
Test Principles and Architectures
d7
80
Chap. 11 - Analog and Mixed-Signal Testing - P.80
ADC – Bits v.s. Throughput
ADC
Bit-Length
Throughput
Flash
~ 6 bits
100 M ~
Pipelined
8 ~ 16 bits
10 ~ 100 MHz
Sigma-Delta
14 ~ bits
~ 10 M
EE141
VLSI
Test Principles and Architectures
81
Chap. 11 - Analog and Mixed-Signal Testing - P.81
ADC – Selection Matrix
17+
14-16
12-13
10-11
8-9
<8
Bits
<10kbps
10Kbps to 100Kbps
100Kbps to 1Mbps
1Mbps to
10Mbps
10 to
100Mbps
100Mbps
+
From Analog Devices Inc.
EE141
VLSI
Test Principles and Architectures
82
Chap. 11 - Analog and Mixed-Signal Testing - P.82
ADC –
Example
AD775
EE141
VLSI
Test Principles and Architectures
83
Chap. 11 - Analog andFrom
Mixed-Signal
- P.83
Analog Testing
Devices
Inc.
11.3 Mixed-Signal Testing
 Introduction
to Analog-Digital Conversion
 ADC and DAC Circuit Structure
 ADC/DAC Specification and Fault Models
 IEEE Std. 1057
 Time-Domain ADC Testing
 Frequency-Domain ADC Testing
EE141
VLSI
Test Principles and Architectures
84
Chap. 11 - Analog and Mixed-Signal Testing - P.84
ADC – Offset Error
• Offset: constant component of the error that is
independent of the inputs
X out
X in
Offset
EE141
VLSI
Test Principles and Architectures
85
Chap. 11 - Analog and Mixed-Signal Testing - P.85
ADC – Gain Error
• Gain Error: difference between the actual
transfer ratio and the ideal ratio
• Also called Calibration Error
X out
X in
EE141
VLSI
Test Principles and Architectures
86
Chap. 11 - Analog and Mixed-Signal Testing - P.86
ADC – Nonlinearity Error
• Nonlinearity error: The deviation of the output
quantity from a specified linear reference
X out
X in
EE141
VLSI
Test Principles and Architectures
87
Chap. 11 - Analog and Mixed-Signal Testing - P.87
ADC – Nonlinearity Error
• Integral Nonlinearity:
Worst-case deviation
from the ideal transfer
characteristic curve
• Differential Nonlinearity:
Difference between the
actual transfer ratio and
the ideal ratio
EE141
VLSI
Test Principles and Architectures
IN = 2 LSB
DN = 0.5 LSB
88
Chap. 11 - Analog and Mixed-Signal Testing - P.88
ADC – Temperature-Dependent Error
• Temperature-Dependent Error: Due to the
change in ambient temperature or temperature
variation due to self-heating (temperature stability,
temperature coefficient)
X out
T3
T2
T1
X in
EE141
VLSI
Test Principles and Architectures
89
Chap. 11 - Analog and Mixed-Signal Testing - P.89
ADC – Load-Dependent Error
• Load Error: Loading error is due to the effect of a
load impedance upon the converter or signal source
driving it.
RL1
X out
RL1
RL1
RL2
X in
EE141
VLSI
Test Principles and Architectures
90
Chap. 11 - Analog and Mixed-Signal Testing - P.90
ADC – Hysteresis Error
• Hysterisis Error: The difference between
the increasing and decreasing input values
that produce the same output
X out
X in
EE141
VLSI
Test Principles and Architectures
91
Chap. 11 - Analog and Mixed-Signal Testing - P.91
ADC – Resolution Error
• Resolution Error: The error due to the inability to
respond to change of a variable smaller than a given
increment
X out
X in
EE141
VLSI
Test Principles and Architectures
92
Chap. 11 - Analog and Mixed-Signal Testing - P.92
ADC – Missing Code Error
Ideal Input Waveform
Quantized with missing Code
Missing Codes
Quantization Error
EE141
VLSI
Test Principles and Architectures
93
Chap. 11 - Analog and Mixed-Signal Testing - P.93
11.3 Mixed-Signal Testing
 Introduction
to Analog-Digital Conversion
 ADC and DAC Circuit Structure
 ADC/DAC Specification and Fault Models
 IEEE Std. 1057
 Time-Domain ADC Testing
 Frequency-Domain ADC Testing
EE141
VLSI
Test Principles and Architectures
94
Chap. 11 - Analog and Mixed-Signal Testing - P.94
IEEE 1057 Standard
 Scope
 Covers electronic digitizing waveform
recorders, waveform analyzers and
digitizing oscilloscopes with digital outputs.
 Applies to, but is not restricted to, generalpurpose waveform recorders and
analyzers.
EE141
VLSI
Test Principles and Architectures
95
Chap. 11 - Analog and Mixed-Signal Testing - P.95
IEEE 1057 Standard
 Purpose
 Provides common methods for testing and
terminology for describing the performance
of waveform recorders.
 Benefits users and manufacturers of such
devices.
 Presents many performance features,
sources of error, and test methods.
EE141
VLSI
Test Principles and Architectures
96
Chap. 11 - Analog and Mixed-Signal Testing - P.96
IEEE 1057 – General Information
Model Number
Dimensions and weight
Power Requirement
Environmental conditions (tem., humidity, EMC/EMI, etc.)
Any special or peculiar characteristics
Available options and accessories
Exception to the above parameters where applicable
Calibration interval
EE141
VLSI
Test Principles and Architectures
97
Chap. 11 - Analog and Mixed-Signal Testing - P.97
IEEE 1057 – Minimum Specification
Number of digitizing bits
Input impedance
Sample rates
Analog bandwidth
Memory length
Input signal ranges
EE141
VLSI
Test Principles and Architectures
98
Chap. 11 - Analog and Mixed-Signal Testing - P.98
IEEE 1057 – Additional Specifications
Gain
Fixed error in sample time
Offset
Trigger delay and jitter
Differential nonlinearity
Trigger sensitivity
Integral nonlinearity
Trigger minimum rate of change
Harmonic distortion
Trigger hysteresis band
Spurious response
Trigger coupling to signal
Maximal static error
Crosstalk
Signal to noise ratio
Monotonicity
Effective bits
Hystersis
Peak error
Over voltage recovery
Random noise
Word error rate
Frequency response
Cycle time
Settling time
Common mode rejection ratio
Slew limit
Differential input impedance
Overshoot and precursors
Maximum operating common
Aperture uncertainty
mode signal level
Long-term stability
Transition duration of step response
Maximum common mode signal level
EE141
VLSI
Test Principles and Architectures
99
Chap. 11 - Analog and Mixed-Signal Testing - P.99
IEEE 1057 – Test Methods
General methods
Triggering
Input impedance
Crosstalk
Gain and offset
Monotonicity
Noise
Hysteresis
Analog bandwidth
Overvoltage Recovery
Frequency response
Word Error Rate
Step Response parameters
Cycle Time
Time base errors
Differential Input Specification
Linearity, harmonic distortion, and spurious responses
EE141
VLSI
Test Principles and Architectures
100
Chap. 11 - Analog and Mixed-Signal Testing - P.100
11.3 Mixed-Signal Testing
 Introduction
to Analog-Digital Conversion
 ADC and DAC Circuit Structure
 ADC/DAC Specification and Fault Models
 IEEE Std. 1057
 Time-Domain ADC Testing
 Frequency-Domain ADC Testing
EE141
VLSI
Test Principles and Architectures
101
Chap. 11 - Analog and Mixed-Signal Testing - P.101
Histogram – Code Bins
T[6] 7
245
W[7]
T[6] 6
543
W[6]
T[5] 5
456
W[5]
T[4] 4
372
W[4]
3
345
W[3]
2
472
W[2]
T[1] 1
529
W[1]
0
302
W[0]
T[3]
T[2]
Code Level
Code Bin
Bin Count H[k]
Code Width W[k]
EE141
VLSI
Test Principles and Architectures
102
Chap. 11 - Analog and Mixed-Signal Testing - P.102
Test Methods - Code Transition Level
Static Test Method
Code Bin
• Start from 2% below the transition level.
• Take a number of samples.
• Adjust the input level until the 50% codes
are greater than k.
T[6] 7
0
T[6] 6
0
T[5] 5
12
T[4] 4
45
3
443
500
2
454
500
T[1] 1
30
0
16
T[3]
T[2]
Samples
64
Precision
45%
EE141
VLSI
Test Principles and Architectures
256
1024 4096
23% 12%
6%
% of rms noise
103
Chap. 11 - Analog and Mixed-Signal Testing - P.103
Test Methods - Code Transition Level
Dynamic Test Method
• Apply full range sine wave
• Calculate the transition level from the bin count
  H c [k  1]
T [k ]  C  A cos

M

T[6] 7
245
T[6] 6
543
T[5] 5
456
T[4] 4
372
3
345
2
472
T[3]
T[2]
•
•
•
•
j
529
A: Amplitude C: Offset
T[1] 1
H[j]: The code count of bin j. H c [ j ]   H [i ]
0
302
i 0
M: Total number of samples
Record Length M and Number of Cycles Mc must not have common term.
EE141
VLSI
Test Principles and Architectures
104
Chap. 11 - Analog and Mixed-Signal Testing - P.104
Test Methods - Gain and Offset
• Apply a slow ramp signal
• Construct the code bin table
Q: ideal width of the code bin
G  T [k ]  Vos   [k ]  Q  (k  1)  T1
T[6]
7
203
T[6]
6
443
5
440
4
435
3
439
2
429
1
447
0
330
T[5]
T[4]
T[3]
T[2]


G 2 1
Vos  T1  Q 2  1  N
 T k 
2  1 k 1
2
G Q
N

N
k 1
 2 N 1

2

 1  T k    T k 
 k 1

k 1


2 N 
2
2 N 1
 1  kT k 
2 N 1
N
2
 Q
EE141
VLSI
Test Principles and Architectures
N

1 2
T[1]
N 1
  T k 
2 N 1
k 1
 2 N 1

2

 1  T k    T k 
 k 1

k 1


2 N 
2 N 1
2
105
Chap. 11 - Analog and Mixed-Signal Testing - P.105
Test Methods - Gain and Offset (Example)
Transfer Curves
Histograms
128
128
Ideal
Gain Error
EE141
VLSI
Test Principles and Architectures
128
128
Offset Error Game/Offset
106
Chap. 11 - Analog and Mixed-Signal Testing - P.106
Test Methods - Nonlinearity
Differential
Nonlinearity
G  W k   Q
Q
G  W k   Q
DNL  max
Q
DNLk  
T[6]
7
203
T[6]
6
443
5
440
4
435
3
439
2
429
1
447
0
330
T[5]
T[4]
T[3]
T[2]
Integral
Nonlinearity
Maximal
Static Error
INL  100
MSE  100
EE141
VLSI
Test Principles and Architectures
max  k 
Q2
N
T[1]
max T k   Q k  1  T1
Q2 N
107
Chap. 11 - Analog and Mixed-Signal Testing - P.107
Test Methods - Sine Wave Fitting
• Try to fit the sine wave to find the gain A’, offset Co,
and phase shift .
• There are matrix based and nonmatrix methods.
 y1, y2 , ym 
yi  Asin oti  Co
y'i  A' sin(ti   )  C
y'i  Asin(ti )  B cos(ti )  C
t1, t2 ,tm 
EE141
VLSI
Test Principles and Architectures
m

Min   ( yi  A costi   B costi   C )2 
i 1

108
Chap. 11 - Analog and Mixed-Signal Testing - P.108
Test Methods - Sine Wave Fitting
Original Signal:
y (t )  Ao sin( ot )  Co
Curve Fitted:
y ' (t )  A sin(t )  B cos(t )  C
Gain Error:
Offset Error:
Phase Error:
Frequency Error:
EE141
VLSI
Test Principles and Architectures
A2  B 2  Ao
Ao
C  Co
1
B
  tan   
 A
(   o )
o
109
Chap. 11 - Analog and Mixed-Signal Testing - P.109
11.3 Mixed-Signal Testing
 Introduction
to Analog-Digital Conversion
 ADC and DAC Circuit Structure
 ADC/DAC Specification and Fault Models
 IEEE Std. 1057
 Time-Domain ADC Testing
 Frequency-Domain ADC Testing
EE141
VLSI
Test Principles and Architectures
110
Chap. 11 - Analog and Mixed-Signal Testing - P.110
ADC – Frequency Domain Testing
• Similar to Analog AC Testing
• Apply sinusoidal waveform
• Do Fourier transform on response waveform
• Obtain F domain properties mathematically.
Filter
dB
FFT
Analysis
Fundamental
Offset
Peak Harm.
Noise Flour
EE141
VLSI
Test Principles and Architectures
111
Chap. 11 - Analog and Mixed-Signal Testing - P.111
ADC – Frequency Domain Testing
THD  10 log
F2
2
 Hi
 100 
F2
2
 Hi
%
SNR  10 log
F2
SNDR  10 log
dB
Fundamental
F
Noise
2
 Ni
F2
2
2
 H i   Ni
Harmonics
DC
Offset
Ni
H2
H3
H4
H5
F
EE141
VLSI
Test Principles and Architectures
112
Chap. 11 - Analog and Mixed-Signal Testing - P.112
11.4 IEEE Std. 1149.4 Standard for a
Mixed-Signal Test Bus
 IEEE
Std. 1149.4 Overview
 IEEE Std. 1149.4 Circuit Structures
 IEEE Std. 1149.4 Instructions
 IEEE Std. 1149.4 Test Modes
EE141
VLSI
Test Principles and Architectures
113
Chap. 11 - Analog and Mixed-Signal Testing - P.113
IEEE 1149.4 - Overview
 Target
mixed signal Printed Circuit Assembles
(PCA).
Discrete
 Components:
Component
M
M
Mixed Signal
Digital
Analog
Discrete
M: Mixed-signal Component
A: Analog Component
D: Digital Component
EE141
VLSI
Test Principles and Architectures
C
A
C




A
C
D
D
Interconnect
114
Chap. 11 - Analog and Mixed-Signal Testing - P.114
IEEE 1149.4 - Scope

Provide standardized approaches to
 Interconnect Test
 Parametric Test
 Internal Test
EE141
VLSI
Test Principles and Architectures
115
Chap. 11 - Analog and Mixed-Signal Testing - P.115
IEEE 1149.4 - Interconnect Test
A
A
D
D
D
A
A
A
D
D
D
A
Open Defects
EE141
VLSI
Test Principles and Architectures
A
A
D
D
D
A
A
A
D
D
D
A
Short Defects
116
Chap. 11 - Analog and Mixed-Signal Testing - P.116
IEEE 1149.4 - Parametric Test
A
A
A
A
A
A
D
D
D-A
D-A
Simple Interconnect Extended Interconnect
EE141
VLSI
Test Principles and Architectures
117
Chap. 11 - Analog and Mixed-Signal Testing - P.117
IEEE 1149.4 - Internal Test
A
A
A
D
D-A
EE141
VLSI
Test Principles and Architectures
Analog
Analog
Analog
Digital
118
Chap. 11 - Analog and Mixed-Signal Testing - P.118
IEEE 1149.4 - Architecture
IC1
IC2
IC Under Test
ICn
Analog
AB1
AB2
AT1
AT2
Test Waveform
Response Waveform
EE141
VLSI
Test Principles and Architectures
Chap. 11 - Analog and Mixed-Signal Testing - P.119
11.4 IEEE Std. 1149.4 Standard for a
Mixed-Signal Test Bus
 IEEE
Std. 1149.4 Overview
 IEEE Std. 1149.4 Circuit Structures
 IEEE Std. 1149.4 Instructions
 IEEE Std. 1149.4 Test Modes
EE141
VLSI
Test Principles and Architectures
120
Chap. 11 - Analog and Mixed-Signal Testing - P.120
IEEE 1149.4 - Architecture
Analog
BM
Digital
BM
D Pins
IC
Core
A
B
M
A
B
M
Internal
A Bus
TBIC
1149.1
TAP
TDI
TDO
TMS
TCK
EE141
VLSI
Test Principles and Architectures
A Pins
TAP Controller
AT1
AT2
Analog
TAP
121
Chap. 11 - Analog and Mixed-Signal Testing - P.121
IEEE 1149.4 - TBIC
A
B
M
A
B
M
Core
AB1
AB2
AB1
VH
AB2
Vc
VL
TBIC
AT1
AT2
TAP
VTH
AT1
AT2
EE141
VLSI
Test Principles and Architectures
Switch
Chap. 11 - Analog and Mixed-Signal Testing - P.122
IEEE 1149.4 - ABM
VTH VH VL VG
Core
Circuit
A
B
M
A
CUT
A
B
M
AB1
AB2
TBIC
CD
A Pin
AT1
AT2
Test Control Circuitry
TAP Controller
EE141
VLSI
Test Principles and Architectures
AB1
AB2
AT1
AT2
TBIC
Chap. 11 - Analog and Mixed-Signal Testing - P.123
1149.4 – Mixed-Signal Architecture
Digital
Inputs
Digital
Core
Circuit
Digital
Outputs
DBM
ABM
A/D
Analog
Inputs
TDI
EE141
VLSI
Test Principles and Architectures
Analog
Core
Analog
Outputs
TDO
124
Chap. 11 - Analog and Mixed-Signal Testing - P.124
11.4 IEEE Std. 1149.4 Standard for a
Mixed-Signal Test Bus
 IEEE
Std. 1149.4 Overview
 IEEE Std. 1149.4 Circuit Structures
 IEEE Std. 1149.4 Instructions
 IEEE Std. 1149.4 Test Modes
EE141
VLSI
Test Principles and Architectures
125
Chap. 11 - Analog and Mixed-Signal Testing - P.125
IEEE 1149.4 - Instructions
 Mandatory




Instructions
BYPASS
SAMPLE/PRELOAD
EXTEST
PROBE
 Same
as IEEE 1149.1
EE141
VLSI
Test Principles and Architectures
126
Chap. 11 - Analog and Mixed-Signal Testing - P.126
IEEE 1149.4 - Instructions
 Optional





Instructions
INTEST
IDCODE/USERCODE
RUNBIST
CLAMP
HIGHZ
 Same
as IEEE 1149.1
EE141
VLSI
Test Principles and Architectures
127
Chap. 11 - Analog and Mixed-Signal Testing - P.127
11.4 IEEE Std. 1149.4 Standard for a
Mixed-Signal Test Bus
 IEEE
Std. 1149.4 Overview
 IEEE Std. 1149.4 Circuit Structures
 IEEE Std. 1149.4 Instructions
 IEEE Std. 1149.4 Test Modes
EE141
VLSI
Test Principles and Architectures
128
Chap. 11 - Analog and Mixed-Signal Testing - P.128
1149.4 – Open/Short Interconnect Test
VH VL
VTH
0
1
Chip 1
AB1
AB2
EE141
VLSI
Test Principles and Architectures
Chip 2
AB1
AB2
Chap. 11 - Analog and Mixed-Signal Testing - P.129
1149.4 – Extended Interconnect Test
• Grounded Impedance Measurement
• Apply current and measure voltage
AB1
T
B
I
C
V
A
B
M
DUT
V
I
ZD
AB2
EE141
VLSI
Test Principles and Architectures
Chap. 11 - Analog and Mixed-Signal Testing - P.130
1149.4 – Extended Interconnect Test
• Equivalent Circuit Model.
I DUT (t )  I s (t ) 
RSIO
RSIO  Z P1  Z DUT
VM (t )  VDUT (t ) 
RSVI
RSVI  Z P 2  Z DUT
Z P1
RSIO
I s (t )
RSVI
Vm (t )
M
EE141
VLSI
Test Principles and Architectures
VDUT
Z P2
Z DUT
I DUT
Chap. 11 - Analog and Mixed-Signal Testing - P.131
1149.4 – Extended Interconnect Test
• Floating Impedance Zd Measurement
AB1
I
T
B
I
C
A
B
M
DUT
V
AB2
EE141
VLSI
Test Principles and Architectures
V ZD
VG
Chap. 11 - Analog and Mixed-Signal Testing - P.132
1149.4 – Extended Interconnect Test
• Floating Impedance ZD with optional Vg
AB1
I
T
B
I
C
A
B
M
V ZD
DUT
V
AB2
VG
Vg
EE141
VLSI
Test Principles and Architectures
Option with
Nonzero Vg
Chap. 11 - Analog and Mixed-Signal Testing - P.133
1149.4 – Extended Interconnect Test
• Apply voltage and measure current
T
B
I
C
A
B
M
EE141
VLSI
Test Principles and Architectures
ZD
A
B
M
T
B
I
C
V
Chap. 11 - Analog and Mixed-Signal Testing - P.134
1149.4 – Extended Interconnect Test
• Equivalent Circuit Model
VDUT (t )  Vs (t ) 
Z DUT
RSVO  Z P1  Z DUT  Z P 2  RSII
With Ideal Voltage Source
and Current Meter
Vs (t ) V
VDUT (t )  Vs (t ) 
I m (t ) 
Vs (t )
RSVO  Z P1  Z DUT  Z P 2  RSII
RSVO
Z P1
VDUT
Z DUT
I DUT
Z DUT
Z P1  Z DUT  Z P2
Vs (t )
I m (t ) 
Z P1  Z DUT  Z P 2
EE141
VLSI
Test Principles and Architectures
Z P2
I m (t ) M
RSII
Chap. 11 - Analog and Mixed-Signal Testing - P.135
1149.4 – Extended Interconnect Test
• Measure complex interconnect network
V13
P1
P3
Z2
Z1
V12
V34
Z3
Vg
P2
EE141
VLSI
Test Principles and Architectures
V
P4
Chap. 11 - Analog and Mixed-Signal Testing - P.136
1149.4 – Extended Interconnect Test
P1
P3
Z2
Z1
Z3
P2
P4
V
Vg
V
h11  1
I1 V  0
2
V
h12  1
V2 I  0
1
I
h21  2
I1 V  0
2
I
h22  2
V2 I  0
1
H
P1
P2
P3
P4
h11
Is/Vm
GND
GND
GND
h12
Vm
GND
Vs
GND
h21
Is
GND
Im
GND
h22
Open
GND
Vs/Im
GND
Notations
Is: Apply Current
Vm: Measure Voltage
Vs: Apply Voltage
Im: Measure Current
EE141
VLSI
Test Principles and Architectures
Chap. 11 - Analog and Mixed-Signal Testing - P.137
1149.4 - High Speed Applications
• Use buffers for better frequency response
VG VL VH VTH
Current Buffer
Voltage Buffer
TBIC
Analog
Core
AB1
AB2
EE141
VLSI
Test Principles and Architectures
ABM
Chap. 11 - Analog and Mixed-Signal Testing - P.138
11.5 Concluding Remarks
AMS testing requires specialized approaches
and experienced engineers because of the large
varieties of signals, functions and circuits.
 DSP approaches are so pervasive that even
basic analog test items can be accomplished.
 IEEE 1057 with formal terminologies and
standardized test methods provides a solid
theoretical background for ADC/DAC testing.
 IEEE 1149.4 is one solution to extending and
incorporating the digital counterpart.

EE141
VLSI
Test Principles and Architectures
139
Chap. 11 - Analog and Mixed-Signal Testing - P.139