8
7
6
5
4
3
2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
1
REV
ECN
DESCRIPTION OF REVISION
6
0001395489
CK
APPD
DATE
SCHEM,MLB,J30
ENGINEERING RELEASED
2012-03-13
03/12/12
D
(.csa)
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
C
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
B
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Contents
Sync
1
Table of Contents
(.csa)
02/15/2011
TABLE_TABLEOFCONTENTS_HEAD
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
03/26/2009
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
2
System Block Diagram
MASTER
3
Revision History
K20A_MLB
4
Revision History
K90I_MLB
5
BOM Configuration
K90I_MLB
7
FUNC TEST
K90I_MLB
8
Power Aliases
K90I_MLB
9
Signal Aliases
K90I_MLB
10
CPU DMI/PEG/FDI/RSVD
MASTER
11
CPU CLOCK/MISC/JTAG
MASTER
CPU DDR3 INTERFACES
MASTER
12
13
CPU POWER
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
09/27/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
MASTER
14
CPU GROUNDS
MASTER
16
CPU DECOUPLING-I
JACK_J30
17
CPU DECOUPLING-II
MASTER
18
PCH SATA/PCIe/CLK/LPC/SPI
J31_MLB
19
PCH DMI/FDI/PM/Graphics
J31_MLB
PCH PCI/USB/TP/RSVD
J31_MLB
PCH GPIO/MISC/NCTF
J31_MLB
20
21
22
PCH POWER
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
09/19/2011
TABLE_TABLEOFCONTENTS_ITEM
J31_MLB
23
PCH GROUNDS
J31_MLB
24
PCH DECOUPLING
K90I_MLB
25
CPU & PCH XDP
J31_MLB
26
Chipset Support
K90I_MLB
USB HUB & MUX
LINDA_J30
27
28
CPU Memory S3 Support
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
11/03/2011
TABLE_TABLEOFCONTENTS_ITEM
06/13/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
33
SD Card Connector
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
31
DDR3 SO-DIMM Connector B
02/15/2011
K90I_MLB
30
DDR3 Byte/Bit Swaps
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
29
DDR3 SO-DIMM Connector A
02/15/2011
YONAS_J30
34
DDR3/FRAMEBUF VREF MARGINING
J31_MLB
X19/ALS/CAMERA CONNECTOR
K90I_MLB
35
36
T29 Host (1 of 2)
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
06/15/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
37
T29 Host (2 of 2)
K90I_MLB
38
T29 Power Support
K90I_MLB
39
ETHERNET PHY (CAESAR IV)
J31_MLB
Ethernet Connector
K90I_MLB
40
41
FireWire LLC/PHY (FW643E)
06/23/2011
TABLE_TABLEOFCONTENTS_ITEM
02/15/2011
TABLE_TABLEOFCONTENTS_ITEM
11/08/2011
TABLE_TABLEOFCONTENTS_ITEM
07/08/2011
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
43
FireWire Connector
TABLE_TABLEOFCONTENTS_ITEM
K90I_MLB
42
FireWire Port & PHY Power
02/15/2011
K90I_MLB
45
SATA/IR/SIL Connectors
YONAS_J30
46
External A USB3 Connector
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
D
Date
Page
Contents
Sync
50
01/02/2012
SMC Support
YONAS_J30
LPC+SPI Debug Connector
J31_MLB
SMBus Connections
K90I_MLB
Power Sensors: Load Side
LINDA_J30
Power Sensors: High Side
YONAS_J30
Thermal Sensors
YONAS_J30
Fan
K90I_MLB
WELLSPRING 1
J31_MLB
WELLSPRING 2
JACK_J30
Digital Accelerometer
K90I_MLB
SPI ROM
K90I_MLB
AUDIO: CODEC/REGULATOR
KAVITHA_J30
AUDIO: DETECT/MIC BIAS
DIRK_J30
AUDIO: HEADPHONE FILTER
KAVITHA_J30
AUDI0: SPEAKER AMP
KAVITHA_J30
AUDIO: JACK
DIRK_J30
51
06/15/2011
52
02/15/2011
53
09/28/2011
54
11/03/2011
55
08/01/2011
56
02/15/2011
57
07/01/2011
58
09/28/2011
59
02/15/2011
61
02/15/2011
62
07/25/2011
64
02/16/2012
65
07/25/2011
66
07/25/2011
67
11/10/2011
68
C
02/20/2012
AUDIO:Jack Translators
DIRK_J30
DC-In & Battery Connectors
JACK_J30
PBus Supply & Battery Charger
JACK_J30
System Agent Supply
JACK_J30
5V/3.3V SUPPLY
JACK_J30
1.5V DDR3 Supply
JACK_J30
CPU IMVP7 & AXG VCore Regulator
JACK_J30
69
07/29/2011
70
09/27/2011
71
09/28/2011
72
08/22/2011
73
07/28/2011
74
08/03/2011
75
07/28/2011
CPU IMVP7 & AXG VCore Output
JACK_J30
CPUVCCIO (1.05V) Power Supply
JACK_J30
Misc Power Supplies
JACK_J30
Power FETs
K90I_MLB
Power Control 1/ENABLE
K90I_MLB
LVDS CONNECTOR
K90I_MLB
DisplayPort/T29 A MUXing
K90I_MLB
76
09/28/2011
77
07/28/2011
78
02/15/2011
79
02/15/2011
90
02/15/2011
93
02/15/2011
94
02/15/2011
Thunderbolt Connector A
K90I_MLB
LCD Backlight Driver
J31_MLB
CPU Constraints
K90I_MLB
Memory Constraints
K90I_MLB
PCH Constraints 1
K90I_MLB
PCH Constraints 2
K90I_MLB
Ethernet/FW Constraints
K90I_MLB
T29 Constraints
K90I_MLB
SMC Constraints
K90I_MLB
Project Specific Constraints
K90I_MLB
PCB Rule Definitions
K90I_MLB
97
07/08/2011
100
02/15/2011
101
02/15/2011
102
B
02/15/2011
103
02/15/2011
104
02/15/2011
105
02/15/2011
106
02/15/2011
108
02/15/2011
109
02/15/2011
J31_MLB
47
07/08/2011
External B USB3 Connector
J31_MLB
Front Flex Support
K90I_MLB
SMC
YONAS_J30
48
02/15/2011
49
12/21/2011
TABLE_TABLEOFCONTENTS_ITEM
A
A
DRAWING TITLE
SCHEM,MLB,J30
DRAWING NUMBER
Schematic / PCB #’s
PART NUMBER
QTY
Apple Inc.
DESCRIPTION
REFERENCE DES
CRITICAL
051-9058
1
SCHEM,MLB,J30
SCH
CRITICAL
820-3115
1
PCBF,MLB,J30
PCB
CRITICAL
BOM OPTION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Tue Mar 13 14:00:17 2012
8
7
6
051-9058
REVISION
5
4
3
2
6.0.0
BRANCH
PAGE
1 OF 109
SHEET
1 OF 86
1
SIZE
D
8
7
6
5
4
U1000
3
2
1
J2500
XDP CONN
INTEL CPU
PG 23
2.X GHz
IVY BRIDGE 2C-35W
J3100
PG 29
J2900
2 DIMMs
DDR3-1333/1600MHZ
PG 9-13
PG 27
DIMM
J6900, J6950
D
D
POWER SUPPLY
DC/BATT
PG 63
GPIO
FDI
DMI
RTC
PG 19
PG 17
PG 17
PG 16
PG 63-73
U5511
TEMP SENSOR
PG 51
U5920
Sudden Motion Sensor
U2600
MISC
CLK
SYSTEM
CLOCK
PG 55
PG 19
U5400,U5410,U5340,U5360,U5370,Q5480,Q5490
BUFFER
SPI
SATA
CONN
HDD
1.05V/6GHZ.
0
PG 41
DP/TMDS
0
U4900
Fan Ser
Prt
ADC
SMC
J5100
LPC+SPI Conn
Port80,serial
SPI
PG 45
1.05V/1.5GHZ.
C
PG 47
1
PG 16
U1800
PG 41
U5701
J3501
MUX
4 LANEs
PG 16-21
HDMI OUT
CTRL
CIO
PG 33,34
DP
DP OUT
DVI OUT
TMDS OUT
USB
PG 17
LVDS OUT
PG 17
PCI
J9000
J5800, J5713
TRACKPAD/
KEYBOARD
TP/KB
PSOC
PG 32
PG 53
PG 54, 53
J3502
PG 17
RGB OUT
T29 Host
X19
Bluetooth
PWR
PCIe x4
PG 76
PG 18
PG 75
eDP OUT
0 1 2 3 4 5 6 7 8 9 10 11 12 13
U3600
CONN
1
I2C SMS
LPC
PG 16
(UP TO 14 DEVICES)
Display Port
/ T29
U9390
PG 52
INTEL
PANTHER POINT-MPCH
J9400
FAN CONN AND CONTROL
SATA
J4500
SATA
CONN
ODD
J5601
PG 56
PG 16
J4501
PG 49, 50
SPI
Boot ROM
PG 16
C
POWER SENSE
U6100
PG 24
CAMERA
U4800
PG 32
U2700
1
2
J4501
IR
Controller
IR
PG 44
PG 41
3
USB
HUB
PG 25
J4700
U2760
EHCI
XHCI
USB
MUX
PG 25
EXTERNAL B
USB 3
PG 18
B
PG 18
PG 16
1 2 3 4
PCI-E
PG 74
PG 43
USB 3
LVDS
CONN
J4600
EXTERNAL A
USB 3
SMBUS
JTAG
B
PG 42
PG 16
PG 16
PCI-E
PEG
3
J2550
PG 16
PG 16
2
DIMM’s
HDA
(UP TO 8 LINES)
PG 16
1
From PCH
PCH XDP
CONN
PG 23
U6201
AUDIO
Codec
PG 57
EXTMIC LINEIN HPOUT SPDIF
MICIN
U6610, U6620, U6630
U6400
U4100
E-NET
FW643E
A
J3300
U3900
LINEOUT
MIC BIAS
BCM57765
SD Card
CONN
PG 36
PG 30
SPEAKER
AMPs
PG58
PG 60
PG 38
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
System Block Diagram
DRAWING NUMBER
J4310
J3501
Apple Inc.
J4000
X19
AirPort
FW800
CONN
E-NET
CONN
PG 32
PG 40
PG 37
J6700
J6701
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
PG 61
8
7
6
5
R
J6702
J6703
AUDIO
CONNs
4
3
051-9058
REVISION
2
6.0.0
BRANCH
PAGE
2 OF 109
SHEET
2 OF 86
1
SIZE
D
A
8
7
6
5
3
2
1
D6990
J30 POWER SYSTEM ARCHITECTURE
PPDCIN_G3H
4
2
ENABLE
3
3.425V G3HOT
PPDCIN_S5_P3V42G3H
R6990
PP3V42_G3H_REG
PM6640
U6990
R6905
4
SMC PWRGD
SMC_RESET_L
SN0903048
U5010
(PAGE 44)
(PAGE 63)
Q5300
D
1
J6900
Q5310
F6905
6A FUSE
AC
V
F7040
PPBUS_G3H
V
DCIN(16.5V)
A
U7000
CPUVCCIOS0_EN
ISL95870
U7600
EN
21
(PAGE 70)
ISL6259HRTZ
1
SMC_DCIN_ISENSE
PBUS SUPPLY/
BATTERY CHARGER
SMC_CPU_FSB_ISENSE
PGOOD
22-1
CPUVCCIOS0_PGOOD
R7050
V
A
24
VR_ON
(9 TO 12.6V)
R5330
SMC_GFX_VSENSE
(PAGE 68)
CPUIMVP_PGOOD
PGOOD
CPUIMVP_AXG_PGOOD
PGOODG
CHGR_BGATE
VIN
S5
C
DDRVTT_EN
16
PPDDR_S3_REG
0.75V
TPS51916
U7300
www.qdzbwx.com
PP5V_S0_FET
(PAGE 44)
PM_SLP_S5_L
COUGAR-POINT
(PCH)
R7917
CPU_VCCSA_VID<0>
SLP_SUS
EN1
PG73
DELAY
PG73
15
DELAY
U1800
P3V3S3_EN
PM_SLP_S4_L
PG73
13-2
13
PG 17
SLP_S4#(H4)
Q9706
F9700
8
VOUT2
15
SMC
25
PP5V_SW_ODD
RSMRST_PWRGD
ODD_PWR_EN_L
14-1
EN
PP3V3_S0_VMON
5
PP5V_S0_VMON
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN//WOL_EN
ISL88042IRTEZ
P17(BTN_OUT)
VMON_Q3
PP1V05_S0_VMON
U9701
PP3V3_S4_FET
PPVOUT_SW_LCDBKLT
VOUT
Q7800
12
CPUIMVP_VR_ON
PM_PWRBTN_L
SLP_S5_L(P95)
SMC_RESET_L
PM_SLP_S4_L
(PAGE 73)
26
PM_SYSRST_L
PM_SLP_S5_L
VMON_Q4
RES*
6-1
4
SLP_S4_L(P94)
PM_SLP_S3_L
(PAGE 76)
R7978
IMVP_VR_ON(P16)
U7960
VMON_Q2
PP1V5_S3RS0_VMON
B
PM_RSMRST_L
99ms DLY
PWR_BUTTON(P90)
SYSRST(PA2)
R7803
10
12
RSMRST_IN(P13)
SMC_ONOFF_L
U3900
CAESAR IV
(PAGE 36)
10-2
9
PM_DSW_PWRGD
PWRGD(P12)
RSMRST_OUT(P15)
PP1V2_ENET_PHY
BCM57765
PP3V3_ENET
Q7922
P5V_3V3_SUS_EN
EN
RESET*
ALL_SYS_PWRGD
P5V3V3_PGOOD
Q7840
PPBUS_SW_LCDBKLT_PWR
(PAGE 9~13)
PVCCSA_PGOOD
Q4590
LCD_BKLT_EN
VIN
LP8550
UNCOREPWRGOOD
P5VS0_EN
TPS51125
U7200
(PAGE 66)
PGOOD
&& BKLT_PLT_RST_L
(PAGE 16~21)
CPUVCCIOS0_PGOOD
PP5V_S0_FET
PP3V3_S5
PP5V_SUS_FET
14
PM_SLP_S3_L PG 17
SLP_S3#(F4)
PP3V3_S5_REG
U1000
P5V3V3_PGOOD
Q7860
PP5V_S3_REG
(R/H)
PP5V_S5_LDO
B
DDRREG_EN
VOUT1
EN2
13-1
CPU
P1V8S0_PGOOD
3.3V
P3V3S5_EN_L
VREG5
RC
30
SM_DRAMPWROK
CPUIMVP_AXG_PGOOD
23-1
(L/H)
7
P5VS3_EN
PVCCSA_PGOOD
PGOOD
14
VIN
5V
P5VS3_EN_L
13
PG73
RC
(PAGE 65)
28
PM_MEM_PWRGD
PPBUS_S5_HS_OTHER_ISNS
A
11
10-1
P5V_3V3_SUS_EN
VID1
R5410
PG 17
SLP_S5#(E4)
CPU_PWRGD
DRAMPWROK
23
VOUT
VID0
C
29
PROCPWRGD
(PAGE 16~21)
ISL95870A
U7100
R7916
11
PLT_RERST_L
PLTRST#
Q7801
PPVCCSA_S0_REG
EN
CPU_VCCSA_VID<1>
PG73
PM_DSW_PWRGD
U2850
DDRREG_PGOOD
PGOOD
VCC
PVCCSA_EN
22
P3V3S4_EN
PM_RSMRST_L
PP1V5_S3RS0_FET
DELAY
SMC_PM_G2_EN
PM_SYSRST_L
RSMRST#
U1800
PP1V5S0FET_GATE
7
SYS_RERST#
PM_PCH_PWRGD
(PAGE 67)
P3V3S5_EN
27
PM_PWRBTN_L
PPVTT_S0_DDR_LDO
VOUT2
SMC
COUGAR-POINT
(PCH) PWRBTN#
26-1
VOUT1
S3
26
25-1
VLDOIN
1.5V
DDRREG_EN
FW_PWR_EN
PPVCORE_S0_AXG_REG
VOUT
PPVBAT_G3H_CHGR_R
RC
PP1V0_FW_FWPHY
EN
V
U7400
Q7055
6
U4202
CPU VCORE
MAX15119GTM
(PAGE 63)
P60
TPS22924
(PAGE 39)
CPUIMVP_VR_ON
PPVBATT_G3H_CONN
25
PPVCORE_S0_CPU_REG
VOUT
SMC_BATT_ISENSE
J6950
R5320
SMC_CPU_VSENSE
VIN
SMC_RESET_L
U4900
D
22
VOUT
IN
3S2P
PPCPUVCCIO_S0_REG
A
1.05VVOUT
VCC
PPVBAT_G3H
VIN
R7640
PP5V_S0_CPUVCCIOS0
A
R7020
ADAPTER
15
R5400
SLP_S3_L(P93)
P3V3S4_EN
PG73
PP3V3_S3
Q4260
F4260
14
U4900
(PAGE 43)
16
PP3V3_S0
Q7810
PPBUS_FW_FET
PM_SLP_S3_L_R
P3V3S3_EN
MAX15053EWL
P1V8_S0_EN
EN
FWP5ORT_PWR_EN
1V05_S0_LDO_EN
A
RC
CPUVCCIOS0_EN
DELAY
RC
PVCCSA_EN
21
21
22
P1V5S0_EN
19
DELAY
RC
P1V8S0_EN
DELAY
8
10-3
17
U7760
PP1V8_S0_REG
18
(PAGE 71)
TPS720105
P1V05_S0_LDO_EN
EN
P5V_3V3_SUS_EN
P5VS0_EN
14-1
U7740
T29_A_HV_EN
PP1V05_SUS_LDO
EN
U7770
PP1V5_S0_REG
SYNC_MASTER=K20A_MLB
SYNC_DATE=03/26/2009
Revision History
20
DRAWING NUMBER
(PAGE8 71)
Apple Inc.
Q7830
U3890
PM_SLP_S3_L_R
TPS22924
PP3V3_FW_P3V3FWFET
14
EN
U4201
5
4
051-9058
REVISION
R
6.0.0
PP3V3_FW_FE5T
NOTICE OF PROPRIETARY PROPERTY:
(PAGE 39)
VOUT PP15V_T29_REG
(PAGE 35)
6
9
TPS62201
P1V5S0_EN
19
(PAGE 71)
VIN
LT3957
14-1
7
PP1V05_S0_LDO
PAGE TITLE
PBUSVSENS_EN
17
U7780
(PAGE 71)
14-1
TPS720105
P3V3S0_EN
19
Q7820
Q3880
DELAY
RC
PP3V3_SUS_FET
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
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8
7
6
5
4
3
2
1
PROTO:
D
D
C
C
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Revision History
DRAWING NUMBER
Apple Inc.
051-9058
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
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BRANCH
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4 OF 109
SHEET
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SIZE
D
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8
7
6
5
BOM Variants
4
3
2
1
Bar Code Labels / EEEE #’s
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
607-8895
CMN PTS,PCBA,MLB,J30
J30_COMMON,FET_PAIR
085-3092
J30 MLB DEVELOPMENT BOM
J30_DEVEL:ENG
607-8721
POWER FETS PAIR,FAIRCHILD,DDR,J30
DDR_POWER_FET:FAIR
607-8722
POWER FETS PAIR,FAIRCHILD,5V_S3,J30
5V_S3_POWER_FET:FAIR
607-8723
POWER FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
CHARGER_POWER_FET:FAIR
607-9309
POWER FETS PAIR,RENESAS,DDR,J30
DDR_POWER_FET:REN
PART NUMBER
DESCRIPTION
REFERENCE DES
826-4393
QTY
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YG]
CRITICAL
CRITICAL
BOM OPTION
EEEE_F1YG
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YH]
CRITICAL
EEEE_F1YH
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YJ]
CRITICAL
EEEE_F1YJ
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YK]
CRITICAL
EEEE_F1YK
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YL]
CRITICAL
EEEE_F1YL
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE:F1YM]
CRITICAL
EEEE_F1YM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
D
TABLE_BOMGROUP_ITEM
607-9310
POWER FETS PAIR,RENESAS,5V_S3,J30
5V_S3_POWER_FET:REN
TABLE_BOMGROUP_ITEM
607-9311
POWER FETS PAIR,RENESAS,PBUS_CHARGER,J30
CHARGER_POWER_FET:REN
639-3752
PCBA,MLB,MOL,2.9G,J30
J30_CMNPTS,CPU_2_9GHZ,SODIMM:MOLEX,EEEE_F1YK
639-3756
PCBA,MLB,HYB,2.9G,J30
J30_CMNPTS,CPU_2_9GHZ,SODIMM:HYBRID,EEEE_F1YH
639-3753
PCBA,MLB,FOX,2.5G,J30
J30_CMNPTS,CPU_2_5GHZ,SODIMM:FOXCONN,EEEE_F1YL
639-3755
PCBA,MLB,HYB,2.5G,J30
J30_CMNPTS,CPU_2_5GHZ,SODIMM:HYBRID,EEEE_F1YJ
639-3751
PCBA,MLB,MOL,2.5G,J30
J30_CMNPTS,CPU_2_5GHZ,SODIMM:MOLEX,EEEE_F1YM
639-3754
PCBA,MLB,FOX,2.9G,J30
J30_CMNPTS,CPU_2_9GHZ,SODIMM:FOXCONN,EEEE_F1YG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Programmable Parts
PART NUMBER
C
J30 BOM GROUPS
REFERENCE DES
CRITICAL
335S0862
QTY
1
IC,FLASH,SERIAL,SPI,!MBIT,2V7,REV F
DESCRIPTION
U3990
CRITICAL
BOM OPTION
341S3096
1
IC ENET,1!MBITFLAH,CIV REV01,K9x
U3990
CRITICAL
ENET_PROG
335S0550
1
IC,EEPROM,SERIAL,SPI,4Kx8,1.8V,MLP8,LF
U3690
CRITICAL
T29ROM:BLANK
341S3430
1
IC,T29 EEPROM,LR,J30/J31
U3690
CRITICAL
T29ROM:PROG
337S3997
1
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
U9330
CRITICAL
T29MCU:BLANK
341S3365
1
IC,PROGRMD,T29,PORT MCU,K90IA,K91A,K92A
U9330
CRITICAL
T29MCU:PROG
338S1098
1
IC,SMC12-A3,40MHZ/50DMIPS MCU,9x9,157BGA
U4900
CRITICAL
SMC_BLANK
341S3300
1
IC,SMC,EXTERNAL,FSB,A3,J30
U4900
CRITICAL
SMC_PROG
335S0807
1
IC,SPI SRL 50MHZ FLASH,64MBT,8SOP,FUSE=1
U6100
CRITICAL
BOOTROM_BLANK
335S0812
1
64 MBIT SPI SRL DUAL I/O FLSH,SOIC8
U6100
CRITICAL
BOOTROM_BLANK
341S3558
1
IC,EFI,V00C7,J30/J31
U6100
CRITICAL
BOOTROM_PROG
341S2384
1
IR,ENCORE II, CY7C63803-LQXC
U4800
CRITICAL
341S3522
1
IC,PSOC,TP/KB,J30/J31
U5701
CRITICAL
ENET_BLANK
C
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
J30_COMMON
ALTERNATE,COMMON,J30_COMMON1,J30_COMMON2,J30_DEBUG:ENG,J30_PROGPARTS,T29BST:Y,TBTHV:P15V
J30_COMMON1
BATT_3S,CPUMEM_S0,USBHUB2513B,HUB_3NONREM,T29:YES,SDRV_PD,SDRVI2C:MCU,AXG_PHASE1,BTPWR:S4,UV_GLUE_J30
J30_COMMON2
MIKEY,TPAD:Z2,RAMCFG_SLOT
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
J30_PROGPARTS
BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG
J30_DEVEL:ENG
BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS_CONN:YES,LOADISNS:YES,DDRVREF_DAC,S0PGOOD_ISL
TPAD_PROG
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
J30_DEVEL:PVT
LPCPLUS_CONN:YES,XDP_CONN
J30_DEBUG:ENG
DEVEL_BOM,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO_DAC
Alternate Parts
TABLE_BOMGROUP_ITEM
TABLE_ALT_HEAD
TABLE_BOMGROUP_ITEM
J30_DEBUG:PVT
DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2514B
J30_DEBUG:PROD
BKLT:PROD,MOJO:YES,XDP,LPCPLUS_R:YES,LOADISNS:NO,VREFDQ:M1_M3,VREFCA:LDO,USBHUB2513B
PART NUMBER
ALTERNATE FOR
PART NUMBER
138S0603
138S0602
BOM OPTION
REF DES
COMMENTS:
ALL
Murata alt to Samsung
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
152S1499
BOM OPTION
REF DES
COMMENTS:
152S0864
ALL
Coilcraft alt to Murata
152S1493
152S1300
ALL
Coilcraft alt to Murata
138S0652
138S0648
ALL
Samsung/Murata alt to Taiyo
138S0684
138S0660
ALL
Murata alt to Taiyo
152S1512
152S1295
ALL
Cyntec alt to NEC
152S1019
152S1271
ALL
Cyntec alt to TOKO
376S1023
376S0960
ALL
Siliconix alt to Renesas
353S3312
353S3055
ALL
NXP alt to Pericom
353S3238
353S1428
ALL
Intersil alt to TI
353S3519
353S2179
ALL
Intersil alt to TI
155S0578
155S0367
ALL
Taiyo alt to Murata
138S0681
138S0638
ALL
Taiyo alt to Samsung
138S0671
138S0673
ALL
Taiyo alt to Murata
376S0903
376S0796
ALL
Fairchidl alt to Vishay
377S0124
377S0057
ALL
Amotech alt to Tdk
341S3492
341S3096
ALL
Numonix alt to Atmel (ENET ROM)
376S1053
376S0604
ALL
Diodes alt to fairchild
376S1076
376S0634
ALL
Diodes alt to onsemi
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
157S0058
157S0084
ALL
Delta alt to TDK Magnetics
TABLE_ALT_ITEM
TABLE_ALT_ITEM
128S0303
Module Parts
128S0353
ALL
Panasonic alt to Sanyo
TABLE_ALT_ITEM
TABLE_ALT_ITEM
138S0676
138S0691
ALL
Murata alt to Samsung
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
152S0778
BOM OPTION
152S0693
ALL
Cyntec alt to Vishay
TABLE_ALT_ITEM
TABLE_ALT_ITEM
337S4113
1
U1000
IC,IVB,2C,35W,1023BGA
CRITICAL
376S0855
376S1032
ALL
Diodes alt to Toshiba
376S0977
376S0859
ALL
Diodes alt to Toshiba
TABLE_ALT_ITEM
CPU_IVB_2C
TABLE_ALT_ITEM
B
337S4264
1
U1000
IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA
CRITICAL
TABLE_ALT_ITEM
CPU_2_5GHZ
TABLE_ALT_ITEM
376S0972
337S4265
1
U1000
IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA
CRITICAL
376S1017
ALL
Rohm alt to Toshiba
TABLE_ALT_ITEM
337S4269
1
PANTHERPOINT,C1,SLJ8C,PRQ,BD82HM77
U1800
CRITICAL
343S0534
1
IC,BCM57765B0,ENET&SD,8X8
U3900
CRITICAL
376S0937
376S0845
ALL
Fairchild alt to Renesas
376S0777
376S0761
ALL
AON alt to Siliconix
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
338S0753
1
U4100
IC,FW643E,1394B PHY/OHCI LINK/PCI-E,12
376S0957
376S0958
ALL
Fairchild alt to Fairchild
376S0953
376S0958
ALL
Fairchild alt to Renesas
TABLE_ALT_ITEM
CRITICAL
TABLE_ALT_ITEM
338S1072
1
IC,T29,PRQ,S LJJY,FCBGA,15x15MM,C1
U3600
CRITICAL
TABLE_ALT_ITEM
T29:YES
TABLE_ALT_ITEM
353S3055
1
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN
U9390
377S0107
CRITICAL
377S0126
ALL
ONsemi alt to Semtech
TABLE_ALT_ITEM
TABLE_ALT_ITEM
946-3827
1
UV_GLUE_J30
J30 MLB DYMAX ADHESIVE 29993-SC 0.48G
CRITICAL
371S0709
UV_GLUE_J30
371S0652
ALL
NXP alt to Infineon
TABLE_ALT_ITEM
TABLE_ALT_ITEM
516S0806
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN
J3100
CRITICAL
514-0788
SODIMM:FOXCONN
514-0671
ALL
Acon(w liteon) alt to Acon
TABLE_ALT_ITEM
TABLE_ALT_ITEM
516-0246
1
J2900
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
B
TABLE_ALT_ITEM
CPU_2_9GHZ
CRITICAL
607-9310
SODIMM:FOXCONN
607-8722
ALL
Renesas alternate to fairchild
TABLE_ALT_ITEM
TABLE_ALT_ITEM
516S0805
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
SODIMM:MOLEX
516-0245
1
CONN,204P,SODIMM,DDR3,P=0.6MM,MOLEX
J2900
CRITICAL
SODIMM:MOLEX
516S0805
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
SODIMM:HYBRID
516-0246
1
CONN,204P,SODIMM,DDR3,P=0.6MM,FOXCONN
J2900
CRITICAL
SODIMM:HYBRID
607-9311
607-8723
ALL
Renesas alternate to fairchild
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Sub BOM
PART NUMBER
A
DESCRIPTION
REFERENCE DES
CRITICAL
085-3092
QTY
1
J30 MLB DEVELOPMENT
DEVEL
CRITICAL
BOM OPTION
DEVEL_BOM
607-8895
1
CMN PTS,PCBA,MLB,J30
CMNPTS
CRITICAL
J30_CMNPTS
607-8721
1
POWER_FETS PAIR,FAIRCHILD,DDR,J30
CSET1
CRITICAL
FET_PAIR
607-8722
1
POWER_FETS PAIR,FAIRCHILD,5V_S3,J30
CSET2
CRITICAL
FET_PAIR
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
BOM Configuration
DRAWING NUMBER
Apple Inc.
051-9058
REVISION
R
607-8723
1
POWER_FETS PAIR,FAIRCHILD,PBUS_CHARGER,J30
CRITICAL
CSET3
FET_PAIR
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
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6.0.0
BRANCH
PAGE
5 OF 109
SHEET
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1
SIZE
D
A
8
7
6
5
4
3
2
NC_EDP_TXP<0..3>
MAKE_BASE=TRUE
NC_EDP_TXN<0..3>
MAKE_BASE=TRUE
NC_EDP_AUXP
MAKE_BASE=TRUE
NC_EDP_AUXN
Functional Test Points
NC NO_TESTs
NO_TEST
X19 CONN
Fan Connectors
I12
I15
I16
TRUE
TRUE
TRUE
PP5V_S0
FAN_RT_PWM
FAN_RT_TACH
6 7
I303
52
I301
52
I302
(NEED TO ADD 1 GND TP)
I300
I299
D
I554
I553
I555
MIC FUNC_TEST
BI_MIC_LO
TRUE
BI_MIC_HI
TRUE
BI_MIC_SHIELD
TRUE
I298
61 62
I293
61 62
I288
61 62
I292
(NEED TO ADD 1 GND TP)
I295
I290
I271
I289
I227
I226
I228
I230
I229
I231
SPEAKER FUNC_TEST
SPKRAMP_L_N_OUT
TRUE
SPKRAMP_L_P_OUT
TRUE
SPKRAMP_R_N_OUT
TRUE
SPKRAMP_R_P_OUT
TRUE
SPKRAMP_SUB_N_OUT
TRUE
SPKRAMP_SUB_P_OUT
TRUE
I595
60 61 85
I594
60 61 85
I593
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
17
(NEED 3 TP) 6
PP3V3_WLAN
PCIE_AP_D2R_PI_P
32
PCIE_AP_D2R_PI_N
32
PCIE_AP_R2D_P
32
PCIE_AP_R2D_N
32
PCIE_CLK100M_AP_CONN_P 32
PCIE_CLK100M_AP_CONN_N 32
PP3V3_S3RS4_BT_F
32
PCIE_WAKE_L
17
USB_BT_CONN_P
32
USB_BT_CONN_N
32
AP_CLKREQ_Q_L
32
AP_RESET_CONN_L
32
AP_TEMP_SMB_SDA_R
32
AP_TEMP_SMB_SCL_R
32
WIFI_EVENT_L_R
32
17
32 46
DEBUG VOLTAGE
81
81
81
I285
85
I414
85
I280
I281
24 32
I282
80
I283
80
I376
I278
I270
I416
I273
I274
I275
60 61 85
I417
60 61 85
I392
I391
60 61 85
I390
IPD_FLEX_CONN
LVDS FUNC_TEST
I372
I370
I259
I258
I260
I407
C
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V3_LCDVDD_SW_F (NEED
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT (NEED
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
2 TP)
6 74
I371
6 74
I369
2 TP)
74 77
I368
8 74
I361
8 74
I366
17 74 80
I365
17 74 80
I363
17 74 80
I364
17 74 80
I362
17 74 80
I360
17 74 80
I359
74 85
I357
74 85
I358
74 77
I377
74 77
I564
74 77
I626
I345
B
I265
I266
I628
I627
I346
(NEED 2 TP)
PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SMC_SSD_TEMP_CTL_R
HDD_OOB_TEMP
I347
6 41
I349
41 45
I348
41 85
I350
41 85
I352
41 80
I351
41 80
I353
I327
I328
(NEED TO ADD 3 GND TP)
I329
I343
SATA HDD/IR/SIL
I342
I341
I319
I314
I315
I318
I317
I307
I309
I625
I311
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I383
53 54
I419
53 54
I382
53 54
I565
53 54
I380
(NEED
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
SMC_SSD_THROTTLE_R
PP5V_S3_IR_R
2 TP)
6 41
I339
41 80
I340
41 80
I338
41 80
I336
41 80
I337
41
I333
41 44
I335
I334
41
I332
(NEED TO ADD 3 GND TP)
I330
I331
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V2_S3_ENET_INTREG
PP1V05_S0
PP1V5_S3RS0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3
PP5V_S3
PPVCCSA_S0_CPU
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET
PP3V3_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP18V5_Z2
PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F
PP4V5_AUDIO_ANALOG
PP1V5_S3
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L
17
7
17
7
NC_CRT_IG_DDC_CLK
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TRUE
MAKE_BASE=TRUE
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
TP_PCH_LVDS_VBG
NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
TRUE
MAKE_BASE=TRUE
17
7 85
17
6 7
17
7
I321
I320
A
I305
TRUE
TRUE
TRUE
TRUE
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
(NEED
PPVBAT_G3H_CONN
16
7 85
16
6 7
16
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
18
6 41
TP_PCI_PME_L
TP_PCI_CLK33M_OUT3
6 74
16
6 74
16
57 62
7
16
45 73
16
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
53 54
38
6 45 48 84
38
TP_FW643_SDA
TP_FW643_SM
TP_FW643_TCK
TP_FW643_TMS
TP_FW643_FW620_L
TP_FW643_VBUF
TP_FW643_OCR10_CTL
5 TP)
63 64
I394
23
53 54
23
54
23
23
(NEED 3 TP)
23
63
23
63
23
16
6 7
16
6 7
LPC+SPI DEBUG_CONN
16
16
I599
53
I600
53
I601
53
I602
53
I603
53
I604
53
I605
53
I606
53
I607
53
I608
53
I610
53
I611
53
I612
53
I614
53
I613
53
I617
53
I616
53
I618
53
I620
53
I619
53
I622
(NEED TO ADD 5 GND TP)
9
=PEG_R2D_C_N<0..7>
9
TRUE
=PEG_D2R_P<0..7>
9
TRUE
=PEG_D2R_N<0..7>
9
TRUE
=PEG_R2D_C_P<8..11>
TRUE
=PEG_R2D_C_N<8..11>
TRUE
=PEG_D2R_P<8..11>
9
=PEG_D2R_N<8..11>
9
NC_PEG_R2D_CN<8..11>
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
NC_FW643_SDA
NC_FW643_SM
NC_FW643_TCK
NC_FW643_TMS
NC_FW643_FW620_L
NC_FW643_VBUF
NC_FW643_OCR10_CTL
NC_PEG_D2RN<8..11>
NC_PCH_GPIO64_CLKOUTFLEX0
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO66_CLKOUTFLEX2
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO67_CLKOUTFLEX3
TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
TP_PSOC_P1_3
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
33
33
33
33
16 45 47 81
33
16 45 47 81
33
24 47 81
33 6
16 45 47 81
33 6
17 45 47
33 6
16 45 47
33 6
19 47
9
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_C_D2RN
NC_SATA_C_D2RP
NC_SATA_C_R2D_CN
NC_SATA_C_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_TBT_MONDC0
TP_TBT_MONDC1
TP_TBT_MONOBSP
TP_TBT_MONOBSN
TP_DP_T29SRC_ML_CP<0..3>
TP_DP_T29SRC_ML_CN<0..3>
TP_DP_T29SRC_AUXCH_CP
TP_DP_T29SRC_AUXCH_CN
TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L
33
33
16 45 47 81
TRUE
MAKE_BASE=TRUE
16
NC_FW643_AVREG
TRUE
MAKE_BASE=TRUE
NC_FW643_TDI
TRUE
MAKE_BASE=TRUE
TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO67_CLKOUTFLEX3
16 45 47 81
9
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
NC_TP_XDP_PCH_OBSFN_A<0..1>
TRUE
MAKE_BASE=TRUE
NC_TP_XDP_PCH_OBSFN_B<0..1>
TRUE
MAKE_BASE=TRUE
NC_TP_XDPPCH_HOOK2
TRUE
MAKE_BASE=TRUE
NC_TP_XDPPCH_HOOK3
TRUE
MAKE_BASE=TRUE
NC_TP_XDP_PCH_OBSFN_D<0..1>
TRUE
MAKE_BASE=TRUE
NC_TP_XDP_PCH_HOOK4
TRUE
MAKE_BASE=TRUE
NC_TP_XDP_PCH_HOOK5
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_TBT_MONDC0
NC_TBT_MONDC1
NC_TBT_MONOBSP
NC_TBT_MONOBSN
NC_DP_T29SRC_ML_CP<0..3>
NC_DP_T29SRC_ML_CN<0..3>
NC_DP_T29SRC_AUXCH_CP
NC_DP_T29SRC_AUXCH_CN
TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L
C
6 33
6 33
6 33
24 47
NO_TEST
NC NO_TESTs
6 7
45 46 47
I500
TRUE
45 46 47
I499
TRUE
45 46 47
I498
TRUE
45 46 47
I497
TRUE
I495
TRUE
45 46 47
45 46 47
I496
TRUE
47
I494
TRUE
47
I493
TRUE
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
40
40
40
40
I522
TRUE
40
I521
TRUE
40
I520
TRUE
I519
TRUE
I518
TRUE
40
I517
47
53
(NEED TO ADD 2 GND TP)
I581
TRUE
I580
TRUE
I582
TRUE
I583
TRUE
I584
TRUE
I585
TRUE
I586
TRUE
I588
TRUE
I587
TRUE
(NEED TO ADD 2 GND TP)
54
54
(NEED TO ADD 1 GND TP)
I547
TRUE
I546
TRUE
I545
TRUE
I544
TRUE
I543
TRUE
I542
TRUE
I541
TRUE
I540
TRUE
81
81
81
40
47
19 47 56
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
XDP_PCH_AP_PWR_EN
XDP_PCH_USB_HUB_SOFT_RST_L
XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN
XDP_PCH_SDCONN_DET_L
XDP_PCH_S5_PWRGD
23
XDP_PCH_PWRBTN_L
23
XDP_PCH_ISOLATE_CPU_MEM_L
XDP_FW_CLKREQ_L
XDP_AP_CLKREQ_L
XDP_PCH_AUD_IPHS_SWITCH_EN
TRUE
8
8
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
81
81
81
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
SMC_BS_ALRT_L
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
81
81
6 81
6 81
81
81
81
81
NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_SMC_BS_ALRT_L
A
SYNC_MASTER=K90I_MLB
PAGE TITLE
FUNC TEST
CAMERA/ALS CONN
BIL CONN
I326
I323
I324
I325
I308
TRUE
TRUE
TRUE
TRUE
TRUE
PP3V42_G3H
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMC_BIL_BUTTON_L
SMC_LID_R
I408
6 7
I409
6 45 48 84
I410
6 45 48 84
I297
45 46 63
I294
63
(NEED TO ADD 2 GND TP)
TRUE
TRUE
TRUE
TRUE
TRUE
DRAWING NUMBER
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
17
6 45 48 84
17
6 45 48 84
32 80
17
32 80
17
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
TP_SDVO_STALLN
TP_SDVO_STALLP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_STALLN
NC_SDVO_STALLP
TP_SDVO_INTN
TP_SDVO_INTP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_INTN
NC_SDVO_INTP
(NEED TO ADD 2 GND TP)
17
7
6
Apple Inc.
32
17
8
5
B
6 33
17 45 47
6 7
TRUE
53
=PEG_R2D_C_P<0..7>
TRUE
MAKE_BASE=TRUE
TP_XDP_PCH_OBSFN_A<0..1>
TP_XDP_PCH_OBSFN_B<0..1>
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
TP_XDP_PCH_OBSFN_D<0..1>
TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5
I491
TRUE
NC_PEG_R2D_CP<8..11>
16
53 54
I492
SMC_KDBLED_PRESENT_L
63
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_FW643_AVREG
TP_FW643_TDI
TRUE
KBDLED_ANODE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
6 45 48 84
(NEED TO ADD 4 GND TP)
TRUE
NC_PEG_D2RN<0..7>
53
38
38
I596
D
TRUE
MAKE_BASE=TRUE
8 17 26 45 73
38
53
TP_CPU_RSVD<8..27>
NC_PEG_D2RP<0..7>
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
17 26 32 45 73
53 54
53
TRUE
MAKE_BASE=TRUE
16
53 54
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_LPCPLUS
LPC_FRAME_L
LPC_PWRDWN_L
LPC_SERIRQ
LPCPLUS_GPIO
LPCPLUS_RESET_L
PM_CLKRUN_L
PP3V42_G3H
PP5V_S0
SMC_RX_L
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TX_L
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_MOSI
SPIROM_USE_MLB
TP_CPU_RSVD<30..45>
NC_PEG_R2D_CN<0..7>
16
38
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TP_CPU_THERMDC
TRUE
NC_PEG_D2RP<8..11>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
16
38
I597
TP_CPU_THERMDA
NC_PEG_R2D_CP<0..7>
6 41
53 54
I598
9
TRUE
NC_CPU_RSVD<8..27>
6 54
53 54
53
TP_EDP_AUX_N
MAKE_BASE=TRUE
18
6 32 46
38
53
9
TRUE
TRUE
MAKE_BASE=TRUE
7
KBD BACKLIGHT CONN
I356
NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
7
53 54
53
TP_EDP_AUX_P
MAKE_BASE=TRUE
7
6 45 48 84
6 45 48 84
NC_CPU_THERMDC
NC_CPU_RSVD<30..45>
7
38
PP18V5_DCIN_FUSE
ADAPTER_SENSE
9
TRUE
MAKE_BASE=TRUE
17
7 85
BATT POWER CONN
I322
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
7
53 54
TRUE
TRUE
9
TP_EDP_TX_N<0..3>
MAKE_BASE=TRUE
17
7
(NEED TO ADD 6 GND TP)
DC POWER CONN
TP_EDP_TX_P<0..3>
TRUE
MAKE_BASE=TRUE
71
54
I304
PP3V3_S4
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
TRUE
MAKE_BASE=TRUE
NC_CPU_THERMDA
53 54
KEYBOARD CONN
SATA ODD CONN
I267
I386
6 54
74 77
I344
I269
I418
6 7
I312
I355
I268
PP3V3_S4
PP18V5_Z2
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
PSOC_F_CS_L
PICKB_L
PP5V_S5_CUMULUS
74 77
I354
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
I388
(NEED TO ADD 2 GND TP)
74 77
(NEED TO ADD 5 GND TP)
I264
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
MAKE_BASE=TRUE
I287
(NEED TO ADD 5 GND TP)
I374
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
81
60 61 85
I375
17
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
1
4
3
051-9058
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
6.0.0
BRANCH
PAGE
7 OF 109
SHEET
6 OF 86
1
SIZE
D
8
7
6
"G3Hot" (Always-Present) Rails
64 63
=PPBUS_G3H
PPBUS_G3H
6
66
=PP3V3_S5_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
35
PPVIN_SW_T29BST
VOLTAGE=12.8V
50
=PPVIN_S5_HS_COMPUTING_ISNS
=PPBUS_S0_LCDBKLT
=PPBUS_S5_FWPWRSW
=PPBUS_S0_VSENSE
=PPVIN_SW_T29BST
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_OTHER_ISNS_R
77
39
50
8 35
50
50
PPBUS_S5_HS_COMPUTING_ISNS
=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_VCCSAS0
=PPVIN_S0_CPUAXG
50
=PPVIN_S5_HS_OTHER_ISNS
63
=PP18V5_DCIN_CONN
67
70
65
69
PPBUS_S5_HS_OTHER_ISNS
72
=PP3V3_SUS_FET
66
=PP3V42_G3H_REG
PP3V42_G3H
64
50
6
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_BATT
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_AUDIO
C
24
=PPVRTC_G3_OUT
72
=PP3V3_S4_FET
45 46
63
64
63
72
=PP3V3_S3_FET
53
72
=PP5V_SUS_FET
24
58
16 17 20
72
=PP3V3_S0_FET
66
=PP5V_S3_REG
54
22
6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_ALSCAMERA
=PP5V_S3_AUDIO
=PP5V_S3_AUDIO_AMP
=PP5V_S3_DDRREG
=PP5V_S3_IR
=PP5V_S3_MEMRESET
=PP5V_S3_ODD
=PP5V_S3_P5VS0FET
=PP5V_S3_USB
=PP5V_S3_SYSLED
72
=PP5V_S0_FET
PP5V_S0
32
57
60
67
41 44
26
41
72
42
46
6
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_RT
=PP5V_S0_HDD_ISNS_R
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS
=PP5V_S0_VCCSAS0
=PP5V_S0_PCH
=PP5V_S0_VMON
=PP5V_S0_ISNS
=PP5V_S0_AUDIO
A
49
=PP5V_S0_HDD_ISNS
77
68 69
70
52
49
54
47
65
8
22 24
73
49
PP5V_S0_HDD
7
76
19
=PPDDR_S3_REG
41
6
40
19 20 22
71
39
PP3V3_FW_FWPHY
=PP3V3_FW_FET
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
20
24
20 22
=PP1V0_FW_FWPHY
67
31
T29 Rails (off when no cable)
6
35 8
PP15V_T29
=PP15V_T29_REG
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE
72
49
=PPHV_SW_TBTAPWRSW
=PP1V5_S3RS0_FET
72
PP1V5_S3RS0
35
PP3V3_T29
=PP3V3_T29_FET
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
56
=PP1V5_S3_CPU_VCCDDR
20 22
=PP1V5_S0_REG
71
10 12 15 26
=PPVDDIO_T29_CLK
=PP3V3_T29_RTR
=PP3V3_T29_PCH_GPIO
PP1V5_S0
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
53 54
46
=PP1V5_S0_RDRVR
=PP1V8R1V5_S0_AUDIO
=PP3V3R1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP1V5_S0_VMON
30
32
6
VOLTAGE=3.3V
MAKE_BASE=TRUE
76
6 85
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
71
46
VOLTAGE=3.3V
MAKE_BASE=TRUE
38 39
29
22
73
D
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MAKE_BASE=TRUE
27
=PP1V5_S3_P1V5S3RS0_FET
=PP1V5_S3_DDR_ISNS_R
16 17 18 19
38 39 40
PP1V0_FW_FWPHY
=PP1V0_FW_FET_R
26
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
20
40
22
39
PP1V5_S3
20 22
6
PP3V3_S0
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
14
=PP3V3_FW_FWPHY
=PP3V3_S0_P1V05FWFET
=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_MEMVREF
72
PP3V3_S3
PPVP_FW
=PPBUS_FW_FET
PP1V5_S3_DDR
73
VOLTAGE=3.3V
MAKE_BASE=TRUE
39
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.8V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
24
41
35
24
33 34 35
16 19
PP1V05_T29
=PP1V05_T29_FET
35
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
57
57
C
=PP1V05_T29_RTR
20 22 24
34
73
32
26
=PPVTT_S3_DDR_BUF
67 31
PPVTTDDR_S3
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
48
48
55
=PPVTT_S0_DDR_LDO
67
PP0V75_S0_DDRVTT
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
25
25
1V05 S0 LDO
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
31
32
24
73
=PPVCCSA_S0_REG
65
27
71
PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_LDO
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
29
26
PPVCCSA_S0_CPU
=PP1V05_S0_PCH_VCCADPLL
6
22
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE
18 24
49
25
=PPVCCSA_S0_CPU
12 15
6 85
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S0_KBDLED
=PP3V3_S0_VMON
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_P1V5S0
=PP3V3_S0_T29PWRCTL
=PP3V3_S0_HS_OTHER_ISNS
=PP3V3_S0_DPSDRVA
=PP3V3_S0_P1V05S0LDO
=PP3V3_S0_IMVPISNS
=PP3V3_S0_XDP
=PP3V3_S0_T29I2C
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_HDD
=PP1V5_S3_DDR_ISNS
49
73
=PP3V3_S0_HDD
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_ISNS
=PP3V3_S0_HS_COMPUTING_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_LCD
=PP3V3_S0_DP_DDC
=PP3V3_S0_ENETPHY
=PP3V3_S0_FAN_RT
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_P3V3T29FET
=PP3V3_S0_SDCARD
=PP3V3_S0_P1V8S0
=PP3V3_S0_ODD
=PP3V3_FW_P3V3FWFET
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCCA_LVDS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMC
72
PP5V_SUS
PP5V_S3
20 22
PP3V3_S4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
72
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
B
17
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_SDBUF
=PP3V3_S3_P3V3ENETFET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_ISNS
=PP3V3_S3_USBMUX
PP5V_S5
=PP5V_SUS_PCH
74
=PP3V3_S3_BT
=PP3V3_S3_MEMRESET
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_SMS
46
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S5_P1V5DDRFET
=PP5V_S5_TPAD
=PP5V_S5_P5VSUSFET
72
PP3V3_SUS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
42
5V Rails
=PP5V_S5_LDO
26
73
48
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE
66
46
6
=PP1V8_S0_CPU_VCCPLL
=PP1V8_S0_PCH_VCCTX_LVDS
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_P1V05S0LDO
=PP1V8R1V5_S0_PCH_VCCVRM
=PPVDDIO_S0_SBCLK
72
=PP3V3_S4_TPAD
=PP3V3_S4_SMC
=PP3V3_S4_SD_HPD
=PP3V3_S4_BT
PPVRTC_G3H
=PPVRTC_G3_PCH
=PP3V3_S5_SMCBATLOW
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
47
1
"FW" (FireWire) Rails
PP1V8_S0
72
=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH
=PP3V3_SUS_PWRCTL
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_SMC
=PP3V3_SUS_ROM
=PP3V3_SUS_PCH_VCC_SPI
66
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
2A max supply
23
67
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
63
=PP1V8_S0_REG
71
24
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
PPDCIN_G3H
=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE
3
6 85
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S5_XDP
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_LCD
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_PWRCTL
=PP3V3_S5_P3V3SUSFET
=PP3V3_S4_TBTAPWRSW
=PP3V3_S5_PCH_GPIO
68 69
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S5_5VS3
=PPVIN_S5_3V3S5
4
1.8V/1.5V/1.2V/1.05V Rails
PP3V3_S5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE
D
5
3.3V Rails
5
PP1V05_SUS
=PP1V05_SUS_LDO
71
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
41
57 61 62
Chipset "VCore" Rails
=PP1V05_SUS_PCH_JTAG
77
23
69
=PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU
50
51
=PPCPUVCCIO_S0_REG
70
PP1V05_S0
8
36
52
39
39 40
35
30
XW0800
SM
71
41
1
2
39
XW0801
SM
16 22
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MAKE_BASE=TRUE
? mA
74
16 17 18 19 30
1
22
20 22
20 22
20 22
20 22
22
20
73
24
24
48
48
48
41
54
2
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
49
=PPVCORE_S0_CPU
=PPCPUVCORE_S0_VSENSE
=PP1V05_S0_CPU_VCCIO
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
=PP1V05_S0_FWPWRCTL
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_VMON
=PP1V05_S0_P1V05T29FET
9 12 14
B
49
9 10 12 14
68
23
69
=PPVCORE_S0_AXG_REG
PPVCORE_S0_AXG
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
46
39
39
=PPVCORE_S0_CPU_VCCAXG
=PPAXGVCORE_S0_VSENSE
73
9 12 15
49
35
PP1V05_S0_PCH
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1V
MAKE_BASE=TRUE
15 12
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
=PP1V5_S3_CPU_VCCDQ
PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
20
16 22
20 22
14 12 8
=PP1V05_S0_CPU_VCCPQE
PP1V05_S0_CPU_VCCPQE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
17
16 20 22
20 22
20 22
14 12
=PP1V8_S0_CPU_VCCPLL_R
PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
20 22
20 22
16 20 22
20 22
20 22
20
20 22
20
20
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Power Aliases
73
27
DRAWING NUMBER
29
35
Apple Inc.
ENET Rails
71
73
=PP3V3_ENET_FET
PP3V3_ENET
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
50
75
49
23
24 36 71
24
24
48
4
R
NOTICE OF PROPRIETARY PROPERTY:
=PP3V3_ENET_PHY
=PP3V3_ENET_SYSCLK
=PPVDDIO_ENET_CLK
71
3
051-9058
REVISION
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
6.0.0
BRANCH
PAGE
8 OF 109
SHEET
7 OF 86
1
SIZE
D
A
8
7
6
5
4
CPU signals
9
9
HEATSINK STANDOFFS
26
MEMVTT_EN
=DDRVTT_EN
26 67
9
MAKE_BASE=TRUE
9
Z0902
DP_EXTA_ML_C_P<3..0>
81 75
STDOFF-4.5OD.98H-1.1-3.48-TH
3
=PEG_R2D_C_P<12..15>
=PEG_R2D_C_N<12..15>
=PEG_D2R_P<12..15>
=PEG_D2R_N<12..15>
DP_EXTA_ML_C_N<3..0>
81 75
33 81
17
33 81
17
=PP3V3_S0_DP_DDC
8 7
TP_DP_IG_B_MLN<3..0>
17
DPA_IG_AUX_CH_P
17
DPA_IG_AUX_CH_N
17
R0920
R0921
R0922
R0923
17
2.2K
2.2K
2.2K
2.2K
17
TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_MLN<3..0>
DPB_IG_AUX_CH_P
DPB_IG_AUX_CH_N
17
TP_DP_IG_D_HPD
1
MAKE_BASE=TRUE
DP_EXTA_AUXCH_C_N
81 75
17
D
1
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
Z0904
DP_T29SNK0_HPD
33
MAKE_BASE=TRUE
17
DP_EXTA_AUXCH_C_P
DPB_IG_HPD
33 81
MAKE_BASE=TRUE
81 75
1
T29 DP Ports
33 81
MAKE_BASE=TRUE
TP_DP_IG_B_MLP<3..0>
MAKE_BASE=TRUE
1
2
PCIE_T29_R2D_C_P<3..0>
MAKE_BASE=TRUE
PCIE_T29_R2D_C_N<3..0>
MAKE_BASE=TRUE
PCIE_T29_D2R_P<3..0>
MAKE_BASE=TRUE
PCIE_T29_D2R_N<3..0>
FAN STANDOFF
1
5%
1/16W
MF-LF
402 2
1
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_AUXCH_C_P
MAKE_BASE=TRUE
DP_T29SNK0_AUXCH_C_N
33 83
MAKE_BASE=TRUE
33 83
MAKE_BASE=TRUE
33 83
33 83
MAKE_BASE=TRUE
DP_T29SNK1_HPD
33
MAKE_BASE=TRUE
D
STDOFF-4.5OD.98H-1.1-3.48-TH
Z0905
1
STDOFF-4.5OD.98H-1.1-3.48-TH
FW_PLUG_DET_L
FW_PME_L
19 39
=FW_PME_L
38 39
17
MAKE_BASE=TRUE
1
17
BELOW CPU
FW643_WAKE_L
39
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
DP_IG_D_CTRL_CLK
MAKE_BASE=TRUE
DP_IG_D_CTRL_DATA
16
16
16
16
LEFT OF CPU
81 16
MLB MOUNTING (TO C. BRACKET) SCREW HOLES
OMIT
81 16
1
NC_PCIE_EXCARD_D2RN
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2RP
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDN
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDP
TRUE
MAKE_BASE=TRUE
PCIE_PCH_D2R_N<5..8>
PCIE_PCH_D2R_P<5..8>
PCIE_PCH_R2D_C_N<5..8>
PCIE_PCH_R2D_C_P<5..8>
PEG_CLK100M_P
PEG_CLK100M_N
3R2P5
1
81 16
81 16
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
R0925
2.2K
2.2K
5%
1/16W
MF-LF
402 2
6
C
Z0908
Z0909
Z0910
3R2P5
3R2P5
3R2P5
1
1
17
6
17
NC_LVDS_IG_B_DATAP<0..3>
DP_EXTA_HPD
DPA_IG_HPD
17
MAKE_BASE=TRUE
OMIT
OMIT
Z0911
Z0912
3R2P5
3R2P5
1
LVDS_IG_B_CLK_N
17 80
5%
1/16W
MF-LF
402
NC_LVDS_IG_A_DATAN<3>
MAKE_BASE=TRUE
74 6
17 80
LVDS_IG_A_DATA_P<3>
17 80
NO_TEST=TRUE
MAKE_BASE=TRUE
2
17 80
LVDS_IG_B_DATA_N<0..3>
NO_TEST=TRUE
NC_LVDS_IG_A_DATAP<3>
LVDS_IG_A_DATA_N<3>
17 80
LVDS_IG_DDC_CLK
17
LVDS_IG_DDC_DATA
17
LVDS_IG_BKL_PWM
17
LVDS_IG_PANEL_PWR
17
LVDS_IG_BKL_ON
17
USBHUB_DN1_N
25
NO_TEST=TRUE
LVDS_DDC_CLK
MAKE_BASE=TRUE
PPBUS_SW_LCDBKLT_PWR
1
0
LVDS_DDC_DATA
MAKE_BASE=TRUE
2
77
PPBUS_SW_BKL
LCD_BKLT_PWM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
NC_PCH_CLKOUT_DPN
TRUE
MAKE_BASE=TRUE
TP_PCH_CLKOUT_DPP
16
17 80
NO_TEST=TRUE
100K
MAKE_BASE=TRUE
TP_PCH_CLKOUT_DPN
LVDS_IG_B_CLK_P
LVDS_IG_B_DATA_P<0..3>
NC_LVDS_IG_B_DATAN<0..3>
R09081
77
16
TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74 6
1
TP_LVDS_IG_B_CLKP
DPA_IG_DDC_CLK
R0910
OMIT
NO_TEST=TRUE
DPA_IG_DDC_DATA
MAKE_BASE=TRUE
OMIT
33 83
BCM57765_CE_L_MS_INS_L
MAKE_BASE=TRUE
DP_EXTA_DDC_DATA
MAKE_BASE=TRUE
MLB MOUNTING (TO TOPCASE) SCREW HOLES
OMIT
33 83
MAKE_BASE=TRUE
MAKE_BASE=TRUE
75
NC_PCIE_PCH_D2RN<5..8>
NC_PCIE_PCH_D2RP<5..8>
NC_PCIE_PCH_R2D_CN<5..8>
NC_PCIE_PCH_R2D_CP<5..8>
NC_PEG_CLK100MP
NC_PEG_CLK100MN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
DP_EXTA_DDC_CLK
75
33 83
33 83
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R0924
5%
1/16W
MF-LF
402 2
75
Z0907
3R2P5
1
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_AUXCH_C_P
MAKE_BASE=TRUE
DP_T29SNK1_AUXCH_C_N
MAKE_BASE=TRUE
NC_BCM57765_CE_L_MS_INS_L
OMIT
Z0906
TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_MLN<3..0>
TP_DP_IG_D_AUXP
TP_DP_IG_D_AUXN
=PP3V3_S0_DP_DDC
SMC_EXCARD_PWR_EN
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
17
17
MAKE_BASE=TRUE
1
17
MAKE_BASE=TRUE
8 7
TP_SMC_EXCARD_PWR_EN
Z0920
17
17
MAKE_BASE=TRUE
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
17
MAKE_BASE=TRUE
=PPBUS_SW_BKL
74
LCD_IG_PWR_EN
MAKE_BASE=TRUE
77
77
LCD_BKLT_EN
C
MAKE_BASE=TRUE
NC_PCH_CLKOUT_DPP
TRUE
MAKE_BASE=TRUE
NC_CPU_VCCIO_SEL
MAKE_BASE=TRUE
CPU_VCCIO_SEL
12 78
NO_TEST=TRUE
1
USB Signals
NC_USB3_EXTD_TXN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
T29BST:N
0
MAKE_BASE=TRUE
USB3_EXTD_RX_N
18
80 53
USB3_EXTD_RX_P
14 12 7
18
80 53
=PP1V05_S0_CPU_VCCPQE
80 44
R0940
B
ZS0900
ZS0901
ZS0902
ZS0910
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
SM
SM
SM
SM
1
DP_A_BIAS0
10
DP_A_BIAS2
75
10
EMI IO (SHORT) POGO PINS
1
1
80 45
USB_TPAD_P
USB_IR_N
USB_IR_P
C0960 1
C0962
0.01UF
0.01UF
10%
10V
X5R-CERM 2
0201
C0964
1
DPLL_REF_CLK_P
DPLL_REF_CLK_N
5%
1/16W
MF-LF
2 402
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
SM
80 45
USB_SMC_P
NC_USB_EXTD_EHCIN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
R0941
MAKE_BASE=TRUE
1K
NC_USB_EXTCN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
T29_A_BIAS_R2DP1
75
T29_A_BIAS_R2DN0
75
PM_SLP_S3_L
MAKE_BASE=TRUE
76
76 75 8
51
1
1/20W
51
201
1/20W
1
MF
VOLTAGE=3.3V
ZS0906
ZS0907
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
SM
SM
SM
SM
1
1
1
R0973 201
1
1
MF
VOLTAGE=3.3V
ZS0922
ZS0923
ZS0924
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
POGO-2.0OD-3.5H-K86-K87
SM
SM
SM
SM
SM
NO STUFF
NO STUFF
1
NO STUFF
NO STUFF
USB_EXTD_XHCI_P
18 80
CPU_THERMD_P
9 85
CPU_THERMD_N
9 85
MAKE_BASE=TRUE
CPU_VTTSELECT
1
2 5%
T29_A_BIAS_D2RN1
MF
VOLTAGE=3.3V
OUT
T29_D2R_P<2..3>
83 33
OUT
T29_D2R_N<2..3>
83 33
IN
T29_R2D_C_P<2..3>
83 33
IN
T29_R2D_C_N<2..3>
33
IN
33
IN
T29_LSEO<2>
T29_LSEO<3>
83 33
C0973 1
Digital Ground
NC_T29_D2RP<2..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_T29_D2RN<2..3>
MAKE_BASE=TRUE
GND
NO_TEST=TRUE
0.01UF
1
10%
10V
X5R-CERM 2
0201
0.01UF
ZS0921
1
TP_CPU_THERMDN
T29_A_BIAS_D2RP1
2 5%
C0972
ZS0920
51
1/20W
51
TALL POGO PINS close to DIMM conn.
1
18 80
MAKE_BASE=TRUE
201
1/20W
1
18
USB_EXTD_XHCI_N
Unused T29 Ports
R0972
A
18
USB3_EXTC_RX_P
MAKE_BASE=TRUE
10%
10V
X5R-CERM 2
0201
TP_CPU_VTT_SELECT
ZS0905
USB3_EXTC_RX_N
B
NO_TEST=TRUE
TP_CPU_THERMDP
0.01UF
10%
10V
X5R-CERM 2
0201
EMI TALL POGO PINS
MAKE_BASE=TRUE
C0971 1
1
0.01UF
ZS0904
18
NO_TEST=TRUE
NC_USB_EXTD_XHCIP
VOLTAGE=3.3V
USB3_EXTC_TX_P
T29_A_BIAS_R2DP0
2 5%
C0970
T29_A_BIAS_R2DN1
18
NO_TEST=TRUE
MAKE_BASE=TRUE
MF
18 80
USB3_EXTC_TX_N
NO_TEST=TRUE
NC_USB_EXTD_XHCIN
2 5%
18 80
USB_EXTC_P
NO_TEST=TRUE
NC_USB3_EXTC_RXP
MAKE_BASE=TRUE
18
USB_EXTC_N
NO_TEST=TRUE
MAKE_BASE=TRUE
=TBT_S0_EN
18
USB_EXTD_EHCI_P
NO_TEST=TRUE
NC_USB3_EXTC_TXN
MAKE_BASE=TRUE
73 45 26 17 6
NO_TEST=TRUE
USB_EXTD_EHCI_N
NO_TEST=TRUE
NC_USB_EXTCP
5%
1/16W
MF-LF
2 402
NO_TEST=TRUE
NO_TEST=TRUE
NC_USB3_EXTC_RXN
R0970
25
NO_TEST=TRUE
NC_USB3_EXTC_TXP
T29_A_BIAS
25
USBHUB_DN2_P
MAKE_BASE=TRUE
NC_USB_EXTD_EHCIP
10%
10V
X5R-CERM 2
0201
R0971 201
1
25
USBHUB_DN2_N
NC_USB_SMCP
DPLL_REF_CLKP
0.01UF
10%
10V
X5R-CERM 2
0201
SM
1
USBHUB_DN3_P
NC_USB_SMCN
MAKE_BASE=TRUE
DPLL_REF_CLKN
1
USB_SMC_N
MAKE_BASE=TRUE
ZS0909
25
MAKE_BASE=TRUE
1
ZS0903
25
USBHUB_DN3_N
MAKE_BASE=TRUE
1
Unused eDP CLK
75
USB_TPAD_N
MAKE_BASE=TRUE
1K
T29_A_BIAS
USBHUB_DN1_P
MAKE_BASE=TRUE
5%
1/8W
MF-LF
805
76 75 8
USB_BT_P
MAKE_BASE=TRUE
NO_TEST=TRUE
7 35
USB_BT_N
MAKE_BASE=TRUE
80 44
=PP15V_T29_REG
2
80 32
NO_TEST=TRUE
NC_USB3_EXTD_RXP
R0960
1
80 32
18
NO_TEST=TRUE
NC_USB3_EXTD_RXN
=PPVIN_SW_T29BST
18
USB3_EXTD_TX_P
MAKE_BASE=TRUE
NC_USB3_EXTD_TXP
35 7
USB3_EXTD_TX_N
NO_TEST=TRUE
10%
10V
X5R-CERM 2
0201
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
NC_T29_R2D_CP<2..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_T29_R2D_CN<2..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
T29_LSOE<2>
MAKE_BASE=TRUE
T29_LSOE<3>
MAKE_BASE=TRUE
OUT
33
OUT
33
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Signal Aliases
DRAWING NUMBER
NO STUFF
TBT JTAG
Apple Inc.
Unused PGOOD signal
051-9058
REVISION
R
23 19
IN
19
IN
19
8
7
6
OUT
JTAG_ISP_TCK
JTAG_TBT_TCK
OUT
33
JTAG_TBT_TDI
OUT
19 33
MAKE_BASE=TRUE
JTAG_ISP_TDI
MAKE_BASE=TRUE
JTAG_ISP_TDO
JTAG_TBT_TDO
MAKE_BASE=TRUE
5
TP_P1V5S3RS0_RAMP_DONE
P1V5S3RS0_RAMP_DONE
IN
72
DDRREG_PGOOD
IN
67
MAKE_BASE=TRUE
TP_DDRREG_PGOOD
MAKE_BASE=TRUE
IN
33
4
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
6.0.0
BRANCH
PAGE
9 OF 109
SHEET
8 OF 86
1
SIZE
D
A
6
5
4
3
NOTE:
OMIT_TABLE
78
IN
78 17
IN
78 17
IN
78 17
IN
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
C
14 12 10 9 7
OUT
78 17
OUT
78 17
OUT
24.9
DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
K1
M8
N4
R2
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
W6
V4
Y2
AC9
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
U6
W10
W3
AA7
FDI0_TX_0
FDI0_TX_1
FDI0_TX_2
FDI0_TX_3
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
W7
T4
AA3
AC8
FDI1_TX_0
FDI1_TX_1
FDI1_TX_2
FDI1_TX_3
OUT
OUT
78 17
OUT
78 17
OUT
78 17
OUT
78 17
IN
78 17
IN
FDI_FSYNC<0>
FDI_FSYNC<1>
78 17
IN
FDI_INT
IN
17
IN
78
AA11
AC12
U11
FDI_LSYNC<0>
FDI_LSYNC<1>
EDP_COMP
EDP_HPD
FDI0_TX_0*
FDI0_TX_1*
FDI0_TX_2*
FDI0_TX_3*
FDI1_TX_0*
FDI1_TX_1*
FDI1_TX_2*
FDI1_TX_3*
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
AA10
AG8
FDI0_LSYNC
FDI1_LSYNC
AD2
AF3
EDP_ICOMPO
EDP_COMPIO
PLACE_NEAR=U1000.AF3:12.7MM
AG11
BGA
(1 OF 9)
DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3
U7
W11
W1
AA6
78 17
17
K3
M7
P4
T3
IVY-BRIDGE
2C-35W
DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
78 17
2
1%
1/16W
MF-LF
402
N3
P7
P3
P11
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
OUT
78 17
=PP1V05_S0_CPU_VCCIO
78
R1030
78
1
IN
78 17
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
EDP_HPD
EDP
R1031
1
10K
6
2
6
1%
1/16W
MF-LF
402
TP_EDP_AUX_N
TP_EDP_AUX_P
AG4
AF4
PLACE_NEAR=U1000.AG11:12.7MM
6
6
6
6
6
6
6
B
6
PEG_ICOMPI G3
PEG_ICOMPO G1
PEG_RCOMPO G4
PCI EXPRESS BASED INTERFACE SIGNALS
IN
78 17
U1000
DMI
78 17
DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
IN
M2
P6
P1
P10
EMBEDDED DISPLAY PORT
D
IN
78 17
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
EDP_AUX*
EDP_AUX
TP_EDP_TX_N<0>
TP_EDP_TX_N<1>
TP_EDP_TX_N<2>
TP_EDP_TX_N<3>
AC3
AC4
AE11
AE7
EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*
TP_EDP_TX_P<0>
TP_EDP_TX_P<1>
TP_EDP_TX_P<2>
TP_EDP_TX_P<3>
AC1
AA4
AE10
AE6
EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3
Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are
shared with other interfaces.
NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications).
If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.
78 23 9
78 23 9
78 23 9
78 23 9
78 23 9
23 9
CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>
1
78 23
1
NOSTUFF
R1044
R1045
1K
1K
5%
5%
5%
1/20W
MF
201
201
1
1/20W
MF
2
CRITICAL
=PP1V05_S0_CPU_VCCIO
2
1%
1/16W
MF-LF
402
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>
PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
R1064
IN
6
49.9
49.9
IN
8
IN
8
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
IN
8
IN
8
IN
6
IN
6
IN
6
Note. VOLTAGE=1.05V
IN
6
Note. VOLTAGE=0V
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
6
IN
8
IN
8
IN
8
IN
8
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
6
OUT
8
OUT
8
OUT
8
OUT
8
PLACE_NEAR=U1000.H43:50.8MM
PLACE_SIDE=BOTTOM
=PPVCORE_S0_CPU
NOSTUFF
1
2
1
R1070
2
PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V
NOSTUFF
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23 9
IN
78 23
IN
78 23
IN
78 23
IN
78 23
IN
7 12 14
=PPVCORE_S0_CPU_VCCAXG
NOSTUFF
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
7 9 10 12 14
7 12 15
23
78
78 23
IN
78 23
IN
78 23
IN
23 9
IN
23
IN
IN
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
SA_DIMM_VREFDQ BE7
SB_DIMM_VREFDQ BG7
U1000
BGA
(5 OF 9)
RESERVED
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
H43 VCC_VAL_SENSE
K43 VSS_VAL_SENSE
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
H45 VAXG_VAL_SENSE
K45 VSSAXG_VAL_SENSE
TP_CPU_VCC_DIE_SENSE
F48 VCC_DIE_SENSE
PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B
RSVD_30
RSVD_31
RSVD_32
RSVD_33
N42
NC
L42
NC
L45
NC
L47
RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38
M13
NC
M14
NC
U14
NC
W14
NC
P13
OUT
31
OUT
31
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
D
NC
NC
RSVD_39 AT49NC
RSVD_40 K24 NC
RSVD_41
RSVD_42
RSVD_43
RSVD_44
AH2
NC
AG13
NC
AM14
NC
AM15
NC
RSVD_45 N50 NC
NOSTUFF
R10651
1
R1071
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
85 8
OUT
85 8
OUT
H48 RSVD_6
K48 RSVD_7
CPU_THERMD_P
CPU_THERMD_N
NOTE: Intel does not recommend to use
BA19
this alnalog sense due to accuracy concern.NC
AV19
NC
AT21
NC
BB21
NC
BB19
PLACE_NEAR=U1000.K43:50.8MM
NC
PLACE_SIDE=BOTTOM
AY21
NC
BA22
NOTE: Intel validation sense lines per
NC
AY22
doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.
NC
AU19
NC
AU21
NC
BD21
NC
BD22
NC
BD25
NC
BD26
NC
BG22
NC
BE22
NC
BG26
NC
BE26
NC
BF23
NC
BE24
2
2
PLACE_NEAR=U1000.K45:50.8MM
PLACE_SIDE=BOTTOM
NC
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
A4
TP_CPU_DC_TEST_A4
C4
CPU_DC_TEST_C4_D3
D3
D1
TP_CPU_DC_TEST_D1
A58 TP_CPU_DC_TEST_A58
A59 CPU_DC_TEST_C59_A59
C59
A61 CPU_DC_TEST_C61_A61
C61
D61 TP_CPU_DC_TEST_D61
BD61 TP_CPU_DC_TEST_BD61
BE61 CPU_DC_TEST_BE59_BE61
BE59
BG61 CPU_DC_TEST_BG59_BG61
BG59
BG58 TP_CPU_DC_TEST_BG58
BG4
TP_CPU_DC_TEST_BG4
BG3
CPU_DC_TEST_C4_BE3_BG3
BE3
BG1
CPU_DC_TEST_C4_BE1_BG1
BE1
BD1
TP_CPU_DC_TEST_BD1
C
B
CPU_CFG<16>
CPU_CFG<3>
CPU_CFG<1>
9 CPU_CFG<0>
78 23 9
1K
1/20W
A
OMIT_TABLE
24.9
1
PLACE_NEAR=U1000.G3:12.7MM
78 23 9
EDP
R1042
CPU_PEG_COMP
1
Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
R1010
CRITICAL
78 17
2
2C-35W
7
IVY-BRIDGE
8
201
NOSTUFF
R1046
R1047
1K
1K
1K
1K
1K
1K
5%
5%
5%
5%
5%
5%
1
1/20W
MF
2
NOSTUFF
201
R1040
1/20W
MF
2
NOSTUFF
1
1/20W
MF
2
201
NOSTUFF
1
NOSTUFF
R1041
R1043
1/20W
MF
201
2
1
201
R1049
1/20W
MF
2
NOSTUFF
1
1/20W
MF
201
2
1
MF
201
2
2
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER
These can be Placed close to J2500 and Only for debug access
Apple Inc.
FOR IVYBRIDGE PROCESSOR
CFG [7] :PEG DEFER TRAINING
R
1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB
CFG [6:5] :PCIE BIFURCATION
11 = 1 X16 (DEFAULT)
CFG [4] :eDP ENABLE/DISABLE
1 = DISABLED
CFG [3] :PCIE x4 LANE REVERSAL
1 = NORMAL OPERATION
0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL
1 = NORMAL OPERATION
0 = LANES REVERSED
8
051-9058
7
10 = 2 X8
NOTICE OF PROPRIETARY PROPERTY:
0 = WAIT FOR BIOS
01 = RSVD
00 = X8, X4, X4
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
0 = ENABLED
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
10 OF 109
SHEET
9 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
14 12 10 9 7
OMIT_TABLE
=PP1V05_S0_CPU_VCCIO
CRITICAL
U1000
1
1
1
R1102
1K
5%
5%
1/20W
1/20W
MF
1/20W
2
2
201
MF
2
NC
201
19
OUT
C
78 45
78 46 19
R1103
CPU_PROCHOT_L
2
78 46 19
78 26 17
IN
78 17
R1121
2
PM_MEM_PWRGD
2
130
78 23 19
CPU_PECI
A48 PECI
C45 PROCHOT*
PM_THRMTRIP_L
D45 THERMTRIP*
IN
PM_SYNC
C48 PM_SYNC
IN
CPU_PWRGD
B46 UNCOREPWRGOOD
PM_MEM_PWRGD_R
1
1%
1/16W
MF-LF
402
BE45 SM_DRAMPWROK
PLT_RESET_LS1V1_L
26
OUT
D44 RESET*
=MEM_RESET_L
AT30 SM_DRAMRST*
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
78
78
78
14 12 10 9 7
BF44 SM_RCOMP_0
BE43 SM_RCOMP_1
BG43 SM_RCOMP_2
=PP1V05_S0_CPU_VCCIO
1
B
R1126 1
1%
1/16W
MF-LF
402
IN
CPU_RESET_L
2
2
R1112
1
140
75
24 23
16 78
IN
16 78
DPLL_REF_CLK AG3
DPLL_REF_CLK* AG1
DPLL_REF_CLK_P
DPLL_REF_CLK_N
BCLK_ITP N59
BCLK_ITP* N58
IN
8
IN
8
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
IN
16 78
IN
16 78
OUT
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
IN
23 78
(IPU)
(IPU)
PRDY* N53
PREQ* N55
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
C
(IPU)
(IPU)
(IPU)
TCK L56
TMS L55
TRST* J58
XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L
(IPU)
TDI M60
TDO L59
1
200
1%
1/16W
MF-LF
402
OUT
IN
C49 CATERR*
R1113
1
25.5
R1114
1%
1%
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
402
2
402
1
200
1%
2
402
JTAG & BPM
R1120
CPU_CATERR_L
CPU_PROCHOT_R_L
1
5%
1/20W
MF
201
=PP1V5_S3_CPU_VCCDDR
F49 PROC_SELECT*
PWR MGMT
26 15 12 7
BI
BI
CPU_PROC_SEL_L
C57 PROC_DETECT*
DDR3 MISC
78 68 46 45
56
OUT
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
201
MF
2
BCLK J3
BCLK* H2
BGA
(2 OF 9)
1/20W
MF
201
THERMAL
5%
IVY-BRIDGE
2C-35W
NOSTUFF
51
5%
R1101
62
NOSTUFF
R1104
1K
CLOCKS
NOSTUFF
R1100
1
DBR* K58
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*
XDP_CPU_TDI
XDP_CPU_TDO
OUT
23 78
XDP_DBRESET_L
OUT
23 24 78
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
G58
E55
E59
G55
G59
H60
J59
J61
BI
23 78
BI
23 78
BI
23 78
BI
23 78
BI
23
BI
23
BI
23
BI
23
R1111
B
10K
5%
1/20W
MF
2
201
R1125
43.2
2
1
1%
1/20W
MF
201
A
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
11 OF 109
SHEET
10 OF 86
1
A
6
5
4
3
OMIT_TABLE
C
B
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 27
OUT
79 27
OUT
79 27
OUT
79 27
OUT
79 27
OUT
79 27
OUT
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>
BD37
BF36
BA28
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
BE39
BD39
AT41
U1000
BGA
(3 OF 9)
2C-35W
79 28
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
IVY-BRIDGE
BI
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
CRITICAL
SA_CK_0 AU36
SA_CK_0* AV36
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
SA_CKE_0 AY26
MEM_A_CKE<0>
SA_CK_1 AT40
SA_CK_1* AU40
SA_CKE_1 BB26
SA_CS_0* BB40
SA_CS_1* BC41
SA_ODT_0 AY40
SA_ODT_1 BA41
MEMORY CHANNEL A
D
BI
79 28
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
1
OMIT_TABLE
CRITICAL
79 28
2
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>
SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
79 28
27 79
BI
OUT
OUT
27 79
OUT
27 79
OUT
27 79
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
BI
28 79
79 28
BI
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
OUT
27 79
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
79 28
BI
SA_BS_0
SA_BS_1
SA_BS_2
79 29
OUT
79 29
OUT
79 29
OUT
SA_CAS*
SA_RAS*
SA_WE*
79 29
OUT
79 29
OUT
79 29
OUT
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>
BG39
BD42
AT22
SB_BS_0
SB_BS_1
SB_BS_2
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
AV43
BF40
BD45
SB_CAS*
SB_RAS*
SB_WE*
U1000
BGA
(4 OF 9)
IVY-BRIDGE
2C-35W
7
MEMORY CHANNEL B
8
SB_CK_0 BA34
SB_CK_0* AY34
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
SB_CKE_0 AR22
MEM_B_CKE<0>
SB_CK_1 BA36
SB_CK_1* BB36
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
SB_CKE_1 BF27
MEM_B_CKE<1>
SB_CS_0* BE41
SB_CS_1* BE47
SB_ODT_0 AT43
SB_ODT_1 BG47
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
MEM_B_CS_L<0>
MEM_B_CS_L<1>
OUT
29 79
OUT
29 79
MEM_B_ODT<0>
MEM_B_ODT<1>
OUT
29 79
OUT
29 79
SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
BI
28 79
D
C
28 79
BI
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
OUT
29 79
B
A
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU DDR3 INTERFACES
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
12 OF 109
SHEET
11 OF 86
1
A
8
7
6
5
4
3
15 12 9 7
2
=PPVCORE_S0_CPU_VCCAXG
1
OMIT_TABLE
CRITICAL
AG51
AJ17
AB53 VAXG_6
AB55 VAXG_7
AJ21
AB56 VAXG_8
AB58 VAXG_9
AB59 VAXG_10
AJ25
AJ43
AL15
AL16
AD50 VAXG_14
AD51 VAXG_15
AD52 VAXG_16
AL20
AL22
AD53 VAXG_17
AD55 VAXG_18
AL26
AD56 VAXG_19
AD58 VAXG_20
AD59 VAXG_21
AL45
AL48
AM16
AE46 VAXG_22
N45 VAXG_23
P47 VAXG_24
AM17
AM21
AM47
AN20
AN42
AN45
P52 VAXG_28
P53 VAXG_29
AN48
P55 VAXG_30
P56 VAXG_31
P61 VAXG_32
W16
AA15
AB17
T48 VAXG_33
T58 VAXG_34
T59 VAXG_35
AB20
AC13
AD16
T61 VAXG_36
U46 VAXG_37
V47 VAXG_38
AD18
AD21
AE15
AF16
AF20
AG15
AG17
AG20
AG21
AJ14
=PP1V05_S0_CPU_VCCIO
15 12 9 7
7 9 10 12 14
R1302
130 PLACE_NEAR=U1000.C44:2.54mm
IVB supports 1.05V VCCIO.
VCCIO_SEL can be NC.
VCCPQE_1
VCCPQE_2
AM25
PLACE_NEAR=R1310.2:2.54mm
1
1
CPU_VCCIO_SEL
2
8 78
1%
1/16W
MF-LF
402
1
201 1/20W
=PP1V05_S0_CPU_VCCPQE
2 5%
1%
1/20W
MF
201
R1311
201 1/20W
A44
B43
C44
CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R
VCC_SENSE
VSS_SENSE
F43
G43
CPU_VCCSENSE_P
CPU_VCCSENSE_N
0 1
IN
68 78
CPU_VIDSCLK
MF
R1312
201 1/20W
0
1
OUT
68 78
OUT
Y48 VAXG_55
Y61 VAXG_56
78 68
OUT
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
14 7
2 5%
CPU_VIDSOUT
MF
BI
Note. VOLTAGE=1.05V
F45 VAXG_SENSE
G45 VSSAXG_SENSE
Note. VOLTAGE=0V
=PP1V8_S0_CPU_VCCPLL_R
68 78
BB3 VCCPLL_1
BC1 VCCPLL_2
BC4 VCCPLL_3
VCCIO_SENSE
VSS_SENSE_VCCIO
AN16
AN17
NOSTUFF
=PPVCORE_S0_CPU
=PP1V05_S0_CPU_VCCIO
15 12 7
7 9 12 14
NOSTUFF
1
R1360
PLACE_NEAR=U1000.F43:50.8mm
PLACE_SIDE=BOTTOM
7 9 10 12 14
NOSTUFF
1
R1362
100
1%
1/16W
MF-LF
402
2
100
2
1%
1/16W
MF-LF
402
PLACEMENT NOTE:
Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V
NOSTUFF
A
PLACE_NEAR=U1000.G43:50.8mm
PLACE_SIDE=BOTTOM
2
AN34
AN38
AR26
AR28
=PPVCCSA_S0_CPU
15 12 7
AR30
AR32
AR34
26 15 12 10 7
AR36
OUT
68 78
OUT
68 78
OUT
70 78
OUT
70 78
=PP1V5_S3_CPU_VCCDDR
R13821
AR40
AV41
100
PLACE_NEAR=U1000.U10:50.8mm
1%
1/16W
MF-LF
402
AW26
R13801
BA40
BB28
2
PLACE_NEAR=U1000.BC43:50.8mm 100
1%
PLACE_SIDE=BOTTOM
1/16W
MF-LF
402
BG33
=PP1V5_S3_CPU_VCCDQ
2
C
7 15
AN26
CPU_VDDQ_SENSE_P
Note.
CPU_VDDQ_SENSE_N
VCCSA_SENSE
U10
CPU_VCCSASENSE
VCCSA_VID_0
VCCSA_VID_1
D48
D49
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
VOLTAGE=1.05V
Note. VOLTAGE=0V
CPU_SM_VREF
VOLTAGE=0.75V
AY43
OUT
65
65
OUT
65
12
R13811
1 1
5%
1/20W
MF
201
1/16W
MF-LF
402
R1313
2
10K
2 2
5%
1/20W
MF
201
PLACEMENT NOTE:
Please place all sense line resistors on BOTTOM side.
B
=PP1V5_S3_CPU_VCCDDR
1
R1330
PLACE_NEAR=U1000.BJ44:2.54mm
1K
5%
1/16W
MF-LF
402
2
CPU_SM_VREF
N16 VCCSA_3
N20 VCCSA_4
2
N22 VCCSA_5
P17 VCCSA_6
P20 VCCSA_7
R16 VCCSA_8
R18 VCCSA_9
R13311
PLACE_NEAR=U1000.BJ44:2.54mm
1K
5%
1/16W
MF-LF
402
1
12
C1330
0.1UF
10%
16V
2 X7R-CERM
2
0402
PLACE_NEAR=U1000.BJ44:2.54mm
R21 VCCSA_10
U15 VCCSA_11
V16 VCCSA_12
V17 VCCSA_13
V18 VCCSA_14
V21 VCCSA_15
W20 VCCSA_16
1
R1363
100
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
Please place all sense line resistors on BOTTOM side.
NOSTUFF
R13611
100
L17 VCCSA_1
L21 VCCSA_2
PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
AN30
=PPVCCSA_S0_CPU
R13711
PLACE_NEAR=U1000.G45:50.8mm
PLACE_SIDE=BOTTOM
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
AM36
AM40
26 15 12 10 7
78 68
2 5%
AM33
10K
PLACE_NEAR=U1000.A44:38mm
7 8
14
AN22
VIDALERT*
VIDSCLK
VIDSOUT
PLACE_NEAR=U1000.F45:50.8mm
PLACE_SIDE=BOTTOM
CPU_VIDALERT_L
MF
100
1%
1/16W
MF-LF
402 2
R13701
75
2
W55 VAXG_52
W56 VAXG_53
W61 VAXG_54
NOSTUFF
R1300
43
R1310
AL38
AL42
W52 VAXG_50
W53 VAXG_51
AJ15
W17
AL34
R1314
V59 VAXG_47
W50 VAXG_48
W51 VAXG_49
=PPVCORE_S0_CPU_VCCAXG
AJ40
AL30
PLACE_NEAR=U1000.BA43:50.8mm 100
1%
PLACE_SIDE=BOTTOM
V55 VAXG_44
V56 VAXG_45
V58 VAXG_46
AG16
D
AJ33
AJ36
BA43
SM_VREF
V51 VAXG_41
V52 VAXG_42
V53 VAXG_43
AF18
BC22
VDDQ_SENSE
VSS_SENSE_VDDQ
BC43
(IPU)
V48 VAXG_39
V50 VAXG_40
AE14
VCCIO_SEL
AM28
(IPU)
P48 VAXG_25
P50 VAXG_26
P51 VAXG_27
AM43
VCCIO_50
VCCIO_51
GRPHICS
AL14
AA14
VCCDQ_1
VCCDQ_2
AC61 VAXG_11
AD47 VAXG_12
AD48 VAXG_13
AK50
AK51
VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49
AJ28
DDR3-1.5V RAILS
AJ47
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
2C-35W
AB50 VAXG_3
AB51 VAXG_4
AB52 VAXG_5
IVY-BRIDGE
(NOT controlled by VCCIO_SEL)
Fixed at 1.05V
AG48
AG50
QUIET
RAIL
AF46
SENSE
LINE
2C-35W
IVY-BRIDGE
PEG AND DDR
CORE SUPLLY
VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29
BGA
(7 OF 9)
SENSE
LINE
B
BGA
(6 OF 9)
QUIET
RAIL
C
U1000
SVID
D
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
U1000
AA46 VAXG_1
AB47 VAXG_2
SENSE
LINES
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
=PP1V5_S3_CPU_VCCDDR
=PP1V05_S0_CPU_VCCIO
CRITICAL
1.8V
RAIL
OMIT_TABLE
SA RAIL
14 12 9 7
=PPVCORE_S0_CPU
100
2
1%
1/16W
MF-LF
402
PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=BOTTOM
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU POWER
DRAWING NUMBER
PLACEMENT NOTE:
Apple Inc.
Please place all sense line resistors on BOTTOM side.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
13 OF 109
SHEET
12 OF 86
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
CRITICAL
OMIT_TABLE
BG21 VSS
BG24 VSS
BG28 VSS
D
BG37 VSS
BG41 VSS
BG45 VSS
BG49 VSS
BG53 VSS
U1000
BGA
(9 OF 9)
VSS
IVY-BRIDGE
2C-35W
BG13 VSS
BG17 VSS
C29 VSS
C35 VSS
C40 VSS
D4 VSS
D6 VSS
D10 VSS
D14 VSS
D18 VSS
D22 VSS
D26 VSS
D29 VSS
D35 VSS
D40 VSS
D43 VSS
D46 VSS
D50 VSS
D54 VSS
D58 VSS
E3 VSS
E25 VSS
E29 VSS
E35 VSS
C
E40 VSS
F13 VSS
F15 VSS
F19 VSS
F29 VSS
F35 VSS
F40 VSS
F55 VSS
G6 VSS
G48 VSS
G51 VSS
G61 VSS
H4 VSS
H10 VSS
H14 VSS
H17 VSS
H21 VSS
H53 VSS
H58 VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9 VSS
A13 VSS
M11
M15
A17 VSS
A21 VSS
A25 VSS
M58
N1
N17
A28 VSS
A33 VSS
A37 VSS
N21
N25
A40 VSS
A45 VSS
N28
N33
N36
A49 VSS
A53 VSS
AA1 VSS
N40
N43
N47
AA8 VSS
AA13 VSS
AA50 VSS
N48
N51
N52
AA51 VSS
AA52 VSS
AA53 VSS
N56
N61
AA55 VSS
AA56 VSS
P9
P14
P16
AB16 VSS
AB18 VSS
AB21 VSS
P18
P21
P58
AB48 VSS
AB61 VSS
AC6 VSS
P59
R4
R17
AC10 VSS
AC14 VSS
AC46 VSS
R20
R46
AD4 VSS
AD17 VSS
T1
T47
T50
AD20 VSS
AD61 VSS
AE8 VSS
T51
T52
T53
AE13 VSS
AF1 VSS
AF17 VSS
T55
T56
U8
AF21 VSS
AF47 VSS
AF48 VSS
U13
V20
AF50 VSS
AF51 VSS
V61
W8
W13
AF52 VSS
AF53 VSS
AF55 VSS
W15
W18
W21
AF56 VSS
AF58 VSS
AF59 VSS
W46
Y4
Y47
AG7 VSS
AG10 VSS
AG14 VSS
Y58
Y59
AG18 VSS
AG47 VSS
J1 VSS
J49 VSS
J55 VSS
AG52 VSS
AG61 VSS
AH4 VSS
K8 VSS
K11 VSS
K21 VSS
B
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
K51 VSS
L16 VSS
L20 VSS
L22 VSS
L26 VSS
L30 VSS
L34 VSS
L38 VSS
L43 VSS
L48 VSS
L61 VSS
M4 VSS
M6 VSS
AH58 VSS
AJ7 VSS
AJ13 VSS
A5
A57
BC61
BD3
AJ16 VSS
AJ20 VSS
AJ22 VSS
BD59
BE4
AJ26 VSS
AJ30 VSS
BE58
BG5
BG57
AJ34 VSS
AJ38 VSS
AJ42 VSS
C3
C58
D59
AJ45 VSS
AJ48 VSS
AK1 VSS
E1
E61
AK52 VSS
AL10 VSS
AL13 VSS
AL17 VSS
AL21 VSS
AL25 VSS
AL28 VSS
AL33 VSS
AL36 VSS
AL40 VSS
AL43 VSS
AL47 VSS
AL61 VSS
AM4 VSS
A
AM13 VSS
AM20 VSS
AM22 VSS
AM26 VSS
AM30 VSS
U1000
BGA
(8 OF 9)
VSS
IVY-BRIDGE
2C-35W
CRITICAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM34
AM38
AM42
AM45
AM48
AM58
D
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36
AT45
C
AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45
B
AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU GROUNDS
BD56
BE5
BG9
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
14 OF 109
SHEET
13 OF 86
1
A
8
7
6
5
4
3
2
1
All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide
CPU VCORE DECOUPLING
Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF
12 9 7
CRITICAL CRITICAL
=PPVCORE_S0_CPU
C1600
1
1
2.2UF
2.2UF
20%
4V
2 X5R
402
D
C1604
C1625
1
2.2UF
C1627
C1628
1
C1650
2.2UF
C1651
2.2UF
20%
2 4V
X5R
402
1
1
2.2UF
1
2.2UF
C1609
2.2UF
1
2.2UF
1
2.2UF
C1635
1
1
2.2UF
C1637
1
1
20%
4V
2 X5R
402
CRITICAL
C1638
1
2.2UF
C1615
2.2UF
20%
4V
2 X5R
402
1
C1639
1
2.2UF
C1640
20%
2 4V
X5R
402
CRITICAL CRITICAL
1
C1623
2.2UF
1
1
C1641
1
2.2UF
20%
2 4V
X5R
402
C1624
2.2UF
20%
4V
2 X5R
402
20%
4V
2 X5R
402
CRITICAL CRITICAL
2.2UF
20%
2 4V
X5R
402
C1617
20%
4V
2 X5R
402
CRITICAL
2.2UF
20%
2 4V
X5R
402
20%
2 4V
X5R
402
CRITICAL CRITICAL
C1613
2.2UF
20%
4V
2 X5R
402
2.2UF
20%
2 4V
X5R
402
CRITICAL
C1612
CRITICAL CRITICAL
2.2UF
20%
2 4V
X5R
402
C1610
20%
4V
2 X5R
402
CRITICAL
C1632
CRITICAL CRITICAL
1
20%
4V
2 X5R
402
CRITICAL
C1631
C1642
1
2.2UF
20%
2 4V
X5R
402
D
CRITICAL
C1643
CRITICAL
1
2.2UF
CRITICAL
C1644
1
2.2UF
20%
2 4V
X5R
402
C1645
2.2UF
20%
2 4V
X5R
402
20%
2 4V
X5R
402
CRITICAL
1
C1647
2.2UF
20%
2 4V
X5R
402
CRITICAL
1
C1648
2.2UF
20%
2 4V
X5R
402
CRITICAL CRITICAL
C1652 C1653 1 C1654
1
2.2UF
20%
2 4V
X5R
402
CRITICAL
C1608
20%
4V
2 X5R
402
20%
2 4V
X5R
402
CRITICAL
1
1
CRITICAL
2.2UF
20%
2 4V
X5R
402
CRITICAL
1
CRITICAL
C1607
20%
4V
2 X5R
402
CRITICAL
20%
2 4V
X5R
402
CRITICAL
CRITICAL
1
2.2UF
20%
4V
2 X5R
402
2.2UF
20%
2 4V
X5R
402
1
C1606
2.2UF
20%
4V
2 X5R
402
CRITICAL CRITICAL
1
CRITICAL
1
2.2UF
20%
2 4V
X5R
402
2.2UF
20%
2 4V
X5R
402
20%
2 4V
X5R
402
PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.
CRITICAL
1
CRITICAL
OMIT
C1655
1
22UF
1
22UF
20%
6.3V
2 X5R-CERM-1
603
C
CRITICAL
OMIT
C1656
CRITICAL
OMIT
C1657
1
22UF
NOSTUFF
C1659
1
22UF
20%
6.3V
2 X5R-CERM-1
603
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1658
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
1
CRITICAL
OMIT
C1660
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1661
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
NOSTUFF
C1662
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
NOSTUFF
C1663
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1664
1
22UF
20%
6.3V
2 X5R-CERM-1
603
1
22UF
20%
6.3V
2 X5R-CERM-1
603
PART NUMBER
CRITICAL
NOSTUFF
C1665
QTY
138S0691
16
22UF
20%
6.3V
2 X5R-CERM-1
603
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
OMIT
C1666
CRITICAL
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
C1655,C1660,C1661,C1664,C1666,C1667,C1670,C1677,C1678,C1679,C1657,C1672,C1658,C1669,C1668,C1656
20%
6.3V
2 X5R-CERM-1
603
C
PLACEMENT_NOTE (C1667-C1679):
Place close to U1000 on bottom side.
CRITICAL
CRITICAL
OMIT
1
CRITICAL
OMIT
C1667
1
22UF
OMIT
C1668
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1669
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
C1670
20%
6.3V
2 X5R-CERM-1
603
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
NOSTUFF
C1671
1
22UF
CRITICAL
C1672
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
NOSTUFF
C1673
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
NOSTUFF
C1674
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
NOSTUFF
C1675
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
NOSTUFF
C1676
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1677
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1678
1
22UF
20%
6.3V
2 X5R-CERM-1
603
C1679
22UF
20%
6.3V
2 X5R-CERM-1
603
20%
6.3V
2 X5R-CERM-1
603
PLACEMENT_NOTE (C1640-C1645):
Place near inductors on bottom side.
1
3
1
C1680
1
C1681
1
C1682
470UF-4MOHM
470UF-4MOHM
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
20%
2.0V
POLY-TANT
D2T-SM1
20%
2.0V
POLY-TANT
D2T-SM1
2
3
2
3
2
C1683
470UF-4MOHM
3
2
20%
2.0V
POLY-TANT
D2T-SM1
CPU VCCIO/VCCPQ DECOUPLING
CPU VCCPLL DECOUPLING
Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF
Intel recommendation (section 6.4): 2x 1uF, 1x 330uF
PLACEMENT_NOTE (C1684-C167F):
12 10 9 7
=PP1V05_S0_CPU_VCCIO
B
PLACEMENT_NOTE (C1646-C1671):
Place on bottom side of U1000
U100.
Place near U1000 on top side
R1600
1
2
C1684
1
C1685
C1686
1
C1687
1
1
C1688
1
C1689
1
C1690
1
C1691
1
C1692
1
C1693
1
C1694
1
C1695
1
C1696
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
2
2
2
2
2
2
2
2
2
2
2
2
=PP1V8_S0_CPU_VCCPLL_R
B
7 12
0
7 =PP1V8_S0_CPU_VCCPLL
1
2
5%
1/16W
MF-LF
402
PLACE_NEAR=U1000.BC1:5mm
1
2
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
C160X
1
C160Y
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
2
1
C160Z
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1697
1
1UF
2
C1698
C1699
1
1UF
10%
10V
X5R
402
2
1
1UF
10%
10V
X5R
402
1
1UF
10%
10V
X5R
402
2
C169A
2
C169B
1
1UF
10%
10V
X5R
402
2
C169C
1
1UF
10%
10V
X5R
402
2
C169D
1
1UF
10%
10V
X5R
402
2
C169E
1
1UF
10%
10V
X5R
402
2
C169F
1
1UF
10%
10V
X5R
402
2
C161A
1
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
C161B
1
1UF
2
10%
10V
X5R
402
C161C
1
1UF
2
10%
10V
X5R
402
C161D
CPU VCCPLL Low pass filter
1UF
2
10%
10V
X5R
402
PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
1
2
1
C161E
1
1
C161F
1
C162A
C162B
1
C162C
1
C162D
1
C162E
1
1
C167A
C167B
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
2
C167D
330UF
1
2
C167E
330UF
1
C167G
330UF
2
1
C167H
330UF
1
2
2
2
2
2
1
C167C
10UF
2
20%
6.3V
CERM-X5R
0402-1
C167J
330UF
20%
20%
20%
20%
20%
2 2.5V
2 2.5V
2 2.5V
2 2.5V
2 2.5V
TANT
TANT
TANT
TANT
TANT
CASE-B2-SM1
CASE-B2-SM1
CASE-B2-SM1
CASE-B2-SM1
CASE-B2-SM1
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/27/2011
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
DRAWING NUMBER
R1601
Apple Inc.
0.010
1
2
=PP1V05_S0_CPU_VCCPQE
7 8 12
051-9058
R
1%
1/4W
MF
0603
1
8
C167F
NOTICE OF PROPRIETARY PROPERTY:
1UF
2
7
10%
10V
X5R
402
Note:The smallest 10mOhm available in the library are 0805s
6
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
16 OF 109
SHEET
14 OF 86
1
A
8
7
6
5
4
3
2
1
VAXG DECOUPLING
Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF
12 9 7
PLACEMENT_NOTE (C1700-C1710):
=PPVCORE_S0_CPU_VCCAXG
Place on bottom side of U1000
U100.
CRITICAL
CRITICAL
C1700
1
C1701
1
1UF
D
1
1UF
10%
10V
X5R
402
2
CRITICAL
C1703
1
1UF
10%
10V
X5R
402
2
CRITICAL
C1702
1UF
10%
10V
X5R
402
2
CRITICAL
1
C1704
1UF
10%
10V
X5R
402
2
CRITICAL
1
C1705
1UF
10%
10V
X5R
402
2
CRITICAL
1
C1706
1
1UF
10%
10V
X5R
402
2
CRITICAL
2
CRITICAL
C1707
1
1UF
10%
10V
X5R
402
2
CRITICAL
C1708
1
1UF
10%
10V
X5R
402
2
C1709
CRITICAL
1
1UF
10%
10V
X5R
402
2
C1710
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
D
PLACEMENT_NOTE (C1711-C1716):
CRITICAL
1
C1711
CRITICAL
CRITICAL
1
1
C1712
CRITICAL
1
C1713
CRITICAL
1
C1714
C1715
10UF
10UF
10UF
10UF
10UF
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
2
2
2
2
2
CRITICAL
1
C1716
10UF
2
20%
6.3V
CERM-X5R
0402-1
PLACEMENT_NOTE (C1717-C1722):
CRITICAL
CRITICAL
OMIT
C1717
1
1
22UF
CRITICAL
OMIT
C1718
1
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
OMIT
C1719
1
22UF
20%
6.3V
2 X5R-CERM-1
603
OMIT
C1720
22UF
20%
6.3V
2 X5R-CERM-1
603
CRITICAL
1
CRITICAL
OMIT
C1721
1
22UF
20%
6.3V
2 X5R-CERM-1
603
OMIT
PART NUMBER
C1722
22UF
20%
6.3V
2 X5R-CERM-1
603
QTY
138S0691
20%
6.3V
2 X5R-CERM-1
603
6
DESCRIPTION
REFERENCE DES
CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG
C1717,C1718,C1719,C1720,C1721,C1722
CRITICAL
BOM OPTION
CRITICAL
PLACEMENT_NOTE (C1723-C1724):
Place near inductors on bottom side.
1
1
C1723
470UF-4MOHM
C
3
C1724
C
470UF-4MOHM
20%
2.0V
POLY-TANT
D2T-SM1
2
3
2
20%
2.0V
POLY-TANT
D2T-SM1
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF
PLACEMENT_NOTE (C1738-C1747):
26 12 10 7
=PP1V5_S3_CPU_VCCDDR
Place on bottom side of U100.
U1000
1
CPU VCCSA DECOUPLING
C1747
Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
PLACEMENT_NOTE (C1758-C1762):
2
10%
10V
X5R
402
C1752
1
C1738
2
1
2
C1739
C1740
1
2
C1741
1
2
1
2
C1742
1
C1743
1
2
C1744
1
2
C1745
1
2
C1746
1
2
12 7
=PPVCCSA_S0_CPU
Place on bottom side of U1000
U100.
Place close to U1000 on bottom side
1
1
B
1
C1748
1
C1749
C1750
1
C1751
1
C1753
1
C1754
1
C1755
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
X5R
603
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
X5R
603
20%
6.3V
CERM-X5R
0402-1
2
1
2
2
2
2
2
2
2
C1756
1
R1702
2
1%
1/4W
MF
0603
1
C1760
1
C1761
1UF
1UF
1UF
2
2
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
1
C1763
1
C1764
2
1
2
1
C1765
10UF
10UF
10UF
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
2
2
2
C1762
1UF
C1766
10UF
1
2
10%
10V
X5R
402
1
C1767
B
10UF
2
20%
6.3V
CERM-X5R
0402-1
C1768
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
0.010
1
C1759
10%
10V
X5R
402
2
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
1
1UF
330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
C1758
=PP1V5_S3_CPU_VCCDQ
1
7 12
C1757
1UF
2
10%
10V
X5R
402
A
SYNC_MASTER=MASTER
SYNC_DATE=02/15/2011
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
17 OF 109
SHEET
15 OF 86
1
A
7
6
5
4
3
2
OMIT_TABLE
C20
C38
(IPU) LDRQ0*
LDRQ1*/GPIO23
(IPU)
SERIRQ
PANTHERPOINT
MOBILE
FCBGA
(1 OF 10)
D
D20
RTC_RESET_L
RTCRST*
16
PCH_SRTCRST_L
G22
SRTCRST*
16
PCH_INTRUDER_L
K22
INTRUDER*
16
81 16
81 16
C17
PCH_INTVRMEN_L
RTC
LPC
16
INTVRMEN
HDA_BIT_CLK_R
N34
HDA_SYNC_R
L34
HDA_SYNC (IPD-BOOT)
T10
SPKR (IPD-PLTRST#)
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_BCLK
VSel strap not functional (VCCVRM = 1.8V)
6
6
6
81 24 16
33 16
24 16
IN
G34
C34
A34
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
(IPD)
(IPD)
(IPD)
(IPD)
HDA_SDOUT_R
A36
HDA_SDO (IPD-BOOT)
JTAG_TBT_TMS
ENET_MEDIA_SENSE_RDIV
C36
HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13
N32
23
XDP_PCH_TCK
J3
IN
JTAG_TCK (IPD)
23
XDP_PCH_TMS
H7
IN
JTAG_TMS (IPU)
23
C
OUT
E34
HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
23
81 47
81 47
81 47
81 47
IN
OUT
XDP_PCH_TDI
K5
XDP_PCH_TDO
H1
T3
OUT
SPI_CLK_R
OUT
SPI_CS0_R_L
OUT
Y14
TP_SPI_CS1_L
T1
SPI_MOSI_R
V4
U3
SPI_MISO
IN
IHDA
IN
HDA_RST*
JTAG_TDI (IPU)
JTAG_TDO
SATA
81 57
K34
HDA_RST_R_L
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
JTAG
81 16
PCH_SPKR
SPI_CS1*
R1800
1
1
330K
R1801
1M
5%
1/20W
MF
201 2
1
E36
TP_LPC_DREQ0_L
TBT_PWR_EN_PCH
81 36
IN
16
81 36
IN
=PP3V3_S0_PCH
16
1
K36
V5
AP7
AP5
AM10
AP11
AP10
Y7
5%
1/20W
MF
2 201
24
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
AD5
AH5
AH4
AF1
Y5
AD1
Y3
Y1
AB1
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SPI_MISO (IPU)
Y11
80
81 32
IN
81 32
OUT
81 32
OUT
81 38
IN
81 38
IN
41 80
81 38
OUT
IN
41 80
81 38
OUT
OUT
41 80
OUT
41 80
8
IN
8
IN
IN
41 80
8
OUT
8
OUT
IN
41 80
OUT
41 80
OUT
41 80
6
6
6
=PP1V05_S0_PCH_VCCIO_SATA
7 20 22
6
1
6
R1830
37.4
1%
1/20W
MF
2 201
6
6
6
=PP1V05_S0_PCH
7 22
6
81 36
PCH_SATAICOMP
81 36
R1831
OUT
OUT
49.9
2
16
1%
1/20W
MF
201
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
PLACE_NEAR=U1800.AB12:2.54mm
PCH_SATA3COMP
PCH_SATA3RBIAS
P3
V14
P1
PCH_SATALED_L
1
16
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
OUT
OUT
23
OUT
IN
FW_CLKREQ_L
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
23
R1832
81 32
OUT
750
81 32
OUT
1%
1/20W
MF
2 201
32 16
2
16
16
16
16
16
16
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L
R1860
R1861
R1862
R1863
R1864
33
33
33
33
33
1
2
33
HDA_BIT_CLK_R
R1810
PLACE_NEAR=U1800.N34:1.27mm
33
HDA_SYNC_R
R1811
PLACE_NEAR=U1800.L34:1.27mm
33
HDA_RST_R_L
R1812
PLACE_NEAR=U1800.K34:1.27mm
33
HDA_SDOUT_R
R1813
PLACE_NEAR=U1800.A36:1.27mm
JTAG_TBT_TMS
1
2
1
2
1
2
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1
1/20W
MF
OUT
6 45 47 81
HDA_BIT_CLK
OUT
57 81
201
5%
1/20W
MF
201
5%
1/20W
MF
201
BI
6 45 47 81
BI
6 45 47 81
BI
6 45 47 81
R1834
R1833
10K
10K
1
1
2
R1842
R1869
R1844
R1845
R1847
R1814
R1815
10K
10K
10K
10K
10K
10K
10K
1
2
1
2
R1843
R1846
R1848
R1853
R1854
R1855
10K
10K
10K
10K
10K
10K
1
2
1
2
R1879
10K
1
2
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
2
2
1
2
1
2
1
1
2
1
2
1
2
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
BB40
BC38
AW38
AY38
Y39
AB49
AB47
M1
AA48
AA47
AP_CLKREQ_L
Y37
OUT
BI
6 45 47 81
6
36 16
IN
6
PCH_GPIO11
H14
SMBUS_PCH_CLK
SMBUS_PCH_DATA
OUT
SML0ALERT*/GPIO60
A12
USB_EXTB_SEL_XHCI
OUT
16 25
C8
SML_PCH_0_CLK
SML_PCH_0_DATA
OUT
48 81
16
FCBGA
C9
BI
48 81
48 81
(2 OF 10)
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
SML0CLK
SML0DATA
PERN5
PERP5
PETN5
PETP5
G12
SML1ALERT*/PCHHOT*/GPIO74
C13
USB_EXTD_SEL_XHCI
SML1CLK/GPIO58
SML1DATA/GPIO75
E14
SML_PCH_1_CLK
SML_PCH_1_DATA
16
OUT
48 81
BI
M7
TP_CLINK_CLK
6
T11
TP_CLINK_DATA
6
CL_RST1*
P10
TP_CLINK_RESET_L
6
PEG_A_CLKRQ*/GPIO47
16
PERN7
PERP7
PETN7
PETP7
M10
PEGCLKRQA_L_GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
AB37
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
CLKOUT_DP_N
CLKOUT_DP_P
AM12
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
Controlled by PCIECLKRQ5#
CLKOUT_PCIE0P
CLKIN_DMI_N
PCIECLKRQ0*/GPIO73
CLKIN_DMI_P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKIN_GND1_N
CLKIN_GND1_P
PCIECLKRQ1*/GPIO18
AB38
AU22
AM13
BF18
BJ30
OUT
10 78
OUT
10 78
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
OUT
8
OUT
8
C
IN
16 80
IN
16 80
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
IN
16 80
IN
16 80
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
IN
16 80
IN
16 80
PCH_CLK14P3M_REFCLK
IN
16 80
PCH_CLK33M_PCIIN
IN
24 80
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
BG30
48 81
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
BE18
D
48 81
OUT
(IPU/IPD) CL_DATA1
(IPU/IPD) CL_CLK1
PERN6
PERP6
PETN6
PETP6
M16
BI
16
16
Y36
A8
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2*/GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
G24
CLKIN_SATA_N
CLKIN_SATA_P
AK7
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
E24
AK5
PCIECLKRQ3*/GPIO25
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
Y43
JTAG_DPMUXUC_TRST_L
L12
PCIECLKRQ4*/GPIO26
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
V45
CLKOUT_PCIE5N
CLKOUT_PCIE5P
ENET_CLKREQ_L
L14
Y45
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
OUT
57 81
HDA_RST_L
OUT
57 81
5%
1/20W
MF
OUT
201
78 10
PCH_SPKR
PCH_SATALED_L
DP_AUXCH_ISOL
SATARDRVR_EN
FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
PCIECLKRQ0_L_GPIO73
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
PCH_GPIO11
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI
ENET_MEDIA_SENSE_RDIV
ITPCPU_CLK100M_N
16
NO STUFF
16
R1841
23 75
78 10
ITPCPU_CLK100M_P
0
AB40
16 39
2
5%
1/20W
MF
201
PEGCLKRQB_L_GPIO56
PEG_CLK100M_N
PEG_CLK100M_P
V40
OUT
T13
PCIECLKRQ6*/GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
V42
IN
PEG_CLKREQ_L
81 33
81 33
OUT
PCIE_CLK100M_T29_N
PCIE_CLK100M_T29_P
V38
OUT
35 16
TBT_CLKREQ_L
K12
IN
78 23
78 23
V37
AK14
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
AK13
1
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCIECLKRQ7*/GPIO46
(IPU-RSMRST#)
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
XCLK_RCOMP
Y47
PLACE_NEAR=U1800.Y47:2.54mm
PCH_XCLK_RCOMP
CLKOUTFLEX0/GPIO64
(IPD-PWROK)
K43
TP_PCH_GPIO64_CLKOUTFLEX0
6
CLKOUTFLEX1/GPIO65
(IPD-PWROK)
F47
TP_PCH_GPIO65_CLKOUTFLEX1
6
CLKOUTFLEX2/GPIO66
(IPD-PWROK)
H47
TP_PCH_GPIO66_CLKOUTFLEX2
6
CLKOUTFLEX3/GPIO67
(IPD-PWROK)
K49
TP_PCH_GPIO67_CLKOUTFLEX3
6
R1872
IN
SYSCLK_CLK25M_SB
1
80 16
16
80 16
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
R1891
R1892
10K
10K
1
1
2
80 16
80 16
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
R1893
R1894
10K
10K
1
2
1
2
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
R1895
R1896
10K
10K
1
2
1
2
16
80 16
80 16
16 25
80 16
PCH_CLK14P3M_REFCLK
R1897
10K
1
2
PCH_CLKIN_GNDP1
PCH_CLKIN_GNDN1
R1870
R1871
10K
10K
1
2
16
16
16
4
1
2
SYSCLK_CLK25M_SB_R
2
1
16 81
1.8V -> 1.1V
R1873
1K
2
16 35
16
604
1%
1/16W
MF-LF
402
Unused clock terminations for FCIM Mode
16 36
5
B
=PP1V05_S0_PCH_VCCDIFFCLK
90.9
2
16
6
16 81
1%
1/20W
MF
201 2
16
16 24
SYSCLK_CLK25M_SB_R
NC
PEG_B_CLKRQ*/GPIO56
OUT
81 24
16
V49
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
81 8
16
0
E6
16 32
16
V47
22 20 7
5%
1/20W
MF
201
23 41
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.
7
1
AB42
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
XTAL25_IN
XTAL25_OUT
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
81 8
57 81
1
V46
DOES THIS NEED LENGTH MATCH???
R1890
16
HDA_SYNC
HDA_SDOUT
2
16 33
201
5%
AY40
IN
6
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
NO STUFF
5%
BJ40
E12
SMBCLK
SMBDATA
16
R1840
2
AV36
V10
6
7 19
1
AU36
J2
39 16
7 17 18 19 30
1
BG38
PCIECLKRQ0_L_GPIO73
81 38
6
10%
10V
X5R
402
MF
BB36
SMBALERT*/GPIO11
MOBILE
16
1UF
1/20W
AY36
Y40
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
16
C1803
2
BH37
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
OUT
7 17 18 19
5%
8
BE38
IN
81 24 16
1
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
81 38
16
81 16
A
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
BG40
EXCARD_CLKREQ_L
2
BB34
BJ38
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
2
AY34
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
OUT
1
BE36
BG37
OUT
1
BF36
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
81 8
81 16
2
AU34
U1800
PANTHERPOINT
PLACE_NEAR=U1800.Y11:2.54mm
6
6
1
AV34
81 8
16
1
BJ36
5%
1/20W
MF
2 201
81 16
4.7K
10K
AY32
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
6
6
AU32
BB32
20K
10%
10V
X5R
402
R1877
R1878
BG36
AV32
PERN1
PERP1
PETN1
PETP1
PLACE_NEAR=U1800.AH1:2.54mm
SATA0GP/GPIO21
SATA1GP/GPIO19
(IPU)
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
1
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
BJ34
BF34
R1803
1UF
10K
BE34
5%
1/20W
MF
201 2
C1802
R1876
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
6
AB12
AB13
IN
IN
Y10
AH1
81 32
6
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
AB3
OUT
6
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
AD3
OUT
81 36
BG34
6
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
AB10
AF3
81 36
6 45 47
BI
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
AM8
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
10K
OUT
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
AM1
AB8
R1820
LPC_SERIRQ
AM3
7 22
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
20K
5%
1/20W
MF
2 201
B
16
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATAICOMPO
SATAICOMPI
SPI_MOSI (IPD-BOOT)
7 17 20
R1802 1
LPC_FRAME_R_L
C37
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATALED*
=PPVRTC_G3_PCH
D36
B37
16
1
SPI_CLK
SPI_CS0*
16
A38
AD7
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SPI
16
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
SMBUS
NC
1
OMIT_TABLE
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
(IPU)
FWH4/LFRAME*
U1800
RTCX1
RTCX2
CLOCKS
A20
SYSCLK_CLK32K_RTC
IN
PCI-E*
C-LINK
81 24
FLEX
CLOCKS
8
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1%
1/20W
MF
2 201
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
PCH SATA/PCIe/CLK/LPC/SPI
DRAWING NUMBER
Apple Inc.
051-9058
R
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
18 OF 109
SHEET
16 OF 86
1
A
8
7
=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE
6
5
4
3
2
1
7 16 17 18 19
7
PLACE_NEAR=U1800.BJ24:12.7mm
R1905 1
1
49.9
OMIT_TABLE
IN
78 9
IN
78 9
IN
78 9
IN
78 9
IN
78 9
IN
78 9
IN
78 9
IN
78 9
OUT
78 9
OUT
78 9
OUT
78 9
OUT
78 9
OUT
78 9
OUT
78 9
OUT
78 9
OUT
DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>
BC24
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>
BE24
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
AW24
BE20
BG18
BG20
BC20
BJ18
BJ20
AW20
BB18
AV18
AY24
DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>
AY20
AY18
AU18
BJ24
PCH_DMI_COMP
BG25
BH21
PCH_DMI2RBIAS
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
OMIT_TABLE
U1800
PANTHERPOINT
MOBILE
FCBGA
(3 OF 10)
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BJ14
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI_ZCOMP
DMI_IRCOMP
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_INT
AW16
FDI_FSYNC0
FDI_FSYNC1
AV12
BC10
AV14
FDI_LSYNC0
FDI_LSYNC1
DMI2RBIAS
BB10
FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>
FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>
FDI_INT
FDI_FSYNC<0>
FDI_FSYNC<1>
FDI_LSYNC<0>
FDI_LSYNC<1>
1%
1/20W
MF
2 201
K3
SUSACK* (IPU)
IN
PM_SYSRST_L
45 24 23
P12
IN
PM_PCH_SYS_PWROK
SYS_PWROK
24
PM_PCH_PWROK
L22
IN
PWROK
24
PM_PCH_APWROK
L10
IN
45 24
C
C12
PCH_SUSACK_L
17
78 26 10
73
PM_RSMRST_L
C21
PCH_SUSWARN_L
K16
IN
PM_PWRBTN_L
E20
IN
SMC_ADAPTER_EN
H20
IN
17
45 23 17
73 46 45
46
B13
PM_MEM_PWRGD
OUT
APWROK
DRAMPWROK
RSMRST*
DSWVRMEN
DPWROK
E22
IN
9 78
IN
9 78
IN
9 78
8
OUT
IN
9 78
8
OUT
IN
9 78
IN
9 78
6
IN
9 78
IN
9 78
IN
9 78
IN
9 78
IN
9 78
IN
9 78
PLACE_NEAR=U1800.AF37:2.54mm
R1950 1
OUT
80 74
OUT
80 74 6
OUT
OUT
9 78
OUT
9 78
80 74 6
OUT
OUT
9 78
80 8
OUT
OUT
9 78
SUS_STAT*/GPIO61
G8
LPC_PWRDWN_L
OUT
6 45 47
PM_CLK32K_SUSCLK_R
OUT
46
E10
A10
PCH_RI_L
SUSWARN*/SUSPWRDNACK/GPIO30
PWRBTN* (IPU)
H4
SLP_S3*
F4
SLP_A*
ACPRESENT/GPIO31
(IPD-DeepS4/S5)
BATLOW*/GPIO72 (IPU)
RI*
IN
BI
6 17 24 32
1
G10
SLP_SUS*
AP14
PMSYNCH
K14
SLP_LAN*/GPIO29
5%
1/20W
MF
201
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
45
R1909
100K
6 17 45 47
2
SLP_S4*
R1915
IN
PM_CLKRUN_L
D10
80 74 6
7 16 20
390K
PM_DSW_PWRGD
5%
1/20W
MF
201
OUT
80 74 6
OUT
80 74 6
OUT
80 8
OUT
80 8
OUT
80 8
OUT
80 8
OUT
80 8
OUT
80 8
OUT
80 8
OUT
17 45 73
OUT
6 17 26 32 45 73
OUT
6 8 17 26 45 73
OUT
80 74 6
80 8
OUT
OUT
80 8
OUT
80 8
OUT
80 8
OUT
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
AK39
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_N<3>
AN48
AK40
AM47
AK47
AJ48
AN47
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_P<3>
AM49
AK49
AJ47
LVDS_IG_B_CLK_N
LVDS_IG_B_CLK_P
AF40
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_N<3>
AH45
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_P<3>
AH43
AF39
AH47
AF49
AF45
AH49
AF47
AF43
PM_SLP_SUS_L
PM_SYNC
GPIO29
OUT
6
17 73
6
OUT
OUT
10 78
6
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
N48
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
T39
P49
T49
=PP3V3_SUS_PCH_GPIO
M40
M47
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
6
6
R1983 1
M49
T43
PCH_DAC_IREF
10K
PCH_SUSWARN_L
17
R1986
0
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
DDPD_CTRLCLK
DDPD_CTRLDATA
(IPD-PLTRST#)
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
6
TP_SDVO_STALLN
TP_SDVO_STALLP
AM40
AP39
TP_SDVO_INTN
TP_SDVO_INTP
AP40
P38
6
6
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
M39
AT49
8
8
DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD
AT47
AT40
AV42
8
8
8
TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
8
8
8
8
8
8
8
8
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
P42
AP47
8
8
DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD
AP49
AT38
AY47
8
8
8
TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
AT45
8
8
8
8
8
8
8
8
8
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
AT43
BH41
BB43
8
8
8
TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
C
8
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
M36
D
6
6
8
8
8
8
8
8
8
8
R1951
PCH_SUSACK_L
5%
1/20W
MF
2 201
17
B
7
1K
1
2
8.2K
1
2
R1982
10K
1
2
R1925
1K
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
R1924
R1921
R1922
R1923
100K
100K
100K
100K
2
1
2
1
2
1
R1981
R1984
100K
100K
2
1
1
1
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
8
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
AM42
6
7 16 18 19 30
R1991
2
LVDSB_CLK*
LVDSB_CLK
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD-PLTRST#)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
AP45
7 16 17 18 19
R1985
2
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AP43
1K
1
5%
1/20W
MF
201
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH
A
1
2
B
T42
PLACE_NEAR=U1800.T43:2.54mm
2
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
17
6
5%
1/20W
MF
201
LVDSA_CLK*
LVDSA_CLK
TP_PM_SLP_A_L
6
19 18 17 16 7
AF36
U1800
SDVO_TVCLKINN
(IPD)
PANTHERPOINT SDVO_TVCLKINP
(IPD)
MOBILE
FCBGA
L_BKLTCTL
SDVO_STALLN
(4 OF 10)
(IPD)
SDVO_STALLP
(IPD)
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
(IPD)
(IPD-PLTRST#)
SDVO_INTP
L_CTRL_CLK
(IPD)
L_CTRL_DATA
SDVO_CTRLCLK
LVD_IBG
SDVO_CTRLDATA
(IPD-PLTRST#)
LVD_VBG
DDPB_AUXN
LVD_VREFH
DDPB_AUXP
DDPB_HPD
LVD_VREFL
L_BKLTEN
L_VDD_EN
2
80 74
9 78
AF37
AE47
9 78
OUT
P39
AE48
9 78
1
K47
1%
1/20W
MF
201
IN
=PPVRTC_G3_PCH
M45
2.37K
IN
N3
SLP_S5*/GPIO63
6
PCH_LVDS_IBG
TP_PCH_LVDS_VBG
17 8
CLKRUN*/GPIO32
N14
T45
6
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
9 78
WAKE*
SUSCLK/GPIO62
T40
IN
PCH_DSWVRMEN
PCIE_WAKE_L
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
OUT
B9
G16
PM_BATLOW_L
IN
SYS_RESET*
SYSTEM POWER
MANAGEMENT
750
A18
LVDS_IG_BKL_PWM
P45
OUT
17 8
2
R1920
8
9 78
PLACE_NEAR=U1800.BH21:2.54mm
1
J47
OUT
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
IN
DIGITAL DISPLAY INTERFACE
D
78 9
LVDS
1%
1/20W
MF
2 201
CRT
5%
1/20W
MF
201 2
DMI
FDI
10K
R1900
1/20W
MF
PM_PWRBTN_L
17 23 45
PM_CLKRUN_L
6 17 45 47
GPIO29
17
PCIE_WAKE_L
6 17 24 32
MAKE_BASE=TRUE
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
SYNC_MASTER=J31_MLB
=TBT_WAKE_L
PCH DMI/FDI/PM/Graphics
75
DRAWING NUMBER
6 8 17 26 45 73
Apple Inc.
6 17 26 32 45 73
17 45 73
051-9058
17 73
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 17
8 17
6
5
4
3
2
SIZE
D
REVISION
R
201
7
SYNC_DATE=06/13/2011
PAGE TITLE
IN
6.0.0
BRANCH
PAGE
19 OF 109
SHEET
17 OF 86
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
D
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
B21
NC
NC
AY16
TP_PCH_TP23
NC
80 42
IN
80 43
IN
C
8
IN
8
IN
80 42
80 43
IN
8
IN
8
IN
80 42
OUT
80 43
OUT
8
OUT
8
OUT
80 42
OUT
80 43
OUT
8
OUT
8
OUT
10K
10K
10K
10K
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
18
OUT
18
OUT
18
OUT
B
NO STUFF
R2054
10K
2
1
5%
1/20W
MF
IN
62 18
IN
75 18
IN
62 18
IN
6
26 24
R2030
A
R2014
R2031
R2033
10K
10K
10K
10K
10K
10K
10K
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
5%
1/20W
MF
201
5%
1/20W
MF
201
NO STUFF
2
1
2
10K
10K
10K
10K
1
2
2
1
2
1
2
2
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
5%
1/20W
5%
1/20W
MF
201
5%
1/20W
BC28
USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N
AV26
USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P
AU26
BE32
BJ32
BE30
BF32
BG32
BB26
AU28
AY30
AY26
AV28
AW30
(5 OF 10)
RSVD5
RSVD6
TP21
TP22
TP23
TP24
USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4
K40
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
K38
H38
G38
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
C46
TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L
D47
BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
G42
TP_PCI_PME_L
K10
C44
E40
E42
F46
OUT
G40
C42
D44
C6
PLT_RESET_L
H49
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
H43
J48
K42
H40
PIRQA*
PIRQB*
PIRQC*
PIRQD*
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
(IPU-PCIERST#)
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PME* (IPU)
PLTRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
(IPD)
AY7
AV7
AU3
BG4
AT10
BC8
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
AU2
RSVD23
RSVD24
AV5
RSVD25
AT8
RSVD26
RSVD27
AY5
RSVD28
RSVD29
AT12
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV10
BA2
BF3
USBP0N
USBP0P
C24
USBP1N
USBP1P
C25
USBP2N
USBP2P
C26
USBP3N
USBP3P
K28
USBP4N
USBP4P
E28
USBP5N
USBP5P
C28
USBP6N
USBP6P
C29
USBP7N
USBP7P
N28
USBP8N
USBP8P
L30
USBP9N
USBP9P
G30
USBP10N
USBP10P
C30
USBP11N
USBP11P
L32
USBP12N
USBP12P
G32
USBP13N
USBP13P
(IPD)
C32
USBRBIAS*
USBRBIAS
C33
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
A14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
NC
NC
NC
NC
NC
NC
NC
A24
B25
A26
H28
D28
A28
B29
M28
K30
E30
USB_EXTA_N
USB_EXTA_P
BI
42 80
BI
42 80
USB_EXTB_XHCI_N
USB_EXTB_XHCI_P
BI
25 80
BI
25 80
USB_EXTC_N
USB_EXTC_P
BI
8 80
BI
8 80
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
BI
8 80
BI
8 80
K32
E32
A32
80
Ext B (XHCI)
Ext D (XHCI) (Mobiles: Trackpad?)
Unused
TP_USB_SDN
TP_USB_SDP
RSVD: SD
TP_USB_WLANN
TP_USB_WLANP
RSVD: WiFi
USB_HUB_UP_N
USB_HUB_UP_P
BI
25 80
BI
25 80
USB_CAMERA_N
USB_CAMERA_P
BI
32 80
BI
32 80
USB_EXTB_EHCI_N
USB_EXTB_EHCI_P
BI
25 80
BI
25 80
BI
8
BI
8
MF
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
USB Hub (All LS/FS Devices)
Camera
Ext B (EHCI)
Ext D (EHCI)
TP_USB_BT_HSN
TP_USB_BT_HSP
RSVD: BT (HS)
TP_USB_12N
TP_USB_12P
Unused
TP_USB_13N
TP_USB_13P
Unused
PCH_USB_RBIAS
B33
PLACE_NEAR=U1800.B33:2.54mm
1
K20
B17
C16
L16
A16
D14
C14
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
IN
18 23
IN
18 23
IN
18 23
IN
18 23
IN
23
IN
23
OUT
23
IN
R2070
22.6
1%
1/20W
MF
2 201
18 23
18
18
18
18 62
18 75
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
18 62
PCH PCI/USB/TP/RSVD
DRAWING NUMBER
18 23
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
AP_PWR_EN
MF
B
201
1
1/20W
C
Ext C (XHCI/EHCI)
TP_USB_4N
TP_USB_4P
USB_EXTD_EHCI_N
USB_EXTD_EHCI_P
A30
Ext A (XHCI/EHCI)
18
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
5%
8
USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P
BC30
FCBGA
RSVD1
RSVD2
RSVD3
RSVD4
Redundant to pull-up on audio page
1
10K
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
BLC_GPIO
NO STUFF
2
R2060
R2061
R2062
R2068
10K
24
2
R2069
R2067
OUT
6
1
1
OUT
24
7 16 17 18 19 30
1
1
81 24
7 24
2
1
OUT
7 16 17 19
1
BE28
201
18
R2016
R2017
R2018
USB3_EXTA_RX_N
USB3_EXTB_RX_N
USB3_EXTC_RX_N
USB3_EXTD_RX_N
MOBILE
=PP3V3_S0_PCH_GPIO
R2010
R2011
R2012
R2013
=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO
BG46
U1800
PANTHERPOINT
PCI
30 19 18 17 16 7
IN
M20
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
USB
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
18 23
18 23
R
18 23
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
6.0.0
BRANCH
18 23
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
23 32 73
201
7
051-9058
REVISION
6
5
4
3
2
PAGE
20 OF 109
SHEET
18 OF 86
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
30 19 18 17 16 7
=PP3V3_S0_PCH_GPIO
RAMCFG3:H
R2172 1
RAMCFG2:H
1
10K
D
5%
1/20W
MF
201
OMIT_TABLE
XDP_FC1_PCH_GPIO0
23 19
MOBILE
19
IN
DPMUX_UC_IRQ
H36
TACH2/GPIO6
(6 OF 10)
45 19
IN
SMC_RUNTIME_SCI_L
E38
TACH3/GPIO7
TP_PCH_GPIO8
C10
GPIO8 (IPU-RSMRST#)
LAN_PHY_PWR_CTRL/GPIO12
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
G2
IN
GPIO15 (IPD)
U2
OUT
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
SATA4GP/GPIO16
BI
LPCPLUS_GPIO
D40
ODD_PWR_EN_L
T5
OUT
19
46 19
IN
23
R2180
TBT_SW_RESET_L
1
PCH_GPIO24
(PU necessary?)
SMC_SCI_L
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
OUT
2
19
5%
MF
1/20W
201
23
OUT
E8
E16
P8
GPIO35
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
M5
OUT
JTAG_ISP_TDO
N2
IN
OUT
JTAG_ISP_TDI
OUT
FW_PWR_EN_PCH
23
A40
MLB_RAMCFG0
P4
PCH_A20GATE
AU16
PCH_PECI
SATA2GP/GPIO36
(IPD-PLTRST#)
SATA3GP/GPIO37
(IPD-PLTRST#)
SLOAD/GPIO38
M3
SDATAOUT0/GPIO39
V13
SDATAOUT1/GPIO48
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
V3
SPIROM_USE_MLB
D6
BI
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
RCIN*
GPIO28 (IPU-RSMRST#)
STP_PCI*/GPIO34
23
56 47 19 6
MLB_RAMCFG1
TACH7/GPIO71
5%
1/20W
MF
201
R2175
10K
2
2
D
5%
1/20W
MF
201
19
R2170
43
1
CPU_PECI
2
5%
MF
GPIO27 (IPU-DeepS4/S5)
K4
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
8
C41
2
5%
1/20W
MF
201
NO STUFF
GPIO24
XDP_DC1_PCH_GPIO35_MXM_GOOD
OUT
24 19
MLB_RAMCFG2
TACH6/GPIO70
2
RAMCFG0:H
1
10K
P5
PCH_RCIN_L
AY11
PCH_PROCPWRGD
BI
1/20W
201
10 46 78
19
SCLOCK/GPIO22
TBT_SW_RESET_R_L
23 19
19 8
MLB_RAMCFG3
B41
(IPD) PECI
TACH0/GPIO17
K1
V8
C
C40
TACH5/GPIO69
A20GATE
SATA5GP/GPIO49/TEMP_ALERT*
GPIO57
VSS_NCTF_0
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
CPU/MISC
41 19
WOL_EN
C4
OUT
GPIO
47 19 6
TACH4/GPIO68
R2174 1
10K
FCBGA
NCTF
23
OUT
U1800
PANTHERPOINT
TACH1/GPIO1
23
35
BMBUSY*/GPIO0
FW_PME_L
A42
IN
73 19
0
T7
39 19 8
RAMCFG1:H
R2173
PROCPWRGD
R2140
0
1
CPU_PWRGD
2
5%
MF
THRMTRIP*
AY10
46
R2156
PM_THRMTRIP_L_R
390
1
PM_THRMTRIP_L
2
5%
MF
INIT3_3V*
(IPU)
T14
DF_TVS
(IPD-PLTRST#?)
AY1
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
AH8
NC_1
P37
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
BG2
1/20W
201
1/20W
201
=PP1V8_S0_PCH_VCC_DFTERM
OUT
1
IN
10 46 78
R2178
PCH_DF_TVS
2
NO STUFF
1K
AH10
5%
1/20W
MF
201
AK10
1K
1
5%
1/20W
MF
201
R2130 1
R2179
2.2K
PCH_INIT3V3_L
AK11
7 20 22
10 23 78
This has internal pull up and should not pulled low.
2
5%
1/20W
MF
201
CPU_PROC_SEL_L
10
DF_TVS:DMI & FDI Term Voltage
Set to Vss when Low
Set to Vcc when High
C
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
2
NC
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
B
B
=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
R2186
R2199
R2160
R2185
R2196
R2190
10K
10K
10K
10K
10K
100K
7
7 16 17 18
7 16 17 18 19 30
7 16
1
2
1
2
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
A
10K
10K
1
2
1
2
R2150
R2155
10K
10K
1
2
1
2
R2194
R2192
R2193
10K
10K
100K
1
2
1
2
1
2
R2191
10K
1
2
R2111
R2195
R2112
R2198
R2113
R2116
20K
100K
10K
10K
10K
10K
2
1
2
1
2
1
2
1
2
1
2
1
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
5%
1/20W
1/20W
MF
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
8
XDP_FC1_PCH_GPIO0
FW_PME_L
SMC_RUNTIME_SCI_L
LPCPLUS_GPIO
8 19
8 33
19 23
8 19 39
19 45
6 19 47
Must stuff R2197 when R2180 NO STUFFed.
NO STUFF
R2197
R2184
JTAG_ISP_TDO
JTAG_TBT_TDI
1/20W
MF
TBT_SW_RESET_R_L
FW_PWR_EN_PCH
PCH_A20GATE
PCH_RCIN_L
19
19 24
19
19
WOL_EN
PCH_GPIO24
SPIROM_USE_MLB
6 19 47 56
SMC_SCI_L
19 46
19 73
SYNC_MASTER=J31_MLB
19
SYNC_DATE=06/13/2011
PAGE TITLE
PCH GPIO/MISC/NCTF
DRAWING NUMBER
DPMUX_UC_IRQ
201
AUD_IPHS_SWITCH_EN_PCH
201
ODD_PWR_EN_L
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
JTAG_ISP_TCK
201
ENET_LOW_PWR_PCH
19
Apple Inc.
23 24
R
NOTICE OF PROPRIETARY PROPERTY:
19 23
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 23
23 24
6
5
4
3
2
SIZE
D
6.0.0
19 41
201
7
051-9058
REVISION
BRANCH
PAGE
21 OF 109
SHEET
19 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
22 20 7
AL29
=PP1V05_S0_PCH_VCCIO_CLK
AL24 left as NC per DG
22 20 7
BH23
NC
AL24
NC
AA19
=PP1V05_S0_PCH_VCCASW
AA21
AA24
AA26
AA27
AA29
AA31
AC26
C
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
PCH output, for decoupling only
PLACE_NEAR=U1800.N16:2.54mm
1
20 7
Y49
=PP1V8R1V5_S0_PCH_VCCVRM
V5REF_SUS
M26
=PP5V_SUS_PCH_V5REFSUS
22
VCCASW_3_CLK
VCCASW_4_CLK
VCCASW_5_CLK
VCCASW_6_CLK
VCCASW_7_CLK
VCCASW_8_CLK
VCCASW_9_CLK
VCCASW_10_CLK
VCCASW_11_CLK
VCCASW_12_CLK
VCCASW_13_CLK
VCCASW_14_CLK
VCCASW_15_CLK
VCCASW_16_CLK
VCCASW_17_CLK
VCCASW_18_CLK
VCCASW_19_CLK
VCCASW_20_CLK
T27
AD23
T29
AF21
AF23
T23
=PP3V3_SUS_PCH_VCCSUS_USB
7 22
AG21
T24
AG23
V23
AG24
V24
AG26
P24
AG27
AG29
AJ23
DCPSUS_4_USB
AN23
VCCSUS3_3_1_USB
AN24
NC
AJ26
NC-ed per DG
AJ27
AJ29
V5REF
P34
=PP3V3_SUS_PCH_VCCSUS
=PP5V_S0_PCH_V5REF
7
AJ31
22
7
VCCSUS3_3_2_GPIO
VCCSUS3_3_3_GPIO
VCCSUS3_3_4_GPIO
VCCSUS3_3_5_GPIO
N20
=PP3V3_SUS_PCH_VCCSUS_GPIO
7 22
N22
P20
22 7
22
2
22
22 20 7
22 16 7
PP1V05_S0_PCH_VCCADPLLA_F
PP1V05_S0_PCH_VCCADPLLB_F
BD47
=PP1V05_S0_PCH_VCCIO_CLK
AF17
BF47
AF33
=PP1V05_S0_PCH_VCCDIFFCLK
55mA Max, 5mA Idle
AF34
AG34
22 7
AG33
=PP1V05_S0_PCH_VCCSSC
VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO
AN16
VCCIO_15_FDI
VCCIO_16_FDI
AN21
AN26
T34
AN27
VCC3_3_2_SATA
AJ2
7 22
AP21
VCCIO_5_PLLSATA
AF13
VCCIO_12_SATA3
VCCIO_13_SATA3
AH13
VCCIO_6_PLLSATA3
AF14
7 22
=PP1V05_S0_PCH_VCCIO_SATA
7 16 20 22
AP24
AP26
AT24
DCPRTC
VCCVRM_4_CLK
VCCADPLLA
VCCADPLLB
AH14
VCCIO_7_CLK
VCCAPLLSATA
VCCVRM_1_SATA
VCCDIFFCLKN
VCCDIFFCLKN
VCCDIFFCLKN
VCCIO_2_SATA
VCCIO_3_SATA
VCCIO_4_SATA
AK1
AF11
AC16
AN33
NC VCCAPLLSATA pin left as NC per DG
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH_VCCIO_SATA
7 16 20 22
AC17
22 7
17 16 7
DCPSUS_1_CLK
DCPSUS_2_CLK
=PP1V05_S0_PCH_V_PROC_IO
BJ8
V_PROC_IO
=PPVRTC_G3_PCH
A22
VCCRTC
C2231
1
1
C2232
1UF
0.1UF
10%
6.3V
CERM
402
20%
10V
CERM
402
2
PLACE_NEAR=U1800.A22:2.54mm
2
1
T21
MISC
2
V19
NC
CPU
T17
NC-ed per DG NC
PLACE_NEAR=U1800.V16:2.54mm
VCCASW_22_MISC
VCCASW_23_MISC
VCCASW_21_MISC
BH29
VCC3_3_3_PCIE
20 7
=PP1V8R1V5_S0_PCH_VCCVRM
AP16
VCCVRM_2_FDI
VCCAFDIPLL pin left as NC per DG
7
VCCSUSHDA
P32
=PP1V05_S0_PCH_VCCASW
VCCIO_25_DP
VCCIO_26_DP
=PP3V3_S0_PCH_VCC3_3_PCI
VCCSSC
DCPSST
VCCIO_17_PCIE
VCCIO_18_PCIE
VCCIO_19_PCIE
VCCIO_20_PCIE
VCCIO_21_PCIE
VCCIO_22_PCIE
VCCIO_23_PCIE
VCCIO_24_PCIE
22 7
7 20
AD17
HDA
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
0.1UF
20%
10V
CERM
402
BJ22
AP23
RTC
C2222
TP_1V05_S0_PCH_VCCAPLLEXP
W16
7
V16
PPVOUT_S0_PCH_DCPSST
B
VCCIO_28_PLLPCIE
VCC3_3_1_GPIO
VCC3_3_8_GPIO
VCC3_3_4_GPIO
=PP3V3_S0_PCH_VCC3_3_SATA
FCBGA
AN19
AN17
=PP3V3_S0_PCH_VCC3_3_GPIO
MOBILE
(7 OF 10)
=PP1V05_S0_PCH_VCCIO_PLLPCIE
P22
AA16
U1800
PANTHERPOINT
NC
BG6
=PP1V05_S0_PCH_VCCIO_PLLFDI
AP17
=PP1V05_S0_PCH_VCCDMI_FDI
AU20
CRT
7
AD21
AN34
0.1UF
20%
10V
CERM
402
N16
PPVOUT_G3_PCH_DCPRTC
=PP1V05_S0_PCH_VCCIO_PLLUSB
SATA
C2210
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
W33
T26
AC23
P28
VCC CORE
VCCAPLLDMI2 pin left as NC per DG
P26
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCAFDIPLL
VCCIO_27_PLLFDI
VCCDMI_2_FDI
VCCADAC
U48
VSSADAC
U47
VCCALVDS
AK36
VSSALVDS
AK37
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
AM37
LVDS
T38
AA23
HVCMOS
PP3V3_S0_PCH_VCC3_3_CLK_F
OMIT_TABLE
=PP1V05_S0_PCH_VCC_CORE
1.44 A Max, 474mA Idle
7 22
PP3V3_S0_PCH_VCCA_DAC_F
22
=PP3V3_S0_PCH_VCCA_LVDS
7
PP1V8_S0_PCH_VCCTX_LVDS_F
22
AM38
C
AP36
AP37
VCC3_3_6_HVCMOS
V33
VCC3_3_7_HVCMOS
V34
=PP3V3_S0_PCH_VCC3_3_HVCMOS
7 22
VCCIO
V12
=PP1V05_S0_PCH_VCCIO_USB
DMI
TP_PPVOUT_PCH_DCPSUSBYP
USB
T16
CLK/MISC
22
=PP3V3_S5_PCH_VCCDSW
N26
PCI/GPIO/
LPC
22 7
U1800
VCCIO_29_USB
PANTHERPOINT VCCIO_30_USB
VCCDSW3_3
MOBILE
VCCIO_31_USB
FCBGA
DCPSUSBYP
(8 OF 10) VCCIO_32_USB
VCCIO_33_USB
VCC3_3_5_CLK
VCCSUS3_3_7_USB
VCCAPLLDMI2
VCCSUS3_3_8_USB
VCCIO_14_PLLCLK
VCCSUS3_3_9_USB
VCCSUS3_3_10_USB
DCPSUS_3_CLK
VCCSUS3_3_6_USB
VCCASW_1_CLK
VCCIO_34_PLLUSB
VCCASW_2_CLK
VCCACLK
FDI
22 7
AD49
NC
DFT/SPI
OMIT_TABLE
VCCACLK pin left as NC per DG
VCCVRM_3_DMI
AT16
=PP1V8R1V5_S0_PCH_VCCVRM
7 20
VCCDMI_1_DMI
AT20
=PP1V05_S0_PCH_VCC_DMI
7 22
VCCCLKDMI
AB36
PP1V05_S0_PCH_VCCCLKDMI_F
22
=PP1V8_S0_PCH_VCC_DFTERM
7 19 22
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM
AG16
=PP3V3_SUS_PCH_VCC_SPI
7 22
VCCSPI
AG17
AJ16
AJ17
V1
7 20 22
B
V21
T19
=PP3V3R1V5_S0_PCH_VCCSUSHDA
7 22 24
10 mA Max, 1mA Idle
C2233
0.1UF
2
20%
10V
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm
A
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
PCH POWER
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
22 OF 109
SHEET
20 OF 86
1
A
8
7
6
5
4
3
OMIT_TABLE
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
D
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
C
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
B
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1800
PANTHERPOINT
MOBILE
FCBGA
(9 OF 10)
VSS
AY4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AY42
AK4
AY46
AK42
AY8
AK46
B11
AK8
B15
AL16
B19
AL17
B23
AL19
B27
AL2
B31
AL21
B35
AL23
B39
AL26
B7
AL27
F45
AL31
BB12
AL33
BB16
AL34
BB20
AL48
BB22
AM11
BB24
AM14
BB28
AM36
BB30
AM39
BB38
AM43
BB4
AM45
BB46
AM46
BC14
AM7
BC18
AN2
BC2
AN29
BC22
AN3
BC26
AN31
BC32
AP12
BC34
AP19
BC36
AP28
BC40
AP30
BC42
AP32
BC48
AP38
BD46
AP4
BD5
AP42
BE22
AP46
BE26
AP8
BE40
AR2
BF10
AR48
BF12
AT11
BF16
AT13
BF20
AT18
BF22
AT22
BF24
AT26
BF26
AT28
BF28
AT30
BD3
AT32
BF30
AT34
BF38
AT39
BF40
AT42
BF8
AT46
BG17
AT7
BG21
AU24
BG33
AU30
BG44
AV11
BG8
AV16
BH11
AV20
BH15
AV24
BH17
AV30
BH19
AV38
H10
AV4
BH27
AV43
BH31
AV8
BH33
AW14
BH35
AW18
BH39
AW2
BH43
AW22
BH7
AW26
D3
AW28
D12
AW32
D16
AW34
D18
AW36
D22
AW40
D24
AW48
D26
AY12
D30
AY22
D32
AY28
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
A
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
8
7
2
1
OMIT_TABLE
6
5
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
U1800
PANTHERPOINT
MOBILE
FCBGA
(10 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
C
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
B
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
VSS
VSS
VSS
B43
VSS
VSS
G14
VSS
T36
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
L28
BE10
BG41
H16
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
SYNC_MASTER=J31_MLB
SYNC_DATE=06/13/2011
PAGE TITLE
BC16
PCH GROUNDS
BG28
DRAWING NUMBER
BJ28
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
23 OF 109
SHEET
21 OF 86
1
A
8
7
6
5
4
3
2
PCH VCCSUS3_3 BYPASS
20 16 7
L2406
16 7
20 19 7
10UH-0.12A-0.36OHM
R2415
0 2
2 PP1V05_S0_PCH_VCCCLKDMI_R
1
=PP1V05_S0_PCH 1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
0603
20
20 7
5%
1/16W
MF-LF
402
1
1
C2484
1
0.1UF
C2411
20%
2 6.3V
CERM-X5R
0402-1
1
1UF
10%
2 6.3V
CERM
402
D
=PP3V3R1V5_S0_PCH_VCCSUSHDA
1
PP1V8_S0_PCH_VCCTX_LVDS_F
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.8V
20 7
C2441
20 7
20%
10V
2 CERM
402
=PP1V05_S0_PCH_V_PROC_IO
1
20%
6.3V 2
CERM
805
C2406 1
C2408 1
0.01UF
0.01UF
10%
16V
X7R-CERM 2
0402
C2416 1
1
4.7UF
10%
16V
X7R-CERM 2
0402
1
0.1UF
20%
6.3V 2
X5R
402
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
C2417
10%
16V
2 X7R-CERM
0402
1
=PP3V3_SUS_PCH_VCC_SPI
1
1UF
PP3V3_S0_PCH_VCCA_DAC_F
2
20
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
10UF
10%
16V
X7R-CERM 2
0402
PLACE_NEAR=U1800.AF17:2.54mm
20 7
=PP3V3_S5_PCH_VCCDSW
C
(PCH PCI 3.3V PWR)
0.1UF
PCH VCCCORE BYPASS
1.05V CORE PWR)
20%
10V
CERM 2
402
20 7
(PCH
=PP1V05_S0_PCH_VCC_CORE
1
PLACE_NEAR=U1800.AT20:2.54mm
C2481
1UF
R2451
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
R2405
D2400
5
NC
SOT-363
6
1
1
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
0603
C2453 1
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
1UF
7
20 7
=PP1V05_S0_PCH_VCCIO
1
=PP3V3_SUS_PCH
=PP5V_SUS_PCH
C24291 C2414
D2400
2
NC
3
SOT-363
NEED PWR CONSTRAINT
1
7
=PP1V05_S0_PCH_VCCADPLL
1
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE
0.1UF
20%
10V
CERM 2
402
PLACE_NEAR=U1800.M26:2.54mm
<1 MA S0-S5
=PP5V_SUS_PCH_V5REFSUS
0
PP1V05_S0_PCH_VCCADPLLA_F
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
PP5V_SUS_PCH_V5REFSUS
C2438 1
PCH VCCADPLLA Filter
(PCH DPLLA PWR)
R2460
BAT54DW-X-G
NC
5%
1/16W
MF-LF
402
1
C24021 C2461
0.1UF
20%
10V
2 CERM
402
20
1
=PP3V3_S0_PCH_VCC3_3_SATA
1
C2421
1
0.1UF
C2423
5%
1/16W
MF-LF
402
0.1UF
10%
16V
2 X7R-CERM
0402
10%
16V
2 X7R-CERM
0402
PLACE_NEAR=U1800.AJ2:2.54mm
20 7
=PP1V05_S0_PCH_VCCASW
PLACE_NEAR=U1800.BD47:2.54MM
10%
6.3V
2 CERM
402
PP1V05_S0_PCH_VCCADPLLB_F
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1
C24651 C2466
0.1UF
20%
10V
2 CERM
402
PLACE_NEAR=U1800.BH29:2.54mm
B
C2426 1 C2456 1 C2496
C2428 1 C2420 1
1UF
10%
6.3V
2 CERM
402
1UF
10%
6.3V
2 CERM
402
22UF
20%
6.3V
CERM 2
805
22UF
20%
6.3V
CERM 2
805
PCH VCCADPLLB Filter
(PCH DPLLB PWR)
R2465
0
20%
6.3V 2
X5R
603
1UF
1UF
20 7
10UF
20
1
=PP3V3_S0_PCH_VCC3_3_PCI
1UF
10%
2 6.3V
CERM
402
68 mA
10%
6.3V
2 CERM
402
20 7
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
4
2
10
C24071 C2463
C2401 1
1UF
10%
2 6.3V
CERM
402
(PCH Reference for 5V Tolerance on USB)
R2404
1
1UF
PCH V5REF_SUS Filter & Follower
1 mA S0-S5
20%
6.3V 2
X5R
603
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm
20
10%
2 6.3V
CERM
402
7
10UF
10%
2 6.3V
CERM
402
10%
10V 2
X5R
402
1UF
B
C2483C2460 1
1UF
<1 MA
=PP5V_S0_PCH_V5REF
10%
10V 2
X5R
402
PLACE_NEAR=U1800.P34:2.54mm
C2454
10UF
PP5V_S0_PCH_V5REF
C2439
1
1UF
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
PLACE_NEAR=U1800.AG26:2.54mm
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2
1 MM
VOLTAGE=3.3V
20%
6.3V
CERM-X5R 2
0402-1
NEED PWR CONSTRAINT
1
C2482
L2451
10UH-0.12A-0.36OHM
1
2 20 PP3V3_S0_PCH_VCC3_3_CLK_F
PP3V3_S0_PCH_VCC3_3_CLK_R
5%
1/16W
MF-LF
402
BAT54DW-X-G
NC
5%
1/16W
MF-LF
402
=PP3V3_S0_PCH_VCC3_3_CLK
7
1
2
100
1
1
1UF
10%
2 6.3V
CERM
402
1 mA
1UF
C2499 1
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
24 7
20
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
69 mA
PLACE_NEAR=U1800.BF47:2.54MM
1UF
10%
2 6.3V
CERM
402
A
SYNC_MASTER=K90I_MLB
20 7
C2469
10%
6.3V
2 CERM
402
1UF
PLACE_NEAR=U1800.T16:2.54mm
=PP3V3_S0_PCH
=PP5V_S0_PCH
1
10%
6.3V
2 CERM
402
C2419
PCH VCC3_3 BYPASS
16 7
=PP1V05_S0_PCH_VCCIO_CLK
C2434
1UF
PLACE_NEAR=U1800.AF34:2.54mm
10%
6.3V
2 CERM
402
0.01UF
10%
16V
X7R-CERM 2
0402
20 7
=PP1V05_S0_PCH_VCC_DMI
C2455 1
0.1UF
20%
6.3V 2
X5R
603
=PP1V05_S0_PCH_VCCDIFFCLK
1
1
C2451 1
20 16 7
PCH VCCIO BYPASS
20 7
C
C2442
10%
2 6.3V
CERM
402
PLACE_NEAR=U1800.V1:2.54mm
C2450 1
1UF
PLACE_NEAR=U1800.P22:2.54mm
10%
16V
2 X7R-CERM
0402
R2450
=PP3V3_S0_PCH_VCCADAC
C2476
10%
6.3V
2 CERM
402
0.1UF
20 7
7
1
C2475
10%
2 6.3V
CERM
402
C2430
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
0
=PP3V3_SUS_PCH_VCCSUS_GPIO
1UF
PLACE_NEAR=U1800.AG33:2.54mm
22UF
20 7
=PP1V05_S0_PCH_VCCSSC
0.1UF
PLACE_NEAR=U1800.P32:2.54mm
C2400 1
C2446
(PCH HD Audio 3.3V/1.5V PWR)
0.1UH
20
1
PLACE_NEAR=U1800.AC17:2.54mm
L2407
2
=PP1V05_S0_PCH_VCCIO_USB
PLACE_NEAR=U1800.P28:2.54mm
10%
6.3V
2 CERM
402
PCH VCCSUSHDA BYPASS
24 20 7
0805
1UF
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.V24:2.54mm
=PP1V8_S0_PCH_VCCTX_LVDS 1
20 7
PLACE_NEAR=U1800.P24:2.54mm
D
7
C2452
1
10%
6.3V
2 CERM
402
20%
10V
2 CERM
402
10%
16V
2 X7R-CERM
0402
C2444
1UF
C2440
0.1UF
PLACE_NEAR=U1800.AJ16:2.54mm
C2413
0.1UF
10%
16V
2 X7R-CERM
0402
10UF
PLACE_NEAR=U1800.AB36:2.54mm
(PCH USB 1.05V PWR)
1
=PP3V3_SUS_PCH_VCCSUS_USB
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
PCH VCCIO BYPASS
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V8_S0_PCH_VCC_DFTERM
(PCH SUSPEND USB 3.3V PWR)
PP1V05_S0_PCH_VCCCLKDMI_F
1
=PP3V3_S0_PCH_VCC3_3_HVCMOS
SYNC_DATE=02/15/2011
PAGE TITLE
PCH DECOUPLING
1
C2424
0.1UF
20 7
DRAWING NUMBER
=PP3V3_S0_PCH_VCC3_3_GPIO
Apple Inc.
10%
16V
2 X7R-CERM
0402
1
C2486 1 C2485
0.1UF
PLACE_NEAR=U1800.V33:2.54mm
10%
2 25V
X5R
402
R
NOTICE OF PROPRIETARY PROPERTY:
PLACE_NEAR=U1800.AA16:2.54mm
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
6
5
4
3
2
SIZE
D
6.0.0
0.1UF
10%
2 25V
X5R
402
PLACE_NEAR=U1800.T34:2.54mm
8
051-9058
REVISION
BRANCH
PAGE
24 OF 109
SHEET
22 OF 86
1
A
8
7
6
5
4
CRITICAL
XDP_CONN
7
M-ST-SM
62
D
78 10
10
IN
10
IN
10
IN
10
IN
78 9
IN
78 9
IN
78 9
IN
78 9
IN
45 23 17
OUT
PM_PWRBTN_L
78 23 9
OUT
CPU_CFG<0>
OUT
R2564
R2565
R2566
R2567
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_PWRGD
45 24 17
R2560
R2561
R2562
R2563
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
IN
78 19 10
(R2560-R2563)
XDP_CPU:BPM
0 1
2
0 1
2 5% 1/20W
0 1
2 5% 1/20W
5% 1/20W
0 1
2
5%
(R2564-R2567)
XDP_CPU:CFG
0 1
2
0 1
2 5%
0 1
2 5%
5%
0 1
2
5%
R2500
MF
MF
MF
MF
78 10
IN
78 10
IN
78 10
IN
78 10
IN
78 9
IN
78 9
IN
201
201
201
201
2
XDP_BPM_L<0>
XDP_BPM_L<1>
OBSDATA_B0
OBSDATA_B1
XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>
OBSDATA_B2
OBSDATA_B3
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
201
5%
1/20W
MF
201
XDP_CPU_CFG<0>
XDP_VR_READY
5%
1/20W
MF
201
5%
1/20W
MF
201
2
XDP
R2501
1K 1
PLACE_NEAR=U1000.B57:2.54mm
2
XDP
330
1
2
48 23
BI
48 23
IN
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
OUT
XDP_CPU_TCK
R2581
XDP SIGNALS
23
OUT
23
OUT
23
OUT
23
23
OUT
OUT
23
IN
23
OUT
23
23
OUT
OUT
23
IN
23
IN
23
IN
23
IN
23
IN
23
IN
23
23
IN
IN
R2520
R2521
R2522
R2523
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
XDP_FC0
XDP_FC1
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
B
OBSFN_B0
OBSFN_B1
XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>
MF
78 23 10
OUT
OBSDATA_A2
OBSDATA_A3
CPU_CFG<10>
CPU_CFG<11>
1/20W
C
23
OBSDATA_A0
OBSDATA_A1
XDP_BPM_L<2>
XDP_BPM_L<3>
5%
XDP
R2502
0 1
PLACE_NEAR=U4900.P17:2.54mm
R2504
1/20W
1/20W
1/20W
1/20W
201
201
201
201
IN
OBSFN_A0
OBSFN_A1
XDP
1K 1
PLACE_NEAR=U1000.C60:2.54mm
PM_PCH_SYS_PWROK
1/20W
MF
MF
MF
MF
BI
5%
1/16W
MF-LF
402 2
R2524
R2525
R2526
R2527
R2528
SDA
SCL
TCK1
TCK0
R2580
1
2
1
2
(R2520-R2537)
5%
1/20W
5%
1/20W
XDP
201 1K
201 1K
MF
MF
PCH SIGNALS
33 1
2
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
5%
1/20W
MF
201
33 1
2
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
201
33 1
2 5% 1/20W MF
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
201
33 1
2 5% 1/20W MF
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
5%
33
33
33
33
33
R2529
R2530
R2531
R2532
R2533
R2534
R2535
33
R2536
R2537
33
33
33
33
33
33
33
33
1
1
1
1
1
2
2
2
2
2
1
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
1
1
1
1
1
1
2
2
2
2
2
2
1
1
C2500
1/20W
MF
5%
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
2
2 5%
5%
MF
64
10%
16V
X7R-CERM 2
0402
201
6
6
23
23
23
6
R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.
23
23
23
23
45 23 17
OUT
PM_PWRBTN_L
R2585
0
1
PLACE_NEAR=J2550.39:2.54mm
2
6
5%
1/20W
MF
201
6
XDP
1
PLACE_NEAR=U4900.P17:2.54mm
2
5%
1/20W
MF
201
6
6
A
48 23
BI
48 23
IN
23 16
9 78
OBSFN_D0
OBSFN_D1
CPU_CFG<8>
CPU_CFG<9>
IN
9 78
IN
9 78
OBSDATA_D0
OBSDATA_D1
CPU_CFG<4>
CPU_CFG<5>
IN
9 78
IN
9 78
OBSDATA_D2
OBSDATA_D3
CPU_CFG<6>
CPU_CFG<7>
IN
9 78
IN
9 78
1
C2501
18
18 23
18 23
IN
IN
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
OUT
OUT
19 23
PCH Micro2-XDP
19
R2511
78 23 10
XDP_CPU_TMS
R2512
51
2
78 23 10
XDP_CPU_TCK
R2513
51
2
78 23 10
XDP_CPU_TRST_L
R2514
51
2
XDP
0
1
23 16
IN
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
23 19
OUT
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
23 16
IN
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
IN
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
=PP3V3_S5_XDP
5% 1/20W MF
201
PLACE_NEAR=U1000.K61:2.54mm
XDP
1
5% 1/20W MF
201
PLACE_NEAR=U1000.H59:2.54mm
XDP
1
5% 1/20W MF
201
PLACE_NEAR=U1000.J58:2.54mm
XDP
1
D
5% 1/20W MF
201
PLACE_NEAR=U1000.H63:2.54mm
XDP
1
5%
1/20W
MF
201
PLACE_NEAR=R1841.1:2.54mm
ITPXDP_CLK100M_P
2
5% 1/20W MF
201
PLACE_NEAR=R1840.1:2.54mm
ITPXDP_CLK100M_N
2
5%
1/20W
MF
201
IN
16 78
IN
16 78
PLACE_NEAR=U1000.G3:2.54mm
2
CPU_RESET_L
IN
5% 1/20W MF
201
10 24
C
R2590
R2591
R2596
R2597
R2573
0
0
0
0
1
1
1
1
0
1
R2570
R2572
R2574
0
1
2
0
1
2
0
2
2 5%
5%
2
5%
2
5%
2
5%
1
USB_EXTA_OC_L
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
201
USB_EXTB_OC_L
201
AP_PWR_EN
201
SDCONN_STATE_CHANGE
201
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
42
IN
42
OUT
IN
SATARDRVR_EN
5%
IN
18 32 73
24
OUT
16 41
ISOLATE_CPU_MEM_L
OUT
26
DP_AUXCH_ISOL
OUT
16 75
OUT
67
OUT
8 19
MEM_VDD_SEL_1V5_L
2
7
CRITICAL
XDP_CONN
16 23
19
J2550
19 23
19 23
62
19 23
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
OBSDATA_A2
OBSDATA_A3
TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>
OBSFN_B0
OBSFN_B1
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
OBSDATA_B0
OBSDATA_B1
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
0.1UF
10%
16V
X7R-CERM 2
0402
6
XDP_CPU_TDI
2
16 23
OBSDATA_A0
OBSDATA_A1
XDP_PCH_TCK
OUT
23 19
M-ST-SM
OUT
IN
23 18
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
19
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
78 23 10
51
PLACE_NEAR=J2500.52:2.54mm
1
Non-XDP Signals
23 18
19 23
OBSFN_A0
OBSFN_A1
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
2
PCH SIGNALS
0.1UF
OUT
IN
R2515
10%
16V
2 X7R-CERM
0402
OUT
C2580 1
7
9 78
IN
23 18
TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
51
ITPCLK/HOOK4 78 XDP_CPU_CLK100M_P
XDP
R2516 0 1
ITPCLK#/HOOK5 78 XDP_CPU_CLK100M_N
VCC_OBS_CD
RESET#/HOOK6 78 XDP_CPURST_L
XDP
XDP_DBRESET_L
R2505 1K 1
DBR#/HOOK7
OUT 10 23 24 78
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_CPU_TDO
TDO
IN 10 23 78
XDP_CPU_TRST_L
TRSTn
OUT 10 23 78
XDP_CPU_TDI
TDI
OUT 10 23 78
XDP_CPU_TMS
TMS
OUT 10 23 78
XDP_PRESENT#
XDP
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
61
5
64
63
998-2516
23 19
OUT
23 19
OUT
23 19
OUT
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
R2575
R2576
R2577
0
0
0
1
1
1
2
2 5%
5%
2
5%
1/20W
1/20W
1/20W
JTAG_ISP_TCK
MF
201
AUD_IPHS_SWITCH_EN_PCH
MF
201
ENET_LOW_PWR_PCH
MF
201
OUT
19 24
OUT
19 24
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
OBSFN_C0
OBSFN_C1
XDP_FC0
XDP_FC1
OBSDATA_C0
OBSDATA_C1
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
23
OBSDATA_C2
OBSDATA_C3
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
23
OBSFN_D0
OBSFN_D1
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
OBSDATA_D0
OBSDATA_D1
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
OBSDATA_D2
OBSDATA_D3
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
23
23
23
23
7
=PP1V05_SUS_PCH_JTAG
6
XDP
6
23 16
XDP_PCH_TDO
R2550
51
2
23
23
23 16
XDP_PCH_TDI
R2551
51
2
23 16
XDP_PCH_TMS
R2552
5% 1/20W MF
201
PLACE_NEAR=U1800.K5:2.54mm
1
5% 1/20W MF
201
PLACE_NEAR=U1800.H7:2.54mm
XDP
23
23
PLACE_NEAR=J2550.52:2.54mm
1
XDP
51
2
TP_XDP_PCH_HOOK4
ITPCLK/HOOK4
6
XDP_PCH_TCK
R2556 51 2
23 16
ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5
6
VCC_OBS_CD
XDPPCH_PLTRST_L
1K series R on PCH Support Page
RESET#/HOOK6
IN 24
XDP_DBRESET_L
DBR#/HOOK7
OUT 10 23 24 78
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_PCH_TDO
TDO
IN 16 23
SYNC_MASTER=J31_MLB
TP_XDP_PCH_TRST_L
TRSTn
PAGE TITLE
XDP_PCH_TDI
TDI
OUT 16 23
XDP_PCH_TMS
TMS
OUT 16 23
XDP_PRESENT#
XDP
Apple
1
5% 1/20W MF
201
PLACE_NEAR=U1800.J3:2.54mm
XDP
1
5%
1/20W
MF
201
SYNC_DATE=06/13/2011
CPU & PCH XDP
XDP
8
IN
23 18
XDP
1K
OBSDATA_C2
OBSDATA_C3
DF40RC-60DP-0.4V
6
R2584
9 78
18
201
23
ALL_SYS_PWRGD
IN
CPU_CFG<2>
CPU_CFG<3>
18
PCH/XDP Signal Isolation Notes:
IN
IN
IN
18
9
9 23 78
IN
IN
IN
CPU_CFG<0>
CPU_CFG<1>
18 23
998-2516
IN
9
OBSDATA_C0
OBSDATA_C1
IN
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L OUT
201
XDP_DC1_PCH_GPIO35_MXM_GOOD OUT
201
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT
201
XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL OUT
201
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK OUT
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.
- For isolated GPIOs:
- ’Output’ non-XDP signals require pulls.
- ’Output’ PCH/XDP signals require pulls.
73 45 24
63
CPU_CFG<16>
CPU_CFG<17>
OBSFN_C0
OBSFN_C1
18 23
IN
201
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
1/20W MF
201
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
1/20W
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
IN
OUT
XDP_FC1_PCH_GPIO0
5%
1
0.1UF
201
2
R2510
61
XDP
201
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
MF
201
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
MF
201
XDP_DB2_PCH_GPIO10_AP_PWR_EN
MF
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
MF
201
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
=PPVCCIO_S0_XDP
XDP
XDP_CPU_TDO
78 23 10
DF40RC-60DP-0.4V
1K
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
1
23 7
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
J2500
=PP3V3_S0_XDP
NO STUFF
R25401
78 10
2
CPU Micro2-XDP
=PPVCCIO_S0_XDP
23 7
3
1
C2581
DRAWING NUMBER
Inc.
051-9058
R
4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
D
6.0.0
0.1UF
10%
16V
2 X7R-CERM
0402
SIZE
REVISION
BRANCH
PAGE
25 OF 109
SHEET
23 OF 86
1
A
8
7
6
5
4
Ethernet WAKE# Isolation
=PP3V3_ENET_PHY
3
2
Platform Reset Connections
Unbuffered
7 36 71
System RTC Power Source & 32kHz / 25MHz Clock Generator
7
C2624 1
0.1UF
10%
16V
X5R-CERM 2
0201
C2622 1
C2620 1
0.1UF
1
0.1UF
10%
16V
X5R-CERM 2
0201
C2602
1UF
10%
16V
X5R-CERM 2
0201
10%
2 10V
X5R
402-1
SYSCLK_CLK25M_X2
1M
25.000MHZ-12PF-20PPM
2
G 1
S
2
3
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_T29
=PPVRTC_G3_OUT 7
OUT
16 81
OUT
16 81
OUT
36 81
OUT
33 81
1
PM_SYSRST_L
2
17 45
BI
R2697
1
2
5
6
1
7
=PP3V3_S0_RSTBUF
5
Buffered
U2680
74LVC1G07
SC70
4
A1
B1
A2
B2
C2650
Y1
Y2
36
ENET_MEDIA_SENSE
IN
1
12K 5%
2 ENET_MEDIA_SENSE_RDIV
7
ENET_LOW_PWR
OUT
30 36
3
FW_PWR_EN
OUT
39
24 18 7
NC
20%
10V
CERM 2
402
OUT
31
XDPPCH_PLTRST_L
OUT
23
=T29_RESET_L
OUT
35
2
BKLT_PLT_RST_L
OUT
77
=FW_RESET_L
OUT
39
Series R is R4283
C
PLT_RST_BUF_L
3
R2680
100K
CPU_RESET_L
5%
1/16W
MF-LF
2 402
R2627
81 18
IN
LPC_CLK33M_SMC_R
SOT563
R26111
18
100K
5%
1/20W
MF
201 2
5 G
IN
1
R2629
IN
PCH_CLK33M_PCIOUT
1
PLACE_NEAR=U1800.H40:2.54MM:5.1mm
08
A1
B1
A2
B2
Y1
Y2
7
3
AUD_IPHS_SWITCH_EN
OUT
35
OUT
62
1
SOT563
23
2 G
1
SDCONN_STATE_CHANGE
CRITICAL
SOT665
4
C2670
1
SDCONN_STATE_CHANGE_SMC
R2663
0.1UF
1K
20%
10V
2 CERM
402
5%
1/16W
MF-LF
402 2
IN
1
ALL_SYS_PWRGD
5
3
2
1
R2620
100K
5%
1/20W
MF
2 201
SPI_DESCRIPTOR_OVERRIDE_LS5V
SPI_DESCRIPTOR_OVERRIDE
1
Q2620
R2621
D 6
1K
5%
1/20W
MF
2 201
SSM6N37FEAPE
SOT563
7 24
C2660
2 G
20%
10V
2 CERM
402
45
SC70-HF
PM_S0_PGOOD
1
5
MC74VHC1G08
IN
R2662
SC70-HF
U2660 4
2
HDA_SDOUT_R
IPD = 9-50k
S 1
OUT
16 81
SPI_DESCRIPTOR_OVERRIDE_L
SYNC_MASTER=K90I_MLB
SYS_PWROK_R 1 3.0K 2
5%
1/16W
MF-LF
402
3
PM_PCH_SYS_PWROK
OUT
R2660
SMC_DELAYED_PWRGD
1
0
5%
1/16W
MF-LF
402
6
2
SYNC_DATE=02/15/2011
PAGE TITLE
Chipset Support
17 23 45
PLACE_NEAR=U1800.L22:5.54mm
DRAWING NUMBER
NO
STUFF
1
R2661
Apple Inc.
0
7
=PP5V_S0_PCH
=PP3V3R1V5_S0_PCH_VCCSUSHDA
0.1UF
3
46 45 35
B
MC74VHC1G08
U2650 4
2
CPUIMVP_PGOOD
1
16 80
Q2620
30 46
D
24 22 20 7
=PP3V3_S5_PCHPWRGD
C2600
OUT
SSM6N37FEAPE
5%
1/16W
MF-LF
402
R2650
PCH_CLK33M_PCIIN
PCH ME Disable Strap
A
Y
SOT563
1
2
22 7
3
1
6 47 81
5%
1/16W
MF-LF
402
20%
10V
2 CERM
402
U2670
2
B
0
OUT
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
7
0.1UF
S 1
TC7SZ08FEAPE 5
1
LPC_CLK33M_LPCPLUS
SDCONN_STATE_CHANGE ISOLATION
ENET_MEDIA_SENSE_EN
=PP3V3_S5_PCHPWRGD
=PP3V3_S0_SB_PM
2
D 6
=PP3V3_S3_SDBUF
5%
1/16W
MF-LF 2
402
PCH S0 PWRGD
22
5%
1/16W
MF-LF
402
SSM6N37FEAPE
0
TBT_PWR_EN
45 81
G 5
20%
10V
2 CERM
402
OUT
4 S
1
2
5
6
R2612
0.1UF
22
LPC_CLK33M_SMC
R2626
PLACE_NEAR=U1800.H43:5.1mm
S 4
Q2610
C2652
2
5%
1/16W
MF-LF
402
LPC_CLK33M_LPCPLUS_R
NO STUFF
IN
22
1
PLACE_NEAR=U1800.H49:5.1mm
Q2610
1
10 23
OUT
VTT voltage divider on CPU page
16
CRITICAL
SSM6N37FEAPE
D 3
=PP3V3_S3_PCH_GPIO
4
8
OUT
402
MF-LF1/16W
GND
68
PCA9557D_RESET_L
R2610
0.1UF
08
74LVC2G08GT
TBT_PWR_EN_PCH
PM_PCH_PWROK
AUD_IPHS_SWITCH_EN_PCH
73 45 23
32
1
1
C2680 1
20%
10V
2 CERM
402
U2652
SOT833
A
OUT
5%
1/16W
MF-LF
402
=PP3V3_S3_PCH_GPIO
B
24 7
2
0
1
C2610
=PP3V3R1V5_S0_PCH_VCCSUSHDA
24 7
AP_RESET_L
R2693
SILK_PART=SYS RESET
0.1UF
CRITICAL 8
VCC
IN
30
Series R is R3803
=PP3V3_S3_PCH_GPIO
ENET_LOW_PWR_PCH
PM_PCH_PWROK
FW_PWR_EN_PCH
24 18 7
23 19
1K
5%
1/16W
MF-LF
2 402
18
IN
2
0
ENET_MEDIA_SENSE_EN_L
IN
OUT
R2689
1
1UF
4
16
=ENET_RESET_L
5%
1/16W
MF-LF
402
10%
2 6.3V
CERM
402
GND
24 17
45
MAKE_BASE=TRUE
74LVC2G08GT
IN
0
1
NC
U2601
SOT833
IN
OUT
XDP
OMIT
ENET_MEDIA_SENSE ISOLATION CIRCUIT
IN
SMC_LRESET_L
D
2
5%
1/16W
MF-LF
402
2
CRITICAL 8
VCC
19
0
1
GPIO Glitch Prevention
24 17
2
5%
1/16W
MF-LF
402
R2671
NOTE: 30 PPM crystal required
24 18 7
23 19
33
1
For SB RTC Power
SYSCLK_CLK25M_X1
5%
50V
C0G-CERM
0402
C
1
6 47
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
25MHZ_A 9
25MHZ_B 8
25MHZ_C 15
THRM
PAD
GND
5%
1/20W
MF
2 201
XDP_DBRESET_L
SYSCLK_CLK32K_RTC
VDD_RTC_OUT 1
R2606
12PF
1
X2
X1
1
SM-3.2X2.5MM
3
C2606
2 4
NC
Y2605
3
4
SYSCLK_CLK25M_X2_R
NO STUFF
2
5%
1/20W
MF
201
CRITICAL
1
5%
50V
C0G-CERM
0402 NC
1
IN
32KHZ_A 12
17
1
VDDIO_25M_A
VDDIO_25M_B
VDDIO_25M_C
23 10
78
81
OUT
R2683
36
5%
1/16W
MF-LF
2 402
XDP
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
OUT
R2688
R2696
0
LPC_RESET_L
LPCPLUS_RESET_L
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
10K
VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.
TQFN
7
10
16
2
0
IN
2
1
SLG3NB148A
R2605
12PF
=ENET_WAKE_L
MAKE_BASE=TRUE
33
1
MAKE_BASE=TRUE
R2695
CRITICAL
C2605
ENET_WAKE_L
PLT_RESET_L
IN
1
U2600
11
6
14
26 18
5%
1/16W
MF-LF
2 402
=PP3V3_S0_SB_PM
24 7
=PPVDDIO_ENET_CLK
=PPVDDIO_S0_SBCLK
=PPVDDIO_T29_CLK
7
+3.42V 13
7
+V3.3A 2
Ethernet XTAL Power
SB XTAL Power
T29 XTAL Power
=PP3V3_ENET_SYSCLK
10K
PCH Reset Button
VDD_25M 5
7
PCIE_WAKE_L
OUT
Coin-Cell & G3Hot:
3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary
D
GreenClk 25MHz Power
32 17 6
=PP3V3_S5_SYSCLK
VESM
D
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
7
R2630
SSM3K15AMFVAPE
=PPVBAT_G3_SYSCLK
R2681
1
Q2630
7
1
5%
1/16W
MF-LF
2 402
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
PM_PCH_PWROK OUT
17 24
PM_PCH_APWROKOUT
17
MAKE_BASE=TRUE
5
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
26 OF 109
SHEET
24 OF 86
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
HUB_ALLREM
HUB_NONREM1_0,HUB_NONREM0_0
HUB_1NONREM
HUB_NONREM1_0,HUB_NONREM0_1
HUB_2NONREM
HUB_NONREM1_1,HUB_NONREM0_0
HUB_3NONREM
HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
USB MUX FOR LS/FS INTERNAL DEVICES
D
25 7
C2700
C2701
1
4.7UF
1
1
2
2
C2702
0.1UF
20%
6.3V
X5R
603
NON_REM 1 : NON_REM 0
STRAP PIN CFG
0
:
0
ALL PORTS ARE REMOVABLE
0
:
1
PORT 1 IS NON REMOVABLE
1
:
0
PORT 1&2 ARE NON REMOVABLE
1
:
1
PORT 1&2&3 ARE NON REMOVABLE
CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
BYPASS=U2700.5::2MM
BYPASS=U27000.5::5MM
=PP3V3_S3_USB_HUB
TABLE_BOMGROUP_ITEM
10%
16V
X7R-CERM
0402
2
1
0.1UF
C2703
D
0.1UF
10%
16V
X7R-CERM
0402
2
10%
16V
X7R-CERM
0402
BOM TABLE
TABLE_5_HEAD
PART#
BYPASS=U2700.15::2MM
BYPASS=U2700.10::2MM
BYPASS=U2700.23::5MM
BYPASS=U2700.23::2MM
QTY
DESCRIPTION
1
USB HUB 2514B
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
CRITICAL
USBHUB2514B
CRITICAL
USBHUB2513B
CRITICAL
USBHUB2512B
TABLE_5_ITEM
338S0824
U2700
TABLE_5_ITEM
338S0923
1
U2700
USB HUB 2513B
TABLE_5_ITEM
0.1UF
10%
16V
X7R-CERM
0402
VOLTAGE=1.8V
VDD33
Y2700
24.000M-60PPM-16PF
1
2
USB_HUB_XTAL2
C2709
1
CRITICAL
18PF
HUB_NONREM1_1
C
R2702
1
HUB_NONREM0_1
1
10K
5%
1/16W
MF-LF
402
1
R2710
2
5%
1/16W
MF-LF
CRITICAL
2
R2704 1
2
R2701
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1
R2705
11
USB_HUB_TEST
2
HUB_NONREM0_0
10K
2
2
1
TEST
OMIT
25
26
USB_HUB_RESET_L
33
USB_HUB_XTAL1
USB_HUB_XTAL2_R
32
RESET*
34
14
1
0.1UF
2
10%
16V
X7R-CERM
0402
2
C2712
1UF
10%
16V
X7R-CERM
0402
2
2
10%
16V
X5R
402
=PP3V3_S3_USB_HUB
1
R2706
5%
1/16W
MF-LF
402
USB_HUB_NONREM1
22
SDA/SMBDATA/NON_REM1
USB_HUB_CFG_SEL0
24
SCL/SMBCLK/CFG_SEL0
USB_HUB_CFG_SEL1
25
HS_IND/CFG_SEL1
SUSP_IND/LOCAL_PWR/NON_REM0
3
6
NC
NC
8
7
9
12
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
NC
R2707
5%
1/16W
MF-LF
402
16
18
20
13
OCS1*
OCS2*
OSC3*
NC
IPU
IPU
IPU
IPU
USBHUB_DN2_N
USBHUB_DN2_P
4
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
10K
2
USBHUB_DN1_N
USBHUB_DN1_P
2
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
XTALIN/CLKIN
XTALOUT
28
1
1
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
BI
8
BI
8
BLUETOOTH FOR J5 & J3X
17
19
21
BI
8
BI
8
25 8
USBHUB_DN3_N
USBHUB_DN3_P
BI
8 25
BI
8 25
USBHUB_DN4_N
USBHUB_DN4_P
BI
25
BI
25
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
J3X USE 197S0284 FOR Y2700 TO SAVE COST
25 8
25
NC FOR J5, SMC DEBUG PORT FOR J3X
=PP3V3_S3_USB_HUB
TP_USB_HUB_OCS1
NC_USB_HUB_OCS2
NC_USB_HUB_OCS3
NC_USB_HUB_OCS4
RBIAS
35
27
USB_HUB_VBUS_DET
USBDM_UP
USBDP_UP
30
USB_HUB_UP_N
USB_HUB_UP_P
R2717
1
R2718
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
7 25
NOSTUFF
1
R2719
10K
5%
1/16W
MF-LF
C
2 402
USBHUB_DN3_N
USBHUB_DN3_P
1
25
USBHUB_DN4_N
USBHUB_DN4_P
7 25
R2708
10K
5%
1/16W
MF-LF
402
USB_HUB_RBIAS
CRITICAL
31
THRM_PAD
BI
18 80
BI
18 80
1
2
37
R2709
12K
PCH PORT 7 (EHCI1)
=PP3V3_S3_USB_RESET
B
1
NOSTUFF
SMC DEBUG PORT FOR J5, TP/KB FOR J3X
TP_USB_HUB_PRTPWR1
NC_USB_HUB_PRTPWR2
NC_USB_HUB_PRTPWR3
NC_USB_HUB_PRTPWR4
VBUS_DET
R2716
NOSTUFF
TP/KB FOR J5, IR FOR J3X
2
7
10%
16V
X5R
402
1UF
2
USB_HUB_NONREM0
10K
2
C2711
NOSTUFF
10K
5%
1/16W
MF-LF
402
1
QFN
100
5%
1/16W
MF-LF
402
2
C2714
USB2513B
5%
50V
C0G-CERM 1
0402
1M
1
R2703
2
R2700
2 402
1
U2700
USB HUB 2512B
U2700
C2710
18PF
0
10K
HUB_NONREM1_0
5%
1/16W
MF-LF
402
5%
50V
C0G-CERM
0402
SYM VER 1
5X3.2X1.4-SM
1
VOLTAGE=1.8V
C2713
0.1UF
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
PLLFILT
BYPASS=U2700.36::2MM
BYPASS=U2650.29::2MM
CRITICAL
1
PPUSB_HUB2_VDD1V8PLL
1
J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
2
5
2
36
0.1UF
10%
16V
X7R-CERM
0402
2
PPUSB_HUB2_VDD1V8
CRFILT
10%
16V
X7R-CERM
0402
2
338S0983
1
29
0.1UF
20%
6.3V
X5R
603
C2708
1
23
4.7UF
C2706
1
15
C2705
1
10
C2704
1%
1/16W
MF
402
B
1
R2712
10K
5%
1/16W
MF-LF
2 402
USB_HUB_RESET_L
C2715
25
1
0.1UF
2
PLACE_NEAR=U2700.26:2.5MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
7
=PP3V3_S3_USBMUX
C2760
1
9
10%
16V
X7R-CERM
0402
0.1UF
18
80
80 18
PCH PORT 9 (EHCI2)
BI
BI
A
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
20%
10V
CERM
402
VCC
2
5 M+
4 M-
Y+ 1
Y- 2
U2760
USB_EXTB_MUX_P
USB_EXTB_MUX_N
BI
43 80
BI
43 80
TO CONNECTOR
PI3USB102ZLE
PCH PORT 1 (XHCI)
18
80
BI
80 18
BI
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
7 D+
6 D-
SYNC_MASTER=LINDA_J30
TQFN
CRITICAL
USB HUB & MUX
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE
8
SEL 10
OE*
3
GND
SYNC_DATE=09/19/2011
PAGE TITLE
USB_EXTB_SEL_XHCI
IN
SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT
16
DRAWING NUMBER
PCH GPIO60
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
051-9058
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
27 OF 109
SHEET
25 OF 86
1
A
8
7
6
5
4
3
2
1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
D
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
D
WHEN LOW:
CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN
= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN
= (ISOLATE_CPU_MEM_L + PLT_RST_L)
1V5 S0 "PGOOD" for CPU
* PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
7
73 45 32 17 6
=PP3V3_S5_CPU_VCCDDR
PM_SLP_S4_L
IN
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
CPUMEM_S0
1
R2805
15 12 10 7
=PP1V5_S3_CPU_VCCDDR
PM_MEM_PWRGD
1
10K
5%
1/16W
MF-LF
2 402
OUT
R2820 1
72
2
5%
1/16W
MF-LF
402
CRITICAL
6
D
Q2820
27.4K
=PP3V3_S3_MEMRESET
CPUMEM_S0
D
Q2805
CPUMEM_S0
1%
1/16W
MF-LF
402
6
SSM6N37FEAPE
R2801 1
10 17 78
10K
P1V5CPU_EN
7
OUT
R2822
DMB53D0UV
SOT-563
G
2
PM_MEM_PWRGD_L
2
SOT563
100K
5%
1/16W
MF-LF
402
CRITICAL
3
2
2
G
S
5
P1V5_S0_DIV
1
Q2820
S
DMB53D0UV
1
SOT-563
P1V5CPU_EN_L
4
CPUMEM_S0
CPUMEM_S0
D
Q2800
3
3
D
SSM6N37FEAPE
C
5
1%
1/16W
MF-LF
402
SOT563
G
S
4
4
S
G
C2820
1
0.001UF
20%
50V
CERM
402
2
C
2
5
ISOLATE_CPU_MEM_L
IN
NO STUFF
1
33.2K
SSM6N37FEAPE
SOT563
23
R2821
Q2805
PM_SLP_S3_L
IN
6 8 17 45 73
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
2 402
26 7
MEMVTT_EN
=PP5V_S3_MEMRESET
OUT
8
MEMVTT Clamp
CPUMEM_S0
CPUMEM_S0
R2815
Q2810
CPUMEM_S0
1
R2802
100K
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
D
6
Ensures CKE signals are held low in S3
SSM6N37FEAPE
1
SOT563
2
2
G
S
7
1
=PPVTT_S0_VTTCLAMP
CPUMEM_S0
MEMVTT_EN_L
R2850
CPUMEM_S0
CPUMEM_S0
Q2800
Q2815
3
D
5%
1/10W
MF-LF
603
Q2810
SSM6N37FEAPE
SSM6N37FEAPE
SOT563
SOT563
2
SSM6N37FEAPE
75mA max load @ 0.75V
60mW max power
2
VTTCLAMP_L
G
SOT563
6
1
10
CPUMEM_S0
D
S
1
4
S
G
5
26 7
=PP5V_S3_MEMRESET
CPUMEM_S0
Q2850
CPUMEM_S0
PLT_RESET_L
IN
18 24
D
6
S
1
B
SSM6N37FEAPE
R2851 1
1
6
D
G
S
2
B
SOT563
100K
5%
1/16W
MF-LF
402
NOSTUFF
C2817
1
=PP1V5_S3_MEMRESET
0.047UF
10%
6.3V
X5R
201
CPUMEM_S0
Q2815
1
5
SSM6N37FEAPE
MEMRESET_ISOL_LS5V_L
C2816
CPUMEM_S0
0.1UF
5%
1/16W
MF-LF
402
2
Q2850
10%
16V
X7R-CERM
0402
D
3
OUT
20%
50V
CERM
402
27 29
5
67 8
CPUMEM_S3
IN
G
1
0.001UF
SOT563
MEM_RESET_L
NO STUFF
C2851
SSM6N37FEAPE
D
CPU_MEM_RESET_L
MAKE_BASE=TRUE
1
R2816
3
=MEM_RESET_L
4
IN
S
2
10
G
CPUMEM_S0
1K
SOT563
G
31
2
2
VTTCLAMP_EN
CPUMEM_S0
2
7
S
2
4
=DDRVTT_EN
R2817
1
0
2
5%
1/16W
MF-LF
402
Step
S0
to
A
S3
to
S0
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
0
1
2
3
ISOLATE_CPU_MEM_L
1
0
0
0
PLT_RESET_L
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
X
CPU_MEM_RESET_L
1
1
1
MEM_RESET_L
MEMVTT_EN
1
1
0
0
P1V5CPU_EN
1
1
1
0
4
5
6
7
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
X
0 (*)
1
1
1
1
1
CPU_MEM_RESET_L
0
1
1
1
1
1
1
1
SYNC_MASTER=K90I_MLB
CPU Memory S3 Support
DRAWING NUMBER
Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTICE OF PROPRIETARY PROPERTY:
Rails will power-up as if from S3, but MEM_RESET_L will not properly assert.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
8
7
6
051-9058
5
4
3
2
SIZE
D
REVISION
R
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition.
SYNC_DATE=02/15/2011
PAGE TITLE
6.0.0
BRANCH
PAGE
28 OF 109
SHEET
26 OF 86
1
A
8
7
6
5
4
3
2
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
7
=PP1V5_S3_MEM_A
Power aliases required by this page:
- =PP1V5_S0_MEM_A
1
- =PP1V5_S3_MEM_A
C2910
- =PP0V75_S0_MEM_VTT_A
2
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
1
- =I2C_SODIMMA_SCL
2
D
C2900
1
BOM options provided by this page:
1
C2912
1
C2913
1
C2914
1
C2915
1
C2916
1
C2917
1
C2918
1
C2919
1
C2920
1
C2921
1
C2922
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
2
2
2
2
2
2
2
2
2
2
2
2
1
C2923
0.1UF
2
20%
10V
CERM
402
C2901
10UF
- =I2C_SODIMMA_SDA
C2911
1
0.1UF
10UF
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
D
31 PP0V75_S3_MEM_VREFDQ_A
(NONE)
1
1
C2930
C2931
2.2UF
0.1UF
20%
6.3V
2
20%
10V
2
CERM
402-LF
CERM
402
OMIT_TABLE
OMIT_TABLE
73
MEM_A_CKE<0>
75
NC
79 11
IN
77
79
MEM_A_BA<2>
81
79 11
IN
MEM_A_A<12>
83
79 11
IN
MEM_A_A<9>
85
87
79 11
IN
MEM_A_A<8>
89
79 11
IN
MEM_A_A<5>
91
93
79 11
IN
MEM_A_A<3>
95
79 11
IN
MEM_A_A<1>
97
99
C
79 11
IN
MEM_A_CLK_P<0>
101
79 11
IN
MEM_A_CLK_N<0>
103
105
IN
MEM_A_A<10>
107
IN
MEM_A_BA<0>
109
79 11
IN
MEM_A_WE_L
113
79 11
IN
MEM_A_CAS_L
115
79 11
79 11
111
117
79 11
79 11
IN
MEM_A_A<13>
119
IN
MEM_A_CS_L<1>
121
123
NC
125
127
28
BI
=MEM_A_DQ<32>
129
28
BI
=MEM_A_DQ<33>
131
133
28
28
BI
=MEM_A_DQS_N<4>
135
BI
=MEM_A_DQS_P<4>
137
139
28
28
BI
=MEM_A_DQ<34>
141
BI
=MEM_A_DQ<35>
143
145
28
28
BI
=MEM_A_DQ<40>
147
BI
=MEM_A_DQ<41>
149
151
28
IN
=MEM_A_DM<5>
153
155
B
28
BI
=MEM_A_DQ<42>
157
28
BI
=MEM_A_DQ<43>
159
161
28
BI
=MEM_A_DQ<48>
163
28
BI
=MEM_A_DQ<49>
165
167
28
BI
=MEM_A_DQS_N<6>
28
BI
=MEM_A_DQS_P<6>
169
171
173
28
28
BI
=MEM_A_DQ<50>
175
BI
=MEM_A_DQ<51>
177
179
28
BI
=MEM_A_DQ<56>
181
28
BI
=MEM_A_DQ<57>
183
185
28
IN
=MEM_A_DM<7>
187
189
28
BI
=MEM_A_DQ<58>
191
28
BI
=MEM_A_DQ<59>
193
195
MEM_A_SA<0>
197
199
7 =PPSPD_S0_MEM_A
MEM_A_SA<1>
201
203
1
1
A
C2940
10K
2.2UF
20%
6.3V
2
CERM
402-LF
1
R2940
2
CKE0
CKE1
VDD
VDD
NC
J2900 A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A0
A1
VDD
VDD
CK0
CK1
CK0*
CK1*
VDD
VDD
A10/AP
BA1
BA0
RAS*
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
(SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-K6
79 11
74
MEM_A_CKE<1>
IN
11 79
28
78
MEM_A_A<15>
IN
11 79
80
MEM_A_A<14>
IN
11 79
BI
=MEM_A_DQ<0>
5
=MEM_A_DQ<1>
7
9
28
11
=MEM_A_DM<0>
IN
82
13
84
MEM_A_A<11>
IN
11 79
28
BI
=MEM_A_DQ<2>
15
86
MEM_A_A<7>
IN
11 79
28
BI
=MEM_A_DQ<3>
17
88
19
90
MEM_A_A<6>
IN
11 79
28
BI
=MEM_A_DQ<8>
21
92
MEM_A_A<4>
IN
11 79
28
BI
=MEM_A_DQ<9>
23
94
25
96
MEM_A_A<2>
IN
11 79
28
BI
=MEM_A_DQS_N<1>
98
MEM_A_A<0>
IN
11 79
28
BI
=MEM_A_DQS_P<1>
27
29
100
31
102
MEM_A_CLK_P<1>
IN
11 79
28
BI
=MEM_A_DQ<10>
104
MEM_A_CLK_N<1>
IN
11 79
28
BI
=MEM_A_DQ<11>
33
35
106
37
108
MEM_A_BA<1>
110
MEM_A_RAS_L
114
116
BI
=MEM_A_DQ<16>
39
BI
=MEM_A_DQ<17>
41
28
BI
=MEM_A_DQS_N<2>
28
BI
=MEM_A_DQS_P<2>
IN
11 79
28
IN
11 79
28
MEM_A_CS_L<0>
IN
11 79
MEM_A_ODT<0>
IN
11 79
112
43
45
47
118
49
120
122
MEM_A_ODT<1>
IN
11 79
28
NC
28
BI
=MEM_A_DQ<18>
51
BI
=MEM_A_DQ<19>
53
124
55
126
28
128
28
130
=MEM_A_DQ<36>
BI
28
132
=MEM_A_DQ<37>
BI
28
BI
=MEM_A_DQ<24>
57
BI
=MEM_A_DQ<25>
59
61
28
63
=MEM_A_DM<3>
IN
134
136
65
=MEM_A_DM<4>
IN
28
138
140
=MEM_A_DQ<38>
BI
28
142
=MEM_A_DQ<39>
BI
28
146
=MEM_A_DQ<44>
BI
28
148
=MEM_A_DQ<45>
BI
28
152
=MEM_A_DQS_N<5>
BI
28
154
=MEM_A_DQS_P<5>
BI
28
158
=MEM_A_DQ<46>
BI
28
160
=MEM_A_DQ<47>
BI
28
164
=MEM_A_DQ<52>
BI
28
166
=MEM_A_DQ<53>
BI
28
=MEM_A_DM<6>
IN
174
=MEM_A_DQ<54>
BI
28
176
=MEM_A_DQ<55>
BI
28
180
=MEM_A_DQ<60>
BI
28
182
=MEM_A_DQ<61>
BI
28
28
28
BI
=MEM_A_DQ<26>
67
BI
=MEM_A_DQ<27>
69
71
=MEM_A_DQ<4>
BI
28
6
=MEM_A_DQ<5>
BI
28
10
=MEM_A_DQS_N<0>
BI
28
12
=MEM_A_DQS_P<0>
BI
28
16
=MEM_A_DQ<6>
BI
28
18
=MEM_A_DQ<7>
BI
28
22
=MEM_A_DQ<12>
BI
28
24
=MEM_A_DQ<13>
BI
=MEM_A_DM<1>
IN
28
26 29
8
14
20
28
26
28
30
MEM_RESET_L
IN
34
=MEM_A_DQ<14>
BI
28
36
=MEM_A_DQ<15>
BI
28
40
=MEM_A_DQ<20>
BI
28
42
=MEM_A_DQ<21>
BI
28
32
C
38
44
46
=MEM_A_DM<2>
IN
50
=MEM_A_DQ<22>
BI
28
52
=MEM_A_DQ<23>
BI
28
56
=MEM_A_DQ<28>
BI
28
58
=MEM_A_DQ<29>
BI
28
62
=MEM_A_DQS_N<3>
BI
28
64
=MEM_A_DQS_P<3>
BI
28
68
=MEM_A_DQ<30>
BI
28
70
=MEM_A_DQ<31>
BI
28
28
48
54
60
66
72
KEY
144
150
156
B
162
168
170
28
172
PP0V75_S3_MEM_VREFCA_A
31
178
1
2.2UF
186
20%
6.3V
188
=MEM_A_DQS_N<7>
BI
28
2
1
C2935
184
=MEM_A_DQS_P<7>
BI
28
192
=MEM_A_DQ<62>
BI
28
194
=MEM_A_DQ<63>
BI
28
C2936
0.1UF
20%
10V
2
CERM
402-LF
CERM
402
190
196
198
MEM_EVENT_L
OUT
29 45 46
200
=I2C_SODIMMA_SDA
BI
202
=I2C_SODIMMA_SCL
IN
"Factory" (top) slot
48
48
204
=PP0V75_S0_MEM_VTT_A
10K
5%
5%
1/16W
MF-LF
MF-LF
2
BI
2
4
7
R2941
1/16W
402
28
76
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
CRITICAL
DQ1
VSS
VSS
DQS0*
J2900 DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
DQ19
VSS
DQ28
VSS
DQ24
DQ29
DQ25
VSS
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
(SYMBOL 1 OF 2)
3
KEY
DDR3-SODIMM-DUAL-K6
1
1
SPD ADDR=0xA0(WR)/0xA1(RD)
402
2
C2950
1
C2951
1
C2952
1UF
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
2
2
1
2
C2953
1UF
SYNC_MASTER=K90I_MLB
10%
10V
X5R
402
PAGE TITLE
SYNC_DATE=02/15/2011
DDR3 SO-DIMM Connector A
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
29 OF 109
SHEET
27 OF 86
1
A
8
7
6
79 11
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
D
79 11
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
=MEM_A_DM<0>
=MEM_A_DQ<3>
=MEM_A_DQ<6>
=MEM_A_DQ<1>
=MEM_A_DQ<5>
=MEM_A_DQ<2>
=MEM_A_DQ<7>
=MEM_A_DQ<0>
=MEM_A_DQ<4>
27
79 11
27
79 11
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MAKE_BASE=TRUE
27
27
79 11
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
79 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DM<1>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<12>
=MEM_A_DQ<9>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<8>
27
79 11
27
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
27
79 11
79 11
79 11
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DM<2>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
27
79 11
27
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
27
27
79 11
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
79 11
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DM<3>
=MEM_A_DQ<26>
=MEM_A_DQ<24>
=MEM_A_DQ<28>
=MEM_A_DQ<25>
=MEM_A_DQ<31>
=MEM_A_DQ<27>
=MEM_A_DQ<30>
=MEM_A_DQ<29>
27
79 11
27
79 11
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
27
79 11
79 11
79 11
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
29
29
29
29
29
29
29
D
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DM<1>
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<13>
=MEM_B_DQ<8>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<12>
=MEM_B_DQ<9>
29
29
29
29
29
29
29
29
29
29
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DM<2>
=MEM_B_DQ<23>
=MEM_B_DQ<18>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<22>
=MEM_B_DQ<19>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
29
29
29
29
29
29
29
29
29
29
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<30>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<27>
=MEM_B_DQ<31>
=MEM_B_DQ<25>
=MEM_B_DQ<24>
C
29
29
29
29
29
29
29
29
29
29
29
CPU CHANNEL B DQS 4 -> DIMM B DQS 4
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DM<4>
=MEM_A_DQ<38>
=MEM_A_DQ<39>
=MEM_A_DQ<37>
=MEM_A_DQ<33>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<32>
=MEM_A_DQ<36>
27
79 11
27
79 11
MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
27
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DM<4>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<33>
=MEM_B_DQ<37>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<32>
=MEM_B_DQ<36>
29
29
29
29
29
29
29
29
29
29
29
MAKE_BASE=TRUE
CPU CHANNEL B DQS 5 -> DIMM B DQS 5
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DM<5>
=MEM_A_DQ<46>
=MEM_A_DQ<43>
=MEM_A_DQ<45>
=MEM_A_DQ<41>
=MEM_A_DQ<47>
=MEM_A_DQ<42>
=MEM_A_DQ<40>
=MEM_A_DQ<44>
27
79 11
27
79 11
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
27
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
27
79 11
79 11
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DM<5>
=MEM_B_DQ<43>
=MEM_B_DQ<46>
=MEM_B_DQ<40>
=MEM_B_DQ<45>
=MEM_B_DQ<47>
=MEM_B_DQ<42>
=MEM_B_DQ<41>
=MEM_B_DQ<44>
29
B
29
29
29
29
29
29
29
29
29
29
MAKE_BASE=TRUE
CPU CHANNEL B DQS 6 -> DIMM B DQS 6
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DM<6>
=MEM_A_DQ<51>
=MEM_A_DQ<54>
=MEM_A_DQ<49>
=MEM_A_DQ<53>
=MEM_A_DQ<50>
=MEM_A_DQ<55>
=MEM_A_DQ<48>
=MEM_A_DQ<52>
27
79 11
27
79 11
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
27
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DM<6>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<53>
=MEM_B_DQ<49>
=MEM_B_DQ<51>
=MEM_B_DQ<50>
=MEM_B_DQ<48>
=MEM_B_DQ<52>
29
29
29
29
29
29
29
29
29
29
29
MAKE_BASE=TRUE
CPU CHANNEL B DQS 7 -> DIMM B DQS 7
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
=MEM_A_DQ<57>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<56>
27
79 11
27
79 11
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
27
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
27
79 11
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MAKE_BASE=TRUE
NOTE:
29
MAKE_BASE=TRUE
CPU CHANNEL A DQS 7 -> DIMM A DQS 7
79 11
MAKE_BASE=TRUE
27
MAKE_BASE=TRUE
A
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU CHANNEL A DQS 6 -> DIMM A DQS 6
79 11
MAKE_BASE=TRUE
29
CPU CHANNEL B DQS 3 -> DIMM B DQS 3
MAKE_BASE=TRUE
79 11
MAKE_BASE=TRUE
29
MAKE_BASE=TRUE
CPU CHANNEL A DQS 5 -> DIMM A DQS 5
79 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
B
MAKE_BASE=TRUE
27
CPU CHANNEL A DQS 4 -> DIMM A DQS 4
79 11
MAKE_BASE=TRUE
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DM<0>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<0>
=MEM_B_DQ<4>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<1>
CPU CHANNEL B DQS 2 -> DIMM B DQS 2
MAKE_BASE=TRUE
79 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DM<7>
=MEM_B_DQ<56>
=MEM_B_DQ<59>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<63>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<62>
29
29
SYNC_MASTER=K90I_MLB
29
DDR3 Byte/Bit Swaps
29
DRAWING NUMBER
29
29
Apple Inc.
29
6
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
29
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
29
5
4
3
2
SIZE
D
REVISION
6.0.0
29
MAKE_BASE=TRUE
7
SYNC_DATE=02/15/2011
PAGE TITLE
29
Ivybridge does not use DM signals per doc 460452 CR SFF DG Section 2.6.14
8
1
MAKE_BASE=TRUE
CPU CHANNEL A DQS 3 -> DIMM A DQS 3
79 11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE
27
CPU CHANNEL A DQS 2 -> DIMM A DQS 2
79 11
2
CPU CHANNEL B DQS 1 -> DIMM B DQS 1
MAKE_BASE=TRUE
79 11
3
MAKE_BASE=TRUE
CPU CHANNEL A DQS 1 -> DIMM A DQS 1
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MAKE_BASE=TRUE
27
MAKE_BASE=TRUE
79 11
4
CPU CHANNEL B DQS 0 -> DIMM B DQS 0
CPU CHANNEL A DQS 0 -> DIMM A DQS 0
79 11
5
BRANCH
PAGE
30 OF 109
SHEET
28 OF 86
1
A
8
7
6
5
4
3
2
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
7
=PP1V5_S3_MEM_B
Power aliases required by this page:
- =PP1V5_S0_MEM_B
1
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
Signal aliases required by this page:
C3100
1
- =I2C_SODIMMB_SCL
1
BOM options provided by this page:
C3112
1
C3113
1
C3114
1
C3115
1
C3116
1
C3117
1
C3118
1
C3119
1
C3120
1
C3121
1
C3122
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
2
2
2
2
2
2
2
2
2
2
2
2
1
C3123
0.1UF
2
20%
10V
CERM
402
10UF
20%
6.3V
X5R
603
2
1
0.1UF
20%
10V
CERM
402
C3101
10UF
- =I2C_SODIMMB_SDA
C3111
1
0.1UF
2
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
D
C3110
2
20%
6.3V
X5R
603
D
31 PP0V75_S3_MEM_VREFDQ_B
(NONE)
1
1
C3130
C3131
2.2UF
0.1UF
20%
10V
20%
6.3V
2
2
CERM
402-LF
CERM
402
OMIT_TABLE
OMIT_TABLE
75
NC
79 11
79
MEM_B_BA<2>
IN
77
81
79 11
IN
MEM_B_A<12>
83
79 11
IN
MEM_B_A<9>
85
87
79 11
IN
MEM_B_A<8>
89
79 11
IN
MEM_B_A<5>
91
93
79 11
IN
MEM_B_A<3>
95
79 11
IN
MEM_B_A<1>
97
99
C
79 11
IN
MEM_B_CLK_P<0>
101
79 11
IN
MEM_B_CLK_N<0>
103
105
IN
MEM_B_A<10>
107
IN
MEM_B_BA<0>
109
79 11
IN
MEM_B_WE_L
113
79 11
IN
MEM_B_CAS_L
115
79 11
79 11
111
117
79 11
79 11
IN
MEM_B_A<13>
119
IN
MEM_B_CS_L<1>
121
123
NC
125
127
28
BI
=MEM_B_DQ<32>
129
28
BI
=MEM_B_DQ<33>
131
133
28
28
BI
=MEM_B_DQS_N<4>
135
BI
=MEM_B_DQS_P<4>
137
139
28
28
BI
=MEM_B_DQ<34>
141
BI
=MEM_B_DQ<35>
143
145
28
28
BI
=MEM_B_DQ<40>
147
BI
=MEM_B_DQ<41>
149
151
28
=MEM_B_DM<5>
IN
153
155
B
28
BI
=MEM_B_DQ<42>
157
28
BI
=MEM_B_DQ<43>
159
161
28
BI
=MEM_B_DQ<48>
163
28
BI
=MEM_B_DQ<49>
165
167
28
BI
=MEM_B_DQS_N<6>
28
BI
=MEM_B_DQS_P<6>
169
171
173
28
28
BI
=MEM_B_DQ<50>
175
BI
=MEM_B_DQ<51>
177
179
28
BI
=MEM_B_DQ<56>
181
28
BI
=MEM_B_DQ<57>
183
185
28
=MEM_B_DM<7>
IN
187
189
28
BI
=MEM_B_DQ<58>
191
28
BI
=MEM_B_DQ<59>
193
195
MEM_B_SA<0>
197
199
7 =PPSPD_S0_MEM_B
MEM_B_SA<1>
201
203
1
1
A
C3140
20%
6.3V
2
CERM
402-LF
1
R3140
10K
2.2UF
2
R3141
10K
5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
2
402
205
207
209
211
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
J3100
VDD
F-RT-BGA6
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK0
CK1
CK0*
CK1*
VDD
VDD
A10/AP
BA1
BA0
RAS*
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ39
DQ34
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DQS7
DM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
(2 OF 2)
73
MEM_B_CKE<0>
IN
DDR3-SODIMM
79 11
MTG PINS
MTG
MTG
MTG
MTG
PIN
PIN
PIN
PIN
74
MEM_B_CKE<1>
IN
11 79
28
76
28
78
MEM_B_A<15>
IN
11 79
80
MEM_B_A<14>
IN
11 79
BI
BI
=MEM_B_DQ<0>
5
=MEM_B_DQ<1>
7
9
28
IN
11
=MEM_B_DM<0>
82
13
84
MEM_B_A<11>
IN
11 79
28
86
MEM_B_A<7>
IN
11 79
28
BI
=MEM_B_DQ<2>
15
BI
=MEM_B_DQ<3>
17
88
19
90
MEM_B_A<6>
IN
11 79
28
BI
=MEM_B_DQ<8>
21
92
MEM_B_A<4>
IN
11 79
28
BI
=MEM_B_DQ<9>
23
94
25
96
MEM_B_A<2>
IN
11 79
28
BI
=MEM_B_DQS_N<1>
27
98
MEM_B_A<0>
IN
11 79
28
BI
=MEM_B_DQS_P<1>
29
100
31
102
MEM_B_CLK_P<1>
IN
11 79
28
BI
=MEM_B_DQ<10>
33
104
MEM_B_CLK_N<1>
IN
11 79
28
BI
=MEM_B_DQ<11>
35
106
37
108
MEM_B_BA<1>
110
MEM_B_RAS_L
114
116
BI
=MEM_B_DQ<16>
39
BI
=MEM_B_DQ<17>
41
28
BI
=MEM_B_DQS_N<2>
45
28
BI
=MEM_B_DQS_P<2>
47
IN
11 79
28
IN
11 79
28
MEM_B_CS_L<0>
IN
11 79
MEM_B_ODT<0>
IN
11 79
112
43
118
49
120
122
MEM_B_ODT<1>
IN
11 79
28
NC
28
BI
=MEM_B_DQ<18>
51
BI
=MEM_B_DQ<19>
53
124
55
126
28
128
28
130
=MEM_B_DQ<36>
BI
28
132
=MEM_B_DQ<37>
BI
28
BI
=MEM_B_DQ<24>
57
BI
=MEM_B_DQ<25>
59
61
28
IN
63
=MEM_B_DM<3>
134
136
65
=MEM_B_DM<4>
IN
28
138
140
=MEM_B_DQ<38>
BI
28
142
=MEM_B_DQ<39>
BI
28
146
=MEM_B_DQ<44>
BI
28
148
=MEM_B_DQ<45>
BI
28
152
=MEM_B_DQS_N<5>
BI
28
154
=MEM_B_DQS_P<5>
BI
28
158
=MEM_B_DQ<46>
BI
28
160
=MEM_B_DQ<47>
BI
28
164
=MEM_B_DQ<52>
BI
28
166
=MEM_B_DQ<53>
BI
28
=MEM_B_DM<6>
IN
174
=MEM_B_DQ<54>
BI
28
176
=MEM_B_DQ<55>
BI
28
180
=MEM_B_DQ<60>
BI
28
182
=MEM_B_DQ<61>
BI
28
28
28
BI
=MEM_B_DQ<26>
67
BI
=MEM_B_DQ<27>
69
71
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
CRITICAL
DQ1
VSS
VSS
DQS0*
J3100 DQS0
DM0
F-RT-BGA6
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ23
DQ18
DQ19
VSS
DQ28
VSS
DQ24
DQ29
DQ25
VSS
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
(1 OF 2)
3
KEY
DDR3-SODIMM
1
2
4
=MEM_B_DQ<4>
BI
28
6
=MEM_B_DQ<5>
BI
28
10
=MEM_B_DQS_N<0>
BI
28
12
=MEM_B_DQS_P<0>
BI
28
16
=MEM_B_DQ<6>
BI
28
18
=MEM_B_DQ<7>
BI
28
22
=MEM_B_DQ<12>
BI
28
24
=MEM_B_DQ<13>
BI
=MEM_B_DM<1>
IN
28
26 27
8
14
20
28
26
28
30
MEM_RESET_L
IN
34
=MEM_B_DQ<14>
BI
28
36
=MEM_B_DQ<15>
BI
28
40
=MEM_B_DQ<20>
BI
28
42
=MEM_B_DQ<21>
BI
28
32
C
38
44
46
=MEM_B_DM<2>
IN
50
=MEM_B_DQ<22>
BI
28
52
=MEM_B_DQ<23>
BI
28
56
=MEM_B_DQ<28>
BI
28
58
=MEM_B_DQ<29>
BI
28
62
=MEM_B_DQS_N<3>
BI
28
64
=MEM_B_DQS_P<3>
BI
28
68
=MEM_B_DQ<30>
BI
28
70
=MEM_B_DQ<31>
BI
28
28
48
54
60
66
72
KEY
144
150
156
B
162
168
170
28
172
PP0V75_S3_MEM_VREFCA_B
31
178
1
2.2UF
186
20%
6.3V
188
=MEM_B_DQS_N<7>
BI
28
2
1
C3135
184
20%
10V
CERM
402-LF
=MEM_B_DQS_P<7>
BI
28
192
=MEM_B_DQ<62>
BI
28
194
=MEM_B_DQ<63>
BI
28
C3136
0.1UF
2
CERM
402
190
196
198
MEM_EVENT_L
OUT
27 45 46
200
=I2C_SODIMMB_SDA
BI
202
=I2C_SODIMMB_SCL
IN
48
"Expansion" (bottom) slot
48
204
MTG PIN
206
MTG PIN
208
MTG PIN
210
MTG PIN
212
=PP0V75_S0_MEM_VTT_B
1
2
C3150
1
C3151
1
C3152
1UF
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
2
2
7
1
2
C3153
1UF
SYNC_MASTER=K90I_MLB
10%
10V
X5R
402
PAGE TITLE
SYNC_DATE=02/15/2011
DDR3 SO-DIMM Connector B
DRAWING NUMBER
Apple Inc.
SPD ADDR=0xA4(WR)/0xA5(RD)
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
31 OF 109
SHEET
29 OF 86
1
A
8
7
6
5
4
3
2
1
SD Card Connector
516-0225
CRITICAL
J3300
SD-CARD-K19-K24
F-RT-TH
CRITICAL
L3300
3
47NH-1.3OHM
82 36
82 36
D
82 36
82 36
IN
OUT
BI
BI
82 36
BI
82 36
BI
82 36
BI
82 36
BI
82 36
BI
82 36
BI
30
SDCONN_CLK
SDCONN_CMD
SDCONN_DATA<0>
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>
SDCONN_DATA<5>
SDCONN_DATA<6>
SDCONN_DATA<7>
SDCONN_CARDDETECT_L
OUT
R3379
R3361
R3371
R3372
R3373
R3374
R3375
R3376
R3377
R3378
33
33
33
33
33
33
33
33
33
33
1
2
5%
1/16W
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W
MF-LF 402
1
2
5%
1/16W
MF-LF 402
1
2
5%
1/16W
MF-LF 402
1
2
5%
1/16W
MF-LF 402
1
2
5%
1/16W
MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W
1
SDCONN_CLK_R
SDCONN_CMD_R
SDCONN_R_DATA<0>
SDCONN_R_DATA<1>
SDCONN_R_DATA<2>
SDCONN_R_DATA<3>
SDCONN_R_DATA<4>
SDCONN_R_DATA<5>
SDCONN_R_DATA<6>
SDCONN_R_DATA<7>
MF-LF 402
MF-LF 402
6
2
SDCONN_CLK_R_L
5
2
0402
7
8
9
1
10
11
12
13
14
15
36
16
SDCONN_WP
=PP3V3_S0_SW_SD_PWR
OUT
30
4
NOSTUFF
1
Place near attr for series resistors:
PLACE_NEAR=U3900.21:5MM
PLACE_NEAR=U3900.26:5MM
NOSTUFF
C3373
NOSTUFF
C3370
18
10PF
10PF
10PF
22PF
15PF
19
5%
50V
COG-CERM
0201
5%
50V
COG-CERM
0201
5%
50V
COG-CERM
0201
5%
50V
CERM
0402
5%
50V
CERM
402
20
2
2
2
2
1
2
1
2
C3371
17
5%
50V
COG-CERM
0201
PLACE_NEAR=U3900.25:5MM
C3381
NOSTUFF
10PF
1
C3379
NOSTUFF
5%
50V
COG-CERM
0201
1
C3377
NOSTUFF
10PF
1
C3375
NOSTUFF
1
2
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
D
CD/DAT3
DAT4
DAT5
DAT6
DAT7
SD Not Inserted, CARD_DETECT is OPEN.
CAESAR-IV Card Detect is programmable,
but a Silicon bug makes the active
high case unusable.
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
PLACE_NEAR=U3900.24:5MM
PLACE_NEAR=U3900.23:5MM
PLACE_NEAR=U3900.22:5MM
NOSTUFF
PLACE_NEAR=U3900.52:5MM
1
PLACE_NEAR=U3900.53:5MM
PLACE_NEAR=U3900.54:5MM
PLACE_NEAR=U3900.55:5MM
NOSTUFF
C3372
1
NOSTUFF
C3374
10PF
10PF
5%
50V
2 COG-CERM
0201
5%
50V
2 COG-CERM
0201
1
NOSTUFF
C3376
1
10PF
2
C3378
NOSTUFF
1
10PF
5%
50V
COG-CERM
0201
2
C3380
10PF
5%
50V
COG-CERM
0201
2
5%
50V
COG-CERM
0201
C
C
SD Detect & Reset Logic
SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit
Converts SDCONN from active-low level signal to active-high pulses.
=PP3V3_S4_SD_HPD
C3310
Must STUFF R3312 and NOSTUFF R3314
when R3311 is NOT STUFFED.
R3314 and R3312 mutually exclusive
to bypass reset logic
1
10
7
1UF
R3311 and R3310 mutually exclusive
to control effect of =ENET_RESET_L
on DET_CHANGED# logic.
10%
10V 2
X5R
402-1
1
CRITICAL
U3311
TDFN
2
R3311
=ENET_RESET_L
1
30
DET_IN
(IPU)
SDCONN_CARDDETECT_L
SD_DET_LVL_L
1
2
1
R3310
1
R3316
SLG_ENET_RESET_OUT_L
1
0
ENET_RESET_L
2
OUT
36 82
OUT
24 46
OUT
36
5%
1/16W
MF-LF
402
DET_CH_EN*
6
SD_DET_CH_EN_L
(OD)
9
SDCONN_STATE_CHANGE_SMC
DET_CHNGD*
(OD)
8
SDCONN_DETECT_L
-> To Isolation Circuit (then to PCH GPIOi) & SMC
-> To ENET Chip
DET_OUT
10K
10K
GND
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
DLY
4
B
DET_LVL
5
B
IN
7
SLG_ENET_RESET_IN_L
2
5%
1/16W
MF-LF
402
-> From SD Conn
(Low active)
RST_IN*
RST_OUT*
THRM
PAD
1
11
IN
3
RST
LOGIC
XOR
24
-> From PCH GPI0
0
R3314
LOW_PWR
XOR
IN
ENET_LOW_PWR
5%
1/16W
MF-LF
402
2
SLG4AP026V
36 24
R3315
10K
VDD
2
NOSTUFF
R3317
1
R3312
10K
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
DLY block is 20ms nominal
When ENET_LOW_PWR deasserts, RST_OUT#
deasserts for >80ms, then asserts for
10ms regardless ofmove RST_IN# state.
Otherwise RST_OUT# follows RST_IN#
NOSTUFF
SD Card 3.3V Overcurrent Protection
TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.
CRITICAL
=PP3V3_S0_SW_SD_PWR
U3300
30
TPS2065-1
7
36
=PP3V3_S0_SDCARD
3
4
ENET_CR_PWREN
A
IN0
IN1
DGN
EN
CRITICAL
C3300
10UF
20%
6.3V
2 X5R
603
1
C3301
0.1UF
GND
1
1
10%
16V
2 X7R-CERM
0402
OUT0
OUT1
OUT2
6
OC*
5
7
PP3V3_S0_SW_SD_PWR
8
THRM
PAD
9
2
353S3004
CRITICAL
1
C3302
1
1
10UF
2
C3303
10%
16V
2 X7R-CERM
0402
R3300
47K
0.1UF
20%
6.3V
X5R
603
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
NOSTUFF
2
=PP3V3_S0_PCH_GPIO
5%
1/16W
MF-LF
402
SYNC_MASTER=YONAS_J30
7 16 17 18 19
SD Card Connector
R33011
DRAWING NUMBER
10K
5%
1/16W
MF-LF
402 2
Apple Inc.
1
0
2
NOTICE OF PROPRIETARY PROPERTY:
SDCONN_OC_L
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5%
1/16W
MF-LF
402
7
6
5
051-9058
4
3
2
SIZE
D
REVISION
R
R3302
SDCONN_OC_L_R
8
SYNC_DATE=11/03/2011
PAGE TITLE
6.0.0
BRANCH
PAGE
33 OF 109
SHEET
30 OF 86
1
A
8
7
7
6
5
4
3
2
NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.
=PP3V3_S3_VREFMRGN
VREFDQ:LDO_DAC
OMIT
R3418
67 7
SHORT
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
DDRVREF_DAC
C3400
20%
6.3V
CERM
402-LF
1
1
2
2
D
C3401
DDRVREF_DAC
0.1UF
C3403
CRITICAL
DDRVREF_DAC
20%
10V
CERM
402
U3400
8
=I2C_VREFDACS_SCL
6 SCL
=I2C_VREFDACS_SDA
7 SDA
MSOP
9 A0
Addr=0x98(WR)/0x99(RD)
1
VREFMRGN_SODIMMA_DQ
VOUTB
2
VREFMRGN_SODIMMB_DQ
10 A1
VOUTC
4
VREFMRGN_SODIMMS_CA
VOUTD
5
VREFMRGN_MEMVREG_FBVREF
A1
VREFMRGN_DQ_SODIMMA_BUF
1
A4
V-
1
1
CRITICAL
R3401
5%
1/16W
MF-LF
PP3V3_S3_VREFMRGN_CTRL
V+
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
NONE
NONE
NONE
402
C2
16
C3402
Power aliases required by this page:
1
0.1UF
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
- =PPDDR_S3_MEMVREF
CRITICAL
DDRVREF_DAC
3
4
Addr=0x30(WR)/0x31(RD)
5
48
BOM options provided by this page:
48
IN
BI
1
VB4
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
1
2
6
P1
P2
P3
P4
P5
P6
P7
7
SCL
SDA
- Stuffs Apple margining circuit.
RESET*
THRM
PAD
17
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
2
PLACE_NEAR=R3405.2:1mm
DDRVREF_DAC
NC
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
9
10
11
12
13
14
1
R3409
200
R3402
1
100K
2
PLACE_NEAR=J2900.126:2.54mm
CRITICAL
5%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
402
DDRVREF_DAC
C3404
DDRVREF_DAC
1
A2
20%
10V
CERM
402
NC
V+
MAX4253
R3410
UCSP
2
A1
A3
15
27
C
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
133
VREFMRGN_CA_SODIMMA_BUF
1
2
PLACE_NEAR=R3409.2:1mm
1%
1/16W
MF-LF
402
A4
V-
GND
PP0V75_S3_MEM_VREFCA_A
VREFCA:LDO_DAC
U3403
B1
0.1UF
B4
8
VREFDQ:LDO - LDO outputs sent to DQ inputs.
29 31
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
VREFCA:LDO_DAC
(OD) P0
A0
A1
A2
133
1%
1/16W
MF-LF
402
PCA9557
QFN
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
VREFMRGN_DQ_SODIMMB_BUF
U3401
2
PLACE_NEAR=J3100.1:2.54mm
R3406
UCSP
C4
VCC
20%
10V
CERM
402
Signal aliases required by this page:
C3
2
VREFDQ:LDO_DAC
U3402
MAX4253
C1
DDRVREF_DAC
200
PP0V75_S3_MEM_VREFDQ_B
DDRVREF_DAC
B1
2 402
2
PLACE_NEAR=R3403.2:1mm
1%
1/16W
MF-LF
402
100K
OMIT
1
D
2
R3405
R3419
SHORT
133
1%
1/16W
MF-LF
402
DDRVREF_DAC
both at the same time!
DDRVREF_DAC
2
27 31
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
VREFDQ:LDO_DAC
a DAC output, cannot enable
3
C
R3404
UCSP
NOTE: MEMVREG and FRAMEBUF share
GND
Page Notes
V+
A3
VOUTA
PLACE_NEAR=J2900.1:2.54mm
VREFDQ:LDO_DAC
MAX4253
B4
DAC5574
IN
BI
2
PP0V75_S3_MEM_VREFDQ_A
U3402
B1
A2
20%
10V
CERM
402
200
1%
1/16W
MF-LF
402
DDRVREF_DAC
1
0.1UF
VDD
48
1
CRITICAL
DDRVREF_DAC
2.2UF
48
R3403
=PPVTT_S3_DDR_BUF
10mA max load
PP3V3_S3_VREFMRGN_DAC
2
NONE
NONE
NONE
402
-
1
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
R3411
VREFCA:LDO - LDO outputs sent to CA inputs.
1
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.
24
IN
PCA9557D_RESET_L
DDRVREF_DAC
1
RST* on ’platform reset’ so that system
watchdog will disable margining.
DDRVREF_DAC
100K
C2
V+
MAX4253
=PPDDR_S3_MEMVREF
UCSP
2
2
1
1
2
1%
1/16W
MF-LF
402
R3408
DDRVREF_DAC
100K
C3405
5%
1/16W
MF-LF
2 402
20%
10V
CERM
402
27 31
6
PP0V75_S3_MEM_VREFDQ_A
CRITICAL
DDRVREF_DAC
1
0.1UF
C2
2
V+
MAX4253
R3414
UCSP
C1
1
VREFMRGN_MEMVREG_BUF
1
1
5
SSM6N15AFE
G
MEMRESET_ISOL_LS5V_L
SOT563
DDRVREF_DAC
C3440
1K
0.1UF
1%
1/16W
MF-LF
402
2
1
R3416 1
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
V+
U3404
MAX4253
UCSP
PART NUMBER
0
A4
V2
B4
R3417
5%
1/16W
MF-LF
402
PLACE_NEAR=R3441.2:1mm
2
1%
1/16W
MF-LF
402
MEM B VREF CA
MEM VREG
A
B
C
C
D
D
1
2
3
4
5
6
VREFDQ:LDO
116S0004
2
RES,MTL FILM,0,5%,0402,SM,LF
R3409,R3411
VREFCA:LDO
REFERENCE DES
CRITICAL
BOM OPTION
RES,MTL FILM,1K,1%,0402,SM,LF
R3421,R3422,R3441,R3442
VREFDQ:M1_DAC
114S0171
2
RES,MTL FILM,332,1%,0402,SM,LF
R3404,R3406
VREFDQ:M1_DAC
DRAWING NUMBER
0.300V - 1.200V (+/- 450mV)
1.000V - 2.000V (+/- 500mV)
1.056V - 1.442V (+/- 180mV)
DAC range:
0.000V - 1.501V (0x00 - 0x74)
0.000V - 3.000V (0x00 - 0x74)
0.000V - 3.300V (0x00 - 0xFF)
VRef current:
+3.4mA - -3.4mA (- = sourced)
NOTICE OF PROPRIETARY PROPERTY:
1.51mV / step @ output
4
051-9058
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
+6.0mA - -5.0mA (- = sourced)
8.59mV / step @ output
SYNC_DATE=06/13/2011
Apple Inc.
Margined target:
-61uA (- = sourced)
SYNC_MASTER=J31_MLB
PAGE TITLE
DDR3/FRAMEBUF VREF MARGINING
1.267V (DAC: 0x8B)
5
DESCRIPTION
4
1.5V (DAC: 0x3A)
+61uA -
QTY
114S0218
0.75V (DAC: 0x3A)
6
BOM OPTION
R3403,R3405
GPU Frame Buffer (1.8V, 70% VRef)
PCA9557D Pin:
7
CRITICAL
RES,MTL FILM,0,5%,0402,SM,LF
5%
1/16W
MF-LF
402
DAC Channel:
8
REFERENCE DES
2
R3415
100K
7.69mV / step @ output
DESCRIPTION
116S0004
PART NUMBER
1
MEM A VREF CA
QTY
VREFMRGN_FRAMEBUF_BUF_R
DDRVREF_DAC
R3442
2
DAC step size:
B
67
29 31
VREFDQ:M1_M3
Nominal value
OUT
Required zero ohm resistors when no VREF margining circuit stuffed
DDRVREF_DAC
1
A1
2
VREFMRGN_MEMVREG_FBVREF_R
D
B1
A2
A3
PP0V75_S3_MEM_VREFDQ_B
MEM B VREF DQ
DDRREG_FB
DDRVREF_DAC
R3413
100K
0
1K
MEM A VREF DQ
2
1%
1/16W
MF-LF
402
CRITICAL
R3441
1
A
33.2K
VREFMRGN_FRAMEBUF_BUF
DDRVREF_DAC
3
S
4
PPCPU_MEM_VREFDQ_B
1
10%
16V
X7R-CERM
0402
PLACE_NEAR=R7320.2:1mm
VB4
PLACE_NEAR=Q3420.3:1mm
VREFDQ:M1_M3
PLACE_NEAR=Q3420.3:2mm
VREFDQ:M1_M3
C4
1%
1/16W
MF-LF
2 402
=PPDDR_S3_MEMVREF
2
9
R3422
NOTE: CPU DAC output step sizes:
DDR3 (1.5V)
7.70mV per step
DDR3L (1.35V) 6.99mV per step
Q3420
31 26
C3
1K
PLACE_NEAR=R3421.2:1mm
CRITICAL
VREFDQ:M1_M3
PLACE_NEAR=R3411.2:1mm
DDRVREF_DAC
U3404
B1
VREFDQ:M1_M3
31 7
2
1%
1/16W
MF-LF
402
V-
DDRVREF_DAC
R3421
1K
10%
16V
X7R-CERM
0402
D
SOT563
S
PPCPU_MEM_VREFDQ_A
1
B
9
1
C3420
0.1UF
SSM6N15AFE
MEMRESET_ISOL_LS5V_L
G
31 26
1
29
PLACE_NEAR=Q3420.6:1mm
VREFDQ:M1_M3
PLACE_NEAR=Q3420.6:2mm
VREFDQ:M1_M3
Q3420
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
133
VREFMRGN_CA_SODIMMB_BUF
C4
B4
CRITICAL
VREFDQ:M1_M3
PLACE_NEAR=J3100.126:2.54mm
R3412
C1
C3
2
VREFCA:LDO_DAC
U3403
B1
5%
1/16W
MF-LF
2 402
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
31 7
CRITICAL
R3407
200
1%
1/16W
MF-LF
402
6.0.0
BRANCH
PAGE
34 OF 109
SHEET
31 OF 86
1
A
8
7
6
5
4
3
2
1
PLACE_NEAR=J3501.15:2.54mm
C3531
2
1
10%
1
2 0.1UF10%
16V
X5R-CERM
0201
PCIE_AP_R2D_C_P IN
PCIE_AP_R2D_C_N IN
0.1UF
16V
X5R-CERM
0201
16 81
16 81
C3530
PLACE_NEAR=J3501.17:2.54mm
D
D
R3510
1
5%1/20W
0
PCIE_AP_D2R_P
PCIE_AP_D2R_N
2
MF 201
R3511
1
5%1/20W
R3500
6
AP_TEMP_SMB_SDA_R1
0
5%1/16W
=AP_TEMP_SMB_SDA BI
2
MF-LF402
0
OUT
16 81
OUT
16 81
3V S3 WLAN FET
MOSFET
TPCP8102
CHANNEL
P-TYPE
2
MF 201
48
20-30 MOHM @2.5V
RDS(ON)
R3501
6
AP_TEMP_SMB_SCL_R1
0
5%1/16W
2
MF-LF402
LOADING
=AP_TEMP_SMB_SCL IN
48
WIFI_EVENT_L
45 46
CRITICAL
R3502
6
WIFI_EVENT_L_R
1
5%1/16W
0
0.727 A (EDP)
2
MF-LF402
Q3550
OUT
DMP2018LFK
DFN2563-6
155S0367
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=1 mm
FERR-120-OHM-3A
PP3V3_WLAN 1
32 PP3V3_WLAN_F
2
46 6
S
4
PCIE_AP_R2D_P
D
606 MA NOMINAL MAX
81 6
PCIE_AP_R2D_N
C3522 1
C3521 1
0.1uF
0.1uF
20%
10V
CERM 2
402
CRITICAL
J3501
81 6
CRITICAL
33
85 6
20%
10V
2 X5R
805
0.1UF
1
2
R3550
P3V3WLAN_SS
4
3
PCIE_CLK100M_AP_P
IN
16 81
1
2
PCIE_CLK100M_AP_N
IN
16 81
33K
1
PP3V3_S3RS4_BT_F
NOSTUFF
BLUETOOTH
80 6
80 6
32 6
PP3V3_S3RS4_BT_F
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
C3532
0.01UF
10%
16V
2 X7R-CERM
0402
2
1
=PP3V3_S4_BT
15K
1
5%
1/20W
MF
201 2
1 Y+
2 Y-
NOSTUFF
15K
FERR-120-OHM-1.5A
0402-LF
1
=PP3V3_S3_BT
PLACE_NEAR=J3501.27:2.54mm
73 45 26 17 6
IN
2
5%
1/20W
MF
201
USB_BT_WAKEP
USB_BT_WAKEN
USB_BT_P
USB_BT_N
BI
8 80
BI
8 80
G
S 2
NOSTUFF
R3512 1R3513
15K
15K
1%
1/20W
MF
2 201
OE* 8
1
1
1%
1/20W
MF
2 201
Delay = 60 ms +/- 20%
NOSTUFF
32
SEL
C3511 1
=PP3V3_S3_WLAN
OUTPUT
1
L
H
USB_BT_WAKE
USB_BT
R3553
100K
1%
1/16W
MF-LF
2 402
1
R3554
VDD
232K
1%
1/16W
MF-LF
2 402
7 32
CRITICAL
1
U3540
P3V3WLAN_VMON
2
C3540
0.1uF
20%
10V
2 CERM
402
SLG4AP016V
TDFN
SENSE +
0.7V
518S0815
DLY
AP_RESET_CONN_L
4 RESET*
CRITICAL
AP_RESET_L
MR* 3
J3502
A
PP5V_S3_ALSCAMERA_F
=I2C_ALS_SCL
=I2C_ALS_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
IN
BI
48
AP_CLKREQ_Q_L
7 IN
1
R3555
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=J3502.6:2.54MM
7
L3507
90-OHM
SYNC_MASTER=K90I_MLB
X19/ALS/CAMERA CONNECTOR
FERR-120-OHM-1.5A
2
DLP0NS
SYM_VER-1
1
=PP5V_S3_ALSCAMERA
DRAWING NUMBER
7
Apple Inc.
0402-LF
4
3
USB_CAMERA_P
BI
18 80
1
2
USB_CAMERA_N
BI
18 80
1
8
7
6
5
051-9058
NOTICE OF PROPRIETARY PROPERTY:
20%
10V
2 CERM
402
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
R
C3552
0.1uF
PLACE_NEAR=J3502.2:2.54MM
SYNC_DATE=02/15/2011
PAGE TITLE
L3508
CAMERA
16
1%
1/16W
MF-LF
2 402
ALS
CRITICAL
GND
18 23 73
AP_CLKREQ_L
100K
275 mA peak
206 mA nominal max
48
THRM
PAD
24
IN
OUT
(OD)
5
6
8
IN
AP_PWR_EN
EN 6
OUT 8
9
819Q-3506-K281
F-RT-SM1
B
Supervisor & CLKFREG # ISolation
PP3V3_WLAN_F
6 17 24
6
46
VESM
1%
1/20W
MF
2 201
BTMUX_SEL
10%
16V
X7R-CERM 2
0402
OUT
15K
BTPWR:S4
D+ 7
D- 6
OUT
D 3SSM3K15AMFVAPE
GND
0.01UF
PCIE_WAKE_L
U3510
10 SEL
R3519
0
1
PM_SLP_S4_L
M- 4
TQFN
BTPWR:S4
7
0402-LF
M+ 5
CRITICAL
1%
1/20W
MF
2 201
FERR-120-OHM-1.5A
80 6
73
R3514
PI3USB102ZLE
15K
1%
1/20W
MF
2 201
PLACE_NEAR=J3501.27:2.54mm
2
80 6
IN
1
10%
2 6.3V
X5R
201
VCC
R3515 1R3516
7
C3510
0.1UF
0
1%
1/20W
MF
2 201
NOSTUFF
1
Q3510
NOSTUFF
R35181
R3517
L3505 BTPWR:S4
1
BTPWR:S4
=BT_WAKE_L
CRITICAL
6 32
BTPWR:S3
1
USB_BT_CONN_P
USB_BT_CONN_N
L3506 BTPWR:S3
6
5
4
3
2
1
PM_WLAN_EN_L
2
PLACE_NEAR=J3501.11:2.54mm
B
6
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
10%
16V
X5R
402-1
DLP11S
SYM_VER-1
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
10%
16V 2
X5R
402
C3550
C
10K
0.033UF
1
34
L3501
330-OHM-80MA
PCIE_AP_D2R_PI_N
85 6
10UF
R3551
C3551 1
PLACE_NEAR=Q3550.6:2.54mm
AIRPORT
9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
C3520
32
1
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
81 6
1
PLACE_NEAR=J3501.29:2.54mm
PCIE_AP_D2R_PI_P
500913-0302
F-ST-SM
32
31
20%
10V
CERM 2
402
3
81 6
516S0582
=PP3V3_S3_WLAN 7
G
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.20603
mm
C
1
2
L3504
727 MA PEAK
6.0.0
BRANCH
PAGE
35 OF 109
SHEET
32 OF 86
1
A
8
7
6
5
4
3
2
1
CRITICAL
81 8
IN
PCIE_T29_R2D_C_P<0>
C3600
1
81 8
IN
PCIE_T29_R2D_C_N<0>
C3601
OMIT_TABLE
2
10%
0.1UF
1
16V
X5R-CERM
0201
81
81
2
10%
0.1UF
16V
V19
T19
PCIE_T29_R2D_P<0>
PCIE_T29_R2D_N<0>
U3600
PER_0_P
PER_0_N
PET_0_P
PET_0_N
T29
V21
T21
81
81
C3640
PCIE_T29_D2R_C_P<0>
PCIE_T29_D2R_C_N<0>
FCBGA
X5R-CERM
0201
1
0.1UF
C3641
1
0.1UF
PCIE_T29_D2R_P<0>
2
10%
16V
2
PCIE_T29_D2R_N<0>
X5R-CERM
0201
10%
16V
2
PCIE_T29_D2R_P<1>
X5R-CERM
0201
OUT
8 81
OUT
8 81
OUT
8 81
OUT
8 81
OUT
8 81
OUT
8 81
OUT
8 81
OUT
8 81
PCIE_T29_R2D_C_P<1>
C3602
1
2
10%
0.1UF
81 8
IN
PCIE_T29_R2D_C_N<1>
C3603
1
IN
PCIE_T29_R2D_C_P<2>
C3604
10%
1
81 8
IN
PCIE_T29_R2D_C_N<2>
C3605
1
IN
PCIE_T29_R2D_C_P<3>
C3606
IN
PCIE_T29_R2D_C_N<3>
C3607
10%
1
16V
X5R-CERM
0201
16V
X5R-CERM
0201
81
81
16V
X5R-CERM
0201
16V
X5R-CERM
0201
2
10%
0.1UF
81 8
81
2
0.1UF
81 8
81
2
10%
0.1UF
D
X5R-CERM
0201
2
0.1UF
81 8
16V
1
81
81
2
10%
0.1UF
16V
P19
M19
PCIE_T29_R2D_P<1>
PCIE_T29_R2D_N<1>
K19
H19
PCIE_T29_R2D_P<2>
PCIE_T29_R2D_N<2>
F19
D19
PCIE_T29_R2D_P<3>
PCIE_T29_R2D_N<3>
PER_1_P
PER_1_N
PER_2_P
PER_2_N
PER_3_P
PER_3_N
TRANSMIT
IN
RECEIVE
81 8
PCIE GEN2
(SYM 1 OF 2)
PET_1_P
PET_1_N
P21
M21
81
81
C3642
PCIE_T29_D2R_C_P<1>
PCIE_T29_D2R_C_N<1>
C3643
PET_2_P
PET_2_N
K21
H21
81
81
C3644
PCIE_T29_D2R_C_P<2>
PCIE_T29_D2R_C_N<2>
C3645
PET_3_P
PET_3_N
F21
D21
81
81
C3646
PCIE_T29_D2R_C_P<3>
PCIE_T29_D2R_C_N<3>
6
TP_TBT_MONDC0
6
TP_TBT_MONDC1
A20
MONDC0
MONDC1
WAKE*
F1
T29_PCIE_WAKE_L
PERST*
E6
T29_RESET_L
5%
1/16W
MF-LF
2 402
1UF
3.3K
10%
6.3V
CERM 2
402
8
VCC
CRITICAL
OMIT_TABLE
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
TP_TBT_MONOBSP
K17
MONOBSP
RSENSE
E14
T29_RSENSE
1
R3622
6
TP_TBT_MONOBSN
M17
MONOBSN
C
5
D
(T29_SPI_CLK)
6
C
(T29_SPI_CS_L)
1
S_L
2
(T29_SPI_MISO)
5%
1/16W
MF-LF
2 402
OUT
R3693
3.3K
83
83
T29ROM_WP_L
3
W_L
T29ROM_HOLD_L
7
HOLD_L
83
VSS
4
X5R-CERM
0201
2
PCIE_T29_D2R_P<2>
10%
16V
2
PCIE_T29_D2R_N<2>
10%
16V
2
PCIE_T29_D2R_P<3>
X5R-CERM
0201
X5R-CERM
0201
10%
16V
2
PCIE_T29_D2R_N<3>
X5R-CERM
0201
10%
16V
X5R-CERM
0201
2
5%
1/20W
MF
D
7 33 34 35
201
35
2
E16
T29_RBIAS
PCIE_RST_0*
PCIE_RST_1*
PCIE_RST_2*
PCIE_RST_3*
K1
J2
K3
J4
Not used in host mode.
TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L
TDI
TMS
TCK
TDO
T3
R4
R2
T1
JTAG_TBT_TDI
JTAG_TBT_TMS
JTAG_TBT_TCK
JTAG_TBT_TDO
REFCLK_100_IN_P
REFCLK_100_IN_N
H17
G16
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
XTAL_25_IN
XTAL_25_OUT
P17
R16
TMU_CLK_OUT
TMU_CLK_IN
U2
E2
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
MLP
16V
1
1%
1/16W
MF-LF
402
RBIAS
35
U3690 Q
M95320-RMC6XG
10%
1K
R3621
1
(T29_SPI_MOSI)
X5R-CERM
0201
R3655
1
10K
PCIE_T29_D2R_N<1>
R36511
IN
DEBUG: For monitoring clock
83
THM
PAD
9
51
=T29_CLKREQ_L
T29_GPIO<1>
T29_GPIO<2>
T29_RSVD
P3
N4
M3
L4
PCIE_CLKREQ_0*
PCIE_CLKREQ_1*
PCIE_CLKREQ_2*
PCIE_CLKREQ_3*
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29_SPI_CLK
P1
M1
N2
L2
EE_DI
EE_DO
EE_CS*
EE_CLK
TP_T29_THERM_DP
A2
THERM_DP
E4
P5
N6
M5
L6
TEST_EN
TEST_POINT_0
TEST_POINT_1
TEST_POINT_2
TEST_POINT_3
Use B1 GND ball for THERM_DN
T29_TEST_EN
TP_T29_TEST_POINT_0
TP_T29_TEST_POINT_1
TP_T29_TEST_POINT_2
T29_TEST_POINT_3
1
R3625
0
5%
1/16W
MF-LF
2 402
JTAG
3.3K
6
POWER ON RESET
R3691
R36231
16V
2
10K
CLOCKS
5%
1/16W
MF-LF
402 2
R36921
1
10%
=PP3V3_T29_RTR
MISC
3.3K
C3690 1
1
0.1UF
C3647
0.1UF
B21
CLK REQUEST
R3690
1
1
0.1UF
TEST PORT
1
1
0.1UF
X5R-CERM
0201
EEPROM
35 34 33 7
1
0.1UF
DEBUG: For monitoring current/voltage
=PP3V3_T29_RTR
1
0.1UF
81
6
6
6
6
IN
8 19
IN
16
IN
8
OUT
8
IN
16 81
IN
16 81
=PP3V3_T29_RTR
C
7 33 34 35
1
R3698
10K
5%
1/16W
MF-LF
2 402
R3695
SYSCLK_CLK25M_T29_R
TP_T29_XTAL25OUT
1
R36961
T29_TMU_CLK_OUT
T29_TMU_CLK_IN
NO STUFF
1K
806
2
SYSCLK_CLK25M_T29
IN
24 81
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402 2
R36991
10K
0.1UF
83 8
IN
DP_T29SNK0_ML_C_P<1>
C3622
1
0.1UF
83 8
IN
DP_T29SNK0_ML_C_N<1>
C3623
1
0.1UF
B
DP_T29SNK0_ML_N<0>
2
83 33
33 83
10% 16V
X5R-CERM
0201
83 33
DP_T29SNK0_ML_P<1>
2
83 33
33 83
10% 16V
X5R-CERM
0201
83 33
DP_T29SNK0_ML_N<1>
2
33 83
10% 16V
X5R-CERM
0201
83 33
83 33
83 8
IN
DP_T29SNK0_ML_C_P<2>
C3624
1
0.1UF
83 8
IN
DP_T29SNK0_ML_C_N<2>
C3625
1
0.1UF
83 8
IN
DP_T29SNK0_ML_C_P<3>
C3626
1
0.1UF
83 8
IN
DP_T29SNK0_ML_C_N<3>
C3627
1
0.1UF
DP_T29SNK0_ML_P<2>
2
33 83
10% 16V
X5R-CERM
0201
8
DP_T29SNK0_ML_N<2>
2
33 83
10% 16V
X5R-CERM
0201
R36301
100K
DP_T29SNK0_ML_P<3>
2
DP_T29SNK0_ML_N<3>
83 33
5%
1/16W
MF-LF
402 2
33 83
10% 16V
X5R-CERM
0201
2
OUT
83 33
83 33
33 83
10% 16V
X5R-CERM
0201
83 33
83 33
83 8
BI
DP_T29SNK0_AUXCH_C_P
C3628
1
0.1UF
83 8
BI
DP_T29SNK0_AUXCH_C_N
C3629
1
0.1UF
2
DP_T29SNK0_AUXCH_P
33 83
DP_T29SNK0_AUXCH_N
33 83
83 33
10% 16V
X5R-CERM
0201
2
83 33
10% 16V
X5R-CERM
0201
83 33
83 33
SNK1 AC Coupling
2
DP_T29SNK1_ML_C_P<0> C3630 1
10% 16V
83 8
IN
83 8
IN
DP_T29SNK1_ML_C_N<0>
C3631
83 8
IN
DP_T29SNK1_ML_C_P<1>
C3632
IN
DP_T29SNK1_ML_C_N<1>
0.1UF
1
0.1UF
1
0.1UF
83 8
C3633
1
0.1UF
A
83 8
IN
DP_T29SNK1_ML_C_P<2>
C3634
1
0.1UF
83 8
IN
DP_T29SNK1_ML_C_N<2>
C3635
1
0.1UF
83 8
IN
DP_T29SNK1_ML_C_P<3>
C3636
1
0.1UF
83 8
IN
DP_T29SNK1_ML_C_N<3>
C3637
1
0.1UF
83 8
BI
DP_T29SNK1_AUXCH_C_P
C3638
BI
DP_T29SNK1_AUXCH_C_N
C3639
1
0.1UF
83 8
1
0.1UF
8
DP_T29SNK0_ML_P<2>
DP_T29SNK0_ML_N<2>
AA6
Y5
DPSNK0_ML_LANE_2P
DPSNK0_ML_LANE_2N
DP_T29SNK0_ML_P<1>
DP_T29SNK0_ML_N<1>
AA8
Y7
DPSNK0_ML_LANE_1P
DPSNK0_ML_LANE_1N
DP_T29SNK0_ML_P<0>
DP_T29SNK0_ML_N<0>
AA10
Y9
DPSNK0_ML_LANE_0P
DPSNK0_ML_LANE_0N
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
V1
W2
DPSNK0_AUX_CHP
DPSNK0_AUX_CHN
DP_T29SNK0_HPD
V5
DPSNK0_HOT_PLUG_DET
83 33
DP_T29SNK1_ML_P<0>
33 83
DP_T29SNK1_ML_N<0>
33 83
DP_T29SNK1_ML_P<1>
33 83
8
OUT
DP_T29SNK1_ML_P<3>
DP_T29SNK1_ML_N<3>
V9
U8
DPSNK1_ML_LANE_3P
DPSNK1_ML_LANE_3N
DP_T29SNK1_ML_P<2>
DP_T29SNK1_ML_N<2>
V11
U10
DPSNK1_ML_LANE_2P
DPSNK1_ML_LANE_2N
DP_T29SNK1_ML_P<1>
DP_T29SNK1_ML_N<1>
V13
U12
DPSNK1_ML_LANE_1P
DPSNK1_ML_LANE_1N
DP_T29SNK1_ML_P<0>
DP_T29SNK1_ML_N<0>
V15
U14
DPSNK1_ML_LANE_0P
DPSNK1_ML_LANE_0N
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
V7
U6
DPSNK1_AUX_CHP
DPSNK1_AUX_CHN
DP_T29SNK1_HPD
U4
DPSNK1_HOT_PLUG_DET
T29_R2D_C_P<0>
T29_R2D_C_N<0>
A6
A4
PRT0_T29T_P
PRT0_T29T_N
T29_D2R_P<0>
T29_D2R_N<0>
C4
C2
PRT0_T29R_P
PRT0_T29R_N
T29_LSEO<0>
T29_LSOE<0>
J6
K5
T29_0_LSEO
T29_0_LSOE
DPSRC0_ML_LANE_3P
DPSRC0_ML_LANE_3N
AA18
Y17
TP_DP_T29SRC_ML_CP<3>
TP_DP_T29SRC_ML_CN<3>
DPSRC0_ML_LANE_2P
DPSRC0_ML_LANE_2N
AA16
Y15
TP_DP_T29SRC_ML_CP<2>
TP_DP_T29SRC_ML_CN<2>
DPSRC0_ML_LANE_1P
DPSRC0_ML_LANE_1N
AA14
Y13
TP_DP_T29SRC_ML_CP<1>
TP_DP_T29SRC_ML_CN<1>
DPSRC0_ML_LANE_0P
DPSRC0_ML_LANE_0N
AA12
Y11
TP_DP_T29SRC_ML_CP<0>
TP_DP_T29SRC_ML_CN<0>
W16
U16
TP_DP_T29SRC_AUXCH_CP
TP_DP_T29SRC_AUXCH_CN
V3
DP_T29SRC_HPD
Y19
Y21
AA20
T29_DP_ATEST
DPSRC0_AUX_CHP
DPSRC0_AUX_CHN
DPSRC0_HOT_PLUG_DET
DP_ATEST
DP_RES_0
DP_RES_1
6
6
6
6
B
6
6
6
6
6
6
100pF SRF > 40MHz
BYPASS=U3600.Y19::2mm
BYPASS=U3600.Y19::5.08mm
C3685
T29_DP_RES
100PF
1
R3685
14.0K
1%
1/16W
MF-LF
402 2
1
R3632
100K
1
5%
50V
CERM 2
0402
1
C3686
0.01UF
10%
2 16V
X7R-CERM
0402
5%
1/16W
MF-LF
2 402
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201
2
100K
10% 16V
X5R-CERM
0201
DP_T29SNK1_ML_N<1>
2
R36311
5%
1/16W
MF-LF
402 2
DP_T29SNK1_ML_P<2>
DP_T29SNK1_ML_N<2>
DP_T29SNK1_ML_P<3>
DP_T29SNK1_ML_N<3>
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
75
OUT
75
IN
83 75
OUT
83 75
OUT
83 75
IN
IN
75
OUT
75
IN
83 48
BI
83 48
OUT
A10
A8
PRT1_T29T_P
PRT1_T29T_N
T29_D2R_P<1>
T29_D2R_N<1>
C8
C6
PRT1_T29R_P
PRT1_T29R_N
T29_LSEO<1>
T29_LSOE<1>
G6
H5
T29_1_LSEO
T29_1_LSOE
I2C_T29_SDA
I2C_T29_SCL
F3
F5
T29_SDA
T29_SCL
T29_R2D_C_P<1>
T29_R2D_C_N<1>
PRT2_T29T_P
PRT2_T29T_N
A14
A12
T29_R2D_C_P<2>
T29_R2D_C_N<2>
PRT2_T29R_P
PRT2_T29R_N
C12
C10
T29_D2R_P<2>
T29_D2R_N<2>
G4
H3
T29_LSEO<2>
T29_LSOE<2>
OUT
8
IN
8
PRT3_T29T_P
PRT3_T29T_N
A18
A16
T29_R2D_C_P<3>
T29_R2D_C_N<3>
OUT
8 83
OUT
8 83
PRT3_T29R_P
PRT3_T29R_N
C16
C14
T29_D2R_P<3>
T29_D2R_N<3>
IN
8 83
IN
8 83
G2
H1
T29_LSEO<3>
T29_LSOE<3>
T29_2_LSEO
T29_2_LSOE
OUT
8 83
OUT
8 83
IN
8 83
IN
8 83
33 83
6
5
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
T29_3_LSEO
T29_3_LSOE
OUT
8
IN
8
33 83
10% 16V
X5R-CERM
0201
7
IN
83 75
10% 16V
X5R-CERM
0201
2
83 75
33 83
10% 16V
X5R-CERM
0201
2
IN
33 83
10% 16V
X5R-CERM
0201
2
83 75
33 83
10% 16V
X5R-CERM
0201
2
OUT
33 83
10% 16V
X5R-CERM
0201
2
OUT
83 75
33 83
10% 16V
X5R-CERM
0201
2
83 75
PORT2
C3621
83 33
PORT3
DP_T29SNK0_ML_C_N<0>
83 33
X5R-CERM
0201
SOURCE PORT 0
IN
83 33
5%
1/16W
MF-LF
402 2
33 83
SINK PORT 0
83 8
1
0
DP_T29SNK0_ML_P<0>
5%
1/16W
MF-LF
402 2
DISPLAY
0.1UF
2
DPSNK0_ML_LANE_3P
DPSNK0_ML_LANE_3N
PORTS
1
AA4
Y3
PORT0
IN
SNK0 AC Coupling
C3620
10% 16V
DP_T29SNK0_ML_C_P<0>
DP_T29SNK0_ML_P<3>
DP_T29SNK0_ML_N<3>
PORT1
83 8
83 33
SINK PORT 1
R36291
NOTE: All unused LSOE/EO pairs should be aliased
together. Other signals okay to float (TP/NC).
4
3
T29 Host (1 of 2)
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
36 OF 109
SHEET
33 OF 86
1
A
8
7
6
5
4
D
3
2
OMIT_TABLE
10UF
20%
6.3V 2
X5R
603
C3701 1
10UF
20%
6.3V 2
X5R
603
1
C3705
1UF
10%
6.3V
2 CERM
402
1
C3710
1UF
10%
6.3V
2 CERM
402
1
C3706
1UF
10%
6.3V
2 CERM
402
1
C3711
1UF
10%
6.3V
2 CERM
402
1
C3707
1UF
10%
6.3V
2 CERM
402
1
C3712
1UF
10%
6.3V
2 CERM
402
1
C3720
1UF
10%
2 6.3V
CERM
402
C
1
C3708
1UF
10%
6.3V
2 CERM
402
1
C3713
1UF
10%
6.3V
2 CERM
402
1
C3721
1UF
10%
2 6.3V
CERM
402
1
C3709
1UF
10%
6.3V
2 CERM
402
1
C3714
1UF
10%
6.3V
2 CERM
402
1
C3722
H9
H11
H13
K9
K11
K13
M9
M11
M13
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
H15
K15
M15
E8
E10
E12
G14
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
R8
R10
R12
VDD1P0_DP_RX1
VDD1P0_DP_TXRX
VDD1P0_DP_TXRX
U3600
VCC3P3
VCC3P3
VCC3P3
T29
FCBGA
(SYM 2 OF 2)
VCC3P3_T29
VCC3P3_T29
VCC3P3_DP_RX1
VCC3P3_DP_RX1
VCC
C3700
1
H7
M7
K7
C3744 1
C3743 1
C3745 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
C3753 1
C3752 1
C3751 1
C3750 1
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
10%
6.3V 2
CERM
402
1UF
G10
G12
1UF
1UF
1
C3746
10UF
20%
2 6.3V
X5R
603
C3747
10UF
20%
2 6.3V
X5R
603
P7
R6
VCC3P3_DP_TXRX
VCC3P3_DP_TXRX
P9
P11
VDD3P3DP_PLL
P13
1UF
1UF
1UF
1UF
C3760 1
1UF
1UF
10%
2 6.3V
CERM
402
10%
6.3V 2
CERM
402
L3730
C
L3770
FERR-120-OHM-1.5A
1
2
PP1V05_T29_VDD_DPPLL
FERR-120-OHM-1.5A
R14
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
VCC3P3_DP_TXRXBIAS
P15
C3730
2.2UF
20%
2 6.3V
CERM
402-LF
B
VDD1P0_DP_PLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
C18
C20
D1
D3
D5
D7
D9
D11
D13
D15
D17
E18
E20
F7
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
T5
T7
T9
T11
T15
T17
V17
W4
W6
W8
W10
W12
W14
Y1
AA2
VSSDP_PLL
T13
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
F9
F11
F13
F15
F17
G18
G20
J16
J18
J20
L16
L18
L20
N16
N18
N20
R18
R20
U18
U20
W18
W20
1
PP3V3_T29_DPBIAS
C3770 1
G8
J8
J10
J12
J14
L8
L10
L12
L14
N8
N10
N12
N14
GND
0402
1
D
=PP3V3_T29_RTR 7 33 35
135 mA (Single-Port)
152 mA (Dual-Port)
EDP: 200 mA
CRITICAL
=PP1V05_T29_RTR
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA
7
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
2
0402
2.2UF
20%
6.3V 2
CERM
402-LF
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
T29 Host (2 of 2)
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
37 OF 109
SHEET
34 OF 86
1
A
5
Page Notes
Power aliases required by this page:
- =PPVIN_SW_T29BST
(8-13V Boost Input)
- =PP18V_T29_REG
(18V Boost Output)
- =PP3V3_T29_P3V3T29FET
(3.3V FET Input)
- =PP3V3_T29_FET
(3.3V FET Output)
- =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET
(1.05V FET Input)
- =PP1V05_T29_FET
(1.05V FET Output)
Q3880
SI8409DB
=PPVIN_SW_T29BST
8-13V Input
Changes required
for 2S.
T29BST:Y
D
2 3
4
L3895
T29BST:Y
T29BST:Y
C3890
C3891
10%
25V 2
X5R
805
1
10%
2 25V
X5R
402
1
10UF
T29BST:Y
0.1UF
5%
1/16W
MF-LF
402 2
R3891
T29BST_SNS1
T29BST:Y
10%
25V 2
X5R
805
VIN
<R1>
25 EN/UVLO
T29BST_EN_UVLO
1
R3881
330K
5%
1/16W
MF-LF
402 2
VESM
C3892
1
IN
TBT_A_HV_EN
1
1
4.7UF
T29BST:Y
C3887
5%
50V
2 CERM
402
S 2
T29BST:Y
1
R3892
1
73.2K
10K
1%
1/16W
MF-LF
402 2
C3893
10%
50V
2 X7R-CERM
0402
7
=PP3V3_T29_RTR
1
41.2K
=T29_RESET_L
SLG4AP016V
Open-Drain GPIO
IN
OUT
R3807
Q3888
SOT563
1 S
7
XW3895
SM
1
NC
1
C3888
22PF
5%
50V
2 CERM
0402
31
T29BST:Y
R38951
137K
1%
1/16W
MF-LF
402 2
<Ra>
T29BST_FBX
T29BST:Y
NO STUFF
1
C3889
100PF
5%
50V
2 CERM
0402
2
T29BST_VSNS
R3896
15.8K
1%
1/16W
MF-LF
402 2
<Rb>
=PP15V_T29_REG
T29BST:Y
1
T29BST:Y
C3895
1
4.7UF
C3897
4.7UF
10%
50V
2 X7R-CERM
1206
10%
50V
2 X7R-CERM
1206
T29BST:Y
T29BST:Y
C3896 1
C3898 1
4.7UF
4.7UF
10%
50V
X7R-CERM 2
1206
10%
50V
X7R-CERM 2
1206
7 8
Vout = 18.3V
Max Current = 0.8A
Freq = 300KHz
T29BST:Y
1
C3899
0.001UF
10%
50V
2 X7R-CERM
0402
Vout = 1.6V * (1 + Ra / Rb)
C
G 2
1
3 MR*
TBT_PWR_EN
TBT_CLKREQ_L
6 EN
8 OUT
RESET* 4
IN 7
(OD)
Pull-up provided by SB page.
B
T29BST:Y
3 D
THRM
PAD
T29_RESET_L
DLY = 60 ms +/- 20%
OUT
33
IN
33
=T29_CLKREQ_L
T29_CLKREQ_ISOL_L
Q3888
SSM6N37FEAPE
5%
1/20W
MF
2 201
SOT563
4 S
G 5
SMC_DELAYED_PWRGD
IN
24 45 46
MAKE_BASE=TRUE
9
5
GND
5%
1/20W
MF
2 201
330K
DLY
TBT_SW_RESET_L
R3888
330K
Max Vgs: 10V
R3887
5%
1/16W
MF-LF
402 1
T29BST:Y
1
T29BST_SHDN_DIV
T29BST:Y
2
+ SENSE
- 0.7V
10K
24
1%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
SSM6N37FEAPE
PP1V05_T29
TDFN
16
1
2
10
35
36
GND
SGND shorted to
GND inside package,
no XW necessary.
PLACE_NEAR=C3897.1:2 mm
T29BST:Y
7 33 34
1
5%
1/16W
MF-LF
2 402
U3800
R38032
IN
49.9K1
T29BST_VSNS_RC2
GND_T29BST_SGND
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
K
R3890
1
SGND
10%
2 6.3V
CERM-X5R
402
100K
VDD
10%
25V 2
X5R
402
Platform (PCIe) Reset
CRITICAL
1
0.1UF
19
QFN
D
D3895
POWERDI-123
DFLS230L
T29BST_SNS2
T29BST:Y
C3894
0.33UF
1%
1/16W
MF-LF
402 2
6 D
IN
3
CRITICAL
T29BST:Y
=PP3V3_S0_T29PWRCTL
C3800 1
24
SNS2
34 SYNC
T29BST:Y
<R2>
C
LT3957
6
FBX
R3894
5%
1/16W
MF-LF
402 2
32 SS
T29BST_SS
T29BST_VC_RC
T29BST:Y
T29BST:Y
1
0.0033UF
1%
1/16W
MF-LF
2 402
Supervisor & CLKREQ# Isolation
T29BST_RT
33 RT
U3890
A
0
SNS1
NC
R38931
47PF
10%
10V 2
X5R
805
G
30 VC
R38891
SW
T29BST:Y
T29BST:Y
D 3
T29BST_VC
CRITICAL
T29BST:Y
4
23
24
37
Q3805
SSM3K15AMFVAPE
76 75
28 INTVCC
T29BST_INTVCC
T29BST_PWREN_L
T29BST_BOOST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
10UF
1%
1/16W
MF-LF
402 2
T29BST_PWREN_DIV_L
2
PCMB063T-100MS
1
200K
T29BST:Y
1
10UH-4A-68-MOHM
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
Voltage not specified here,
add property on another page.
2
CRITICAL
T29BST:Y
PPVIN_SW_T29BST
G
C3880
1
470K
BOM options provided by this page:
T29BST:Y - Stuffs 18V boost circuitry.
7
T29BST:Y
R38801
Signal aliases required by this page:
- =T29_CLKREQ_L
- =T29_RESET_L
S
BGA
3
T29 15V Boost Regulator
-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C
1
D
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
CRITICAL
T29BST:Y
8 7
4
8
9
20
21
38
6
12
13
14
15
16
17
7
27
8
B
3.3V T29 Switch
U3810
7
TPS22924
=PP3V3_S0_P3V3T29FET
A2
B2
CSP
VIN
VOUT
=PP3V3_T29_FET
A1
B1
7
Max Current = 2A (85C)
U3810
CRITICAL
C3810 1
10%
6.3V 2
CERM
402
GND
Part
TPS22924C
C1
C2 ON
1UF
Type
Load Switch
R(on)
@ 2.5V
18.3 mOhm Typ
24 mOhm Max
R38161
0
5%
1/16W
MF-LF
402 2
TBT_PWR_EN_RC
1.05V T29 Switch
U3815
TPS22920
=PP1V05_S0_P1V05T29FET
A2
B2
C2
A
C3815
1
1UF
10%
6.3V 2
CERM
402
CSP
VIN
VOUT
CRITICAL
D2 ON
=PP1V05_T29_FET
A1
B1
C1
7
Max Current = 4A (85C)
U3815
Part
TPS22920
Type
Load Switch
R(on)
@ 1.05V
8 mOhm Typ
11.5 mOhm Max
SYNC_MASTER=K90I_MLB
T29 Power Support
DRAWING NUMBER
Apple Inc.
NO STUFF
051-9058
1UF
NOTICE OF PROPRIETARY PROPERTY:
10%
6.3V 2
CERM
402
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
6
5
4
3
2
SIZE
D
REVISION
R
C3816 1
8
SYNC_DATE=02/15/2011
PAGE TITLE
GND
D1
7
6.0.0
BRANCH
PAGE
38 OF 109
SHEET
35 OF 86
1
A
8
7
6
5
4
3
2
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
1
=PP1V2_ENET_PHY
71
???mA (1000base-T, Caesar V)
71 36 24 7
=PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV)
36
VDD for Card Reader I/O
=PP3V3R1V8_ENET_LR_OUT
CRITICAL
1
2
D
ENET_SR_LX
71
ENET_SR_VFB
71
Internal 1.2V Switching Regulator pins.
L3900
FERR-600-OHM-0.5A
CRITICAL
L3920
PP3V3_S3_ENET_PHY_XTALVDDH
FERR-600-OHM-0.5A
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
SM
C3900
PP1V2_ENET_PHY_AVDDL
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
0.1UF
10%
16V
X7R-CERM
0402
CRITICAL
C3921
2
1
2
2
1
2
CRITICAL
2
C3926
1
R3910 1
OUT
81
81
C3956
1
1
(See note)
0
2
IN
81 16
IN
82 30
10%
16V
X7R-CERM
0402
2
16
30 24
58
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
27
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
33
28
34
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
31
30
AVDDL
L3930
36
36
36
36
11
PERST*
(IPD)
12
CLKREQ*
(OD)
ENET_WAKE_R_L
3
WAKE*
(OD)
4
6
10
BCM57765_SCLK
BCM57765_MISO
BCM57765_MOSI
BCM57765_CS_L
66
64
65
63
TP_BCM57765_SPD100LED_L
TP_BCM57765_TRAFFICLED_L
81 24
2
67
SYSCLK_CLK25M_ENET
IN
C3930
10%
6.3V
X5R-CERM
603
18
NC
BCM57765_RDAC
19
38
1
1
10%
16V
X7R-CERM
0402
C3935
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
the card reader on-chip I/O.
Connect only to U3900 pin 20.
10UF
2
2
10%
6.3V
X5R
805
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
GPIO_0/CR_ACT_LED*
GPIO_1/LR_OUT
GPIO_2/MEDIA_SENSE
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
40
41
44
43
46
47
50
49
5
37 82
BI
37 82
BI
37 82
BI
37 82
BI
37 82
BI
37 82
BI
37 82
BI
37 82
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
1
2
C3970
1
C3971
4.7UF
0.1UF
10%
6.3V
X5R-CERM
603
10%
16V
X7R-CERM
0402
2
1
C3972
0.1UF
2
10%
16V
X7R-CERM
0402
NC
ENET_MEDIA_SENSE
9
OUT
24
IN
30
NOTE: "IPx" == Programmable pull-up/down
LOW_PWR
(IPD)
SMB_CLK
SMB_DATA
CR_CMD
26
SDCONN_CMD
IN
30 82
CR_CLK
21
SDCONN_CLK
OUT
30 82
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
25
SDCONN_DATA<0>
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>
SDCONN_DATA<5>
SDCONN_DATA<6>
SDCONN_DATA<7>
MS_INS*
CR_LED*/CR_BUS_PWR
CR_WP*
SR_DISABLE
59
(IPU)
(IPD)
SCLK_SPD1000LED*
SI/EEDATA
SO_LINKLED*
CS*/EECLK
SPD100LED*/SERIAL_DO
TRAFFICLED*/SERIAL_DI
(OD)
(OD)
XTALI
XTALO
RDAC
SDCONN_DETECT_L
SD_DETECT o1
24
23
22
52
53
54
55
60
TP_CE_L_MS_INS_L
ENET_CR_PWREN
OUT
BDM57765_SR_DISABLE
R3980
30
57
68
No MS (Memory Stick) Insert feature needed.
Control signal to light LED or control SD bus power.
SDCONN_WP
1K
1
2
5%
MF-LF
BI
30 82
BI
30 82
BI
30 82
BI
30 82
BI
30 82
BI
30 82
BI
30 82
IN
B
30
402
69
1/16W
30 82
BI
R3965
1.24K
ROM contains MAC address, PCIe config
info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
=PP3V3_ENET_PHY
1%
1/16W
MF-LF
2 402
6
71 36 24 7
1
BI
8
THRM_PAD
PHY Non-Volatile Memory
C
36
PP3V3R1V8_ENET_LR_OUT_REG
BCM57765B0
PCIE_REFCLK_P
PCIE_REFCLK_N
ENET_CLKREQ_L
ENET_LOW_PWR
2
SM
=PP3V3R1V8_ENET_LR_OUT
PCIE_RXD_P
PCIE_RXD_N
ENET_RESET_L
IN
1
4.7UF
C3936
VDDC
PCIE_TXD_N
PCIE_TXD_P
IN
61
35
32
36
GPHY_PLLVDDL
29
51
45
39
13
16
SR_LX
SR_VFB
15
62
14
7
56
20
17
37
48
VMAIN_PRSNT (IPD)
OUT
BCM57765_SMB_CLK
BCM57765_SMB_DATA
Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
B
VDDO
(IPx)
SD_DETECT can only be used active low due to errata.
5%
1/16W
MF-LF
402
WAKE#
81 16
0.1UF
2
0.1UF
2
2
PCIE_ENET_R2D_C_N
=ENET_WAKE_L
AVDDH
U3900
81
R3943
24
10%
16V
X7R-CERM
0402
(IPU)
IN
CRITICAL
CRITICAL
0.1UF
QFN-8X8
10%
16V
X7R-CERM
0402
10%
16V
X7R-CERM
0402
81 16
2
ENET_VMAIN_PRSNT
81
1
2
1
2
C3916
(IPD)
1
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_P
1
0.1UF
0.1UF
IN
10%
6.3V
X5R-CERM
603
Current
Limiting
Resistor
C3951
C3955
81 16
1
4.7UF
SR_VDDP
2
10%
16V
X7R-CERM
0402
C3915
1
0.1UF
SR_VDD
2
C3931
(IPU)
OUT
5%
1/16W
MF-LF
402
2
PCIE_PLLVDDL
5%
1/16W
MF-LF
402
2
81 16
10%
6.3V
X5R-CERM
603
PP1V2_ENET_PHY_GPHYPLL
1K
2
10%
16V
X7R-CERM
0402
4.7UF
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
(IPU)
1
4.7K
10%
16V
X7R-CERM
0402
2
R3941
5%
1/16W
MF-LF
402
0.1UF
R3942
0.1UF
OUT
2
C3911
10%
16V
X7R-CERM
0402
XTALVDDH
=PP3V3_S0_ENETPHY
1
4.7K
1
0.1UF
BIASVDDH
R3940 1
2
C3910
42
5%
1/16W
MF-LF
402
C3950
2
C3925
FERR-600-OHM-0.5A
4.7K
PCIE_ENET_D2R_N
1
2
SM
PP3V3_S3_ENET_PHY_AVDDH
SM
81 16
1
0.1UF
10%
16V
X7R-CERM
0402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
L3925
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
10%
16V
X7R-CERM
0402
FERR-600-OHM-0.5A
7
CRITICAL
PP1V2_ENET_PHY_PCIEPLL
C3905
L3910
C
10%
6.3V
X5R-CERM
603
FERR-600-OHM-0.5A
0.1UF
1
C3920
PP3V3_S3_ENET_PHY_BIASVDDH
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
SM
D
2
SM
4.7UF
10%
16V
X7R-CERM
0402
FERR-600-OHM-0.5A
2
1
0.1UF
L3905
1
1
1
BCM57765 supports both active-levels for WP.
SR_DISABLE must be pulled down to use
internal SR. IPD has a race condition.
C3990
0.1UF
VCC
U3990
2
AT45DB011D
10%
16V
X7R-CERM
0402
SOIC-8S1
36
BCM57765_SCLK
2
36
BCM57765_CS_L
4
CS*
5
WP*
3
RESET*
SCK
OMIT
SI
1
BCM57765_MOSI
36
SO
8
BCM57765_MISO
36
SYNC_MASTER=J31_MLB
ETHERNET PHY (CAESAR IV)
NOSTUFF
1
GND
R3990
1
DRAWING NUMBER
R3997
4.7K
4.7K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
Apple Inc.
7
051-9058
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures ENET for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: ENETM requires SI pull-down instead of SO.
8
SYNC_DATE=06/15/2011
PAGE TITLE
7
A
6
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
6.0.0
BRANCH
PAGE
39 OF 109
SHEET
36 OF 86
1
SIZE
D
A
8
7
6
5
4
3
2
1
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
D
D
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
C4000
1
0.1UF
C4002
0.1UF
10%
16V
2 X5R-CERM
0201
10%
16V
2 X5R-CERM
0201
1
C4004
0.1UF
10%
16V
2 X5R-CERM
0201
1
C4006
0.1UF
10%
16V
2 X5R-CERM
0201
OMIT_TABLE
CRITICAL
82 36
BI
ENET_MDI_P<0>
1
82 36
BI
ENET_MDI_N<0>
T4000
SM
12
85
ENETCONN_P<0>
2
11
85
ENETCONN_N<0>
3
10
ENET_CTAP0
4
9
ENET_CTAP1
CRITICAL
J4000
RJ45-M97-3
TX
F-RT-TH
TLA-6T213HF
C
9
C
10
82 36
BI
ENET_MDI_P<1>
5
8
85
ENETCONN_P<1>
82 36
BI
ENET_MDI_N<1>
6
7
85
ENETCONN_N<1>
1
2
82 36
82 36
BI
ENET_MDI_P<3>
1
BI
ENET_MDI_N<3>
2
3
RX
4
OMIT_TABLE
CRITICAL
5
T4001
SM
6
7
12
85
ENETCONN_P<3>
8
11
85
ENETCONN_N<3>
11
12
3
10
ENET_CTAP2
4
9
ENET_CTAP3
ENET_MDI_N<2>
5
8
85
ENETCONN_N<2>
ENET_MDI_P<2>
6
7
85
ENETCONN_P<2>
TX
514-0636
TLA-6T213HF
82 36
82 36
BI
BI
RX
Transformers should be
mirrored on opposite
sides of the board
R40001 R40011
75
5%
1/16W
MF-LF
402 2
B
75
5%
1/16W
MF-LF
402 2
1
R4002
75
5%
1/16W
MF-LF
2 402
1
R4003
75
CRITICAL
5%
1/16W
MF-LF
2 402
1000PF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
PART NUMBER
QTY
157S0084
2
DESCRIPTION
REFERENCE DES
CRITICAL
XFMR,ISO,HALF-PORT,1000T,12P,SMD,HF
T4000,T4001
CRITICAL
B
C4008
ENET_BOB_SMITH_CAP
1
2
10%
2KV
CERM
1206
BOM OPTION
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Ethernet Connector
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
40 OF 109
SHEET
37 OF 86
1
A
8
7
6
5
4
3
2
1
=PP3V3_FW_FWPHY
7 mA I/O
1
C4120
C4121
1
C4122
1
C4123
1
C4124
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
2
2
7 38 39 40
138 mA
2
2
1
2
L4130
120-OHM-0.3A-EMI
D
114 mA FireWire PHY
C4130
PP3V3_FW_FWPHY_VDDA
1
C4131
1UF
1UF
1UF
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
C4132
10%
6.3V
CERM
402
1
2
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
L4110
39 7
L4135
120-OHM-0.3A-EMI
=PP1V0_FW_FWPHY
1
135 mA
120-OHM-0.3A-EMI
2
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
0402-LF
1
C4110
1
1UF
2
10%
6.3V
CERM
402
2
17 mA PCIe SerDes
C4111
C4135
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
110 mA Digital Core
1
2
C4100
1
1
PP3V3_FW_FWPHY_VP25
C4136
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
0402-LF
1UF
10%
6.3V
CERM
402
2
2
0 mA VReg PWR
C4101
1
C4102
1
C4103
1
C4104
1
C4105
1
C4106
C4141
1UF
1UF
1UF
1UF
1UF
1UF
1UF
0.1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
20%
10V
CERM
402
2
D
2
0402-LF
2
2
2
2
2
1
1
2
2
C4140
1UF
10%
6.3V
CERM
402
C
C
K12
L9
L6
L5
L10
D8
D6
D5
M2
A12
L3
J1
L11
F1
G12
C1
C12
N3
N11
L1
K2
M12
H2
H12
E2
E10
B1
C13
A1
B12
PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400
C4170
1
0.1UF
VDD10
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
3
2
191
2
2
6
1%
1/16W
MF-LF
402
6
5%
50V
CERM
0402
6
6
R4162 1
6
1
470K
5%
1/16W
MF-LF
402
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
2
N13
J2
L13
D12
D1
A10
H13
K13
TP_FW643_OCR10_CTL
C4162
J12
NC
0.33UF
2
M13
J13
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
NAND_TREE
REXT
XO
XI NT-9
NT-OUT
NOTE: NT-xx notes show
NAND tree order.
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-1
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
SERIAL EEPROM
CONTROLLER
NT-7 SCL
NT-6 SDA
CHIP RESET
NT-5 PERST*
N2
M1
IN
16 81
IN
16 81
0.1UF
OUT
16 81
OUT
16 81
16V X7R-CERM 0402
PCIE_FW_D2R_P
10%
16 81
16V X7R-CERM 0402
PLACEMENT_NOTE=Place C4175 close to U4100
PLACEMENT_NOTE=Place C4176 close to U4100
6
6
=PP3V3_FW_FWPHY
7 38 39 40
6
FW643_LDO
C2
D13
E1
D2
L2
R4165 1
=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L
G2
G1
OUT
8 39
OUT
39
1
H1
F2
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
1
R4166
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
R4164
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
B
NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
1394B physical plug detect.
WITH PLUG DETECT:
- Gate CLKREQ# based on PHY power
- TP (or NC) PME#
WITHOUT PLUG DETECT:
- Alias both signals to drop = prefix
6
IN
1
39
R4163
10K
OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS
10%
6.3V
CERM-X5R
402
10%
2
IN
16V X7R-CERM 0402
PCIE_FW_D2R_N
2
1
16 81
MISCELLANEOUS
2
VREG_VSS
K6
4
1%
1/16W
MF-LF
402
R4170
FW643_TRST_L
K10
1
2.94K
G13
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
N1
NT-16 (IPD) SCIFCLK
NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
SCIF
L7
R4161 1
L8
F13
R0
TPCPS
K9
SM-3.2X2.5MM
K1
1
0.1UF
5%
1/16W
MF-LF
2 402
K8
2
24.576MHZ
B10
C4175
IN
16V X7R-CERM 0402
PCIE_FW_R2D_C_P
10%
10K
K7
Y4150
B11
TPBIAS0
TPBIAS1
TPBIAS2
K5
1
NC
NC
A2
FW643_R0
FW643_TPCPS
2
1%
1/16W
MF-LF
402
C3
K4
2
412
1
22PF
1
BI
B7
N9
N10
NT-19 (IPU) TRST*
POWER MANAGEMENT
NT-12 (IPD)
NT-13
J10
FW_CLK24P576M_XO
CRITICAL
C4151
40
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
81
M3
FIXME!!! - TYPO IN SYMBOL REGCTL
J9
2
5%
50V
CERM
0402
BI
R4150
22PF
1
BI
A4
J5
C4150
40
40 39
B4
J4
1%
1/16W
MF-LF
402
BI
H8
200K
BI
40
H10
R4160 1
B
40
81
N6
NT-21 (IPU) TCK
NT-20 (IPU) TDI
(IPU) TDO
NT-18 (IPU) TMS
(OD)
NT-10 (IPD)
H7
=PPVP_FW_PHY_CPS
A6
B2
40
BI
B6
81
N5
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
1394 PHY
H6
82 40
BI
A9
H4
82 40
B9
G8
BI
G10
BI
G7
BI
82 40
A3
G6
40
82 40
B3
81
N7
M4
TEST CONTROLLER
G4
BI
A5
F8
40
B5
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
F10
BI
A8
F7
BI
82 40
B8
F6
82 40
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
REFCLKN
REFCLKP
PCI EXPRESS PHY
F4
BI
N8
2
BGA
E9
BI
82 40
E13
E5
82 40
E12
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
10%
1
C4176
E4
IN
C4171
VREG_PWR
FW643E
DS0 (IPD) NT-2
DS1 (IPD) NT-3
DS2 (IPD) NT-4
D10
IN
40
F12
VP25
U4100
D9
40
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
A11
ATBUSB
ATBUSH
ATBUSN
D7
IN
A13
D4
40
B13
VP
5%
1/16W
MF-LF
402
L12
NC
NC
NC
VDDH
VDD33
OMIT
CRITICAL
PCIE_FW_R2D_C_N
2
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
FireWire LLC/PHY (FW643E)
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
41 OF 109
SHEET
38 OF 86
1
A
8
Page Notes
D
Power aliases required
- =PPBUS_S5_FWPWRSW
- =PPBUS_FW_FET
- =PP3V3_FW_P3V3FWFET
- =PP3V3_FW_FET
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
- =PP3V3_S0_FWPWRCTL
- =PP1V05_S0_FWPWRCTL
- =PP1V05_FW_P1V0FWFET
- =PP1V0_FW_FET_R
- =PP1V0_FW_FWPHY
7
6
5
4
3
2
1
FireWire Port Power Switch
by this page:
(FW VP FET Input)
(FW VP FET Output)
(3.3V FET Input)
(3.3V FET Output)
(PHY 3.3V Power)
CRITICAL
Q4260
CRITICAL
FDC638P_G
CRITICAL
F4260
SM
D4260
1.1A-24V
6
7
=PPBUS_S5_FWPWRSW
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
5
4
2
PPBUS_FW_FWPWRSW_F
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
=PPBUS_FW_FET
SM
PPBUS_FW_FWPWRSW_D
2
A
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MINISMDC110H24
7
K
CRS08-1.5A-30V
1
(5KPD Bias Rail)
(1.0V FET Input)
(1.0V FET Output)
(PHY 1.0V)
R4262
1
1
10K
2
2
S
5
R4263
SOT-363
1
D
0.1UF
10%
25V
X5R
402
3
2
FWPORT_PWREN_L_DIV
Q4262
1
D
10
5%
1/16W
MF-LF
402
(SYM-VER2)
BSS8402DW
G
BOM options provided by this page:
(NONE)
C4260
5%
1/16W
MF-LF
402
4
FWPORT_FASTOFF_L_DIV
Signal aliases required by this page:
- =FW_CLKREQ_L
- =FW_PME_L
R4260
300K
5%
1/16W
MF-LF
402
3
2
FWPORT_FASTOFF_L
1
470K
D
5%
1/16W
MF-LF
402
Q4262
=PP3V3_S0_FWLATEVG
2
BSS8402DW
G
2
7
=PP3V3_S0_FWPWRCTL
FWPORT_PWREN_L
SOT-363
S
(SYM-VER1)
Q4261
1
D 3
C4261
G
10%
25V
X5R
402
S 2
10%
25V
X5R
402
24
2
IN
=FW_RESET_L
1
CRITICAL
U4290
2
R4290
100K
VDD
SLG4AP016V
2
5%
1/16W
MF-LF
402
=PP1V0_FW_FWPHY
TDFN
2
FWPORT_PWR_EN
IN
1
0.1UF
1
0.1UF
VESM
1
C4290
NO STUFF
SSM3K15AMFVAPE
40
Supervisor & CLKREQ# Isolation
1
40 7
R4261
6
R4283
10K
1
C
5%
1/16W
MF-LF
402
+ SENSE
- 0.7V
2
RESET*
4
7 38
DLY
FW_RESET_R_L
3
MR*
FW_RESET_L
OUT
38
IN
38
C
DLY = 60 ms +/- 20%
16
IN
OUT
FW_PWR_EN
FW_CLKREQ_L
6
8
EN
OUT
IN
(OD)
Pull-up provided by another page.
5
GND
7
=FW_CLKREQ_L
FW_CLKREQ_PHY_L
7
MAKE_BASE=TRUE
THRM
PAD
9
39 24
=PP1V05_S0_FWPWRCTL
FireWire Port 5K Pull-Down Detect
R4275 1
All FireWire devices require 5K pull-down on TPB pair.
Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.
1K
5%
1/16W
MF-LF
402 2
3.3V FW Switch
FW_PWR_EN_L
U4201
D
330K
Q4275
SOT-563
IN
FW_PWR_EN
2
7
5%
1/16W
MF-LF
402 2
3
B2
1
B
3
Q4270
6
5
BC847CDXV6TXG
SOT563
10%
16V
X7R-CERM
0402
BC847CDXV6TXG
SOT563
4
C2
10%
6.3V
CERM
402
GND
4
2
2
Part
TPS22924C
Type
Load Switch
R(on)
18 mOhm Typ
50 mOhm Max
1.0V FW Switch
U4202
R4273 1
1K
12K
5%
1/16W
MF-LF
402 2
7
TPS22924
=PP1V05_FW_P1V0FWFET
5%
1/16W
MF-LF
402 2
CSP
A2
B2
VIN
PP1V05_FW_FET
A1
VOUT
B1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
CRITICAL
PLACE_NEAR=C4360.1:2 mm
C4202
FW_P1_TPBIAS
1
10%
6.3V
CERM
402
FireWire PHY WAKE# Support
C2
1
ON
GND
1UF
2
LSI FireWire PHY requires 1.0V.
To avoid an extra power supply,
1.05V is used with a series R
to reduce voltage.
R4202
0.549
2
1%
1/16W
MF
402
=PP1V0_FW_FET_R
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
40 38 7
=PP3V3_FW_FWPHY
1
1) 5K Pull-down Detect when FW_PWR_EN is low.
2) FW643 WAKE# (PME#) when PHY is powered.
R4276
10K
100K
FW_PME_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
Pull-up provided on another page.
CRITICAL
2
2
3
6
D
=FW_PME_L
8
FW643_WAKE_L
2
C4276
8 19
DMB53D0UV
NO STUFF
A
OUT
Q4276
5
FW_WAKE
IN
SOT-563
1
4
SYNC_MASTER=K90I_MLB
0.1UF
10%
16V
X7R-CERM
0402
FireWire Port & PHY Power
DRAWING NUMBER
G
MAKE_BASE=TRUE
Apple Inc.
Q4276
S
DMB53D0UV
NOTICE OF PROPRIETARY PROPERTY:
SOT-563
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.
6
051-9058
5
4
3
2
SIZE
D
REVISION
R
1
7
SYNC_DATE=06/23/2011
PAGE TITLE
2
CRITICAL
8
7
Dual-purpose output:
R4277 1
38 8
B
Max Output: 2A
FWDET_EMIT
R4272 1
IN
U4201 & U4202
ON
1
FW_P1_TPBIAS_R
40 38
7
B1
0.1UF
Q4270
2
FWDET_MIRROR
C4270
CRITICAL
1
1UF
SOT-563
CRITICAL
=PP3V3_FW_FET
EDP = 0.14A (85C)
A1
VOUT
CRITICAL
C4201
DMB53D0UV
1
VIN
CRITICAL
Q4275
5
FW_5KPD_DET_RC
CSP
A2
MAKE_BASE=TRUE
G
S
TPS22924
=PP3V3_FW_P3V3FWFET
FW_5KPD_DET_L
56K
5%
1/16W
MF-LF
2 402
DMB53D0UV
39 24
R4271 1
R4270
C1
CRITICAL
C1
1
6
6.0.0
BRANCH
PAGE
42 OF 109
SHEET
39 OF 86
1
A
8
Page Notes
7
6
4
FW643 TPCPS Leakage Protection
Power aliases required by this page:
- =PPVP_FW_PORT1
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS
(To PHY)
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
3
2
Unused FireWire Ports
FW643 has internal leakage path from TPCPS pin to VDD33.
FET blocks current to TPCPS until VDD33 is powered.
Configures PHY for:
- Port "1" Bilingual (1394B)
BSS8402DW
SOT-363
470K
5%
1/16W
MF-LF
402
D
=PPVP_FW_PHY_CPS
G
R4311
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE
3
From Port
38
IN
FW_P0_TPBIAS
82 38
BI
FW_P0_TPA_P
BI
FW_P0_TPA_N
82 38
BI
FW_P0_TPB_P
82 38
BI
FW_P0_TPB_N
IN
FW_P2_TPBIAS
BI
FW_P2_TPA_P
BI
FW_P2_TPA_N
BI
FW_P2_TPB_P
82 38
PPVP_FW_CPS
S
=PPVP_FW_PHY_CPS_FET
4
7
Q4300
(SYM-VER2)
40 39 38 7
Signal aliases required by this page:
- =FW_PHY_DS0
- =FW_PHY_DS1
- =FW_PHY_DS2
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
38
=PP3V3_FW_FWPHY
NC_FW0_TPBIAS
MAKE_BASE=TRUE
R4382 1
NO_TEST=TRUE
NC_FW0_TPAP
6
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPAN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW0_TPBP
1
10K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
6
MAKE_BASE=TRUE
R4380
10K
FWPHY_DS0
NO_TEST=TRUE
=FW_PHY_DS0
MAKE_BASE=TRUE
NC_FW0_TPBN
6
MAKE_BASE=TRUE
FWPHY_DS1
NO_TEST=TRUE
=FW_PHY_DS1
MAKE_BASE=TRUE
To FW643
38
38
2
BOM options provided by this page:
(NONE)
1
FireWire PHY Config Straps
Disabled per LSI instructions
(All unused port signals TP/NC)
5
D
5
CPS_EN_L_DIV
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
38
R4312
38
1
330K
38
5%
1/16W
MF-LF
402 2
BI
NC_FW2_TPBIAS
MAKE_BASE=TRUE
NC_FW2_TPAP
1
NO_TEST=TRUE
NC_FW2_TPAN
NO_TEST=TRUE
NC_FW2_TPBP
6
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW2_TPBN
38
OUT
38
OUT
38
R4381
10K
6
MAKE_BASE=TRUE
=FW_PHY_DS2
MAKE_BASE=TRUE
6
MAKE_BASE=TRUE
FW_P2_TPB_N
FWPHY_DS2
6
NO_TEST=TRUE
D
OUT
2
1%
1/16W
MF-LF
402
6
MAKE_BASE=TRUE
NO_TEST=TRUE
CPS_EN_L
6
D
40 39 38 7
Q4300
=PP3V3_FW_FWPHY
2
BSS8402DW
G
SOT-363
S
(SYM-VER1)
1
C
C
CRITICAL
Cable Power
Termination
Place close to FireWire PHY
7
L4310
=PPVP_FW_PORT1
1
39 38
IN
Note: Trace PPVP_FW_PORT1 must handle up to 5A
FERR-250-OHM
2
FW_P1_TPBIAS
SM
1
PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
C4314
0.01UF
1
C4360
2
0.33UF
2
10%
6.3V
CERM-X5R
402
10%
50V
X7R
402
(FW_PORT1_TPA_P)
(FW_PORT1_TPA_N)
"Snapback" & "Late VG" Protection
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
B
BI
FW_P1_TPA_N
PLACE_NEAR=U4350.1:2 mm
1%
1/16W
MF-LF
402 2
C4350
J4310
1
0.1UF
10%
16V
X7R-CERM
0402
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
1394B-M97
F-RT-TH
VCC
U4350
2
TPD4S1394
3
TP_FWLATEVG_VCLMP
LLP
VCLMP
MAKE_BASE=TRUE
82 38
BI
FW_P1_TPB_P
FW_PORT1_TPB_P
82 38
BI
FW_P1_TPB_N
FW_PORT1_TPB_N
39
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1
R4362
R4350
MAKE_BASE=TRUE
FWPWR_EN
1
GND
100K
5%
1/16W
MF-LF
402
56.2
1%
1/16W
MF-LF
2 402
4
FWPORT_PWR_EN
CRITICAL
R4363
56.2
OUT
1%
1/16W
MF-LF
402 2
D1+
8
D1-
7
D2+
6
D2-
5
2
NC
220PF
2
5%
25V
C0G-CERM
0402
VP
4
OUTPUT
TPB+
B
VP
SC/NC
NC
VG
TPA-
VG
TPA-
5
TPA<R>
TPA+
TPA(R)
INPUT
TPA+
10
PLACE_NEAR=J4310.5:2 mm
10%
50V
X7R
603-1
1
4.99K
1%
1/16W
MF-LF
402
TPB<R>
7
3
(FW_PORT1_TPA_P)
C4319
R4364
TPB-
TPB+
6
11
1
(FW_PORT1_TPB_P)
(FW_PORT1_TPB_N)
1
13
2
514S0605
R4319
1M
2
5%
1/16W
MF-LF
2 402
CHASSIS
GND
12
0.1uF
C4364
TPB(R)
9
(GND)
(FW_PORT1_TPA_N)
FW_PORT1_AREF
FW_PORT1_TPB_C
1
TPB-
8
(PINS 5/6 AND 7/8 ARE
SWAPPED FOR BETTER ROUTING)
2
1
(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)
2
82 38
FW_P1_TPA_P
CRITICAL
56.2
1%
1/16W
MF-LF
2 402
BI
BILINGUAL
R4361
56.2
82 38
PORT 1
=PP3V3_S0_FWLATEVG
1
R4360
39 7
AREF needs to be isolated from all
local grounds per 1394b spec
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
FireWire Connector
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
43 OF 109
SHEET
40 OF 86
1
A
8
7
6
5
4
Q4590
ODD Power Control
DFN2563-6
=PP5V_S3_ODD
6
1
100K 2
D
S
G
3
1
2
10%
16V
X7R-CERM
0402
SSM6N37FEAPE
R45971
SOT563
100K
5%
1/16W
MF-LF
402 2
2 G
S 1
516S0616
=PP3V3_S0_ODD
D 3
SATA_ODD_R2D_N
C4520 1
85 6
S 4
45 6
ODD_PWR_EN_L
OUT
SATA HDD Connector (Gen3)
41 7
SATA_ODD_D2R_C_N
C4526 1
SATA_ODD_D2R_C_P
C4525 1
2
=PP3V3_S0_HDD
2
2
0.1UF
41
7
1
NOSTUFF
1
PLACE_NEAR=L4500.1:2MM
1
R4538
20%
10V
CERM
402
SSD_OOBD2R_FTL_L
1
5%
1/16W
MF-LF
2 402
PLACE_NEAR=L4500.2:2MM
R45371
SSD_OOBR2D_L
453
6
1%
L4539 1
SSD_OOBD2R_L
R45311
SYS_LED_ANODE_R
C4531 1
4.7
SMC_SSD_OOBR2D_L
2
1/16W
IN
MF-LF 402
2
SSD_OOBD2R_FTL_L
FERR-220-OHM 0402
5%
1/16W
41
IN
46
MF-LF 402
0.001UF
10%
50V
X7R-CERM 2
0402
41 7
OUT
ADD0
Address (R/W)
L
0x96/0x97
L
H
0x98/0x99
H
L
0xB6/0xB7
H
H
0xB8/0xB9
=PP1V5_S0_RDRVR
VALUE: 4.5 DB
R45361
2
68.1
GND_VOID
80 6
GND_VOID
GND_VOID
SATA_HDD_D2R_C_P
80 6
SATA_HDD_D2R_C_N
1
0201
C4535
5.0PF
1
0201
2
2
2
SMC_SSD_OOBD2R_L
46
C4584
0.1UF
20%
10V
2 CERM
402
=PP1V5_S0_RDRVR
NO STUFF
4.7K
5%
1/16W
MF-LF
402 2
41 7
5%
1/16W
MF-LF
402 2
SATARDRVR_I2C_ADDR0
SATARDRVR_I2C_ADDR1
41
41
=PP1V5_S0_RDRVR
C4514
1
0.1UF
C4519
C4518 & C4517 Placement Note:
It is critical that these two should be near
to U1800 pin AM1 and AM3.
0.01UF
20%
10V
2 CERM
402
20%
16V
2 X7R-CERM
0402
B
PLACE_NEAR=U4510.16:2MM
PLACE_NEAR=U4510.6:2MM
C0G
C0G
SATA_HDD_D2R_RC_P
25V
80
SATA_HDD_D2R_RC_N
25V
C4516 1
0.01UF
C4515 1
0.01UF
2
GND_VOID=TRUE
85
SATA_HDD_D2R_RDRIN_P
85
C4518 1
SATA_HDD_D2R_RDROUT_P
0.01UF
10% 16VX7R-CERM
0402
2
GND_VOID=TRUE
85
SATA_HDD_D2R_RDRIN_N
85
C4517 1
SATA_HDD_D2R_RDROUT_N
0.01UF
10% 16VX7R-CERM
0402
2
GND_VOID=TRUE
SATA_HDD_D2R_P
OUT
16 80
SATA_HDD_D2R_N
OUT
16 80
SATA_HDD_R2D_C_N
IN
16 80
SATA_HDD_R2D_C_P
IN
16 80
10% 16VX7R-CERM
0402
2
10% 16VX7R-CERM
0402
PLACE_NEAR=U1800.AM3:5MM
GND_VOID=TRUE
1% 1/20W MF 201
VDD
516S0687
41.2
CRITICAL
C4534
SATA_HDD_R2D_N
U4510
2
80 6
SATA_HDD_R2D_P
C4533
15PF
R4532
0
R45331
5%
1/16W
MF-LF
2 402
41.2
PS8521A
GND_VOID=TRUE
1% 1/20W MF 201
1
2
15PF
7 44
GND_VOID=TRUE
5% 25V
0201
1
2
SATA_HDD_R2D_RC_N
NP0-CERM
GND_VOID=TRUE
5% 25V
0201
80
80
SATA_HDD_R2D_RC_P
0.01UF
C4510 1
2
85
SATA_HDD_R2D_RDROUT_N
1 A_INP
2 A_INN
SATA_HDD_R2D_RDROUT_P
4
5
PLACE_NEAR=U4510.12:5MM
GND_VOID=TRUE
TQFN
GND_VOID GND_VOID A_OUTP 15
GND_VOID GND_VOID A_OUTN 14
85
C4513 1
SATA_HDD_R2D_RDRIN_N
0.01UF
10% 16VX7R-CERM
0402
2
GND_VOID=TRUE
85
B_OUTN GND_VOID
B_OUTP GND_VOID
GND_VOID
GND_VOID
B_INN 12
B_INP 11
85
C4512 1
SATA_HDD_R2D_RDRIN_P
23 16
IN
0.01UF
SATARDRVR_EN
41
IN
SATARDRVR_I2C_ADDR0
8 B_PRE0/I2C_ADDR0
A_PRE1/SCL_CTL 19
=SATARDRVR_I2C_SCL
IN
41
IN
SATARDRVR_I2C_ADDR1
9 APRE0/I2C_ADDR1
B_PRE1/SDA_CTL 17
=SATARDRVR_I2C_SDA
BI
NP0-CERM
2 GND_VOID=TRUE
1% 1/20W MF 201
C4511 1
GND_VOID=TRUE
0.01UF
10% 16VX7R-CERM
0402
REXT 20
7 EN
PP5V_S3_IR_R
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
R2D Passive DeEmphasis
SATARDRVR_I2C_EN_L
10 I2C_EN*
VALUE: 3.0 DB
SATARDRVR_TEST
18 TEST
R4511
0
5%
1/16W
MF-LF
402
2
48
48
R4512
2
SATA/IR/SIL Connectors
1%
1/16W
MF-LF
402
DRAWING NUMBER
Apple Inc.
338S0907
CRITICAL
6
5
4
3
051-9058
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
SYNC_DATE=11/08/2011
PAGE TITLE
3.74K
21
1
10%
16V
2 X7R-CERM
0402
2
10% 16VX7R-CERM
0402
SYNC_MASTER=YONAS_J30
3
13
0.1UF
10% 16VX7R-CERM
0402
PLACE_NEAR=U4510.11:5MM
GND_VOID=TRUE
1
C4532
2
SATARDRVR_REXT
GND THRM
PAD
8
OUT
PLACE_NEAR=U1800.AM1:5MM
GND_VOID=TRUE
80
GND_VOID=TRUE
2
68.1
1
1
GND_VOID=TRUE
+/-0.1PF
R45351
80 6
6
1
0
GND_VOID=TRUE
+/-0.1PF
R45341
=PP5V_S3_IR
100K
1
5%
1/16W
MF-LF
402
GND
1% 1/20W MF 201
C4536
5.0PF
GND_VOID
R4584
C
R4586
SMC_SSD_OOBD2R_R_L
6
16
2
4
6
8
10
12
14
16
18
20
22
SC70-5
4
NOSTUFF
F-ST-SM
1
3
5
7
9
11
13
15
17
19
21
5%
1/16W
MF-LF
2 402
LMV331
4.7K
5%
1/16W
MF-LF
402 2
D2R Passive DeEmphasis
J4501
1K
R45131 R45151
R45101
6 44
R4585
U4580
41 7
4.7K
54722-0224
1
5%
1/16W
MF-LF
2 402
L
1
2
1
IR_RX_OUT
B
3
SSD_OOBD2R_R_L 1
5%
1/16W
MF-LF
402
ADDR1
46
OUT
SYS_LED_ANODE
2
3.3K 2
Internally PD ~150K
Write:0xB6 Read:0xB7
100K
PLACE_NEAR=J4501.7:10MM
PLACE_NEAR=J4501.7:10MM
A
IN
C4580
PLACE_NEAR=U4580.8:2MM
5
SSD_OOB1V0REF
SATA Redriver
C4502
0.1UF
20%
10V
CERM
402
16 80
49.9K
1%
1/16W
MF-LF
2 402
1
1
2
NOSTUFF
C4501
OUT
R4583
R4582
7
CRITICAL
2
20%
10V
X5R-CERM
1206
2 GND_VOID=TRUE
SATA_ODD_D2R_P
10% 16VX7R-CERM
0402
20%
10V
2 CERM
402
VCC+
=PP5V_S0_HDD
0603
PLACE_NEAR=J4501.9:6MM
100UF
16 80
0.1UF
FERR-70-OHM-4A
C4538
OUT
1
5%
1/16W
MF-LF
2 402
L4500
20%
10V
X5R-CERM
1206
0.01UF
2 GND_VOID=TRUE
SATA_ODD_D2R_N
10% 16VX7R-CERM
0402
1
100K
100UF
0.01UF
=PP1V5_S0_RDRVR
R4581
C4537
16 80
=PP3V3_S0_SMC
1
1
IN
Notes:
OOBD2R was OOB_TEMP, from SSD, to SMC
OOBR2D was TEMP_CTL, from SMC, to SSD
7
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
16 80
SATA OOB Comparator
SMC_ODD_DETECT
Note: Indicates disc presence.
PP5V_S0_HDD_FLT
IN
2 GND_VOID=TRUE
SATA_ODD_R2D_C_N
10% 16VX7R-CERM
0402
33K
5%
1/16W
MF-LF
402 2
5 G
6
0.01UF
2 GND_VOID=TRUE
SATA_ODD_R2D_C_P
10% 16VX7R-CERM
0402
R4590
SOT563
C
0.01UF
1
SSM6N37FEAPE
IN
C4521 1
CRITICAL
41 7
19
SATA_ODD_R2D_P
D
85 6
ODD_PWR_EN
Q4596
80 6
F-ST-SM
1
2
4
3
6
5
8
7
10
9
12
11
14
13
16
15
0.01UF
ODD_PWR_SS
5%
1/16W
MF-LF
402
D 6
Q4596
J4500
54722-0164
C4596
R4595
=PP3V3_S0_ODD
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
80 6
10%
10V
X5R-CERM 2
0402
5%
1/16W
MF-LF
402 2
ODD_PWR_EN_LS5V_L
41 7
PP5V_SW_ODD
0.068UF
100K
Note: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.
1
2
R4596
1
1
4
C4595
1
2
SATA ODD Connector
DMP2018LFK
7
D
3
CRITICAL
6.0.0
BRANCH
PAGE
45 OF 109
SHEET
41 OF 86
1
A
8
7
6
5
4
3
2
1
D
USB Port Power Switch
D
USB Port A (Front Port)
CRITICAL
CRITICAL
U4600
L4605
TPS2561DR
FERR-120-OHM-3A
SON
2
=PP5V_S3_USB
3
23
OUT
23
OUT
10
USB_EXTA_OC_L
USB_EXTB_OC_L
6
4
73
5
=USB_PWR_EN
C4690
1
2
2
C4691
10UF
20%
6.3V
X5R
603
1
FAULT1* ILIM
FAULT2*
EN1
EN2
GND
C4696
0.1UF
OUT1
OUT2
9
PP5V_S3_USB_A_ILIM
7
USB_ILIM
PP5V_S3_USB_A_F
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
0603
C4605
PP5V_S3_USB_B_ILIM
43
1
0.01UF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
20%
16V
X7R-CERM
0402
CRITICAL
2
CRITICAL
J4600
L4600
90-OHM-100MA
DLP11S
USB-3.0-J30
F-RT-TH
SYM_VER-1
R4600
1
C4695
23.2K
1%
1/16W
MF-LF
402
220UF-35MOHM
20%
10V
CERM
402
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
8
THRM
PAD
1
CRITICAL
1
IN_0
IN_1
11
7
20%
2 6.3V
POLY-TANT
CASE-B2-SM1
1
10UF
2
20%
6.3V
X5R
603
C4617
80
1
4
USB_EXTA_MUXED_N
3
10UF
20%
6.3V
X5R
603
2
80
80
2
USB_EXTA_MUXED_P
1
2
80
80
Current limit per port (R4600): 2.18A min / 2.63A max
NC
IO
NC
IO
2 5 3 4
6 VBUS
80
80
1 GND
80
C
USB_EXTA_MUXED_F_N
USB_EXTA_MUXED_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_RX_F_P
USB3_EXTA_TX_F_N
USB3_EXTA_TX_F_P
1
2
3
4
5
6
7
8
9
D4600
10
RCLAMP0582N
11
SLP1210N6
CRITICAL
C
12
13
14
SHIELD
15
16
GND_VOID=TRUE
CRITICAL
www.qdzbwx.com
VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND_DRAIN
STDA_SSTXSTDA_SSTX+
17
18
L4610
80OHM-25%-100MA
0504
L2
Mojo SMC Debug Mux
80 18
OUT
USB3_EXTA_RX_N
4
OUT
USB3_EXTA_RX_P
1
80 18
3
2
L1
7
=PP3V42_G3H_SMCUSBMUX
MOJO:YES
1
MOJO:YES
1
M-
U4650
Y+
1
Y-
2
PI3USB102ZLE
80 18
BI
80 18
BI
USB_EXTA_P
USB_EXTA_N
B
7
6
8
D+
D-
GND_VOID=TRUE
CRITICAL
TQFN
CRITICAL
MOJO:YES
OE*
L4620
SEL
SMC_DEBUGPRT_EN_L
10
3
GND
SIGNAL_MODEL=MOJO_MUX
45
SEL=0 Choose SMC
SEL=1 Choose USB
C4620
L2
0.1UF
IN
USB3_EXTA_TX_N
1
2
80 18
MOJO:NO
IN
80
USB3_EXTA_TX_C_N
4
80
USB3_EXTA_TX_C_P
1
3
C4621
10% 6.3V
X5R 201
USB3_EXTA_TX_P
0.1UF
1
2
2
L1
R4651
10% 6.3V
X5R 201
0
GND_VOID=TRUE
2
5%
1/16W
MF-LF
402
0504
GND_VOID=TRUE
80 18
1
B
80OHM-25%-100MA
IN
CRITICAL
MOJO:NO
D4610
R4652
0
1
5
M+
4
PGTSLP91-XSON-COMBO
2
5%
1/16W
MF-LF
402
3
GND
ESD3V3U4ULC-IP4292CZ10
A
NC
5
4
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
6
7
8
9
IN
OUT
2
2
46 45
46 45
5%
1/16W
MF-LF
2 402
VCC
1
0.1UF
20%
10V
CERM
402
R4650
10K
9
C4650
SYNC_MASTER=J31_MLB
SYNC_DATE=07/08/2011
PAGE TITLE
External A USB3 Connector
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
46 OF 109
SHEET
42 OF 86
1
A
8
7
6
5
4
3
2
1
D
USB Port B (Back Port)
D
CRITICAL
L4705
FERR-120-OHM-3A
42
1
PP5V_S3_USB_B_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
2
PP5V_S3_USB_B_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
0603
C4705
1
0.01UF
20%
16V
X7R-CERM
0402
CRITICAL
2
CRITICAL
J4700
L4700
90-OHM-100MA
DLP11S
USB-3.0-J30
F-RT-TH
SYM_VER-1
80 25
USB_EXTB_MUX_N
BI
4
3
80
80 25
1
USB_EXTB_MUX_P
BI
2
80
NC
IO
NC
IO
2 5 3 4
6 VBUS
80
80
80
1 GND
80
USB_EXTB_F_N
USB_EXTB_F_P
USB3_EXTB_RX_F_N
USB3_EXTB_RX_F_P
USB3_EXTB_TX_F_N
USB3_EXTB_TX_F_P
D4700
VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND_DRAIN
STDA_SSTXSTDA_SSTX+
10
11
RCLAMP0582N
C
1
2
3
4
5
6
7
8
9
SLP1210N6
CRITICAL
C
12
13
14
15
SHIELD
16
17
GND_VOID=TRUE
CRITICAL
18
L4710
80OHM-25%-100MA
0504
L2
80 18
OUT
USB3_EXTB_RX_N
4
OUT
USB3_EXTB_RX_P
1
80 18
3
2
L1
GND_VOID=TRUE
CRITICAL
B
B
L4720
80OHM-25%-100MA
0504
GND_VOID=TRUE
C4720
L2
0.1UF
80 18
IN
USB3_EXTB_TX_N
1
2
IN
USB3_EXTB_TX_C_N
4
80
USB3_EXTB_TX_C_P
1
3
C4721
10% 6.3V
X5R 201
80 18
80
USB3_EXTB_TX_P
0.1UF
1
2
2
L1
5
4
CRITICAL
2
GND_VOID=TRUE
1
10% 6.3V
X5R 201
D4710
PGTSLP91-XSON-COMBO
NC
6
7
8
9
3
GND
ESD3V3U4ULC-IP4292CZ10
NOTE: Swapped pin4 and 5, pin6 and 7 for layout.
A
SYNC_MASTER=J31_MLB
SYNC_DATE=07/08/2011
PAGE TITLE
External B USB3 Connector
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
47 OF 109
SHEET
43 OF 86
1
A
8
7
6
5
4
3
2
1
IR SUPPORT
D
41 7
D
=PP5V_S3_IR
1
C4801
0.1UF
10%
16V
X7R-CERM
0402
14
2
VCC
U4800
CY7C63803-LQXC
QFN
80 8
80 8
BI
BI
DIFFERENTIAL_PAIR=USB2_TPAD
DIFFERENTIAL_PAIR=USB2_TPAD
12 P1.0/D+
USB_IR_P
13 P1.1/DUSB_IR_N
IR_VREF_FILTER 15 P1.2/VREG
16 P1.3/SSEL
17 P1.4/SCLK
1 C4803
18 P1.5/SMOSI
1UF
10%
19 P1.6/SMISO
10V
2
X5R
402-1
8
P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6
7
6
5
4
R4800
3
2
100
IR_RX_OUT_RC
1
1
CRITICAL
OMIT
9
1
10
P/N 338S0633
IR_RX_OUT
IN
6 41
C4804
0.001UF
20
21
2
5%
1/16W
MF-LF
402
2
NC
10%
50V
X7R-CERM
0402
22
C
C
23
VSS
11
THRML
PAD
25
24
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Front Flex Support
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
48 OF 109
SHEET
44 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
U4900
LM4FSXAH5BB
81 47 16 6
BI
81 47 16 6
BI
81 47 16 6
BI
81 47 16 6
BI
81 24
IN
81 47 16 6
IN
24
IN
47 16 6
BI
47 17 6
OUT
47 17 6
IN
19
OUT
46
OUT
84 48
C
BI
84 48
BI
84 48
BI
84 48 6
BI
84 48 6
BI
84 48
BI
84 48
BI
46
BI
46
BI
84 48 6
BI
84 48 6
BI
52
OUT
52
IN
46
OUT
46
IN
46
OUT
46
OUT
54
OUT
46
OUT
46
BI
63
IN
46
IN
41 6
IN
46
IN
46
OUT
63 46 6
IN
46
IN
46
B
BI
84 48
46
73 46
IN
IN
OUT
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_4_ASF_SCL
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMC_FAN_0_CTL
SMC_FAN_0_TACH
SMC_FAN_1_CTL
SMC_FAN_1_TACH
SMC_MPM5_LED_PWR
SMC_MPM5_LED_CHG
SMC_SYS_KBDLED
SMC_T25_EN_L
SYS_TDM_ONEWIRE
SYS_ONEWIRE
HISIDE_ISENSE_OC
SMC_ODD_DETECT
B13
A13
C12
D11
H12
D12
C13
H13
G11
F13
F12
B12
(OD)
(OD)
E10
D13
M4
N2
N8
M8
L8
K8
N7
M7
N4
N3
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
NC FOR ENG PKG
NC FOR ENG PKG
(OD)
(OD)
PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1
PN2/FAN0PWM2
D10 PN3/FAN0TACH2
NC FOR STACK BRD
NC FOR STACK BRD
L11
N12
N11
M11
PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4
J4 PH2/FAN0PWM5
J2 PH3/FAN0TACH5
(OD)
CPU_PECI_R
SMC_PECI_L
46
IN
OUT
55
IN
63 46
IN
46
IN
73 26 17 8 6
IN
73 32 26 17 6
IN
73 17
IN
53 46
IN
47 46 6
IN
47 46 6
OUT
80 8
BI
80 8
BI
AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23
E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
SMC_ADC8
SMC_ADC9
SMC_ADC10
SMC_ADC11
SMC_ADC12
SMC_ADC13
SMC_ADC14
SMC_ADC15
SMC_ADC16
SMC_ADC17
SMC_ADC18
SMC_ADC19
SMC_ADC20
SMC_ADC21
SMC_ADC22
SMC_ADC23
C0C0+
C1PC5/C1+
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+
K2
K1
L2
L1
C5
D5
CPU_PROCHOT_L
IN
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN
SPI_DESCRIPTOR_OVERRIDE_LOUT
CPU_CATERR_L
IN
CPU_THRMTRIP_3V3
IN
SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5
M2
M3
L4
N1
SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT
U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7
F11
E11
F4
F3
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
SMC_SYS_LED
SMC_GFX_THROTTLE_L
SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
PF4
PF5
M9
N9
L10
K10
L9
K9
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA
H11
L13
C11
A12
G3
C4 PECI0RX
C6 PECI0TX
SMC_BIL_BUTTON_L
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN
M13
L12
M5
J12
J13
L5
NC
D8
NC
K6
NC FOR ENG PKG
63 53 46
BGA
LPC0AD0
(1 OF 2)
LPC0AD1
OMIT
LPC0AD2
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5
SMC_LID
ENET_ASF_GPIO
SMS_INT_L
SMC_BC_ACOK
G3_POWERON_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L
D4
E4
F5
N5
N6
K5
M6
L6
(OD)
PP0/IRQ116
PP1/IRQ117
PP2/IRQ118
PP3/IRQ119
PP4/IRQ120
PP5/IRQ121
PP6/IRQ122
PP7/IRQ123
PQ0/IRQ124
PQ1/IRQ125
PQ2/IRQ126
PQ3/IRQ127
PQ4/IRQ128
PQ5/IRQ129
PQ6/IRQ130
PQ7/IRQ131
USB_SMC_N
USB_SMC_P
E13 USB0DM
E12 USB0DP
46
IN
46
IN
46
IN
46
IN
46
IN
46
46
46
IN
46
IN
46
IN
46
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
NC FOR STACK BRD
IN
46
1.2V FOR ENG PKG
SPI_SMC_MISO NC FOR
SPI_SMC_MOSI NC FOR
SPI_SMC_CLK
NC FOR
SPI_SMC_CS_L NC FOR
S5_PWRGD
PM_PCH_SYS_PWROK
PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
(OD)
SMC_ADAPTER_EN
T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3
C9
B9
A9
C8
SMC_OOB1_RX_L
SMC_OOB1_TX_L
SMC_IR_RX_OUT_RC
BDV_BKL_PWM
SMC_BATLOW_L
46
IN
IN
J3
H4
H3
G4
WT5CCP1/PM3 H10
46
IN
IN
WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7
L3 U0RX
M1 U0TX
SMC_RX_L
SMC_TX_L
46
IN
NC FOR STACK BRD
IN
=PP3V3_S5_SMC
L4901
1
1
20%
10V
2 CERM
603
C4907
20%
10V
2 CERM
402
46
C4904
0.1UF
20%
10V
2 CERM
402
1
C4905
0.1UF
20%
10V
2 CERM
402
1
PP3V3_S5_SMC_VDDA
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
1
R4902
C4906
1M
0.1UF
IN
1
C4908
0.1UF
20%
10V
2 CERM
402
1
BI
C4909
0.1UF
20%
10V
2 CERM
402
46
IN
46
46
46
46
0.1UF
BGA
(2 OF 2)
SWCLK/TCK
OMIT
SWDIO/TMS
PK4/RTCCLK
SWO/TDO
WAKE*
TDI
HIB*
NC
XOSC0
XOSC1
VDDA
OSC0
OSC1
VREFA+
VREFAVBAT
SMC_RESET_L
G10 RST*
WIFI_EVENT_L (OD)
SMC_WAKE_L
NC_SMC_HIB_L
B11
N13
M12
SMC_CLK32K
NC_SMC_XOSC1
M10
SMC_EXTAL
SMC_XTAL
G12
G13
N10
K12
10 78
46
OUT
IN
42 46
OUT
42 46
OUT
46
D7
E6
E8
E9
F10
J7
J9
J10
46
46
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V
46 81
STACK BRD
OUT
46 81
STACK BRD
OUT
46 81
STACK BRD
OUT
GNDA
VDD
GND
J1
J6
PP1V2_S5_SMC_VDDC
K13
D6
C4901
20%
10V
2 CERM
402
LM4FSXAH5BB
24
46
1
U4900
5%
1/20W
MF
2 201
20%
10V
2 CERM
402
10 46 68 78
24 35 46
VDDC
C10
A10
A11
B10
A2
SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI
6 46 47
6 46 47
6 46 47
C
6 46 47
NC
D3
PP3V3_S5_AVREF_SMC
D2
D1
C3
E3
46
XW4900
SM
50
49
46
GND_SMC_AVSS
2
1
PLACE_NEAR=U4900.A1:4MM
A1
C7
D9
E5
F9
H5
H9
J5
J8
J11
1
C4920
1
0.01UF
10%
10V
2 X5R-CERM
0201
C4921
1UF
10%
10V
2 X5R
402
K11
46 81
IN
73
IN
17 23 24
OUT
42
IN
46
B
1
C4910
1UF
10%
2 25V
X5R
402
23 24 73
OUT
46
OUT
17 23
IN
20%
10V
2 CERM
402
0.1UF
IN
NC FOR ENG PKG
0.1UF
1
17
BI
C4903
1
46 32
OUT
OUT
1
64 47 46
OUT
OUT
C4902
1UF
OUT
IN
2
0402
6 73
BI
7 46
30-OHM-1.7A
STACK BRD
ALL_SYS_PWRGD
SMC_THRMTRIP
WT2CCP0/PH0 K3
WT2CCP1/PH1 K4
46
IN
NC FOR STACK BRD
SMC_DEBUGPRT_EN_L
SMC_GFX_OVERTEMP
WT0CCP0/PG4 K7
WT0CCP1/PG5 L7
IN
1
C4911
1UF
10%
2 25V
X5R
402
1
C4912
1UF
10%
2 25V
X5R
402
1
C4913
0.1UF
1
C4914
0.1UF
20%
10V
2 CERM
402
1
C4915
0.1UF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
1
C4916
0.1UF
20%
10V
2 CERM
402
1
C4917
0.1UF
20%
10V
2 CERM
402
NOSTUFF
17 24
27 29 46
17 46 73
46
OUT
46
NC FOR ENG PKG
IN
46
NC FOR ENG PKG
OUT
46
OUT
46 73
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A
NOTE:
Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
SYNC_MASTER=YONAS_J30
SYNC_DATE=12/21/2011
PAGE TITLE
SMC
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
49 OF 109
SHEET
45 OF 86
1
A
8
7
6
5
SMC Reset "Button", Supervisor & AVREF Supply
46 45 7
7
=PP3V3_S5_SMC
=PPVIN_S5_SMCVREF
C5020 1
0.47UF
V+
10%
6.3V
CERM-X5R 2
402
53 46 45
IN
C5001
0
OUT
45 47 64
C5025
1
10uF
20%
6.3V 2
X5R
603
SILK_PART=SMC_RST
1
OMIT
C
6
SMC_DCIN_VSENSE
D
Q5059
SMC_DCIN_ISENSE
SMC_ADC5
45
SMC_ADC6
SMC_PBUS_VSENSE
CRITICAL
50
SMC_HDD_ISENSE
SMC_ADC7
S
1
SMC_ADC8
VESM
SMC_PROCHOT
45
SMC_ADC9
45
SMC_ADC10
1
R5052
45
IN
50
19
SMC_OTHER_HI_ISENSE
50
OUT
SMC_PECI_L
SMC_MEM_ISENSE
49
3
0.01UF
45
10%
16V
2 X7R-CERM
0402
SMC_ADC12
45
SMC_ADC13
5%
1/10W
MF-LF
2 603
45
SMC_ADC14
45
SMC_ADC15
45
SMC_ADC16
45
SMC_ADC17
45
SMC_ADC18
45
SMC_ADC19
2
S
4
NC_SMC_ADC14
NOSTUFF
SMC_THRMTRIP
IN
45 46
NC_SMC_ADC15
R5054
NC_SMC_ADC16
46 45
MAKE_BASE=TRUE
OUT
CPU_THRMTRIP_3V3
45
CPU_PECI_R
OUT
Q5058
49
45
SMC_ADC22
SMC_ADC23
PM_THRMTRIP_B_L 1 3.3K
1
MMBT3904LP-7
NC_SMC_ADC19
DFN1006-3
MAKE_BASE=TRUE
46 45
R5058
3
SMC_AXG_ISENSE
MAKE_BASE=TRUE
NC_SMC_ADC20
PM_THRMTRIP_L
2
5%
1/16W
MF-LF
402
CRITICAL 2
MAKE_BASE=TRUE
CPU_PECI
BI
10 19 78
From/To CPU/PCH.
SMC12 SPI Support
Series resistors are no stuffed until the
topology of 2 SPI Masters are verified.
NC_SMC_ADC21
MAKE_BASE=TRUE
NC_SMC_ADC22
MAKE_BASE=TRUE
SMC_ADC23
45 46
MAKE_BASE=TRUE
45
SMC_GFX_OVERTEMP
45
SMC_GFX_THROTTLE_L
45
SMC_FAN_1_CTL
R5021 NO
NC_SMC_GFX_OVERTEMP
MAKE_BASE=TRUE
81 45
SPI_SMC_MISO
IN
NC_SMC_GFX_THROTTLE_L
NO STUFF
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL
45
SMC_FAN_1_TACH
45
ENET_ASF_GPIO
81 45
IN
SPI_SMC_MOSI
NC_ENET_ASF_GPIO
81 45
IN
SPI_SMC_CLK
45
SMC_MPM5_LED_PWR
45
SMC_MPM5_LED_CHG
45
SYS_TDM_ONEWIRE
45
SMC_OOB1_RX_L
45
SMC_OOB1_TX_L
NC_SMC_MPM5_LED_PWR
NO STUFF
MAKE_BASE=TRUE
NC_SMC_MPM5_LED_CHG
81 45
MAKE_BASE=TRUE
SPI_SMC_CS_L
IN
0
1
0
1
2
0
SPI_MLB_MOSI
R5023 NO
0
1
2
2
SPI_MLB_CS_L
PLACE_NEAR=U6100.1:1MM
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
SMC_SSD_OOBD2R_L
STUFF
SPI_MLB_CLK
PLACE_NEAR=U6100.6:1MM
5%
1/16W
MF-LF
402
R5024
NC_SYS_TDM_ONEWIRE
STUFF
SPI_MLB_MISO
PLACE_NEAR=U6100.2:1MM
PLACE_NEAR=U6100.5:1MM
5%
1/16W
MF-LF
402
1
2
5%
1/16W
MF-LF
402
R5022
NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE
Note:
ADC10 and ADC11 are shared
with comparators on Stack Board.
2
10 19 78
IN
MAKE_BASE=TRUE
SMC Crystal Circuit
43
5%
1/16W
MF-LF
402
To SMC.
NC_SCM_ADC17
MAKE_BASE=TRUE
SMC USB Clock require these crystal
values:5,6,8,10,12,16,18,20,24,25 MHz
1
MAKE_BASE=TRUE
SMC_ADC21
5%
1/16W
MF-LF
2 402
G 5
MAKE_BASE=TRUE
SMC_ADC20
330
5%
1/16W
MF-LF
402
CRITICAL
49
MAKE_BASE=TRUE
45
SILK_PART=PWR_BTN
PLACE_SIDE=TOP
SMC_AXG_VSENSE
R5051
1.6K
SOT563
NC_SMC_ADC13
D
1
R5053
SSM6N15AFE
MAKE_BASE=TRUE
S 2
1
Q5059
49
MAKE_BASE=TRUE
45
45 46 53
SMC_CPUVCCIO_ISENSE
MAKE_BASE=TRUE
45
45 49 50
0
SMC_ADC11
D
G
SMC_PECI_L_R
2
5%
1/16W
MF-LF
402
From SMC.
PM_THRMTRIP_L_R
0
1
MAKE_BASE=TRUE
C5026
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=0V
IN
45
50
SMC_CPU_HI_ISENSE
D 3
SSM3K15AMFVAPE
G 2
49
SMC_BMON_ISENSE
Q5050
SOT563
50
7 46
CRITICAL
SSM6N15AFE
50
MAKE_BASE=TRUE
MAKE_BASE=TRUE
R5015
SILK_PART=PWR_BTN
PLACE_SIDE=BOTTOM
=PPVCCIO_S0_SMC
NC_SMC_ADC2
MAKE_BASE=TRUE
45
45
45
1
0
5%
1/10W
MF-LF
603 2
CPU_PROCHOT_L
BI
MAKE_BASE=TRUE
Debug Power "Buttons"
R50161
SMC_ADC4
MAKE_BASE=TRUE
1
SMC12 PECI Support
78 68 45 10
49
MAKE_BASE=TRUE
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.
OUT
SMC_ADC3
45
PAD
10%
16V
X7R-CERM 2
0402
SMC_ONOFF_L
OMIT
45
45
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
8
THRM
0.01UF
5%
1/10W
MF-LF
2 603
SMC_RESET_L
PP3V3_S5_AVREF_SMC
GND
1
SMC_ADC2
2
49
SMC_CPU_ISENSE
MAKE_BASE=TRUE
RESET* 5
CRITICAL REFOUT
2
R5001
45
SMC_CPU_VSENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
(IPU)
4 DELAY
SMC_MANUAL_RST_L
OMIT
1
DFN
(IPU)
SN0903048
SMC_ADC1
3
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2 402
U5010
6 MR1*
7 MR2*
SMC_ADC0
100K
VREF-3.3V-VDET-3.0V
SMC_TPAD_RST_L
SMC_ONOFF_L
IN
R5000
VIN
9
D
53
1
3
1
Desktops: 5V
Mobiles: 3.42V
45
45
4
OUT
47 56 81
OUT
47 56 81
OUT
47 56 81
OUT
47 56 81
C
41
MAKE_BASE=TRUE
R5010
45
SMC_XTAL
2.49K2
64 50
SMC_XTAL_R
1
1%
1/20W
MF
201
Y5010
3.2X2.5MM-SM
SMC_EXTAL
1
NC
1
3
2
4
NC
CRITICAL
C5010
1
12PF
C5011
12PF
5%
50V
2 C0G-CERM
0402
Note:
Pull-up for SMC_PME_S4_DARK_L
are in page33 (R3315).
B
45 46 63
MAKE_BASE=TRUE
45
SMBUS_SMC_4_ASF_SCL
45
SMBUS_SMC_4_ASF_SDA
Notes:
OOBD2R was OOB_TEMP, from SSD, to SMC
OOBR2D was TEMP_CTL, from SMC, to SSD
41
SMC_BC_ACOK
HISIDE_ISENSE_OC
NC_SMBUS_SMC_4_ASF_SCL
53 46 45
MAKE_BASE=TRUE
NC_SMBUS_SMC_4_ASF_SDA
45
BDV_BKL_PWM
NC_BDV_BKL_PWM
SMC_PME_S4_DARK_L
SDCONN_STATE_CHANGE_SMC
63 53 45
47 45 6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_SCI_L
47 45 6
24 30
PP1V2_S5_SMC_VDDC
45
SMC_WAKE_SCI_L
45 42
45
MAKE_BASE=TRUE
45 42
1
45
SMC_T25_EN_L
NC_SMC_T25_EN_L
45
SMC_IR_RX_OUT_RC
NC_SMC_IR_RX_OUT_RC
MAKE_BASE=TRUE
R5012
22
2
PLACE_NEAR=U1800.N14:5MM
R5099
47 45 6
0
47 45 6
5%
1/16W
MF-LF
2 402
MAKE_BASE=TRUE
PM_CLK32K_SUSCLK_R 1
IN
45
SCM12 Eng Pkg Support
MAKE_BASE=TRUE
SMC_ADC23
46 45
17
47 45 6
47 45 6
63 45 6
SMC_PACKAGE:ENG
SMC_CLK32K
5%
1/20W
OUT
MF 201
45
46 7
63 46 45
=PPVCCIO_S0_SMC
45
45 29 27
1
R5097
46 45
100K
S4 HPD SMC Wake Source
1%
1/16W
MF-LF
2 402
System (Sleep) LED Circuit
45
7
SMC_VCCIO_CPU_DIV2
47
SMC_ONOFF_L
G3_POWERON_L
SMC_LID
SMC_TX_L
SMC_RX_L
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
MEM_EVENT_L
CPU_THRMTRIP_3V3
7 46
1
R5020
R5030
20
5%
1/20W
MF
2 201
5
4
32
=PSOC_WAKE_L
D
B
E
IN
=BT_WAKE_L
SMC_DELAYED_PWRGD
73 45
R5082
R5040
100K
5%
1/20W
MF
201 2
Q2
Q1
73 45
OUT
S
G
C
1
2
3
IN
SMC_BATLOW_L
CRITICAL
SMC_S4_WAKESRC_EN
R5090
2
1
2
201
201
201
201
201
201
201
201
201
201
201
201
201
201
5%
5%
1/20W
1/20W
MF
MF
201
201
5%
1/20W
MF
201
5%
1/20W
MF
100K
100K
1
201
5%
1/20W
MF
201
5%
1/20W
MF
201
B
2
1
2
PP3V3_WLAN
SMC_SYS_LED
6
R5089
10K
1
2
SYS_LED_ANODE
5
OUT
5%
1/16W
MF-LF
402
41
4
MF
201
SYNC_DATE=01/02/2012
PAGE TITLE
VESM
0
1/20W
SYNC_MASTER=YONAS_J30
Q5040
1
IN
WIFI_EVENT_L
SMC Support
SSM3K15AMFVAPE
DRAWING NUMBER
PM_BATLOW_L
Apple Inc.
OUT
17
Internal 20K pull-up on
PM_BATLOW_L in PCH.
R5041
45
45
7
=PP3V3_SUS_SMC 7
1
SYS_LED_L
1
MAKE_BASE=TRUE
8
1
10K
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
5%
Q5030
DMB54D0UV
S 2
SMC_PME_S4_WAKE_L
=PP3V3_S5_SMCBATLOW
SOT-563
7 46
5%
1/20W
MF
2 201
IN
45 35 24
R5086
R5085
R5091
CRITICAL
G 1
1%
1/20W
MF
201 2
6
100K
53
SMC_ADAPTER_EN
45 32
1.47K
S
G
SMC_THRMTRIP
73 45 17
2
NOSTUFF
3
051-9058
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
2
1
DP_A_EXT_HPD
7
R50321
D 3
=PP3V3_S4_SMC
IN
10K
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
45
D
OUT
VESM
75
2
2
32 6
SSM3K15AMFVAPE
A
BATLOW# Isolation
3
Q5020
1
1
SYS_LED_L_VDIV
SMC_DP_HPD_L
CRITICAL
46 45
1%
1/16W
MF-LF
2 402
SYS_LED_ILIM
10K
100K
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/20W
MF
2 201
1%
1/16W
MF-LF
2 402
1
100K
2
2
2
2
2
2
2
2
2
2
2
2
2
2
R5088
R5096
1%
1/20W
MF
201 2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
100K
=PP3V3_S4_SMC
10K
10K
100K
10K
100K
10K
100K
10K
10K
10K
10K
10K
470K
100K
SMC_ROMBOOT
1
523
R5070
R5072
R5071
R5073
R5074
R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087
R5092
R5014
R5017
1K
=PP5V_S3_SYSLED
R50311
=PP3V3_S5_SMC
46 45 7
NC_HISIDE_ISENSE_OC
MAKE_BASE=TRUE
45
19
5%
50V
2 C0G-CERM
0402
=CHGR_ACOK
45
12.000MHZ-30PPM-10PF
45
SMC_SSD_OOBR2D_L
MAKE_BASE=TRUE
6.0.0
BRANCH
PAGE
50 OF 109
SHEET
46 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
7
7
81 45 16 6
81 45 16 6
BI
47 6
IN
OUT
OUT
46 45 6
OUT
46 45 6
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
IN
45 17 6
24 6
LPC_AD<0>
LPC_AD<1>
BI
47 6
81 45 16 6
IN
OUT
46 45 6
31
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
IN
C
32
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
33
34
IN
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
LPCPLUS_GPIO
6 24 81
BI
6 16 45 81
BI
6 16 45 81
OUT
6 19 56
IN
6 47
IN
6 47
6 16 45
BI
IN
6 17 45
OUT
6 45 46
OUT
6 45 46
OUT
45 46 64
OUT
46
OUT
6 45 46
OUT
6 19
C
516S0573
SPI Bus Series Termination
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS_R:YES
1
2
PLACE_NEAR=U1800.AV3:5mm
81 16
IN
B
81 16
IN
PLACE_NEAR=U1800.AY1:5mm
81 16
IN
R5111
SPI_MOSI_R
1
15
2
2
OUT
81
47
47
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
2
1
1
81
SPI_MOSI
1
R5123
1
15
5%
1/16W
MF-LF
402
47
5%
1/16W
MF-LF
402
SPI_MLB_CS_L
OUT
46 56 81
OUT
46 56 81
SPI_MLB_MOSI
OUT
46 56 81
SPI_MLB_MISO
IN
46 56 81
PLACE_NEAR=R5125.2:5mm
B
SPI_MLB_CLK
2
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
47
SPI_CLK
R5122
SPI_MISO
PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm
PLACE_NEAR=J5100.11:5mm
47
SPI_CS0_L
R5121
81
2
R5125
47
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
81 16
R5126
6 47
LPCPLUS_R:YES
1
0
5%
1/16W
MF-LF
402
15
1
R5112
R5127
6 47
R5120
15
1
SPI_CLK_R
R5128
LPCPLUS_R:YES
1
R5110
SPI_CS0_R_L
PLACE_NEAR=U1800.BA2:5mm
LPCPLUS_R:YES
1
6 47
6 47
PLACE_NEAR=R5126.2:5mm
2
PLACE_NEAR=R5127.2:5mm
2
PLACE_NEAR=U6100.2:5mm
A
SYNC_MASTER=J31_MLB
SYNC_DATE=06/15/2011
PAGE TITLE
LPC+SPI Debug Connector
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
51 OF 109
SHEET
47 OF 86
1
A
8
7
6
5
PCH SMBus "0" Connections
48 7
81 16
1
1K
5%
1/16W
MF-LF
402
U1800
(MASTER)
D
7
R5200 1
R5201
SO-DIMM "A"
1K
2
2
SMBUS_PCH_CLK
U4900
(MASTER)
=I2C_SODIMMA_SCL
27
84 45
=I2C_SODIMMA_SDA
27
84 45
7
R5250 1
1
R5251
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
MAKE_BASE=TRUE
=PP3V42_G3H_SMBUS_SMC_BSA
R5280 1
SMC
U4900
(MASTER)
SMBUS_SMC_0_S0_SCL
84 45 6
SMBUS_SMC_5_G3_SCL
84 45 6
SMBUS_SMC_5_G3_SDA
=I2C_VREFDACS_SCL
=I2C_SODIMMB_SCL
29
=I2C_VREFDACS_SDA
=I2C_SODIMMB_SDA
29
Margin Control
2
ISL6258 - U7000
(Write: 0x12 Read: 0x13)
=SMBUS_CHGR_SCL
64
=SMBUS_CHGR_SDA
64
=I2C_PCA9557D_SCL
=I2C_BKL_1_SCL
77
=AP_TEMP_SMB_SCL
32
=I2C_PCA9557D_SDA
=I2C_BKL_1_SDA
77
=AP_TEMP_SMB_SDA
32
7
=PP3V3_S3_SMBUS_SMC_MGMT
R5290 1
SMC "2" SMBus Connections
58 62
84 45
SMBUS_SMC_3_SCL
84 45
SMBUS_SMC_3_SDA
1
R5291
4.7K
4.7K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
Mikey
U6880
(Write: 0x72 Read: 0x73)
NO STUFF
NO STUFF
SMC
=I2C_MIKEY_SDA
63
(Write: 0x90 Read: 0x91)
31
J2500 & J2550
(MASTER)
63
=SMBUS_BATT_SDA
SMC "3" SMBus Connections
(WRITE: 0x58 READ: 0x59)
=I2C_MIKEY_SCL
=SMBUS_BATT_SCL
X19
U9701
XDP Connectors
D
J6955
(See Table)
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)
31
=SMBUS_XDP_SDA
2
Battery Charger
Battery
LED BACKLIGHT
U3401
(Write: 0x30 Read: 0x31)
23
5%
1/16W
MF-LF
402
Battery
31
=SMBUS_XDP_SCL
2.0K
SO-DIMM "B"
31
23
R5281
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
J3100
(Write: 0xA4 Read: 0xA5)
U3400
(Write: 0x98 Read: 0x99)
C
1
2.0K
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
VRef DACs
1
SMC "5" SMBus Connections
MAKE_BASE=TRUE
SMBUS_PCH_DATA
2
=PP3V3_S0_SMBUS_SMC_0_S0
SMC
J2900
(Write: 0xA0 Read: 0xA1)
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
81 16
3
SMC "0" SMBus Connections
=PP3V3_S0_SMBUS_PCH
Cougar-Point
4
5%
1/16W
MF-LF
2 402
C
NOTE: SMC RMT bus remains powered and may be active in S3 state
58 62
7
SATA_Redriver
=PP3V3_S3_SMBUS_SMC_A_S3
R5270 1
SMC
U4510
(Write: 0xB6 Read: 0xB7)
=SATARDRVR_I2C_SCL
41
=SATARDRVR_I2C_SDA
41
R5271
Trackpad
1K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
84 45 6
1
1K
5%
1/16W
MF-LF
2 402
J5800
(Write: 0x90 Read: 0x91)
SMBUS_SMC_2_S3_SCL
=I2C_TPAD_SCL
54
=I2C_TPAD_SDA
54
MAKE_BASE=TRUE
84 45 6
SMBUS_SMC_2_S3_SDA
T29 I2C Connections
MAKE_BASE=TRUE
ALS
7
J3502
(Write: 0x72 Read: 0x73)
=I2C_ALS_SCL
32
=I2C_ALS_SDA
32
=PP3V3_S0_T29I2C
R5230 1
4.7K
T29 IC
5%
1/16W
MF-LF
402
U3600
(MASTER)
B
Digital SMS
PCH "SMLink 0" Connections
48 7
R5210
U1800
(MASTER)
81 16
1
1
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
83 33
2
5%
1/16W
MF-LF
402
2
T29 Plug uC
U9330
(Write: 0x26 Read: 0x27)
I2C_T29_SCL
=I2C_T29AMCU_SDA
75
=I2C_T29AMCU_SCL
75
B
MAKE_BASE=TRUE
=I2C_SMC_SMS_SCL
55
=I2C_SMC_SMS_SDA
55
SDRVI2C:MCU
SDRVI2C:MCU
R52341
1
R5235
0
0
5%
1/20W
MF
201 2
For Compliance Testing
SDRVI2C:SB
0 1
2
SML_PCH_0_CLK
R5236
MAKE_BASE=TRUE
81 16
4.7K
I2C_T29_SDA
R5211
8.2K
Microcontroller abstracts
actual CDR(s) in plug.
R5231
MAKE_BASE=TRUE
LIS331DLH: U5920
(Write: 0x30 Read: 0x31)
=PP3V3_S0_SMBUS_PCH
Cougar-Point
83 33
1
SML_PCH_0_DATA
5%
MF
MAKE_BASE=TRUE
SMC "1" SMBus Connections
R5237
DP Re-driver
I2C_DPSDRVA_SCL
MAKE_BASE=TRUE
U9310
(Write: 0x94 Read: 0x95)
SDRVI2C:SB
0 1
2
5%
MF
7
1/20W
201
5%
1/20W
MF
2 201
I2C_DPSDRVA_SDA
1/20W
201
MAKE_BASE=TRUE
=PP3V3_S0_SMBUS_SMC_B_S0
=I2C_DPSDRVA_SCL
75
=I2C_DPSDRVA_SDA
75
PCH "SMLink 1" Connections
R5260 1
SMC
U4900
(MASTER)
Cougar-Point
84 45
1
R5261
4.7K
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
CPU Temp
EMC1414: U5511
(Write: 0x98 Read: 0x99)
SMBUS_SMC_1_S0_SCL
=I2C_CPUTHMSNS_SCL
51
=I2C_CPUTHMSNS_SDA
51
MAKE_BASE=TRUE
A
U1800
(Write: 0x88 Read: 0x89)
84 45
SMBUS_SMC_1_S0_SDA
MAKE_BASE=TRUE
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
81 16
SML_PCH_1_CLK
81 16
SML_PCH_1_DATA
SMBus Connections
DRAWING NUMBER
Apple Inc.
051-9058
R
SMLink 1 is slave port to
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
access PCH & CPU via PECI.
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
52 OF 109
SHEET
48 OF 86
1
A
8
7
6
5
4
3
2
1
CPU VCCIO 1.05V Load Side Current Sense (IC1C)
Gain: 100x, EDP: 20.1 A
Rsense: 0.001 (R7640)
V across Rsense: 20.1 mV
Gain needed: 164.2x
7
CPU Core Load Side Current Sense (IC0C)
1
0.1uF
3
D
U5360
85 70
IN
CPUVCCIOS0_CS_N
IN
CPUVCCIOS0_CS_P
5 IN-
C5360
20%
10V
2 CERM
402
V+
85 70
Gain: 161.5x, EDP: 53 A
Rsense: 2x of 0.00075 (R7510, R7520), Rsum: 0.000375
V across Rsense: 19.8 mV
Gain needed: 166.1x
=PP3V3_S0_ISNS
SC70
OUT
PLACE_NEAR=R7640.3:5MM
4 IN+
D
LOADISNS:YES
INA214
R5369
CPUVCCIO_IOUT
6
SMC_CPUVCCIO_ISENSE
1%
1/16W
MF-LF
402
REF 1
PLACE_NEAR=R7640.4:5MM
OUT
46
85 69 68
IN
C5369
2
85 69 68
IN
LOADISNS:YES
CRITICAL
IN
DDR 1.5V S3 (Memory) Current Sense (IM0C)
PLACE_NEAR=R7510.3:5MM
LOADISNS:YES
85 69
1
R5371
3 ISNS_1V5_S3_DDR_P
1
0.001
1%
1W
MF-1
0612
C
7
OUT
2.74K 2
ISNS_1V5_S3_DDR_R_P
1%
1/16W
MF-LF
402
85
3
+IN
V+
-IN
V-
R5372
2 4
=PP1V5_S3_DDR_ISNS
1
ISNS_1V5_S3_DDR_N
1
2.74K
2
4 ISNS_1V5_S3_DDR_IOUT 1
2
SMC_MEM_ISENSE
1
OUT
1M
1M
1
2
=PP5V_S0_ISNS
45 46 49 50
1%
1W
MF-1
0612
7
OUT
=PP5V_S0_HDD_ISNS
1
ISNS_5V_S0_HDD_R_P
1%
1/20W
MF
201
85
3
+IN
-IN
R5382
2 4
ISNS_5V_S0_HDD_N
B
1K
1
2
1%
1/20W
MF
201
R5344
GND_SMC_AVSS
45 46 49 50
LOADISNS:YES
SIGNAL_MODEL=EMPTY
0.1%
1/16W
MF
402
715K
IN
1%
1/16W
MF-LF
402
V-
85 69
SMC_HDD_ISENSE
1M
OUT
IN
CPUIMVP_ISNS2G_P
C5389
20%
6.3V
X5R
402
85 69
IN
CPUIMVP_ISNS1G_N
R5384
1M
1
LOADISNS:YES
85 69
IN
CPUIMVP_ISNS2G_N
CPUIMVP_ISUMG_R_P
V+
VTHRM
1.54K2 85 CPUIMVP_ISUMG_R_N
4
9
1
OPA2333
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
SMC_AXG_ISENSE
1
OUT
46
C5359
0.22UF
20%
2 6.3V
X5R
402
B
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
LOADISNS:YES
4.42K2
R5359
DFN
7 CPUIMVP_ISUMG_IOUT 14.53K2
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R5351
1
0.1%
1/16W
MF
0402
LOADISNS:YES
5
6
1
PLACE_NEAR=R7560.4:5MM
1%
1/16W
MF-LF
402
CPUIMVP_ISNSG_N
R5358
45 46 49 50
8
85
R5353
85
0.1%
1/16W
MF
0402
PLACE_NEAR=R7550.4:5MM
GND_SMC_AVSS
2
4.42K2
1
1.54K2
1
1%
1/16W
MF-LF
402
R5357
0.22UF
U5340
R5352
CPUIMVP_ISNSG_P
85
0.1%
1/16W
MF
0402
PLACE_NEAR=U4900.B4:5MM
1%
1/16W
MF-LF
2 402
4.42K2
LOADISNS:YES
1
CRITICAL
LOADISNS:YES
1
PLACE_NEAR=R7560.3:5MM
46
=PP3V3_S0_IMVPISNS
LOADISNS:YES
0.1%
1/16W
MF
0402
PLACE_NEAR=R7550.3:5MM
2
R5383
49 7
4.42K2
1
LOADISNS:YES
PLACE_NEAR=U4900.B4:5MM
1
CPUIMVP_ISNS1G_P
R5356
4 ISNS_5V_S0_HDD_IOUT1 4.53K 2
ISNS_5V_S0_HDD_R_N
85 69
R5389
SC70-5
V+
2
85
1
R5355
C5380
0.1UF
OPA330
5
85
715K 2
1
AXG Core Load Side Current Sense (IN0C)
20%
10V
2 CERM
402
U5380
R5381
2
PLACE_NEAR=U4900.E1:5MM
R5341
C
PLACE_NEAR=U5380.5:3MM
CRITICAL
1K
LOADISNS:YES
LOADISNS:YES
Gain: 190.6x, EDP: 46 A
Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375
V across Rsense: 17.25 mV
Gain needed: 191.3x
=PP5V_S0_HDD_ISNS_R
1
0.22UF
20%
2 6.3V
X5R
402
20%
6.3V
X5R
402
GND_SMC_AVSS
1
3 ISNS_5V_S0_HDD_P
PLACE_NEAR=U4900.E1:5MM
46
PLACE_NEAR=U4900.B6:5MM
R5374
7
0.001
LOADISNS:YES
OUT
C5349
C5379
HDD Current Sense (IHDC)
R5380 1
9
0.1%
1/16W
MF
0402
1
46
1%
1/16W
MF-LF
402
IN
1%
1/16W
MF-LF
402
4
0.22UF
R5373
1%
1/16W
MF-LF
2 402
7
4.53K2 SMC_CPU_ISENSE
LOADISNS:YES
1
Gain: 1000x, EDP: 2.5 A (12.5 W)
Rsense: 0.001 (R5380)
V across Rsense: 2.5 mV
Gain needed: 1320x
R5349
CPUIMVP_ISUM_IOUT 1
SIGNAL_MODEL=EMPTY
4.53K
2
1%
1/16W
MF-LF
402
2.21K2 85 CPUIMVP_ISUM_R_N
0.1%
1/16W
MF
2 402
1%
1/16W
MF-LF
402
PLACE_NEAR=U4900.B6:5MM
ISNS_1V5_S3_DDR_R_N
0.1UF
R5379
SC70-5
2
85
OPA2333
DFN
1
C5340
V-
1
20%
10V
2 CERM
402
OPA330
5
85
C5370
V+
THRM
0.1%
1/16W
MF
0402
LOADISNS:YES
3
2
0.1UF
U5370
=PP1V5_S3_DDR_ISNS_R
R5370 1
IN
PLACE_NEAR=U5370.5:3MM
CRITICAL
IN
CPUIMVP_ISNS_N
CPUIMVP_ISNS2_N 14.42K2
PLACE_NEAR=R7520.4:5MM
=PP3V3_S3_ISNS
CPUIMVP_ISUM_R_P
R5343
85
0.1%
1/16W
MF
0402
R5348
7
7
CPUIMVP_ISNS1_N 14.42K2
8
85
0.1%
1/16W
MF
0402
R5347
45 46 49 50
2.21K2
1
1
20%
10V
2 CERM
402
U5340
R5342
CPUIMVP_ISNS_P
85
0.1%
1/16W
MF
0402
LOADISNS:YES
85 69
Gain: 364.9x, EDP: 9 A
Rsense: 0.001 (R5370)
V across Rsense: 9 mV
Gain needed: 366.6x
4.42K2
1
PLACE_NEAR=R7520.3:5MM
PLACE_NEAR=U4900.A6:5MM
GND_SMC_AVSS
CPUIMVP_ISNS2_P
PLACE_NEAR=U5340.8:3MM
CRITICAL
LOADISNS:YES
R5346
20%
2 6.3V
X5R
402
LOADISNS:YES
=PP3V3_S0_IMVPISNS
LOADISNS:YES
0.1%
1/16W
MF
0402
LOADISNS:YES
0.22UF
PLACE_NEAR=U4900.A6:5MM
49 7
CPUIMVP_ISNS1_P 14.42K2
PLACE_NEAR=R7510.4:5MM
1
LOADISNS:YES
GND
LOADISNS:YES
R5345
4.53K2
1
1
R5354
715K
0.1%
1/16W
MF
2 402
715K 2
0.1%
1/16W
MF
402
GND_SMC_AVSS
45 46 49 50
LOADISNS:YES
SIGNAL_MODEL=EMPTY
LOADISNS:YES
SIGNAL_MODEL=EMPTY
CPU Core Voltage Sense (VC0C)
PLACE_NEAR=R7510.2:5 MM
PLACE_NEAR=U4900.E2:5MM
XW5320
SM
7
=PPCPUVCORE_S0_VSENSE 1
2
R5329
CPUVSENSE_IN
4.53K2
SMC_CPU_VSENSE
1
1%
1/16W
MF-LF
402
OUT
46
PLACE_NEAR=U4900.E2:5MM
1
C5329
0.22UF
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
116S0114
3
RES,MTL FLIM,100K,1/16W,0402,SMD,LF
C5349,C5359,C5369
CRITICAL
BOM OPTION
LOADISNS:NO
20%
2 6.3V
X5R
402
GND_SMC_AVSS
A
45 46 49 50
AXG Core Voltage Sense (VN0C)
SYNC_MASTER=LINDA_J30
SYNC_DATE=09/28/2011
PAGE TITLE
Power Sensors: Load Side
PLACE_NEAR=R7550.2:5 MM
PLACE_NEAR=U4900.C1:5MM
XW5330
SM
7
=PPAXGVCORE_S0_VSENSE 1
2
DRAWING NUMBER
R5339
AXGVSENSE_IN
4.53K2
1%
1/16W
MF-LF
402
Apple Inc.
SMC_AXG_VSENSE
1
OUT
46
R
1
C5339
NOTICE OF PROPRIETARY PROPERTY:
0.22UF
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
GND_SMC_AVSS
7
45 46 49 50
6
5
4
3
2
SIZE
D
6.0.0
PLACE_NEAR=U4900.C1:5MM
20%
2 6.3V
X5R
402
8
051-9058
REVISION
BRANCH
PAGE
53 OF 109
SHEET
49 OF 86
1
A
8
7
6
5
4
CPU High Side Current Sense (IC0R)
3
CRITICAL
Q5480
NTUD3169CZ
1
3
OUT
=PPVIN_S5_HS_COMPUTING_ISNS
R5400
1 3 85
5 INISNS_HS_COMPUTING_N
85
4 IN+
ISNS_HS_COMPUTING_P
R5409
INA213
SC70
Enables PBUS VSense
divider when in S0.
20%
10V
2 CERM
402
U5400
PLACE_NEAR=U5400.5:10MM
SOT-963
N-CHANNEL
C5401
0.1UF
V+
7
OUT
6
HS_COMPUTING_IOUT
4.53K2
1
0.003
2%
0.5W
MF
0612
CRITICAL
IN
1%
1/16W
MF-LF
402
REF 1
2 4
PLACE_NEAR=U4900.B5:5MM
GND
=PPVIN_S5_HS_COMPUTING_ISNS_R
PLACE_NEAR=U5400.4:10MM
2
7
1
PBUS Voltage Sense & Enable (VP0R)
Gain: 50x, EDP: 17.4 A
Rsense: 0.003 (R5400)
V across Rsense: 52.2 mV
Gain needed: 63.2x
=PP3V3_S0_HS_COMPUTING_ISNS
7
D
2
CRITICAL
73
SMC_CPU_HI_ISENSE OUT
1
=PBUSVSENS_EN
IN
D
6
PBUSVSENS_EN_L
D
2
R54821
100K
G
1%
1/16W
MF-LF
402 2
S
46
1
3
C5409
0.22UF
PBUS_S0_VSENSE
D
20%
2 6.3V
X5R
402
=PPBUS_S0_VSENSE
7
5
R54881
27.4K
G
1%
1/16W
MF-LF
402 2
S
PLACE_NEAR=U4900.B5:5MM
4
GND_SMC_AVSS
PLACE_NEAR=U4900.A3:5MM
Rthevenin = 4573 Ohms
P-CHANNEL
45 46 49 50
SMC_PBUS_VSENSE
OUT
46
1
R5481
OTHER High Side Current Sense (IO0R)
3 85
ISNS_HS_OTHER_N
5 IN-
85
ISNS_HS_OTHER_P
4 IN+
2%
0.5W
MF
IN
SC70
OUT
6
HS_OTHER_IOUT
GND
4.53K2
1
1%
1/16W
MF-LF
402
REF 1
2 4
=PPVIN_S5_HS_OTHER_ISNS_R
PLACE_NEAR=U5410.4:10MM
GND_SMC_AVSS
45 46 49 50
C
R5419
INA214
PLACE_NEAR=U4900.A5:5MM
2
7
0.22UF
20%
2 6.3V
X5R
402
C5411
0.003
0612
CRITICAL
C5489
20%
10V
2 CERM
402
U5410
PLACE_NEAR=U5410.5:10MM
R5410 1
1%
1/16W
MF-LF
402 2
0.1UF
3
=PPVIN_S5_HS_OTHER_ISNS
1
5.49K
PLACE_NEAR=U4900.A3:5MM
V+
OUT
PLACE_NEAR=U4900.A3:5MM
PBUSVSENS_EN_L_DIV
1
7
R5489
1%
1/16W
MF-LF
402 2
Gain: 100x, EDP: 8.8 A
Rsense: 0.003 (R5410)
V across Rsense: 26.4 mV
Gain needed: 125x
=PP3V3_S0_HS_OTHER_ISNS
7
C
1
100K
CRITICAL
SMC_OTHER_HI_ISENSE
OUT
1
46
C5419
0.22UF
20%
2 6.3V
X5R
402
PLACE_NEAR=U4900.A5:5MM
GND_SMC_AVSS
45 46 49 50
DC In Voltage Sense & Enable (VD0R)
CRITICAL
Charger (BMON Production) Current Sense (IPBR)
Charger Gain: 36x
Rsense: 0.010 (R7050)
Max Current Measured: 9.2 A
64 46
PLACE_NEAR=U4900.A4:5MM
IN
=CHGR_ACOK
IN
CHGR_BMON
45.3K2
1
1%
1/16W
MF-LF
402
B
SMC_BMON_ISENSE
1
MF
46
73
IN
PM_SUS_EN
1
MF
1
SOT-963
N-CHANNEL
6
DCINVSENS_EN_L
D
R54921
2
5% 1/20W 201
DCIN_VSENSE_EN
0
2
100K
G
1%
1/16W
MF-LF
402 2
S
R5494
OUT
NTUD3169CZ
NO STUFF R5493
0
R5429
64
Q5490
Enables DC-In VSense
divider when AC present.
1
2
3
5% 1/20W 201
C5429
DCIN_S5_VSENSE
D
7
=PPDCIN_S5_VSENSE
5
27.4K
G
1%
1/16W
MF-LF
402 2
S
4
PLACE_NEAR=U4900.A4:5MM
B
R54981
0.022UF
20%
16V
2 CERM
402
PLACE_NEAR=U4900.F1:5MM
Rthevenin = 4573 Ohms
P-CHANNEL
GND_SMC_AVSS
SMC_DCIN_VSENSE
R54911
45 46 49 50
1
100K
R5499
1%
1/16W
MF-LF
402 2
1
5.49K
1%
1/16W
MF-LF
402 2
DC-In (AMON) Current Sense (ID0R)
46
C5499
0.22UF
20%
2 6.3V
X5R
402
PDCINVSENS_EN_L_DIV
Charger Gain: 20x
Rsense: 0.020 (R7020)
Max Current Measured: 8.3 A
OUT
PLACE_NEAR=U4900.F1:5MM
GND_SMC_AVSS
45 46 49 50
PLACE_NEAR=U4900.F1:5MM
PLACE_NEAR=U4900.B3:5MM
R5439
64
IN
CHGR_AMON
4.53K2
1
1%
1/16W
MF-LF
402
SMC_DCIN_ISENSE
1
OUT
46
C5439
0.22UF
20%
2 6.3V
X5R
402
A
PLACE_NEAR=U4900.B3:5MM
GND_SMC_AVSS
SYNC_MASTER=YONAS_J30
SYNC_DATE=11/03/2011
PAGE TITLE
Power Sensors: High Side
45 46 49 50
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
54 OF 109
SHEET
50 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
Thermal Sensor:
CPU Proximity, Fin Stack, Memory Proximity, 5V/3.3V Proximity
I2C Write, 0x98, I2C Read: 0x99
R5510
=PP3V3_S0_CPUTHMSNS
7
1
47
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
85
Thermal Diode: Fin Stack
PLACE_NEAR=Q5520.3:5MM
Placement Note:
Place Q5520 on BOTTOM side.
Close to Fin Stack.
1
C5520
22PF
NOSTUFF
C
5%
50V
2 CERM
0402
Q5520
85
1
C5510
BC846BMXXH
NOSTUFF
5%
50V
2 CERM
0402
2
1
CRITICAL
PLACE_SIDE=TOP
3
85
C5515
22PF
NOSTUFF
PLACE_NEAR=Q5510.3:5MM
PLACE_NEAR=U5511.3:5MM
THMSNS_D2_P
PLACE_NEAR=Q5515.3:5MM
SOT732-3
1
22PF
10%
50V
CERM 2
402
CRITICAL
THMSNS_D1_N
5%
50V
2 CERM
0402
PLACE_NEAR=U5511.4:5MM
3
Q5515
0.0022uF
10%
50V
CERM 2
402
SIGNAL_MODEL=EMPTY
SOT732-3
2
CRITICAL
PLACE_NEAR=Q5515.2:5MM
THMSNS_D2_N
C5512 1
1
BC846BMXXH
U5511
0.0022uF
SIGNAL_MODEL=EMPTY
85
Q5510
C5511 1
1
SOT732-3
PLACE_NEAR=Q5520.2:5MM
PLACE_NEAR=Q5510.2:5MM
1
VDD
PLACE_NEAR=U5511.2:5MM
BC846BMXXH
PLACE_NEAR=U5511.5:5MM
Thermal Diode: 5V/3.3V Proximity
Thermal Diode: Memory Proximity
Placement Note:
Place Q5510 on the TOP side,
Next to 5V and 3.3V power supplies.
Placement Note:
Place Q5515 on the EITHER side, on the
right of DIMM connectors.
C5513
0.1uF
R55111
20%
10V
2 CERM
402
THMSNS_D1_P
3
2
1
10K
5%
1/16W
MF-LF
402 2
1
R5512
10K
5%
1/16W
MF-LF
2 402
EMC1414
DFN
2 DP1
THERM*/ADDR
7
CPUTHMSNS_THM_L
3 DN1
ALERT*
8
CPUTHMSNS_ALERT_L
4 DP2
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
48
5 DN2
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
48
GND
6
C
THRM_PAD
11
PLACE_SIDE=BOTTOM
Thermal Sensor: CPU Proximity
Placement Note:
Place U5511 on bottom side under CPU
Thermal Sensor: T29 Die
B
B
33
BI
TP_T29_THERM_DP
85
T29_THERMD_P
MAKE_BASE=TRUE
1
R5520
10K
5%
1/16W
MF-LF
2 402
1
2
85
T29_THERMD_N
XW5520
PLACE_NEAR=U3600.B1:2MM
SM
NOSTUFF
PLACE_SIDE=BOTTOM
Note: Use GND pin B1 on U3600 for N leg.
A
SYNC_MASTER=YONAS_J30
SYNC_DATE=08/01/2011
PAGE TITLE
Thermal Sensors
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
55 OF 109
SHEET
51 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
7
=PP5V_S0_FAN_RT
7
=PP3V3_S0_FAN_RT
CRITICAL
R5660 1
C
47K
5%
45
1/16W
MF-LF
402
R5665
47K 2
1
SMC_FAN_0_TACH
6
J5601
C
78171-0004
NC
M-RT-SM
5
2
1
FAN_RT_TACH
2
5V DC
TACH
3
5%
1/16W
MF-LF
402
4
NC
MOTOR CONTROL
GND
6
R5661 1
Q5660
100K
45
1
G
VESM
6
FAN_RT_PWM
3
D
2
2
SMC_FAN_0_CTL
518S0521
SSM3K15AMFVAPE
S
5%
1/16W
MF-LF
402
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Fan
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
56 OF 109
SHEET
52 OF 86
1
A
8
7
6
5
PSOC USB CONTROLLER
-
4
IC
USB INTERFACES TO MLB
SPI HOST TO Z2
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
PIN NAME
CURRENT
3
R_SNS
V_SNS
2
POWER
TMP102
V+
10UA
80UA
2.55 KOHM 0.0255 V
0.204 V
3V3 LDO
VDD
VOUT
60MA (MAX)
10 OHM
60MA (MAX) 0.2 OHM
0.6
0.012
V
V
36E-3 W
0.72E-3 W
PSOC
VDD
8MA (TYP) 1.5 OHM
14MA (MAX)
0.012
0.021
V
V
96E-6 W
294E-6 W
18V BOOSTER
VIN
4MA (MAX) 4.7 OHM
0.0188 V
75.2E-6 W
Keyboard Connector
0.255E-6 W
16.32E-6 W
54 53 7
PLACE_SIDE=BOTTOM
54 53 7
R5704
=PP3V3_S4_TPAD
D
2
1.5
BYPASS=U5701.22:19:11 mm
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:5 mm
PP3V3_S3_PSOC
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
1
1
100PF
R57031
5%
1/16W
MF-LF
402 2
C5705
54 6
53
54 6
53
53
53
53
53
53
TPAD_VBUS_EN
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
IN
54 6
54 6
54 6
54 6
C
54 6
54 6
54 6
54 6
54 6
54 6
6
NC
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
CRITICAL
OMIT
U5701
CY8C24794
MLF
(SYM-VER2)
337S2983
15 P1_7
16 P1_5
17 P1_3
18 P1_1
19 VSS
20 D+
21 D22 VDD
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
54 6
73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
WS_CONTROL_KEY
Z2_KEY_ACT_L
53
53
6 53
53
6 53
53
6 53
R5714
6 53
6 53
53
WS_KBD15_C
1
TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
24
WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
85
Z2_CLKIN
TP_P7_7
USB_TPAD_N
1
24
53
2
85
USB_TPAD_R_N
5%
1/16W
MF-LF
402
C5702
100PF
5%
50V
2 CERM
0402
WS_KBD16N
1
10K
2
53
53
53
53
1%
1/16W
MF-LF
402
53
53
53
6 53
R5710
6 53
6 53
46 45
6 53
OUT
SMC_ONOFF_L
C5710 1
6 53
0.1UF
6 53
20%
10V
CERM 2
402
6 53
6 53
6 53
1
1K
5%
1/16W
MF-LF
402
2
53
53
53 6
53 6
53 6
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
PLACEMENT_NOTE=NEAR J5713
NC
6 53
C
31
F-RT-SM
6 53
518S0637
6 53
6 53
6 53
6 54
SMC Manual Reset & Isolation
(PP3V3_S3_PSOC)
1
53
J5713
5%
1/16W
MF-LF
402
80 8
6 53
53
53
1%
1/16W
MF-LF
402
6 53
53
D
CRITICAL
USB_TPAD_R_P
R5702
WS_KBD1
WS_KBD2
WS_KBD3
6
WS_KBD4
6
WS_KBD5
6
WS_KBD6
6
WS_KBD7
6
WS_KBD8
6
WS_KBD9
6
WS_KBD10
6
WS_KBD11
6
WS_KBD12
6
WS_KBD13
6
WS_KBD14
6
6 WS_KBD15_CAP
6 WS_KBD16_NUM
WS_KBD17
6
WS_KBD18
6
WS_KBD19
6
WS_KBD20
6
WS_KBD21
6
WS_KBD22
6
WS_KBD23
6
6 WS_KBD_ONOFF_L
FF14-30A-R11B-B-3H
WS_KBD4
WS_KBD5
WS_KBD6
TP_ISSP_SDATA_P1_0
ISSP SDATA/I2C SDA
2
2
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
57
R5701
USB_TPAD_P
80 8
470
R5715
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
NC
53 6
20%
2 6.3V
X5R
603
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
=PP3V3_S4_TPAD
=PP3V42_G3H_TPAD
53 6
C5706
56
55
54
53
52
51
50
49
48
47
46
45
44
43
53
53 7
4.7UF
10%
16V
2 X7R-CERM
0402
=PSOC_WAKE_L
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
OUT
1
0.1UF
5%
50V
2 CERM
0402
220K
46
C5704
1
1
C5703
0.1UF
10%
16V
2 X7R-CERM
0402
1
C5701
4.7UF
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
20%
2 6.3V
X5R
603
BYPASS=U5701.49:50:5 mm
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.49:50:11
Keys ANDed with MSP power to isolate when MSP is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).
53 7
=PP3V42_G3H_TPAD
mm
B
1
B
C5750
0.1UF
10%
16V
2 X7R-CERM
0402
10
CRITICAL
VDD
U5750
TPAD Buttons Disable
SLG4AP021
TQFN
BUTTON_DISABLE
53
54 53 7
=PP3V3_S4_TPAD
4 OE
(IPD)
D 3
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
53 6
1
63 46 45
IN
SMC_LID
G
WS_LEFT_SHIFT_KBD
1 IN_1
(IPD)
53 6
WS_LEFT_OPTION_KBD
2 IN_2
53 6
WS_CONTROL_KBD
3 IN_3
(IPD)
S 2
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V
OUT_1 9
WS_LEFT_SHIFT_KEY
OUT_2 8
WS_LEFT_OPTION_KEY
OUT_3 7
WS_CONTROL_KEY
53
53
53
(IPD)
Pull-up in U5010.
OUT_ALL# 6
5
GND
SMC_TPAD_RST_L
OUT
46
THRM
PAD
11
Q5701
SSM3K15AMFVAPE
CRITICAL VESM
A
SYNC_MASTER=J31_MLB
SYNC_DATE=07/01/2011
PAGE TITLE
WELLSPRING 1
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
57 OF 109
SHEET
53 OF 86
1
A
8
7
6
5
4
3
2
1
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
D
D
TPAD:Z2
CRITICAL
L5801
3.3UH-870MA
PP5V_S4_P18V5S5
TPAD:Z2
=PP5V_S5_TPAD
2
TPAD:Z2
D5802
R5806
SOD-323
P18V5S4_SW
2
A
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE
VLF3010AT-SM-HF
TPAD:Z2
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
5%
1/16W
MF-LF
402
C5818
1
1
5%
50V
L
3
DO
2
CERM
0402
U5805
1
FB
4
P18V5S4_FB
CTRL
5
Z2_BOOST_EN
2
2.2UF
10%
16V
10%
2
16V
THRML
X5R
603
PAD
9
2
1
6 54
R5811
100K
2
IPD Flex Connector
J5800
TPAD:Z2
TPAD:Z2
1
1
2
1%
1/16W
MF-LF
402
PP18V5_Z2
M-ST-SM
C5815
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
6 54
1000PF
10%
25V
2
X5R
603-1
R5813
55560-0228
=PP3V3_S4_TPAD
53 7
5%
25V
NP0-C0G
402
2
53 6
53 6
71.5K
TPAD:Z2
1
8
GND
0.1UF
X7R-CERM
0402
CRITICAL
TPAD:Z2SW
C5817
6 54
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
CRITICAL
1%
1/16W
MF-LF
402
TPAD:Z2
6
1
PGND
1
7
C5816
TPAD:Z2
1UF
QFN-1
NC
TPAD:Z2
PP18V5_Z2
2
R5812
C5819
TPS61045
TPAD:Z2
0
5%
1/16W
MF-LF
402
1M
39PF
VIN
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
B0520WSXG
PP5V_S5_P18V5S5_VIN
1
PP18V5_S4_R
K
2
7
0
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
R5805
TPAD:Z2
CRITICAL
53 6
1%
1/16W
MF-LF
402
53 6
53 6
54 6
53 6
6
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
PP5V_S5_CUMULUS
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
53 6
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
6 53
6 53
6 53
6 53
6 53
6 53
6 53
48
48
C
C
516S0689
TPAD:CUMULUS
L5800
FERR-120-OHM-1.5A
1
PIN 21 IS NC ON CUMULUS FLEX
2
0402-LF
PIN 18 IS NC ON Z2 FLEX
PLACE_NEAR=J5800.18:3MM
TPAD:CUMULUS
1
C5800
0.1UF
PLACE_NEAR=J5800.18:3MM
2
20%
10V
CERM
402
Keyboard Backlight Driver & Detection
7
=PP5V_S0_KBDLED
Keyboard Backlight Connector
CRITICAL
B
L5850
7
=PP3V3_S0_KBDLED
1
2
1098AS-SM
R5853 1
C5850
470K
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
10V
X5R
402-1
2
2
6
2
1
STLA02
R5854
3 LX
5%
1/16W
MF-LF
402
DFN6
VOUT 4
CRITICAL
6 EN/PWM
FB 5
KBDLED_ANODE
4
R5855
10
2
518S0691
1%
1/16W
MF-LF
402
KBDLED_CAP
NO STUFF
R5852 1
10K
5%
1/16W
MF-LF
402
J5815 pin 1 is grounded
on keyboard backlight flex
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
U5850
4.7K
1
3
VIN
1
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
F-RT-SM
SMC_KDBLED_PRESENT_L
2
SMC_SYS_KBDLED
If LOW, keyboard backlight present
If HIGH, keyboard backlight not present
FF18-4A-R11AD-B-3H
6
10%
GND
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
THRM_PAD
7
BI
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
J5815
1UF
2
45
KBDLED_SW
1
5%
1/16W
MF-LF
402
1
B
CRITICAL
10UH-0.58A-0.35OHM
1
C5855
1
0.47UF
2
2
CERM-X5R
0603
C5856
0.47UF
10%
50V
10%
2
50V
CERM-X5R
0603
(SMC_KBDLED_PRESENT_L)
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/28/2011
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
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REVISION
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1
A
8
7
6
5
4
3
2
1
D
D
7
=PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
1
C5922
10UF
C
20%
6.3V
X5R
603
0.1UF
2
2
VDD
10%
16V
X7R-CERM
0402
R5924 1
BYPASS=U5920.14:13:8 mm
NC
NC
10K
5%
1/16W
MF-LF
402
45
OUT
1
1
14
CRITICAL
C5926
3
NC
LIS331DLH
15
LGA
CS
11
9
8
5%
1/16W
MF-LF
402
2
SDO
SDA/SDI/SDO
SCL/SPC
INT1
INT2
0
1
7
6
4
SMS_ADDR_SELECT
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R
=I2C_SMC_SMS_SDA
BI
=I2C_SMC_SMS_SCL
IN
48
R5922
R5921 1
16
13
5
2
5%
1/16W
MF-LF
402
GND
12
R5923
SMS_I2C_SEL
RESERVED
2
C
10K
PLACE_SIDE=TOP
U5920
10
SMS_INT_L
TP_SMS_INT2
R5920 1
VDD_IO
2
0
1
2
10K
338S0687
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=See schematic for orientation.
2
48
5%
1/16W
MF-LF
402
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)
SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
Desired orientation when placed on top-side:
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y
+X
Front of system
+Z (up)
B
B
Circle indicates pin 1 location when placed
in correct orientation
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Digital Accelerometer
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
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REVISION
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SHEET
55 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
C
C
=PP3V3_SUS_ROM
1
R6101
3.3K
C6100
8
7
1
20%
10V
CERM
402
CRITICAL
VDD
0.1UF
5%
1/16W
MF-LF
2 402
2
U6100
64MBIT
81 47 46
IN
SPI_MLB_CLK
6
SCK
SOIC
SI
5
SPI_MLB_MOSI
IN
46 47 81
SO
2
SPI_MLB_MISO
OUT
46 47 81
SST25VF064C
81 47 46
47 19 6
IN
IN
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
1
3
7
CE*
WP*
HOLD*
OMIT
VSS
4
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
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REVISION
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PAGE
61 OF 109
SHEET
56 OF 86
1
A
8
7
6
5
4
3
2
1
AUDIO CODEC
APPLE P/N 353S3199 as of July 2011
L6201
U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL
FERR-220-OHM
7
1
=PP1V8R1V5_S0_AUDIO
IN
=PP5V_S3_AUDIO
2
C6210
D
1
1
C6211
4.7UF
0.1UF
20%
4V
X5R-1
402
10%
16V
X7R-CERM
0402
2
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
=PP3V3R1V5_S0_AUDIO
C6218
C6221
1
1
1
R6210
2.67K
57
OUT AUD_GPIO_0
60
TP_AUD_GPIO_1
TP_AUD_GPIO_2
OUT AUD_GPIO_3
62
IN
AUD_SENSE_A
62 61 57 7
IN
=PP3V3_S0_AUDIO
GPIO3 = SPKR AMP SHDN CONTROL
2
CS4206_FP
CS4206_FN
CRITICAL
1%
1/20W
MF
201
2
VBIAS_DAC
20%
10V
X5R-CERM
0402-1
13
SENSE_A
45
43
42
FLYP
FLYC
FLYN
2
12
C6222
1
1
C6223
1
2.2UF
C6226
2.2UF
20%
6.3V
CERM
402-LF
0.1UF
10%
16V
X7R-CERM
0402
2
25
14
15
29
44
41
CS4206_FLYP
CS4206_FLYC
2
20%
6.3V
CERM
402-LF
2
CS4206_FLYN
U6201
3
VL_HD
1
VL_IF
6
BITCLK
C
IN
HDA_BIT_CLK
81 16
IN
HDA_SYNC
81 16
OUT
HDA_SDIN0
10
R6211
81 16
IN
81 16
IN
1
22
2
81
AUD_SDI_R
8
5
5%
1/16W
MF-LF
402
HDA_SDOUT
HDA_RST_L
TP_AUD_SPDIF_IN
1
11
47
48
AUD_SPDIF_OUT_CHIP
10%
10V
X5R
402-1
C6217
2
10%
16V
X7R-CERM
0402
10UF
2
2
1
10%
16V
X7R-CERM
0402
1
20%
16V
TANT-POLY
2012-LLP
2
2
10UF
CRITICAL
20%
10V
X5R-CERM
0402-1
GND_AUDIO_HP_AMP
57 58 59
GND_AUDIO_CODEC
38
40
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.10MM
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.10MM
39
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
57 62
AUD_HP_PORT_L
AUD_HP_PORT_R
OUT
OUT
HPAMP_REF
IN
TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R
35
34
36
37
AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R
MICBIAS
16
AUD_CODEC_MICBIAS
SDI
SDO
RESET*
SPDIF_IN
SPDIF_OUT
59 61
59 61
58
OUT
60 85
OUT
60 85
OUT
60 85
OUT
60 85
OUT
60 85
OUT
60 85
OUT
62
FR SPKR AMP. SIG. SOURCE
LFT. SPKR AMP. SIG. SOURCE
RT. SPKR AMP. SIG. SOURCE
C
28 CS4206_VCOM
21
LINEIN_L+
LINEIN_CLINEIN_R+
22
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
27
NC
NC
NC
23
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
IN
62
IN
62
IN
62
IN
62
AUD_DMIC_CLK OUT
57
EXT MIC CODEC INPUT
BI MIC CODEC INPUT
CS4206_VREF_ADC
R6214
DMIC_SCL
2
5%
1/16W
MF-LF
402
AUD_DMIC_SCL
4
DGND THRM_PAD AGND
7
1
22
2
5%
1/16W
MF-LF
402
C6224
1
1
2
2
1UF
20%
16V
TANT
0603-SM
GND_AUDIO_HP_AMP
C6225
NOSTUFF
10UF
1
20%
16V
TANT-POLY
2012-LLP
B
2
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_AUDIO_CODEC
R6213
100K
59 58 57
62 57
C6213
26
AUD_SPDIF_OUT
OUT
1
0.1UF
2
31
30
32
33
VCOM
6 57 62
SYNC
49
61
C6214
0.1UF
R6212
39
IN
1
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
CRITICAL
81 16
10%
16V
X7R-CERM
0402
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206B
HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-
10UF
2
46
C6220
10UF
20%
10V
X5R-CERM
0402-1
24
CRITICAL
PP4V5_AUDIO_ANALOG
IN
1
0.1UF
2
9
62 57 6
20%
16V
TANT-POLY
2012-LLP
C6215
1UF
1
10UF
GND_AUDIO_HP_AMP
1
7
D
PP4V5_AUDIO_ANALOG
C6216
C6219
59 58 57
7 57
PP1V8R1V5_S0_AUDIO_DIG
0402
5%
1/20W
MF
201
Digial Mic - Only for mock ups
as of July 2011
57
AUD_DMIC_CLK
TP_AUD_DMIC_CLK
57
AUD_GPIO_0
TP_AUD_DMIC_SDATA
B
MAKE_BASE=TRUE
4.5V POWER SUPPLY FOR CODEC
MAKE_BASE=TRUE
APPLE P/N 353S2281 as of July 2011
NOTES ON J30 audio
L6200
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
FERR-220-OHM
57 7
IN
=PP5V_S3_AUDIO
IN
=PP3V3_S0_AUDIO
1
2
TPS71745
4V5_REG_IN
6
IN
4V5_REG_EN
4
EN
0402
2.21K
1
SON
OUT
1
PP4V5_AUDIO_ANALOG
BI
Codec HPamp used for Lineout/HPout. No external HPamp.
3 Spk amplifiers - 2 tweeters and a sub woofer
No line input capability
SPDIF out
China headset support
6 57 62
CRITICAL
R6200
62 61 57 7
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V
U6200
NR/FB
3
NC
5
4V5_NR
2
1%
1/16W
MF-LF
402
GND
1
1
C6200
R6203
1UF
2
10%
10V
X5R
402
5%
1/16W
MF-LF
402
2
NC
2
1
100K
1
C6201
C6202
2
1
10%
10V
X5R
402
10%
16V
X7R-CERM
0402
C6203
1UF
0.1UF
1UF
2
2
www.qdzbwx.com
10%
10V
X5R
402
GND_AUDIO_CODEC
XW6200
57 62
SM
A
1
2
SYNC_MASTER=KAVITHA_J30
NOSTUFF
1
0
SYNC_DATE=07/25/2011
PAGE TITLE
R6201
AUDIO: CODEC/REGULATOR
2
DRAWING NUMBER
5%
1/16W
MF-LF
402
Apple Inc.
R
XW6201
SM
1
8
7
051-9058
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
2
6
NOTICE OF PROPRIETARY PROPERTY:
GND_AUDIO_HP_AMP
SIZE
D
REVISION
6.0.0
BRANCH
57 58 59
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
PAGE
62 OF 109
SHEET
57 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
EXTERNAL (HEADSET) MIC INPUT CIRCUITRY APN:353S3066 as of July 2011
L6400
PP_AUDIO_CHS
FERR-220-OHM
=PP3V42_G3H_AUDIO
1
2
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.42V
0402
1
C6403
10UF
20%
2 6.3V
CERM-X5R
0402-1
1
C6400
0.1UF
10%
16V
2 X7R-CERM
0402
1
C6405
10UF
20%
2 6.3V
CERM-X5R
0402-1
CHS_CLAMPI
A1
7
VDD
R6403
U6400
RAMPI
C4
RAMPO/CLAMPI
D4
CLAMPO
D3
R6401
2.21K2
1
WCSP
C
R6402
2.21K2
TS3A8237A0YZPR
1.02K2
1
1%
1/16W
MF-LF
402
1
1%
1/16W
MF-LF
402
EXT_MIC_BIAS
IN
62
1%
1/16W
MF-LF
402
C
EXT_MIC_P
61
IN
OUT
CHS_CLAMP0
AUD_HS_MIC1
62
NOSTUFF
C6416
FROM HEADSET
61
MIC
REF
5%
50V
C0G-CERM 2
0402
SCL
SDA
A3
A4
CPO
B4
IN
1
20%
6.3V
2 CERM-X5R
0402-1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
C6401
TO MIKEY & FILTER
10UF
20%
6.3V
2 CERM-X5R
0402-1
EXT_MIC_N
OUT
62
R6404
NOSTUFF
0
1
1
2
5%
1/16W
MF-LF
402
C6406
10%
50V
2 X7R-CERM
0402
AUD_HS_RET1
1
CPP
0.001UF
AUD_HS_RET2
C6402
10UF
GND2
GND1
B2
C2
DGND
GND
C3
B3
AUD_HS_MIC2
IN
D2
D1
CHS_CAP_REF
61
IN
B1 MIC1
C1 MIC2
A2
61
1
33PF
CHS_SCL
R6406
1
0
2
=I2C_MIKEY_SCL
IN
48 62
5%
1/16W
MF-LF
402
CHS_SDA
R6405
59 57
GND_AUDIO_HP_AMP
1
0
R6407
2
1
5%
1/16W
MF-LF
402
0
2
=I2C_MIKEY_SDA
BI
48 62
5%
1/16W
MF-LF
402
B
B
XW6400
SM
1
HPAMP_REF
2
OUT
57
I2C ADDRESSES: CHS uses SMBus 0 connections
CHS
CHS
U6400
U6400
READ
WRITE
0111
0111
0111
0110
0x77
0x76
A
SYNC_MASTER=DIRK_J30
SYNC_DATE=02/16/2012
PAGE TITLE
AUDIO: DETECT/MIC BIAS
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
64 OF 109
SHEET
58 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
61 57
IN
AUD_HP_PORT_L
CRITICAL
C6500
1
0.1UF
10%
16V
X7R-CERM
0402
2
AUD_HP_ZOBEL_L
C
R6500
C
1
39
5%
1/16W
MF-LF
402
58 57
IN
2
GND_AUDIO_HP_AMP
R6510
1
39
5%
1/16W
MF-LF
402
2
AUD_HP_ZOBEL_R
CRITICAL
C6510
1
0.1UF
10%
16V
X7R-CERM
0402
61 57
IN
2
AUD_HP_PORT_R
B
B
A
SYNC_MASTER=KAVITHA_J30
SYNC_DATE=07/25/2011
PAGE TITLE
AUDIO: HEADPHONE FILTER
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
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PAGE
65 OF 109
SHEET
59 OF 86
1
A
8
7
6
5
SATELLITE
4
3
2
1
& SUB TWEETER AMPLIFIER
Gain Pin
Gain dB
Connect to VDD
Connect to VDD through 100k
Not connected
Connect to GND through 100k
Connect to GND
12
9
6
3
0
APN:353S2888 as of July 2011
D
SATELLITE
FC=1.2kHz typical
SUB
FC= 172 HZ typical
GAIN
3DB with Rin=28k typical
D
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
85 57
1
AUD_LO2_P_R
IN
C6607
CRITICAL
L6611
C6611
FERR-1000-OHM
85
0.1UF
10%
0.0047UF
2
SPKRAMP_INR_P
1
1
A1
60 7
16V
2
X7R-CERM
0402
10%
FERR-1000-OHM
85 57
1
AUD_LO2_N_R
IN
2
85
MAX98300
WLP
CRITICAL
25V
C6610
CERM
402
0.0047UF
1
SPKRAMP_INR_N
85
2
85
A3 IN+
B3 IN-
SSM2315_R_P
SSM2315_R_N
CRITICAL
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT
C6601
47UF
U6610
0402
L6610
1
PVDD
2
2
CRITICALOUT-
B1
C1
GAIN
C3
OUT+
20%
6.3V
TANT1
2012-LLP
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT
6 61 85
BI
OUT
6 61 85
0402
10%
25V
CERM
402
NC
C
0
AUD_GPIO_3
IN
1
2
2
5%
1/16W
MF-LF
402
60
NC
SPKAMP1_GAIN
1
R6612
100K
R6611
R6610
57
SHDN*
B2
100K
PGND
5%
1/16W
MF-LF
402
A2
1
C2
5%
1/16W
MF-LF
C
2402
SPKRAMP_SHDN
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
CRITICAL
L6621
85 57
IN
1
AUD_LO1_P_R
2
85
C6608
C6621
FERR-1000-OHM
1
1
0.1UF
0.033UF
SPKRAMP_INSUB_P
A1
60 7
10%
2
16V
X7R-CERM
0402
0402
FERR-1000-OHM
85 57
IN
1
AUD_LO1_N_R
16V
2
85
X5R
402
C6620
0.033UF
SPKRAMP_INSUB_N
1
A3
B3
SSM2315_SUB_P
SSM2315_SUB_N
85
2
85
MAX98300
WLP
IN+
IN-
CRITICAL
C6603
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT
100UF
2
U6620
10%
CRITICAL
L6620
1
PVDD
2
OUT+
CRITICALOUT-
20%
6.3V
TANT
CASE-AL1
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT
B1
C1
OUT
6 61 85
OUT
6 61 85
0402
10%
16V
X5R
402
NC
C2
SHDN*
B2
NC
GAIN
C3SPKAMP2_GAIN
1
R6622
100K
5%
1/16W
MF-LF
PGND
2402
A2
SPKRAMP_SHDN
60
B
B
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
=PP5V_S3_AUDIO_AMP
C6609
CRITICAL
L6631
85 57
IN
AUD_LO2_P_L
1
85
2
10%
16V
0.0047UF
SPKRAMP_INL_P
1
1
0.1UF
C6631
FERR-1000-OHM
X7R-CERM
0402
2
10%
25V
CERM
402
PVDD
FERR-1000-OHM
85 57
IN
AUD_LO2_N_L
1
85
2
SPKRAMP_INL_N
2
U6630
CRITICAL
C6630
0.0047UF
1
85
2
85
A3
B3
SSM2315_L_P
SSM2315_L_N
MAX98300
WLP
IN+
IN-
CRITICAL
C6605
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT
47UF
2
0402
L6630
1
A1
60 7
OUT+
CRITICALOUT-
20%
6.3V
TANT1
2012-LLP
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT
B1
C1
OUT
6 61 85
OUT
6 61 85
0402
10%
25V
CERM
402
NC
C2
SHDN*
B2
NC
GAIN
C3SPKAMP3_GAIN
1
R6632
100K
PGND
SPKRAMP_SHDN
A2
60
5%
1/16W
MF-LF
2402
A
SYNC_MASTER=KAVITHA_J30
SYNC_DATE=07/25/2011
PAGE TITLE
AUDI0: SPEAKER AMP
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
66 OF 109
SHEET
60 OF 86
1
A
8
7
6
5
4
AUDIO JACK:LO/HP CONNECTOR, SPDIF TX
3
2
1
L6701
FERR-1000-OHM
1
AUD_HS_MIC1_UNFILT
AUD_HS_MIC1
2
OUT
58
=PP3V3_S0_AUDIO
2
SM
CRITICAL
L6703
FERR-120-OHM-2.0A
1
62 57 7
XW6700
0402
1
AUD_HS_RET2
2
OUT
58
OUT
58
OUT
58
0402
Place XW on/near Jack pin
L6702
FERR-1000-OHM
D
1
AUD_HS_MIC2_UNFILT
2
SM
CRITICAL
L6706
1
AUD_CONNJ1_USMIC
SPDIF-TXRX-K24
FERR-120-OHM-2.0A
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
F-RT-TH
CRITICAL
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
XW6701
APN:514-0671
J6700
D
AUD_HS_MIC2
2
0402
Place XW on/near Jack pin
1
AUD_HS_RET1
2
AUD_CONNJ1_USGND
0402
6
5
AUD_CONNJ1_USGND_DET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
2
1
3
4
AUDIO
A - VIN
B - VCC
C - GND
7
AUD_SPDIF_OUT
IN
57
8
9
OPERATING VOLTAGE 3.3
POF
1
10
SHELL
L6704
2
ANALOG MIC CONNECTOR
FERR-120-OHM-2.0A
10%
12
SHIELD
PINS
CRITICAL
C6700
1UF
11
6.3V
CERM
402
1
2
13
AUD_HP_PORT_L
BI
CRITICAL
APN:518S0520
57 59
J6701
0402
C
78171-0003
CRITICAL
C
M-RT-SM
L6705
4
FERR-120-OHM-2.0A
1
2
AUD_HP_PORT_R
BI
62 6
57 59
0402
62 6
R6700
CRITICAL
2
2
DZ6705
DZ6703
6.8V-100PF
DZ6701
402
1
1
402
402
1
1
1
CRITICAL
DZ6700
1
2
ESDALC5-1BM2
SOD882
OUT
62
OUT
62
5
C6701
100PF
4.7
AUD_J1_TIPDET_R
2
5%
1/16W
MF-LF
402
CRITICAL
SPEAKER CONNECTOR
5%
2
J6702
50V
78171-0002
CERM
0402
M-RT-SM
APN:518S0519
GND_CHASSIS_AUDIO_JACK
VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
3
AUD_J1_SLEEVEDET_R
2
R6701
6.8V-100PF
6.8V-100PF
2
CRITICAL
DZ6704
1
2
10K
BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI
5%
1/16W
MF-LF
402
6.8V-100PF
402
2
CRITICAL
1
CRITICAL
62 6
1
CHASSIS GND STITCHES
XW6710
85 60 6
IN
SM
85 60 6
IN
1
3
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
1
2
2
4
XW6711
85 60 6
SM
1
IN
SPKRAMP_SUB_P_OUT
2
R6760
B
1
0
CRITICAL
B
J6703
2
78171-0004
5%
1/16W
MF-LF
402
M-RT-SM
5
1
85 60 6
IN
85 60 6
IN
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
2
3
4
6
APN:518S0521
85 60 6
IN
SPKRAMP_R_N_OUT
C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES
A
SYNC_MASTER=DIRK_J30
SYNC_DATE=11/10/2011
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
67 OF 109
SHEET
61 OF 86
1
A
8
7
6
5
4
3
2
1
CODEC OUTPUT SIGNAL PATHS
FUNCTION
VOLUME
CONVERTER
PIN COMPLEX
MUTE CONTROL
DET ASSIGNMENT
HP/LINE OUT
0X02 (2)
0X02 (2)
0X09 (9,A)
N/A
0X09 (A)
SATELLITES
0X04 (4)
0X04 (4)
0X0B (11)
GPIO_3
N/A
SUB
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
SPDIF OUT
N/A
0X08 (8)
0X10 (16)
N/A
0X0D (B)
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ
MIKEY
L6880
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
FERR-1000-OHM
1
=PP3V3_S0_AUDIO
61 57 7
2
PP3V3_S0_AUDIO_F
WCSP MIKEY 1A
APN:353S2640
0402
PIN COMPLEX
VREF
DET ASSIGNMENT
0X0D (13,B,RIGHT)
MIC_BIAS (80%)
N/A
HEADSET MIC
0X06 (6)
0X0D (13,V22,B,LEFT)
MIKEY
MIKEY
R6885
0x73
0x72
C6880
100K
5%
1
1UF
1/16W
10%
MF-LF
402
A2
CONVERTER
0X06 (6)
1
2
U6880
CD3282A1
2
X5R
402
SOUTHBRIDGE RESOURCES
PULLUPS for I2C ON PCH PAGE
FUNCTION
SYSTEM GPIO
AUD_IPHS_SWITCH_EN
PANTHER_POINT GPIO16
N/A
AUD_I2C_INT_L
N/A
PANTHER_POINT GPIO5/PIRQH
AUD_IP_PERIPHERAL_DET
WCSP
SYSTEM INTERRUPT
N/A
58 48
IN
=I2C_MIKEY_SCL
58 48
BI
=I2C_MIKEY_SDA
PANTHER_POINT GPIO3/PIRQH
18
24
D
CRITICAL
MIKEY
AVDD
10V
SCL
MICBIAS
B3
SDA
DETECT
B1 HS_SW_DET
BYPASS
D1
OUT
AUD_I2C_INT_L
D3
IN
AUD_IPHS_SWITCH_EN
A3
ENABLE
A1
HDET
B2
CS
62
TIPDET_UNFILT
1
R6880
C1
C3
INT*
100K
MIKEY
1
HS_RX_BP
CRITICAL
C6882
2.2UF
2
AGND
FUNCTION
BUILT-IN MIC
CRITICAL
MIKEY
DGND
D
I2C addresses: Mikey uses SMBus 0
MIKEY
U6880
READ
0111
0011
MIKEY
U6880
WRITE
0111
0010
MIKEY
20%
6.3V
TANT
402-1
1
GND_AUDIO_CODEC
57 62
C6881
0.01UF
C2
5%
1/16W
MF-LF
402
D2
CODEC INPUT SIGNAL PATHS
16V
10%
0402 X7R-CERM
MIKEY
2
R6881
2
1
1K
1%
62 57
GND_AUDIO_CODEC
1/16W
MIKEY
CRITICAL
402
MIKEY
C6883
PORT A DETECT (HEADPHONES)
OUT AUD_SENSE_A
57
1
OUT AUD_MIC_INP_L
MIKEY
CRITICAL
1
PP4V5_AUDIO_ANALOG_FLT
39.2K
2
R6804
C
1
IN
SOT563
P-CH
5%
1/16W
MF-LF
402
AUD_J1_SLEEVEDET_R
62
D 3
AUD_J1_SLEEVEDET_R_INV
0.1UF
1%
1/16W
MF-LF
2 402
AUD_PORTA_DET_L
57
1
OUT AUD_MIC_INN_L
2
HS_MIC_HI_RC
EXT_MIC_P
2
R6883
1
MIKEY
5 G
0.01UF
2
10%
16V
X7R-CERM
0402
SSM6N37FEAPE
220K
Q6801
D
5%
1/16W
MF-LF
2 402
4 S
D 6
GND_AUDIO_CODEC
R6812
0.0082UF
2
2
62
58
C6885
27PF
25V
10%
X7R-CERM 0402
2
CRITICAL
5%
CERM
50V
0402-1
C
CRITICAL
SSM6N37FEAPE
D
6
Q6801
SOT563
G
S
4
2
AUD_J1_SLEEVEDET_R_BUF
G
NC
S
PORT B RIGHT(BUILT-IN MIC)
1
2
62
AUD_J1_SLEEVEDET_R_INV
IN
MIKEY
1
C6884
5%
1/16W
MF-LF
402
CRITICAL
3
SOT563
5
62
58
MF-LF
402
100K
2
CRITICAL
C6802
IN
5%
1/16W
1
10%
25V
X5R
402
AUD_PORTB_DET_L
1
MIKEY
10%
25V
X5R
402
EXT_MIC_N
1
1
62 57
C6886
R6805
20.0K
1%
1/16W
MF-LF
2 402
Q6803
DMC2400UV
150K
61
1
R6806
58
2.2K
57
62
OUT
2
R6884
0.1UF
PORT B DETECT(SPDIF DELEGATE)
EXT_MIC_BIAS
MF-LF
2 G
R6850
AUD_J1_SLEEVEDET_R_BUF
R6803
1
1 S
N-CH
R6851
100
57
220K
APN:376S1081
IN
2.4K
1
AUD_CODEC_MICBIAS
2
5%
1/16W
MF-LF
402
1%
1/20W
MF
201
MIC_BIAS_FILT
1
1
2
1%
1/20W
MF
201
CRITICAL
C6852
2.2UF
GND_AUDIO_CODEC
2
62 57
20%
6.3V
TANT
402-1
62 57 GND_AUDIO_CODEC
CRITICAL
CRITICAL
L6801
57 6
1
PP4V5_AUDIO_ANALOG
IN
57
62
1
OUT AUD_MIC_INP_R
0.1UF
62 57
20%
CERM
10%
25V
X5R
402
C6851
0.1UF
57
AUD_J1_DET_NMOS_DRN
1
OUT AUD_MIC_INN_R
GND_AUDIO_CODEC
2
1
R6852
CRITICAL
BI_MIC_HI
IN
6 61
100K
2
5%
1/16W
MF-LF
402
IN
6 61
IN
6 61
1
C6853
0.001UF
50V
10%
0402 X7R-CERM
L6851
2
B
FERR-1000-OHM
R6853
BI_MIC_LO_F
2.4K
1
62 57 GND_AUDIO_CODEC
1
BI_MIC_HI_F
2
10%
25V
X5R
402
2
2
0402
CRITICAL
PP4V5_AUDIO_ANALOG_FLT
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=5V
1
C6804
10V
402
FERR-1000-OHM
0.1UF
2
0402
B
L6850
C6850
FERR-1000-OHM
1
2
BI_MIC_LO
2
0402
1%
1/20W
MF
201
XW6851
APN:376S0634
1
SM
4
1
S
S
1
SOT-563-HF
R6801
5%
1/16W
MF-LF
2 402
61
IN
AUD_J1_TIPDET_R
1
100K
R6807
AUD_J1_DET_RC
2
1
1
C6801
0.1UF
NOSTUFF
2
R6830
20%
CERM
10V
402
TIPDET_UNFILT
0
2
G
62
100K
5%
1/20W
MF
201
HP=80HZ
NTZD3152P
Q6800
Q6804
SSM3K15AMFVAPE
G
Q6804
D
D
R6802
5%
1/20W
MF
201
1
2
NTZD3152P
5
AUD_J1_DET_RC2
220K
BI_MIC_SHIELD
2
APN:376S1017
SOT-563-HF
D 3
VESM
6
3
AUD_J1_DET_RC2_INV
1
2
1
1
1
C6803
0.1UF
2
20%
CERM
10V
402
R6808
R6809
G
S 2
AUD_J1_DET_NMOS_GATE
220K
220K
5%
1/16W
MF-LF
402
2
2
62 57
5%
1/16W
MF-LF
402
GND_AUDIO_CODEC
5%
1/16W
MF-LF
402
R6810
1
10K
5%
1/16W
MF-LF
402
A
2
AUD_IP_PERIPHERAL_DET
OUT
18
EXTRACTION NOTIFICATION
SYNC_MASTER=DIRK_J30
SYNC_DATE=02/20/2012
PAGE TITLE
AUDIO:Jack Translators
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
68 OF 109
SHEET
62 OF 86
1
A
8
7
6
5
4
3
2
1
MagSafe DC Power Jack
CRITICAL
J6900
CRITICAL
78048-0573
F6905
M-RT-SM
1
PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
1
=PP18V5_DCIN_CONN
C6905
=PP3V42_G3H_ONEWIREPROT
0.01UF
1
20%
50V
2 CERM
0603
CRITICAL
SMC_BC_ACOK_VCC
R6929
2.0K
518S0656
402
MF-LF
1/16W
5%
7 63
B
MAX9940
SYS_ONEWIRE
BI
A
4 INT
SC70-5
2
PLACE_NEAR=U6901.5:1mm
Y
U6900
1
45
4
D
20%
10V
2 CERM
402
U6901
CRITICAL
7
C6908
0.1UF
TC7SZ08FEAPE 5
SOT665
VCC
1
SMC_BC_ACOK
3
45 46
EXT 5
GND
NC
3
ADAPTER_SENSE
1
6
2
1206-1
2
D
6AMP-24V
6
2
1
2
3
4
5
NC
1-Wire OverVoltage Protection
BIL CONNECTOR
7
=PP3V42_G3H_BATT
CRITICAL
J6955
CPB6312-0101F
C
C
F-ST-SM
14
13
63 48
TO SMC
63 48
46
45 6
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL
SMC_BIL_BUTTON_L
BI
BI
C6952 1
2
4
6
8
10
NC 12
1
3
5
7
9
11
16
15
R6961
6
C6954
C6953
1
0.001UF
47PF
10%
50V
X7R-CERM 2
0402
D6990
BAT30CWFILM
1
5.0
5%
1/3W
MF-LF
0805
B
PBUS_G3H_R
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
C6951
=PP18V5_DCIN_CONN
1
47
2
1
516S0523
C6955
0.001UF
20%
10V
CERM 2
402
10%
50V
2 X7R-CERM
0402
5%
50V
CERM 2
402
C6990 1
4.7UF
10%
35V
X5R-CERM 2
0805
C6996
0.1UF
1
R6995
1.00M
P18V5_DCIN_CONN_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
5%
1/3W
MF
0805
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
2
R6990
63 7
1
1
0.1UF
P3V42G3H_REF3
3
1%
1/8W
MF-LF
2 805
P3V42G3H_TON
3 TON
4 EN
P3V42G3H_FB
C6991 1
NC
1 REF
PM6640
DFN
CRITICAL
CRITICAL
33UH-20%-0.44A-0.455OHM
THRM
GND PAD
5
1UF
10%
25V 2
X5R
603-1
353S2776
B
BYP 9
U6990
8 VCC
2 FB
10%
2 16V
X5R
402-1
REF3 10
=PPBUS_G3H
L6995
SW 6
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
11
64 7
45 46 53
Supply needs to guarantee 3.31V delivered to SMC VRef generator
SOT-323
1
VIN 7
R6905
SMC_LID
3.425V "G3Hot" Supply
CRITICAL
CRITICAL
1
1
2
1/16W
402
5%
MF-LF
NC
47PF
5%
50V
CERM 2
402
100
SMC_LID_R
C6994
1
=PP3V42_G3H_REG
7
2
Vout = 3.465
D52LC-SM
DIDT=TRUE
350mA max output
1
f = 470 kHz
0.1UF
518-0375
CRITICAL
10%
16V 2
X5R
402-1
BATTERY CONNECTOR
J6950
1
22UF
BAT-K90-K91-K92
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
=SMBUS_BATT_SCL
SYS_DETECT_L
=SMBUS_BATT_SDA
64 6 PPVBAT_G3H_CONN
C6950 1
C6960 1
10%
25V 2
X5R
402
10%
25V 2
X5R
603-1
0.1UF
10
11
12
13
48 63
48 63
CRITICAL
RCLAMP2402B
SC-75
2
D6950
1
6
1
R6950
SYNC_MASTER=JACK_J30
DC-In & Battery Connectors
DRAWING NUMBER
Apple Inc.
051-9058
NOTICE OF PROPRIETARY PROPERTY:
7
6
5
4
3
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
SYNC_DATE=07/29/2011
PAGE TITLE
10K
5%
1/16W
MF-LF
402 2
1UF
3
A
M-RT-TH
1
2
3
4
5
6
7
8
9
P1
P2
P3
P4
P5
P6
P7
P8
P9
C6999
20%
2 6.3V
X5R-CERM-1
603
6.0.0
BRANCH
PAGE
69 OF 109
SHEET
63 OF 86
1
A
8
7
6
5
4
3
2
1
R7091
0
1
AON6405L
AON6405L
DFN5X6
DFN5X6
603-1
VIN
470K
CHGR_AGATE_DIV
5
10%
25V
2 X5R-CERM
0603
4.7UF
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
CHGR_SGATE_DIV
64
PPCHGR_DCIN_D
20
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
1
30mA max load
R7010
30.1K
SMC_RESET_L
IN
0
1
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
48
IN
48
BI
73
IN
CHGR_ACIN
1
R7011
9.31K
1%
1/16W
MF-LF
2 402
1
R7015
84
100K
84
1%
1/16W
MF-LF
2 402
BATT_2S
R70131
1
1%
1/16W
MF-LF
402 2
1
3
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
5
7
8
18
17
C7050
C7015
330PF
Vout = 1.25V * (1 + Ra / Rb)
4 2
2
PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
10%
2 25V
X5R
402
64
PPCHGR_DCIN
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
26
1
28 84
27 84
25
24
23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
21
CHGR_LGATE
1
R7025
0
5%
1/16W
MF-LF
402 2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
10%
2 25V
X5R
603-1
20%
25V
2 POLY-TANT
CASE-D2-SM
1
C7036
1UF
10%
2 25V
X5R
603-1
1
C7037
0.001UF
10%
50V
2 X7R-CERM
0402
C
PLACE_NEAR=C7036.1:3mm
CHGR_BGATE
CHGR_AMON
CHGR_BMON
=CHGR_ACOK
16
9
15
14
5
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1
C7025
10%
10V
2 CERM
402
4
Q7030
G
RJK03E1DNS
HWSON-8
PLACE_NEAR=U7000.25:2mm
CRITICAL
S
DIDT=TRUE
OUT
50
OUT
46 50
OMIT
CRITICAL
4
G
Q7035
CHGR_PHASE_RC
RJK03E1DNS
DIDT=TRUE
7 63
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
0.5%
1W
MF
0612-3
Q7055
1
3
DFN5X6
2
4
PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
1
10%
25V 2
X5R
603-1
CHGR_VNEG_R
470PF
(CHGR_CSO_N)
2
0
1
2
85
CHGR_CSO_R_P
85
CHGR_CSO_R_N
B
TO/FROM BATTERY
SYM-VER-2
OMIT
1UF
1
CRITICAL
AON6403L
C7055
2.2
0.001UF
0.01
PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm
R7051
R7052
C7045
10%
50V
2 X7R-CERM
0402
R7050
C7039
(GND)
(CHGR_CSO_P)
1
C7040
20%
25V
2 POLY-TANT
CASE-D2-SM
CRITICAL
BATT_3S
10%
50V
2 CERM
0402
XW7000
SM
CRITICAL
1
22UF
NO STUFF
1
1 2 3
10%
50V
2 CERM
0402
=PPBUS_G3H
180
5%
1/10W
MF-LF
603 2
470PF
C7016
2
1206
NO STUFF
5
D
2
1
R70391
353S2929
1
8AMP-24V
1
2
IHLP4040DZ-SM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
TO SYSTEM
F7040
4.7UH-9.5A
GATE_NODE=TRUE
DIDT=TRUE
50
CRITICAL
L7030
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 1 2 3
GATE_NODE=TRUE
DIDT=TRUE
OUT
Max Current = 8A
(L7030 limit)
f = 400 kHz
OMIT
CRITICAL
D
0.22UF
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
0
1
C7035
1UF
22UF
PLACE_NEAR=Q7030.5:1mm
S
1%
1/16W
MF-LF
402 2
1
C7031
20
2
R7042
3.01K
CRITICAL
1
C7030
20%
25V
2 POLY-TANT
CASE-D2-SM
0.1UF
1
R7016
CRITICAL
1
22UF
HWSON-8
1
20%
10V
2 X5R
603
0.5%
1W
MF
RL1632W
C7021
5%
2 50V
COG
402
5%
1/16W
MF-LF
2 402
R7020
0.02
CHGR_BOOT_R
U7000
10%
2 16V
X5R
402
1
10%
25V 2
X5R
402
VDDP
VHST CRITICAL DCIN
SMB_RST_N
SGATE
SCL
AGATE
TQFN
SDA
CSIP
VFRQ
CSIN
CELL
BOOT
ACIN
UGATE
ICOMP
PHASE
VCOMP
LGATE
VNEG
CSOP
BGATE
CSON
20V/V AMON
36V/V BMON
(OD) ACOK
1UF
CHGR_VCOMP_R
1K
12
13
11
10
4
6
CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL
2
Float CELL for 1S
B
VDD
R7000
47
45
46
ISL6259
1
5%
1/16W
MF-LF
2 402
64
1
0.1UF
10%
10V 2
X5R
402
100K
GND_CHGR_AGND
C7022
1UF
22 PGND
1K
C7001
3 1
5%
1/16W
MF-LF
402
1
C7099
CRITICAL
R7022
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
5%
1/16W
MF-LF
402
2
CHGR_CSI_R_N
10
1
10UF
20%
10V
2 X5R
603
1%
1/20W
MF
201 2
85
PP5V1_CHGR_VDDP
R7002
10%
10V 2
X5R
402
1%
1/16W
MF-LF
402 2
64
1
1UF
R70121
2
NO STUFF
C7002 1
BATT_3S
4.7
(AGND)
29 THRM_PAD
C
1
19
7
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
NO STUFF
CRITICAL
200K
CHGR_CSI_R_P
1
R7001
C7098
10UF
1
85
0.047UF
=PP3V42_G3H_CHGR
1
NO STUFF <Rb>
5%
1/16W
MF-LF
402
C7020
10%
10V
2 X5R-CERM
0402
PP5V1_CHGR_VDD
10
1
5%
1/16W
MF-LF
402
(Switcher limit)
NO STUFF
CRITICAL
1%
1/20W
MF
201 2
P5V5G3H_FB
R7021
(CHGR_DCIN)
D
200MA MAX OUTPUT
NO STUFF
R7096
Divider sets ACIN threshold at 13.55V
Input impedance of ~40K meets
sparkitecture requirements
5%
50V
2 NP0-C0G-CERM
0201
64
Vout = 5.506V
<Ra>
(CHGR_SGATE)
2
PPCHGR_DCIN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.5V
1
C7095 R7095
681K
(CHGR_AGATE)
R7005
NO STUFF
PP5V5_CHGR_VDDP
2
22PF
10%
35V
X5R-CERM 2
0805
64
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.5V
DP418C-SM
NO STUFF
1
5%
1/16W
MF-LF
2 402
SOT-323
1
2
GND
1
PP5V1_CHGR_VDDP
SWITCH_NODE=TRUE
DIDT=TRUE
FB 1
THRM
PAD
62K
BAT30CWFILM
ACIN pin threshold is 3.2V, +/- 50mV
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
CRITICAL
4.7UF
R7081
1%
1/16W
MF-LF
402 2
3
C7090
L7095
1
2
5%
1/16W
MF-LF
402
33UH-20%-0.39A-0.435OHM
P5V5G3H_SW
SW 4
BIAS 2
NO STUFF
1
332K
D7005
7 NC
5%
1/16W
MF-LF
2 402
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
R70861
CRITICAL
8 SHDN*
NO STUFF
CRITICAL
0.22UF
10%
10V
CERM 2
402
0
1
C7094 1
DFN
R7080
C7087
1
NO STUFF
LT3470A
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
1
100K
1%
1/16W
MF-LF
2 402
NO STUFF
U7090
PPDCIN_G3H_INRUSH
3 2 1
D
D
S
5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V
R7092
DIDT=TRUE
BOOST
5
0.1UF
R7085
G
10%
2 25V
X5R
402
2 25V
X5R
1
4
10%
1UF
C7085
G
1
4
C7086
3 2 1
NO STUFF
1
PPDCIN_G3H_INRUSH_FET
P5V5G3H_BOOST
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
OMIT
OMIT
D
PPCHGR_DCIN_D_R
2
5%
1/16W
MF-LF
402
S
=PPDCIN_S5_CHGR
0
1
3
Q7080
9
Q7085
NO STUFF
5%
1/16W
MF-LF
402
R7093
PPCHGR_DCIN_D
64
CRITICAL
FROM ADAPTER
7
Reverse-Current Protection
CRITICAL
6
Inrush Limiter
5.5V "G3Hot" Supply
NO STUFF
2
C7056
0.1UF
1
10%
16V 2
X5R
402-1
C7057
3 S
2
1
1
0.01UF
10%
16V
X7R-CERM 2
0402
D
5
PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
6 63
G
4
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
(PPVBAT_G3H_CHGR_R)
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
CHGR_ICOMP_RC
1
C7042
C7011 1
0.068UF
0.01UF
10%
10V
2 X5R-CERM
0402
10%
16V
X7R-CERM 2
0402
1
C7000
C7005 1
1UF
0.22UF
10%
2 10V
X5R
402-1
C7026 1
0.001UF
20%
25V
X5R 2
603
10%
50V
X7R-CERM 2
0402
TABLE_5_HEAD
PART#
GND_CHGR_AGND
64
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
BOM OPTION
TABLE_5_ITEM
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
107S0129 1
RES,5MOHM,1%,1W,0612,4-TERM
R7050
DESCRIPTION
REFERENCE DES
CRITICALBATT_2S
A
SYNC_MASTER=JACK_J30
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
PART NUMBER
QTY
CRITICAL
376S0927
2
FDMC3020DC
Q7030,Q7035
CRITICAL
CHARGER_POWER_FET:FAIR
376S0761
1
SI7137DP
Q7055
CRITICAL
376S0966
2
RJK03E1DNS
Q7030,Q7035
CRITICAL
CHARGER_POWER_FET:REN
376S0845
1
SI7149DP
Q7080
CRITICAL
376S0845
1
SI7149DP
Q7085
BOM OPTION
PBus Supply & Battery Charger
DRAWING NUMBER
Apple Inc.
CRITICAL
NOTICE OF PROPRIETARY PROPERTY:
8
7
6
5
4
3
051-9058
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT
SYNC_DATE=09/27/2011
PAGE TITLE
6.0.0
BRANCH
PAGE
70 OF 109
SHEET
64 OF 86
1
A
8
7
6
5
4
3
2
1
System Agent Power Supply
D
D
7
7
=PPVIN_S0_VCCSAS0
=PP5V_S0_VCCSAS0
CRITICAL
1
R71011
C7101
VCCSAS0_BOOT_RC
R71301
0
5%
1/10W
MF-LF
603 2
19
20
PVCC
IN
=PVCCSA_EN
IN
CPU_VCCSASENSE 11.62K2
CPU_VCCSASENSE_DIV
1%
1/16W
MF-LF
402
1
R7147
41.2K
1%
1/16W
MF-LF
2 402
R7153
VCCSAS0_RTN
1.62K2
73
OUT
VCCSAS0_OCSET
11 OCSET
VCCSAS0_FSEL
2
C7103 1
0.022UF
R71031
10%
16V
X5R-X7R-CERM 2
0402
PLACE_NEAR=C1761.2:1mm1
R7148
1
R7152
C7106 R7154
4.64K
4.64K
10PF
1%
5%
1/16W
50V
2 C0G-CERM
MF-LF
0402
2 402
1%
1/16W
MF-LF
2 402
1
C7105
10PF
5%
50V
2 C0G-CERM
0402
VCCSAS0_SET_R
1
1%
1/16W
MF-LF
2 402
1
17
4
CRITICAL
VCCSAS0_DRVH
GATE_NODE=TRUE
DIDT=TRUE
7
VCCSAS0_LL
1
2
FDV0630H-SM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
2
4
7
6A Max Output
f = 300 kHz
8 SET0
9 SET1
3 4 5
6 VID0
5 VID1 (ENDIAN SWAP)
GND
1
PGND
R7141
VCCSAS0_CS_P
85
VCCSAS0_CS_N
C7140
1000PF
2
CPU_VCCSA_VID<1>
CPU_VCCSA_VID<0>
1
5%
25V
NP0-C0G
402
R7149
499K
1
R7142
1K
1%
1/16W
MF-LF
2 402
1
(VCCSAS0_OCSET)
1%
1/16W
MF-LF
2 402
85
1K
1%
1/16W
MF-LF
402 2
IN
1
MIN_LINE_WIDTH=0.6 mm 3
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
=PPVCCSA_S0_REG
GATE_NODE=TRUE
DIDT=TRUE
82.5K2
12
PPVCCSA_S0_REG_R
152S0913
1
IN
1%
1W
MF-1
0612
1.0UH-7.7A
SWITCH_NODE=TRUE
DIDT=TRUE
C
0.001
L7100
1
C7102
12
R7140
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VCCSAS0_DRVL
RTN
10%
2 16V
X5R
603
1%
1/16W
MF-LF
402
RJK0222DNS
6
13 FSEL
2.2UF
R7150
Q7100
2
14 PGOOD
VCCSAS0_SET1
5%
1/16W
MF-LF
402 2
52.3K
BOOT 18
LGATE 1
VCCSAS0_SET0
0
1
376S0944
CRITICAL
HWSON
PHASE 16
SREF
3
XW7101
SM
1
12 VO
VCCSAS0_RTN_DIV
1%
1/16W
MF-LF
402
B
7
VCCSAS0_VO
PLACE_NEAR=C7121.1:3mm
DIDT=TRUE
CRITICAL
UGATE
OMIT_TABLE
10 FB
VCCSAS0_SREF
PVCCSA_PGOOD
1
UTQFN
15 EN
C7122
5%
25V
2 NP0-C0G
402
PLACE_NEAR=Q7100.2:1mm
2
12
73
0.22UF
10%
10V
2 CERM
402
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
U7100
R7151
C7130
1000PF
10%
25V 2
X5R
603-1
20%
16V 2
POLY
B1A-SM
VCCSAS0_VBST
ISL95870A
C
1
1
1
1UF
39UF-0.027OHM
PP5V_S0_VCCSAS0_VCC
VCC
C7121
C7120 1
DIDT=TRUE
20%
2 10V
X5R
603
5%
1/16W
MF-LF
402 2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
10UF
2.2
B
OCP = R7141 x 8.5uA / R7140
OCP = 8.5A
(VCCSAS0_VO)
XW7100
SM
VCCSAS0_AGND
1
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
PLACE_NEAR=U7100.3:1mm
INTEL TABLE:
VID1
VID0
353S3074 IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P
1
U7100
CRITICAL
Voltage
0
0
0.9V
1
0
0.8V
0
1
0.725V
1
1
0.675V
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/28/2011
PAGE TITLE
System Agent Supply
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
.
8
7
6
5
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
71 OF 109
SHEET
65 OF 86
1
A
8
7
6
5
4
3
2
1
5V_S3/3.3V_S5 POWER SUPPLY
D
D
VOUT = (2 * RA / RB) + 2
VOUT = (2 * RC / RD) + 2
<RA>
<RB>
<RD>
<RC>
21K
13.7K
10K
6.49K
R7267
XW7203
SM
2
5V_S3_VFB_XW7203
1
1%
1/16W
MF-LF
402
1
R7268
1%
1/16W
MF-LF
402
1
2
R7269
1%
1/16W
MF-LF
402
1
2
R7270
1%
1/16W
MF-LF
402
1
2
XW7204
SM
2
3V3S5_VFB_R7270
PLACE_NEAR=L7260.1:1 MM
2
1
PLACE_NEAR=L7220.2:1 MM
XW7205
SM
73
C
C
R7273
XW7202
1
SM
5%
1/16W
MF-LF
402
10%
2 25V
X5R
603-1
1
PLACE_NEAR=C7291.1:1 MM
1
100K
C7272
1UF
2
2
=PP5V_S5_LDO
=PPVIN_S5_5VS3
C7281
1UF
1
C7260
5
4
G
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2
CRITICAL
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
S
L7260
MAX CURRENT = 12.947A
PWM FREQ. = 300 KHZ
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2 1
DIDT=TRUE
1
2
PCMB104E4R7-SM
20 LL1
P5VS3_DRVL
5
0.001UF
20%
50V
2 CERM
402
C7290
10UF
20%
2 10V
X5R
603
D
G
RJK03E0DNS
220UF
24 VO1
2 VFB1
4
DRVH2 10
DRVL2 12
1 ENTRIP1
PP5V_S5_LDO
P3V3S5_VBST
P3V3S5_DRVH
1UF
10%
2 25V
X5R
603-1
P3V3S5_VO2
P3V3S5_VFB
VCLK 18
R7271
115K
1%
1/16W
MF-LF
2 402
S
3 2 1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
DIDT=TRUE
PLACE_NEAR=C7241.1:3MM
CRITICAL
7
DIDT=TRUE
L7220
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2.2UH-14A
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1
2
IHLP2525CZ-SM1
6
DIDT=TRUE
B
=PP3V3_S5_REG
7
3 4 5
CRITICAL
1
1
5V3V3_REG_EN
C7273
1
2
1
C7251
20%
2 6.3V
X5R
603
20%
2 6.3V
POLY
B1A-SM
1%
1/16W
MF-LF
402
1
C7250
10UF
150UF
78.7K
10UF
20%
2 6.3V
X5R
603
R7272
1
C7253
0.001UF
20%
50V
2 CERM
402
MAX CURRENT = 7.45A
PWM FREQ. = 375 KHZ
2
XW7201
SM
Q7221
PLACE_NEAR=U7200.25:1 MM
P5V3V3_PGOOD
SOT563
2 G
0.001UF
RJK0216DPA
SSM6N37FEAPE
=P5VS3_EN_L
20%
50V
2 CERM
402
NC
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
IN
20%
ELEC
B6S-SM
82UF
WPAK2
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
P3V3S5_ENTRIP
GND_5V3V3S5_SGND
73
C7240
2 16V
CRITICAL
P3V3S5_VBST_R
PGOOD 23
EN0 13
GND THRM_PAD
C7242
1
Q7220
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
P3V3S5_DRVL
VO2 7
1
PLACE_NEAR=Q7220.2:1MM
2
P3V3S5_LL
VFB2 5
ENTRIP2 6
1
D 6
5%
1/16W
MF-LF
402
1
C7241
DIDT=TRUE
HWSON-8
20%
2 6.3V
ELEC
D1A-SM
9
LL2 11
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
Q7261
C7291
U7200
QFN
1
0.1UF
0
VREG5 17
15
C7293
1
P5VS3_ENTRIP
OMIT
CRITICAL
CRITICAL
1
21 DRVH1
19 DRVL1
P5VS3_VFB
1
VREG3 8
4 TONSEL
P5VS3_LL
P5VS3_VO1
=PP5V_S3_REG
C7220
R7220
VREF
P5VS3_VBST22 VBST1 CRITICAL VBST2
P5VS3_DRVH
DIDT=TRUE
4.7UH-13A-15MOHM3
CRITICAL
1
10%
16V
X7R-CERM 2
0402
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
HWSON-8
VIN
14 SKIPSEL
R7260
10%
0
16V
5%
X7R-CERM
1/16W
0402
MF-LF
402
2
1 P5VS3_VBST_R 1
D
Q7260
RJK03E1DNS
C7271
10%
10V
2 CERM
402
0.1UF
=PPVIN_S5_3V3S5 7
1UF
0.22UF
PLACE_NEAR=C7281.1:3MM
OMIT
CRITICAL
C7270
20%
10V
2 CERM
603
P5VP3V3_VREF
10%
2 25V
X5R
603-1
PLACE_NEAR=Q7260.5:1MM
20%
2 16V
ELEC
B6S-SM
3
1
C7280
82UF
20%
50V
2 CERM
402
25
1
0.001UF
16
C7282
1
TPS51125
1
7
7
P5VP3V3_REG3
CRITICAL
B
1
=PPVIN_S5_5VS3
66 7
66 7
2
=P5V3V3_REG_EN
S 1
D 3
73
Q7221
SSM6N37FEAPE
SOT563
A
PART NUMBER
DESCRIPTION
REFERENCE DES
376S0927
QTY
1
FDMC3020DC
Q7260
CRITICAL
5V_S3_POWER_FET:FAIR
BOM OPTION
376S0928
1
FDMC2514SDC
Q7261
5V_S3_POWER_FET:FAIR
376S0966
1
RJK03E1DNS
Q7260
5V_S3_POWER_FET:REN
73
IN
=P3V3S5_EN_L
5 G
S 4
SYNC_MASTER=JACK_J30
5V/3.3V SUPPLY
DRAWING NUMBER
Apple Inc.
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
376S0895
1
Q7261
RJK03E0DNS
SYNC_DATE=08/22/2011
PAGE TITLE
R
NOTICE OF PROPRIETARY PROPERTY:
7
6
5
4
3
2
SIZE
D
6.0.0
5V_S3_POWER_FET:REN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
051-9058
REVISION
BRANCH
PAGE
72 OF 109
SHEET
66 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
7
=PPVIN_S3_DDRREG
TABLE_ALT_HEAD
CRITICAL
1
C7330
39UF-0.027OHM
7
20%
2 16V
POLY
B1A-SM
=PPVIN_S0_DDRREG_LDO
CRITICAL
CRITICAL
1
1
C7331
C7332
1
1UF
39UF-0.027OHM
0.001UF
10%
2 25V
X5R
603-1
20%
2 16V
POLY
B1A-SM
C7333
10%
50V
2 X7R-CERM
0402
1
PART NUMBER
C7334
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
33UF
20%
2 16V
POLY-TANT
CASED2E-SM
128S0299 128S0218
ALL
128S0093 128S0218
ALL
TABLE_ALT_ITEM
NO STUFF
PLACE_NEAR=Q7330.5:1mm
=PP5V_S3_DDRREG
7
PLACE_NEAR=C7332.1:3mm
C7301 1
10UF
20%
10V 2
X5R
603
C7300 1
10UF
5
PLACE_NEAR=U7300.2:1mm
20%
10V 2
X5R
603
PLACE_NEAR=U7300.12:1mm
D
2
(DDRREG_DRVH)
C
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
VLDOIN
12 V5IN
31
IN
26 8
IN
73
DDRREG_FB
=DDRVTT_EN
=DDRREG_EN
IN
VTT Enable
VDDQ/VTTREF Enable
DDRREG_1V8_VREF
U7300
17 S3
16 S5
TPS51916
1
R7315
20.0K
0.1UF
DDRREG_MODE
DDRREG_TRIP
1%
1/16W
MF-LF
2 402
10%
16V
X7R-CERM 2
0402
PLACE_NEAR=U7300.6:1mm
PLACE_NEAR=U7300.8:5mm
DRVL
CRITICAL PGOOD
VDDQSNS
8 REFIN
VTT
19 MODE
VTTSNS
18 TRIP
VTTREF
11
20
9
3
1
7
3
D
0.01UF
1%
1/16W
MF-LF
2 402
DDRREG_P1V35_L
C7316
R7317 1R7318
1
10%
16V
2 X7R-CERM
0402
PLACE_NEAR=U7300.8:1mm
PLACE_NEAR=U7300.8:5mm
200K
1%
1/16W
MF-LF
2 402
Q7319
DDRREG_DRVL GATE_NODE=TRUE
DIDT=TRUE
DDRREG_PGOOD
OUT 8
DDRREG_VDDQSNS
=PPVTT_S0_DDR_LDO XW7360
1
2
C7360 1
10UF
20%
6.3V 2
X5R
603
2
XW7300
SM
C7350 1
1
CRITICAL
1
CRITICAL
C7361
CRITICAL
20%
2 2.0V
POLY-TANT
CASE-B2-SM1
RJK0226DNS
G
4
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
1
HVSON-333
C7341 1
OMIT
330UF
S
20%
2.0V 2
POLY-TANT
CASE-B2-SM1
1 2 3
C7346
0.001UF
CRITICAL
10UF
20%
2 6.3V
X5R
603
Vout = 1.5V
14.1A max output
(Q7335 limit)
f = 400 kHz
C7340
330UF
Q7335
(DDRREG_DRVL)
1
=PPDDR_S3_REG
1
C7345
10%
50V
2 X7R-CERM
0402
10UF
2
20%
2 6.3V
X5R
603
XW7301
SM
1
PLACE_NEAR=C7340.1:1mm
PLACE_NEAR=C3101.1:3mm
to memory
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
0.22UF
VESM
0.88UH-20%-19A-2.3MOHM
1
2
MPCG1040LR88-SM
D
CRITICAL
L7330
1 2 3
10%
25V
X5R
402
2
C7360, C7361 close
CRITICAL
5
=PPVTT_S3_DDR_BUF
5
C
OMIT
S
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
PLACE_NEAR=C7361.1:3mm
PLACE_NEAR=C3101.1:1mm
1%
1/16W
MF-LF
2 402
1
SM
DDRREG_VTTSNS
66.5K
PLACE_NEAR=U7300.19:3mm PLACE_NEAR=U7300.18:3mm
SSM3K15AMFVAPE
(DDRREG_LL)
DIDT=TRUE
21
100K
1%
1/16W
MF-LF
2 402
NO STUFF
1
HVSON-3333
DDRREG_VBST_RC
GATE_NODE=TRUE
VTT THRM
GND PAD
4
R7316
150K
7
1
10
R7319
0
RJK0225DNS
0.1UF
DIDT=TRUE
QFN
PGND GND
1
MF-LF
1/16W
2
CRITICAL
Q7330
G
C7325
MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm
10mA max load
NO STUFF
402
5%
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
SWITCH_NODE=TRUE
6 VREF
C7315 1
DDRREG_VBST
DDRREG_DRVH
DDRREG_LL
VBST 15
DRVH 14
SW 13
R7325
4
10%
10V
CERM 2
402
PLACE_NEAR=U7300.21:1mm
2
S
G 1
B
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V
MEM_VDD_SEL_1V5_L
PART NUMBER
IN
QTY
B
23
DESCRIPTION
REFERENCE DES
376S0979
1
FDMC0225
Q7330
CRITICAL
DDR_POWER_FET:FAIR
BOM OPTION
376S0874
1
FDMC0202S
Q7335
DDR_POWER_FET:FAIR
A
SYNC_MASTER=JACK_J30
SYNC_DATE=07/28/2011
PAGE TITLE
1.5V DDR3 Supply
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
73 OF 109
SHEET
67 OF 86
1
A
8
7
6
5
4
3
=PP5V_S0_CPUIMVP
2
1
7 69
R7401
PP5V_S0_CPUIMVP_VCC
68
10
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
D
7
2
5%
1/16W
MF-LF
402
=PPVCCIO_S0_CPUIMVP
=PPVIN_S0_CPUIMVP
1
1
R7480
1%
1/16W
MF-LF
2 402
PLACE_NEAR=U7400.16:2mm
29
19
Note: value needs scrubbing
VDDB
VCC 46
PLACE_NEAR=U7400.19:2mm
PLACE_NEAR=U7400.29:2mm
1
MAX15119GTM
CPUIMVP_AXG_PWM2
NC
C7450
24
43PF
OUT
73
OUT
78 12
IN
47
EN
CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L
21
23
22
VDIO
CLK
ALERT*
5.76K
R7466
1
1%
1/16W
MF-LF
2 402
1
1
1
R7462
NOSTUFF
196K
NONE
NONE
NONE
2 402
SR
CPUIMVP_IMAXA
CPUIMVP_IMAXB
35
36
IMAXA
IMAXB
1%
1/16W
MF-LF
2 402
R7460
8
215K
CRITICAL
R7469
R7467
1
100KOHM
100KOHM
0402
0402
1%
1/16W
MF-LF
2 402
1
R7465
R7463
200K
2
137K
1%
1/16W
MF-LF
2 402
1
R7461
137K
OUT
69
OUT
69
1
C7408
150PF
1
OUT
BSTB
DHB
LXB
DLB
14
16
15
18
CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G
CSPB2
CSPB1
CSNB
FBB
11
9
10
6
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
OUT
69
69
2
OUT
68
2
1
C
AXG_PHASE1
2
1
R7430
5%
1/20W
MF
201
0
5%
1/16W
MF-LF
2 402
CPUIMVP_ISUMG2_P
IN
69
CPUIMVP_ISUMG1_P
IN
69
CPUIMVP_ISUMG_N
IN
69 85
69
C7418
100PF
5%
25V
2 NP0-CERM
0201
1
NO STUFF
1
C7419
100PF
5%
25V
2 NP0-CERM
0201
NO STUFF NO STUFF NO STUFF
1
C7414
100PF
5%
25V
2 NP0-CERM
0201
1
C7415
100PF
5%
25V
2 NP0-CERM
0201
1
C7416
100PF
5%
25V
2 NP0-CERM
0201
NO STUFF
1
C7423
100PF
5%
25V
2 NP0-CERM
0201
C7452
1
1
10%
16V
2 X7R-CERM
0201
5%
25V
NP0-CERM
0201
R7440
10
1
2
CPU_AXG_SENSE_N
IN
12 78
5%
1/20W
MF
201
CPUIMVP_ISUMG_AVE_P
C7441 1
R7412
68
CPUIMVP_FBA
7.68K2
1
R7441
CPU_VCCSENSE_R
NO STUFF
C7442
1000PF
10%
16V
2 X7R-CERM
0201
PLACE HOLDER
10
1
2
CPU_VCCSENSE_N
IN
12 78
C7443
1000PF
10%
16V
2 X7R-CERM
0201
R7413
CPUIMVP_FBA_R
10
1
CPU_VCCSENSE_P
2
IN
12 78
5%
1/20W
MF
201
1
5%
MF
201
C7422
1000PF
NO STUFF1/20W
1
C7412
1%
1/20W
MF
201
1000PF
1
2
1
CPU_AXG_SENSE_R
10%
16V
X7R-CERM 2
0201
B
100PF
C7440
1000PF
IN
PP5V_S0_CPUIMVP_VCC
1
NO STUFF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
69
49 69 85
IN
R7410
10%
16V
X7R-CERM
0201
GND_CPUIMVP_SGND
B
CPUIMVP_ISNS2_P
CPUIMVP_ISUM_R
1
OUT
2
68
NO STUFF
1
XW7400
SM
1%
1/16W
MF-LF
2 402
PLACE_NEAR=Q7510.1:1mm
PLACE_NEAR=Q7550.1:1mm
2
200
10%
25V
X7R-CERM
0201
1000PF
69
49 69 85
IN
69
C7409
OUT
CPUIMVP_ISNS1_P
5%
1/20W
MF
201
NO STUFF
IN
CPUIMVP_ISUM2_P
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2
CPUIMVP_FBB
69
2
R7407
1%
1/16W
MF-LF
402
69
OUT
150K 2
68
44
34
32
33
31
CSPBAVE
1%
1/16W
MF-LF
2 402
CPUIMVP_ISUM
CPUIMVP_ISUM_N
CPUIMVP_FBA
OUT
200
5%
1/20W
MF
201
R7402
1
CSPA2
BSTA2
DHA2
LXA2
DLA2
1
AGND
CRITICAL
2
38
1
1%
1/16W
MF-LF
402
CPUIMVP_BOOT1
CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM1_P
CSPAAVE 41
CSNA 43
FBA 3
THERMA
THERMB
CPUIMVP_SLEW
OMIT
R7464
5.76K
1%
1/16W
MF-LF
2 402
39
40
5
20
R7468
1
POKA
POKB
CPUIMVP_VR_ON
CPUIMVP_NTC
CPUIMVP_NTCG
1
24
12
30
IN
CSPA3
VRHOT*
CRITICAL
BSTA1 25
DHA1 27
LXA1 26
DLA1 28
CSPA1 42
THRM
PAD
PGNDA
IN
78 12
45
4
49
IN
78 12
CPUIMVP_TONA
GNDSB
C
73
CPUIMVP_TONB
TONA 48
GNDSA
5%
50V
2 C0G-CERM
0402
CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD
TONB 1
DRVPWMA
7
1
DRVPWMB
37
2
OUT
CPU_PROCHOT_L
QFN
13
182K 2
PGNDB
OUT
17
69
R7406
R7403
U7400
78 46 45 10
20%
10V
2 X5R-CERM
402
130
VDDA
1%
1/16W
MF-LF
402 2
PLACE_NEAR=U7400.18:2mm
20%
10V
X5R-CERM 2
402
D
7 69
C7403
2.2UF
20%
10V
2 X5R-CERM
402
2.2UF
54.9
1
2.2UF
C7401 1
R74791
C7402
R7422
1000PF
10%
16V
2 X7R-CERM
0201
PLACE HOLDER
68
CPUIMVP_FBB
8.25K2
1
1%
1/20W
MF
201
C7462
10%
16V
2 X7R-CERM
0201
R7423
CPUIMVP_FBB_R
10
1
CPU_AXG_SENSE_P
2
IN
12 78
5%
1/20W
MF
201
100PF
1
2
5%
25V
NP0-CERM
0201
NO STUFF
A
SYNC_MASTER=JACK_J30
SYNC_DATE=08/03/2011
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
74 OF 109
SHEET
68 OF 86
1
A
8
7
69 68 7
6
1
DIDT=TRUE
CPUIMVP_BOOT1
IN
1
5%
1/16W
MF-LF
402 2
MIN_LINE_WIDTH=0.25
MM
MIN_NECK_WIDTH=0.2 MM
C7511
D
IN
CPUIMVP_UGATE1
MIN_LINE_WIDTH=0.5
MM
DIDT=TRUE
MIN_NECK_WIDTH=0.2
GATE_NODE=TRUE
MM
68
10%
16V
2 X5R-CERM
0805
2 16V
10UF
C7517
1UF
1
C7518
1
0.001UF
10%
2 25V
X5R
402
10%
16V
2 X5R-CERM
0805
C7519
1
0.001UF
10%
50V
2 X7R-CERM
0402
C7540
33UF
10%
50V
2 X7R-CERM
0402
20%
16V
2 POLY-TANT
CASED2E-SM
NOSTUFF
CRITICAL
CRITICAL
Q7510
MIN_LINE_WIDTH=0.5
DIDT=TRUE
MM
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2
MM
0.00075
L7510
1%
1W
MF
0612
0.36UH-20%-35A-0.00081OHM
PPVCORE_S0_CPU_PH1_L
1
2 PPVCORE_S0_CPU_PH1
VSW 6
7
8
4 TGR
R7510
CRITICAL
VIN 1
SON5X6
3 TG
DIDT=TRUE
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MM
VOLTAGE=1.25V
1
3
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MM
VOLTAGE=1.25V
FCUL1040-SM
SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
D
=PPVCORE_S0_CPU_REG 7
2
4
CPUIMVP_ISNS1_N
CPUIMVP_ISNS1_P
152S1271
69
OUT
49 85
OUT
49 68 85
5 BG
CPUIMVP_LGATE1
IN
1
CRITICAL
1
PLACE_NEAR=Q7510.1:1mm
PLACE_NEAR=C7517.1:3mm
DIDT=TRUE
MIN_LINE_WIDTH=1.5
MIN_NECK_WIDTH=0.2 MM
MM
20%
ELEC
B6S-SM
10UF
C7516
DIDT=TRUE
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.2 MM
MM GATE_NODE=TRUE
1
1
R7513
PGND
R7514
46.4
9
68
IN
2
376S1005
CPUIMVP_UGATE1_R
2
3
CRITICAL
1
CSD58872Q5D
5%
1/16W
MF-LF
402
CPUIMVP_PHASE1
1
0.22UF
10%
10V
2 CERM
402
DIDT=TRUE
1
1
CRITICAL
C7515
C7514
82UF
20%
16V
2 ELEC
B6S-SM
R7515
68
CRITICAL
1
C7513
82UF
R75111
3.3
4
THESE TWO CAPS ARE FOR EMC
CRITICAL
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
PHASE 1
68
5
=PPVIN_S0_CPUIMVP
CPUIMVP_BOOT1_RC
1%
1/20W
MF
201
10
1%
1/20W
MF
2 201
2
CPUIMVP_ISUM_N
IN
68 69
IN
68
PLACE_NEAR=U7400.43:1mm
1
C7571
2200PF
69 68 7
=PPVIN_S0_CPUIMVP
CPUIMVP_BOOT2_RC
5%
1/16W
MF-LF
402 2
CPUIMVP_BOOT2
MIN_LINE_WIDTH=0.25
MM
MIN_NECK_WIDTH=0.2 MM
IN
CPUIMVP_UGATE2
C7521
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
68
68
GATE_NODE=TRUE
CPUIMVP_PHASE2
IN
MIN_LINE_WIDTH=1.5
MIN_NECK_WIDTH=0.2 MM
MM
1
20%
ELEC
B6S-SM
10%
16V
2 X5R-CERM
0805
10UF
82UF
2 16V
1
C7526
10UF
1
1UF
10%
16V
2 X5R-CERM
0805
C7528
1
0.001UF
10%
2 25V
X5R
402
C7529
1
0.001UF
10%
50V
2 X7R-CERM
0402
20%
16V
2 POLY-TANT
CASED2E-SM
NOSTUFF
CRITICAL
Q7520
3 TG
SON5X6
MIN_LINE_WIDTH=0.5
DIDT=TRUE
MM
MIN_NECK_WIDTH=0.25
GATE_NODE=TRUE
MM
4 TGR
SWITCH_NODE=TRUE
R7520
CRITICAL
0.00075
L7520
VIN 1
PPVCORE_S0_CPU_PH2_L
VSW 6
7
8
DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MM
VOLTAGE=1.25V
1
3
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MM
VOLTAGE=1.25V
FCUL1040-SM
SWITCH_NODE=TRUE
152S1271
PGND
CPUIMVP_ISNS2_N
CPUIMVP_ISNS2_P
9
7 69
OUT
49 85
OUT
49 68 85
1
R7524
46.4
Removed snubber with EMC’s comment
=PPVCORE_S0_CPU_REG
2
4
R75231
376S1005
C
1%
1W
MF
0612
0.36UH-20%-35A-0.00081OHM
1
2 PPVCORE_S0_CPU_PH2
5 BG
DIDT=TRUE
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.2 MM
MM GATE_NODE=TRUE
C7530
33UF
10%
50V
2 X7R-CERM
0402
PLACE_NEAR=Q7520.1:1mm
PLACE_NEAR=C7527.1:3mm
CPUIMVP_UGATE2_R
2
C7527
1
CRITICAL
CPUIMVP_LGATE2
IN
C7525
C7524
CRITICAL
CRITICAL
CSD58872Q5D
5%
1/16W
MF-LF
402
DIDT=TRUE
1
CRITICAL
0.22UF
10%
10V
2 CERM
402
DIDT=TRUE
1
1
C7523
20%
16V
2 ELEC
B6S-SM
R7525
68
CRITICAL
82UF
1
2.2
C
1
DIDT=TRUE
R75211
IN
CPUIMVP_ISUM1_P
THESE TWO CAPS ARE FOR EMC
CRITICAL
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.25 MM
MM
PHASE 2
68
10%
10V
2 X7R-CERM
0201
10
1%
1/20W
MF
201 2
1%
1/20W
MF
2 201
CPUIMVP_ISUM_N
PLACE_NEAR=U7400.43:1mm
1
IN
68 69
IN
68
C7572
2200PF
10%
10V
2 X7R-CERM
0201
7
CPUIMVP_ISUM2_P
=PPVIN_S0_CPUAXG
THESE TWO CAPS ARE FOR EMC
CRITICAL
1
CPUIMVP_UGATE1G_R
82UF
MIN_NECK_WIDTH=0.25DIDT=TRUE
MM
MIN_LINE_WIDTH=0.5 GATE_NODE=TRUE
MM
B
C7551
0.22UF
10%
10V
CERM 2
402
CPUIMVP_BOOT1G
MIN_LINE_WIDTH=0.25
MM
MIN_NECK_WIDTH=0.2DIDT=TRUE
MM
4 TGR
CPUIMVP_UGATE1G
1
MIN_NECK_WIDTH=0.2
MM
DIDT=TRUE
MIN_LINE_WIDTH=0.5
GATE_NODE=TRUE
MM
68
68
CPUIMVP_PHASE1G
IN
C7557
1UF
1
C7558
R7550
0.001UF
C7559
1
0.001UF
33UF
L7550
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MMFCUL1040-SM
152S1271
1
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MM 3
VOLTAGE=1.05V
1%
1W
MF
0612
NOSTUFF
CPUIMVP_ISNS1G_P
R7553
46.4
PGND
1%
1/20W
MF
201
2
=PPVCORE_S0_AXG_REG
NOSTUFF
AXG_PHASE2
7 69
CRITICAL
CPUIMVP_ISNS1G_N
Q7560
OUT
SON5X6
3 TG
R7554
1%
1/20W
MF
201
IN
CPUIMVP_LGATE1G
1
IN
C7565
1
10UF
AXG_PHASE2
1
5
10K
VDD
68
IN
CPUIMVP_SKIP
2
6
TQFN
PWN
BST 1
10%
2 25V
X5R
402
AXG_PHASE2
DH 8
LX 7
DL 4
GND
9
THRM
PAD
0
5%
1/16W
MF-LF
402 2
AXG_PHASE2
CPUIMVP_BOOT2G
CRITICAL
L7560
R7560
MIN_LINE_WIDTH=0.5 MM FCUL1040-SM
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.25MM
MM
MIN_NECK_WIDTH=0.25 MM
152S1271 VOLTAGE=1.05V
VIN 1
SWITCH_NODE=TRUE
OUT
CPUIMVP_ISNS2G_P
AXG_PHASE2
MF
0612
1
1AXG_PHASE2
69
OUT
49 85
OUT
68 69 85
OUT
68
R7562
10
1%
1/20W
MF
2 201
PGND
CPUIMVP_ISUMG_N
PLACE_NEAR=U7400.10:1mm
376S1005
1
C7573 AXG_PHASE2
2200PF
10%
10V
2 X7R-CERM
0201
68
CPUIMVP_ISUMG2_P
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.2 MM
MM
AXG_PHASE2
1
C7542
0.22UF
Note: value needs scrubbing
10%
10V
2 CERM
402
1
1
DIDT=TRUE
GATE_NODE=TRUE 5%
1/16W
MF-LF
402
CPUIMVP_PHASE2G
2
100
200
1%
1/20W
MF
201 2
1%
1/20W
MF
2 201
Note: value needs scrubbing
CPUIMVP_ISUMG_AVE_P
OUT
68
SYNC_MASTER=JACK_J30
SYNC_DATE=07/28/2011
PAGE TITLE
CPUIMVP_UGATE2G_R
R7566
DRAWING NUMBER
0
5%
1/20W
MF
2 201
GATE_NODE=TRUE
SWITCH_NODE=TRUE
Note: value needs scrubbing
OUT
10%
16V
X7R-CERM
0201
CPUIMVP_ISUMG_N
Note:
4
3
Apple Inc.
1
051-9058
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
REVISION
R
CPUIMVP_ISUMG_AVE_R_P
NOSTUFF
C7568 1
5
CPU IMVP7 & AXG VCore Output
1
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.2 MM
MM
DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.2 MM
MM GATE_NODE=TRUE
6
49 69 85
R7564
DIDT=TRUE
MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_LGATE2G
OUT
AXG_PHASE2
1
R75631
85 69 68
7
=PPVCORE_S0_AXG_REG 7
CPUIMVP_ISNS2G_N
2
4
46.4
1000PF
8
B
1
3
R7561
R7567
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_UGATE2G
MIN_LINE_WIDTH=1.5
0.001UF
AXG_PHASE2
CRITICAL
CPUIMVP_ISNS1G_P
R75421
MIN_LINE_WIDTH=0.25
MM
DIDT=TRUE
CRITICAL
SKIP*
C7567
10%
50V
2 X7R-CERM
0402
PLACE_NEAR=Q7560.1:1mm
PLACE_NEAR=C7565.1:3mm
NOSTUFF
AXG_PHASE2
MAX17491
CPUIMVP_AXG_PWM2
1
DIDT=TRUE
U7542
3
A
5%
1/16W
MF-LF
2 402
AXG_PHASE2
10%
50V
2 X7R-CERM
0402
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.25 MM
MM
C7541
1UF
R7540
C7566
0.001UF
10%
2 25V
X5R
402
CPUIMVP_BOOT2G_RC
AXG_PHASE2
1
1
1UF
10%
16V
2 X5R-CERM
0805
5 BG
C7574
CPUIMVP_ISUMG1_P
C7564
1%
1/20W
MF
201 2
9
AXG PHASE 2
CRITICAL
1
68 69 85
10%
10V
2 X7R-CERM
0201PLACE_NEAR=U7400.10:1mm
=PP5V_S0_CPUIMVP
10%
16V
2 X5R-CERM
0805
VSW 6
7
8
4 TGR
CPUIMVP_ISUMG_N
DIDT=TRUE
MIN_LINE_WIDTH=0.5
MIN_NECK_WIDTH=0.2 MM
MM GATE_NODE=TRUE
10UF
33UF
85 49
10
C7563
0.36UH-20%-35A-0.00081OHM
0.00075
1
2 PPVCORE_S0_AXG2_L
1%
CPUIMVP_VSWG2
1W
CSD58872Q5D
49 85
1
2
CRITICAL
1
C7562
Reserve for acoustic noise
DIDT=TRUE
OUT
CRITICAL
1
20%
20%
2 16V
2 16V
POLY-TANT
POLY-TANT
CASED2E-SM
CASED2E-SM
CRITICAL
2
4
C7561
33UF
20%
16V
2 POLY-TANT
CASED2E-SM
2200PF
68 7
CRITICAL
1
C7560
0.00075
DIDT=TRUE
MIN_LINE_WIDTH=1.5
MM
MIN_NECK_WIDTH=0.2
MM
SWITCH_NODE=TRUE
IN
1
10%
10%
10%
10%
16V
50V
50V
2 X5R-CERM
2 25V
2 X7R-CERM
2 X7R-CERM
X5R
402
0402
0402
0805
PLACE_NEAR=Q7550.1:1mm
PLACE_NEAR=C7557.1:3mm
1
5%
1/16W
MF-LF
402
1
10UF
5 BG
2
CRITICAL
C7556
0.36UH-20%-35A-0.00081OHM
1
2 PPVCORE_S0_AXG_R
CPUIMVP_VSWG
SWITCH_NODE=TRUE
THESE TWO CAPS ARE FOR EMC
CRITICAL
1
CRITICAL
9
IN
10%
16V
2 X5R-CERM
0805
20%
2 16V
ELEC
B6S-SM
85 69 49
R7555
1
VSW 6
7
8
C7555
10UF
82UF
VIN 1
SON5X6
3 TG
1
CRITICAL
1
C7554
CSD58872Q5D
5%
1/16W
MF-LF
402 2
68
CRITICAL
1
Q7550
DIDT=TRUE
2.2
IN
CRITICAL
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.25 MM
MM
R75511
68
20%
16V
2 ELEC
B6S-SM
376S1005
CPUIMVP_BOOT1G_RC
AXG PHASE 1
C7553
6.0.0
BRANCH
C7569
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
10%
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 16V
2
X7R
II NOT TO REPRODUCE OR COPY IT
201
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
value needs scrubbing IV ALL RIGHTS RESERVED
330PF
2
PAGE
75 OF 109
SHEET
69 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
CPU VCCIO (1.05V S0) Regulator
7
7
=PPVIN_S0_CPUVCCIOS0
=PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_VBST_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
1
R7601
2.2
20%
2 10V
X5R
603
5%
1/16W
MF-LF
402 2
R7604
3.01K
1%
1/16W
MF-LF
402 2
1
R7644
2.74K
1%
1/16W
MF-LF
402 2
73
=CPUVCCIOS0_EN
IN
OUT
1
R7645
1%
1/16W
MF-LF
2 402
C7602
2.2UF
5%
50V
CERM 2
402
1
10%
16V 2
X5R
603
<Rb>
47PF
CPUVCCIOS0_FB
6
CPUVCCIOS0_SREF
4
UTQFN
EN
CRITICAL
FB
DIDT=TRUE
8
VO
CPUVCCIOS0_OCSET
7
OCSET
9 PGOOD
CPUVCCIOS0_RTN
2
CPUVCCIOS0_FSEL
5 FSEL
1
C7605
47PF
5%
50V
2 CERM
402
1
R7603
C7630
1
C7624
1UF
10%
25V
603-1
2 X5R
PLACE_NEAR=Q7630.2:1mm
PLACE_NEAR=C7624.1:3mm
C
CRITICAL
UGATE 11
CPUVCCIOS0_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
CRITICAL
FDMS3602S
POWER56
1
CPUVCCIOS0_LL
PHASE
7
R7640
CRITICAL
0.001
L7630
0.68UH-18A-3.3MOHM
1
2 PPCPUVCCIO_S0_REG_R
MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
PCMB103T
SWITCH_NODE=TRUE
DIDT=TRUE
CPUVCCIOS0_DRVL
6
1%
1W
MF-1
0612
1
3
=PPCPUVCCIO_S0_REG
2
4
2
GATE_NODE=TRUE
DIDT=TRUE
3 4 5
2.2
C7623 1
1000PF
5%
25V
NP0-C0G 2
402
CPUVCCSAS0_SNUB
1
5%
1/10W
MF-LF
603
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
7
Vout = 1.05V
R7631
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
20.1A Max Output
f = 300 kHz
NOSTUFF
PGND
0
5%
25V
2 NP0-C0G
402
20%
16V
2 POLY
B1A-SM
10%
25V
X5R
402
RTN
1
C7622
1000PF
39UF-0.027OHM
Q7630
BOOT 12
LGATE 15
CPUVCCIOS0_PGOOD
1
C7621
1UF
2
2
PHASE 10
SREF
CPUVCCIOS0_VO
NOSTUFF
1
C7631
0.001UF
10%
50V
2 X7R-CERM
0402
5%
1/16W
MF-LF
2 402
C7603
0.047UF
10%
16V
2 X7R-CERM
0402
XW7600
SM
CPUVCCIOS0_AGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
B
3
GND
2.74K
C7604 1
1
ISL95870
1%
1/16W
MF-LF
2 402
73
R7605
PVCC
1
C7620
20%
16V
2 POLY
B1A-SM
U7600
3.01K
<Ra>
1
VCC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL
1
16
1
14
CPU_VCCIOSENSE_N
5%
1/16W
MF-LF
2 402
CRITICAL
39UF-0.027OHM
0
CPUVCCIOS0_VBST
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
13
78 12
C
PP5V_S0_CPUVCCIOS0_VCC
CPU_VCCIOSENSE_P
1
78 12
C7601 R7630
10UF
1
1
2
PLACE_NEAR=U7600.1:1mm
R76411
85 49
CPUVCCIOS0_CS_P
85 49
CPUVCCIOS0_CS_N
B
3.09K
1%
1/16W
MF-LF
402 2
C7640
1000PF
2
1
5%
25V
NP0-C0G
402
1
R7642
3.09K
1%
1/16W
MF-LF
2 402
(CPUVCCIOS0_OCSET)
(CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640
OCP = 26.265A
Vout = 0.5V * (1 + Ra / Rb)
A
SYNC_MASTER=JACK_J30
SYNC_DATE=09/28/2011
PAGE TITLE
CPUVCCIO (1.05V) Power Supply
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
76 OF 109
SHEET
70 OF 86
1
A
8
7
6
5
4
3
2
1
CAESAR IV 1.2V INT.VR CMPTS
1.05V SUS LDO
CRITICAL
L7700
D
Cougar Point requires JTAG pull-ups to be powered at 1.05V in SUS.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
4.7UH-0.91A
36 24 7
=PP3V3_ENET_PHY
1
1
C7717
4.7UF
20%
2 6.3V
CERM
603
1
C7718
2
ENET_SR_LX
PLE031B-SM
PLACE_NEAR=U3900.16:1mm
0.1UF
10%
16V
2 X7R-CERM
0402
36
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
SWITCH_NODE=TRUE
DIDT=TRUE
CRITICAL
XDP_PCH
XW7700
SM
1
U7740
ENET_SR_VFB
2
PLACE_NEAR=C7725.1:1mm
PLACE_NEAR=U3900.14:1mm
PLACE_NEAR=U3900.14:3mm
36
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
TPS720105
=PP3V3_SUS_P1V05SUSLDO
7
SON
=PP1V05_SUS_LDO
4 BIAS
=PP1V2_ENET_PHY
36
3 EN
NC 2
XDP_PCH
C7740 1
PP1V2_S3_ENET_INTREG
C7725
10UF
20%
2 6.3V
X5R
603-2
1
C7726
0.1UF
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
GND
5
1UF
6
7
Vout = 1.05V
Max Current = 0.35A
OUT 1
6 IN
1
D
NC
XDP_PCH
THRM
PAD
7
1
C7741
2.2UF
10%
6.3V 2
CERM
402
10%
2 6.3V
X5R
402
10%
16V
2 X7R-CERM
0402
PLACE_NEAR=L7700.1:1mm
PLACE_NEAR=L7700.1:3mm
C
7
=PP3V3_S0_P1V8S0
1
C7760
1
22UF
C7761
1
C7768
0.1UF
20%
2 6.3V
CERM-X5R
805
1UF
10%
10%
10V
2 16V
2 X5R
X5R
402-1
402
PLACE_NEAR=U7760.A3:1mm
U7760
MAX15053EWL
=P1V8S0_EN
IN
P1V8S0_SS
C7764
R7765
0.022UF
3.24K2
10%
1
P1V8_S0_COMP_RC
P1V8S0_COMP
16V
2 X5R-X7R-CERM
0402
B2
SKIP
B3
EN
CRITICAL
LX A2
C2
SS/REFIN
C1
FB
B1
L7760
IN A3
1.0UH-20%-11A-0.013OHM
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
PGOOD C3
1
P1V8S0_PGOOD
OUT
COMP
R7760 1 C7766
GND
1%
1/16W
MF-LF
402
20.0K
1% NOSTUFF
1/16W
MF-LF
2 402
73
100PF
1%
1/16W
MF-LF
2 402
5%
50V
2 CERM
0402
1
1
C7767
2
100PF
5%
50V
CERM NOSTUFF
1500PF
10%
2 25V
X7R
402
C7762
22UF
20%
2 6.3V
X5R-CERM-1
603
P1V8_S0_RC
C7765
7
1
R7767
10K
P1V8SO_FB
1
=PP1V8_S0_REG
1
2
PIC0503H-SM
P1V8S0_SW
A1
1
CRITICAL
WLP
PLACE_NEAR=C7768.1:3mm
73
C
Vout = 1.8V
MAX CURRENT = 2A
F = 1MHZ
1.8V S0 Switcher
1
C7772
22UF
1
20%
2 6.3V
X5R-CERM-12
603
C7763
0.1UF
10%
16V
X5R
402-1
1
R7761
10K
1%
1/16W
MF-LF
2 402
0402
B
B
1.05V S0 LDO
1.5V S0 Switcher
CRITICAL
=PP1V5_S0_REG
7
Vout = 1.5V
MAX CURRENT = 0.3A
F = 1MHZ
=PP3V3_S0_P1V5S0
1
CRITICAL
CRITICAL
L7770
10UH-0.55A-330MOHM
VI
PCAA031B-SM
C7770 1
1
10uF
20%
6.3V 2
X5R
603
73
A
IN
=P1V5S0_EN
1
U7770
4
3
TPS62201
SOT23-5
FB
SW 5
EN
GND
2
7
U7780
TPS720105
SON
C7773
7
=PP3V3_S0_P1V05S0LDO
4 BIAS
7
=PP1V8_S0_P1V05S0LDO
6 IN
73
=1V05_S0_LDO_EN
=PP1V05_S0_LDO
3 EN
NC 2
10uF
2
P1V5S0_SW
20%
2 6.3V
X5R
603
C7782
1UF
1
10%
6.3V 2
CERM
402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
C7780
1UF
1
GND
5
10%
6.3V 2
CERM
402
THRM
PAD
7
7
Vout = 1.05V
Max Current = 0.35A
OUT 1
NC
1
C7781
2.2UF
10%
2 6.3V
X5R
402
SYNC_MASTER=JACK_J30
PLACE_NEAR=U7780.4:1mm
PLACE_NEAR=U7780.6:1mm
SYNC_DATE=07/28/2011
PAGE TITLE
Misc Power Supplies
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
77 OF 109
SHEET
71 OF 86
1
A
7
6
5
0
3
2
1
NO STUFF
R7803
1
4
3.3V S0 FET
2
5%
CRITICAL
Q7830
1/10W
SIA427DJ
MF-LF
603
SC70-6L
=PP3V3_S0_P3V3S0FET
=PP3V3_S0_FET
4
7
SIA427DJ
D
Q7800
7
CRITICAL
S
3.3V S4 FET
3.3V S0 FET
SC70-6L
D
1
Q7812
7
5%
1/16W
MF-LF
2 402
G
2
R7800
5.1K
1
2
3.3V S4 FET
C7800
0.01UF
P3V3S4_GATE
1
5%
1/16W
MF-LF
402
2
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
10%
16V
X7R-CERM
0402
73
MOSFET
IN
5 G
=P3V3S0_EN
91K
1
S 4
D
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
C7830
RDS(ON)
0.01UF
P3V3S0_SS
2
1
26 mOhm @1.8V
2
LOADING
5%
1/16W
MF-LF
402
3.2 A (EDP)
10%
16V
X7R-CERM
0402
3.3V_SUS FET Q7820
26 mOhm @1.8V
LOADING
2
R7830
P3V3S0_EN_L
3
10%
16V
X5R
402
P3V3S4_EN_L
S 2
=P3V3S4_EN
1
0.033UF
220K
5%
1/16W
MF-LF
2 402
G
1
IN
C7809
R7802
D 3
VESM
73
SOT563
1
Q7803
10%
16V
X5R
402
3
7
4
=PP3V3_S4_FET
1
0.033UF
10K
SSM6N37FEAPE
SSM3K15AMFVAPE
C7831
R7832
D 3
G
1
=PP3V3_S4_P3V3S4FET
S
D
7
7
1
8
CRITICAL
1.35 A (EDP)
SIA427DJ
SC70-6L
D 6
C7821
SOT563
CRITICAL
Q7810
2 G
SIA427DJ
73 72
1
0.01UF
1
2
MOSFET
SiA427
CHANNEL
P-TYPE 8V/5V
RDS(ON)
10%
16V
X7R-CERM
0402
=PP5V_S5_P5VSUSFET
C7841
1
LOADING
1.608 A (EDP)
Q7822
R7842
D 3
5 G
73 72
IN
=P5V_3V3_SUS_EN
10%
16V 2
X5R
402
5%
1/16W
MF-LF
2 402
P5VSUS_EN_L
S 4
1
0.033UF
220K
SOT563
R7840
3.3K
1
2
0.01UF
2
SiA427
CHANNEL
RDS(ON)
P-TYPE 8V/5V
16 mOhm @4.5V
LOADING
100? mA (EDP)
CRITICAL
Q7860
DMP2018LFK
DFN2563-6
=PP5V_S0_FET
7
=PP5V_S3_P5VS0FET
APN 376S0928
5
R7862
220K
B
1
SLG5AP020
2
3
TDFN
ON
CRITICAL
SHDN*
D
G
7
S
6
PG
8
NO STUFF
1
4.7UF
10%
6.3V
X5R-CERM 2
603
5
CRITICAL
D
1
P1V5S0FET_GATE
0
5%
1/16W
MF-LF
2402
Q7801
R7801
4
2
5%
P1V5S0FET_GATE_R
1/16W
MF-LF
402
SI7108DN
G
PWRPK-1212-8-HF
P5V0S0_EN_L
S
1
2 3
=PP1V5_S3RS0_FET
C7861
10%
16V
X5R
R7860
10K
1
2
TPCP8102
CHANNEL
P-TYPE
B
2
C7860
402
0.01UF
P5V0S0_SS
1
2
RDS(ON)
18 MOHM @4.5V
LOADING
1.678 A (EDP)
5%
1/16W
7
THRM
PAD
402
Q7802
9
4
5.0V S0 FET
MOSFET
0.033UF
MF-LF
GND
1
3
VCC
U7801
G
1
2
7
D
1
1
2
20%
10V
CERM
402
C7802
1
10%
16V
X7R-CERM
0402
5.0V S0 FET
=PP1V5_S3_P1V5S3RS0_FET
0.1UF
P1V5CPU_EN
MOSFET
C7840
5%
1/16W
MF-LF
402
=PP5V_S5_P1V5DDRFET
C7801
IN
7
5V SUS FET
P5VSUS_SS
1.5V S3/S0 FET
26
=PP5V_SUS_FET
31 mOhm @1.8V
SSM6N37FEAPE
7
1
SC70-6L
7
1
C7810
P3V3S3_SS
5%
1/16W
MF-LF
402
7
C
CRITICAL
D
2
100? mA (EDP)
Q7840
G
=P3V3S3_EN
5V_SUS FET
3.3V S3 FET
S
IN
47K
1
LOADING
SIA413DJ
R7810
P3V3S3_EN_L
S 1
26 mOhm @1.8V
7
1
2
P-TYPE 8V/5V
RDS(ON)
10%
16V
X7R-CERM
0402
4 7
SOT563
73
10%
16V
X5R
402
SiA427
CHANNEL
2
3
SSM6N37FEAPE
2 G
C7811
0.033UF
5%
1/16W
MF-LF
2402
1
5%
1/16W
MF-LF
402
3
D 6
=PP3V3_S3_FET
G
R7812
100K
1
Q7812
D
S
4
=PP3V3_S3_P3V3S3FET
C
=P5V_3V3_SUS_EN
MOSFET
0.01UF
P3V3SUS_SS
4
7
IN
3.3V SUS FET
C7820
R7820
P3V3SUS_EN_L 1 12K 2
S 1
7
SC70-6L
10%
16V 2
X5R
402
S
3.3V S3 FET
0.033UF
5%
1/16W
MF-LF
2 402
7
3
Q7822
SSM6N37FEAPE
=PP3V3_SUS_FET
1
G
R7822
100K
1
D
S
7
=PP3V3_S5_P3V3SUSFET
4
7
10%
16V
X7R-CERM
0402
D 3
SSM3K15AMFVAPE
1.5V S3/S0 FET
P1V5S3RS0_RAMP_DONE
OUT
MOSFET
SI7108DN
CHANNEL
N-TYPE
RDS(ON)
6 mOhm @4.5V
LOADING
5 A (EDP)
VESM
1
8
73
IN
=P5VS0_EN
G
S 2
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Power FETs
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
78 OF 109
SHEET
72 OF 86
1
A
8
7
6
5
4
3
2
S5 Rail Enables & PGOOD
73 7
73 7
10V
CERM 2
402
VDD
343S0497
1
U7941
SMC_PM_G2_EN
2
=PP3V3_S5_PWRCTL
Threshold: ??
DLY > 10 ms
S5PGOOD_DLY
1
R7941
6
IN_A
OUT_A*
(IPD)
(OD,IPU)
OUT_A
IN_B
4
3
(OD,IPU)
2:1 +
1.3V -
7
DLY_1C
C7941
220PF
P3V3S5_EN_L
MAKE_BASE=TRUE
1
C7942
Deep Sleep (S4)
66
10%
2 16V
X5R
402
PM_SLP_S5_L
1
Sleep (S3)
=P3V3S5_EN_L
OUT
0.033UF
SMC_PM_G2_ENABLE
Run (S0)
PM_SLP_S4_L
1
1
0
1
1
0
0
Deep Sleep (S5)
P3V3S5_EN_L_R
NO STUFF
MAKE_BASE=TRUE
P5V3V3_REG_EN
MAKE_BASE=TRUE
=P5V3V3_REG_EN
OUT
Battery Off (G3Hot)
1
0
0
0
0
0
0
0
S5_PWRGD
8
45 32 26 17 6
1
PM_SLP_S4_L
IN
MAKE_BASE=TRUE
2
C7970
R7911
10%
10V
X5R-CERM
0201
S5_PWRGD (old name RSMRST_PWRGD)-->SMC
SMC-->PM_DSW_PWRGD
1
U7970
6
45 17
PM_SLP_S5_L
5%
1/16W
MF-LF
1 402
PLACE_NEAR=Q7812.2:6mm
1 G
S
2
IN
P3V3_S4_EN
=P3V3S4_EN
MAKE_BASE=TRUE
SOT891
SSM3K15AMFVAPE
VESM
P3V3S3_EN
72
OUT
=TBTAPWRSW_EN
4
2
1
76
OUT
1
2
S0 ENABLE
3
IN
=P3V3S3_EN
OUT
72
=DDRREG_EN
OUT
67
=USB_PWR_EN
OUT
42
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
10%
6.3V
CERM-X5R
402
2
PLACE_NEAR=Q7812.2:6mm
PLACE_NEAR=U7300.16:6mm
73 45 26 17 8 6
IN
0
100
1
PM_SLP_S3_L
(PM_SLP_S3_R_L)
2
PM_SLP_S3_R_L
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
2
2
5%
1/16W
MF-LF
402
PLACE_NEAR=U7400.7:5mm
C7910 1 C7912
R7978
SMC_S4_WAKESRC_EN
68
R7981
20K
R7987
2
33K
5%
1/16W
MF-LF
1
402
PLACE_NEAR=U7600.3:6mm
5%
1/16W
MF-LF
402
1
2
R7988
2
R7986
1
5%
1/16W
MF-LF
402
5.1K
39K
5%
1/16W
1 MF-LF
402
PLACE_NEAR=U7770.3:6mm
=P5VS0_EN
OUT
72
=P3V3S0_EN
OUT
72
=PBUSVSENS_EN
OUT
50
PLACE_NEAR=U7760.B3:6mm
PLACE_NEAR=U1800.G18:5mm
PLACE_NEAR=U7100.15:6mm
P1V8S0_EN
=P1V8S0_EN
OUT
71
=P1V5S0_EN
OUT
71
MAKE_BASE=TRUE
7
73
=PP3V42_G3H_PWRCTL
P1V5S0_EN
2
3.3V/5.0V Sus ENABLE
C
0.1uF
=PP3V3_S5_VMON
R7956
46 45
150K
1%
1/16W
MF-LF
402 2
1
R7951
15.0K
1%
1/16W
MF-LF
2 402
IN
SMC_BATLOW_L
ALL_SYS_PWRGD
3
23 24 45 73
17
R7952
7.15K
1
1K
1
NC
7
Q2
1
ASMCC0179
NO STUFF
DFN2015H4-8
R7917
1
=PP1V05_S0_VMON 1
1K
5%
1/16W
MF-LF
402
0
S0PGD_BJT_GND_R
=PP3V3_S5_PWRCTL
R79571
100
1
P5V_DIV_VMON
5 SENSE
=PP3V3_SUS_PWRCTL
20%
10V
CERM 2
402
U7930 RESET*
=PP3V3_S0_PWRCTL
68
IN
71
IN
NO STUFF
100
1
CPUIMVP_AXG_PGOOD
2
7
70
IN
100
1
U7960
ISL88042IRTEZ
IN
PVCCSA_PGOOD
TDFN
3
(IPU)
V2MON CRITICAL
MR*
1
1
8
15.0K
1%
1/16W
MF-LF
4022
9
R7973
4
10K
353S2310
SOT23-6
MR* 3
(90K IPU)
PM_RSMRST_L
OUT
PM_ENET_EN_L
PM_RSMRST_L goes to U1800.C21
1
100
1
2
100
2
IN
WOL_EN
5
G
P3V3ENET_SS
2
1
10%
16V
X7R-CERM
0402
"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
S
Q7921
D
3
PM_WLAN_EN_L
SSM3K15AMFVAPE
2
73 45 26 17 8 6
IN
OUT
32
6
Q7925
D
1
G
S
2N7002DW-X-G
2
G
SOT-363
2
AP_PWR_EN
IN
18 23 32
PM_SLP_S3_L
1
2
5%
1/16W
MF-LF
402
(AC_EN_L)
AC_EN_L
Q7920
NO STUFF
0
IN
SMC_ADAPTER_EN
2
G
S
1
OUT
SYNC_DATE=02/15/2011
Power Control 1/ENABLE
3
R79291
D
ALL_SYS_PWRGD
SYNC_MASTER=K90I_MLB
PAGE TITLE
2N7002DW-X-G
6
SOT-363
6
C7922
0.01UF
100K 2
WLAN Enable Generation
D
5%
1/16W
MF-LF
402 2
Q7920
D
2N7002DW-X-G
DRAWING NUMBER
SOT-363
5
(PM_SLP_S3_L)
G
Apple Inc.
S
5
4
3
051-9058
4
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
6.0.0
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
23 24 45 73
5%
1/16W
MF-LF
402
7
1
SOT-363
19
R7962
2
7
3
Q7925
S0PGOOD_ISL
330
=PP3V3_ENET_FET
3
1
5%
1/16W
MF-LF
402
2N7002DW-X-G
46 45 17
1
R7922
NC
NO STUFF
R7964
D
G
0.033UF
5%
1/16W
MF-LF
402 2
17
4
100
S
C7921
10%
2 16V
X5R
402
10K
R7966
1
1
R79211
2
5%
1/16W
MF-LF
402
NC
R7971
5%
1/16W
MF-LF
402
S
R7963
65
2
100K
5%
1/16W
MF-LF
402
2
CPUVCCIOS0_PGOOD
VDD
=PP3V3_S3_P3V3ENETFET
7
VESM
5%
1/16W
MF-LF
402
20%
10V
CERM 2
402
C7931
20%
50V
2 CERM
402
2
5%
1/16W
MF-LF
402
P1V8S0_PGOOD
P5V3V3_PGOOD
1
0.001UF
5%
1/16W
MF-LF
402 2
R7968
R7965
IN
1
10K
=PP3V3_S0_VMON
66
B
SOT-23-HF
GND
R79671
R7961
1%
1/16W
MF-LF
4022
3.3V ENET FET
NTR4101P
VDD
P1V5S0_PGOOD from U7710
5 V3MON
P1V5_DIV_VMON
S0PGOOD_ISL
1
S0PGOOD_ISL 8 ALL_SYS_PWRGD_R
P1V05_DIV_VMON 6 V4MON
RST*
1
15.0K S0PGOOD_ISL
1%
S0PGOOD_ISL
1
GND THRM_PAD
1/16W
MF-LF
4022
2
R7933
0.1uF
CRITICAL
5%
1/16W
MF-LF
402 2
Version in development)
C7960
1%
1/16W
MF-LF
402 2
10%
6.3V
CERM-X5R
402
=PP3V3_SUS_PWRCTL
C7930
No stuff C7931, 12ms
Min delay time
U7930 Sense input
threhold is 3.07V
Worst-Case Thresholds:
S0PGOOD_ISL
6.04K
0.47UF
Q7922
=PP1V5_S0_VMON
1
=PP1V05_S0_VMON
73 7
S0PGOOD_ISL
1
0.1uF
1/16W
MF-LF
402 2
2
C7986
2
PLACE_NEAR=U7930.6:2.3mm
=PP5V_S0_VMON
4022
10%
6.3V
CERM-X5R
402
3.3V SUS Detect
353S2809
S0 Rail PGOOD Circuitry
A
0.47UF
10%
6.3V
CERM-X5R
402
ENET Enable Generation
73 7
VMON_Q4_BASE
2
7
R7960 S0PGOOD_ISL
6.04K R79701
1%
10K S0PGOOD_ISL
1/16W
R79721
MF-LF
1%
0.47UF
10%
6.3V
CERM-X5R
402
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")
S4_PGOOD_CT 4 CT
73 7
0.47UF
2
1
C7988
72
2
TPS3808G33DBVRG4
73 7
S
PLACE_NEAR=U7770.3:6mm
1
CRITICAL
73 7
7
G
C7981
Q4
Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V
Thresholds:
(ISL
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
OUT
1
VFRQ Low: Fix Frequency
VFRQ High: Variable Frequency
5%
1/16W
MF-LF
402
CRITICAL
3
73 7
=P5V_3V3_SUS_EN
C7987
CHGR VFRQ Generation
R7955
B
PM_SUS_EN
MAKE_BASE=TRUE
2
Q3
2
NC
50
65
OUT
C
8
VMON_Q3_BASE
2
5%
1/16W
MF-LF
402
PP1V5_S0
PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm
1
GND
Q1
R7954
=PP1V5_S0_VMON
B
70
PLACE_NEAR=U7760.B3:6mm
3
VESM
6
PM_SLP_SUS_L
Q7950
5
1%
1/16W
MF-LF
2 402
IN
4
5%
1/16W
MF-LF
402
1
73 7
6
VMON_Q2_BASE
2
D
=PVCCSA_EN
MAKE_BASE=TRUE
SSM3K15AMFVAPE
Y 4
R7953
1K
PVCCSA_EN
C
71
64
2
S0PGD_C
VMON_3V3_DIV 1
Q7931
U7940
74AUP1G3208
SOT891
1 A
SMC_BATLOW_L:100K pull up on SMC page
1
MAKE_BASE=TRUE
CHGR_VFRQOUT
VCC
=1V05_S0_LDO_ENOUT
=CPUVCCIOS0_EN OUT
CPUVCCIOS0_EN
5
20%
10V
CERM 2
402
6
7
5%
1/16W
MF-LF
402
1
C7943
S0 Rail PGOOD (BJT Version)
MAKE_BASE=TRUE
10K
PLACE_NEAR=U7940.1:2.3mm
1
=PP3V3_S0_VMON
R7931
=PP3V3_S5_PWRCTL
73 7
73 7
D
Q7911
MAKE_BASE=TRUE
74LVC1G32
2
1
5%
1/16W
MF-LF
402
53
OUT
9.1K
5.1K
5%
1/16W
MF-LF
402
PLACE_NEAR=U7300.16:6mm
NO STUFF
R7919
OUT
3
MAKE_BASE=TRUE
CPUVCORE ENABLE
CPUIMVP_VR_ON
D
DDRREG_EN
0.1UF
2
R7912
=PP3V3_S5_PWRCTL
THRM
PAD
5
0
10%
10V
X5R-CERM
0402
TPAD_VBUS_EN
PLACE_NEAR=U7970.6:3mm
46 45
1
0.068UF
2
66
5
R7974
NO STUFF
1 C7913
2
45
OUT
66
PLACE_NEAR=U5701.3:6mm
NC
ALL_SYS_PWRGD
3.3K
5%
1/16W
MF-LF
402
1
73 7
MAKE_BASE=TRUE
(OD,IPU)
=P5VS3_EN_L OUT
MAKE_BASE=TRUE
2
NC
73 45 24 23
1
1
P5VS3_EN_L
R7914
PM_SLP_S3_L
1
1
3.3V S4 ENABLE
OUT_B
DLY
GND
5%
2 25V
C0G-CERM
0402
100 2
5%
1/16W
MF-LF
402
SLG4AP012
TDFN
MAKE_BASE=TRUE
73 7
CRITICAL
9
D
1
0.1uF
20%
2
5%
1/16W
MF-LF
402
State
IN
1
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_PWRCTL Internal pull-ups 100K +/- 20%
C7940 1
45 6
1
R7913
3.3V,5V S3 ENABLE
68K
BRANCH
PAGE
79 OF 109
SHEET
73 OF 86
1
A
8
7
6
5
4
3
2
1
D
D
LCD CONNECTOR
LVDS CONNECTOR:518S0787
8
LCD_IG_PWR_EN
CRITICAL
J9000
20525-130E-01
F-RT-SM
CRITICAL
C9015
U9000
0.001UF
FPF1009
1 ON
7
=PP3V3_S5_LCD
3 VIN_2
C
GND
6
C9009
0.1UF
2
10%
16V
X7R-CERM
0402
31
10%
50V
X7R-CERM
0402
2
2
1
FERR-120-OHM-1.5A
2 VIN_1
1
1
0.001UF
10%
50V
X7R-CERM
0402
L9004
MFET-2X2-8IN
C9010
1
VOUT_1 4
PP3V3_LCDVDD_SW
VOUT_2 5
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
THRM
PAD
7
1
C9011
1
10UF
10%
16V
2 X7R-CERM
0402
20%
6.3V
X5R
603
2
L9008
1
C9012
0.1UF
6
CRITICAL
3
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
4
=PP3V3_S0_LCD
NC
2
0402-LF
7
MIN_NECK_WIDTH=0.20 MM
120-OHM-0.3A-EMI
MIN_NECK_WIDTH=0.20 MM
1
2
2
0402-LF
6
PP3V3_S0_LCD_F
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
5
6
7
(LVDS DDC POWER)
80 17 6
LVDS_IG_A_DATA_N<0>
80 17 6
LVDS_IG_A_DATA_P<0>
C
8
9
10
1
1
R9008
10K
5%
1/16W
MF-LF
2 402
8 6
LVDS_DDC_CLK
8 6
LVDS_DDC_DATA
2
R9009
80 17 6
LVDS_IG_A_DATA_N<1>
11
10K
80 17 6
LVDS_IG_A_DATA_P<1>
12
5%
1/16W
MF-LF
402
80 17 6
LVDS_IG_A_DATA_N<2>
14
80 17 6
LVDS_IG_A_DATA_P<2>
15
13
16
CRITICAL
L9080
90-OHM-100MA
DLP11S
85 6
LVDS_CONN_A_CLK_F_N
17
85 6
LVDS_CONN_A_CLK_F_P
18
LVDS I/F
SYM_VER-1
19
80 17
LVDS_IG_A_CLK_N
4
3
80 17
LVDS_IG_A_CLK_P
1
2
77 6
PPVOUT_SW_LCDBKLT
20
NC
C9020
21
1
0.001UF
10%
50V
X7R-CERM
0402
22
2
23
NC
24
LED BKLT I/F
25
26
27
28
77 6
LED_RETURN_1
77 6
LED_RETURN_2
77 6
LED_RETURN_3
77 6
LED_RETURN_4
77 6
LED_RETURN_5
33
77 6
LED_RETURN_6
34
29
30
NC
B
B
35
36
37
38
39
40
41
32
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
LVDS CONNECTOR
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
90 OF 109
SHEET
74 OF 86
1
A
C9301
DP_EXTA_ML_C_N<0>
IN
1
81 8
C9302
DP_EXTA_ML_C_P<1>
IN
C9303
DP_EXTA_ML_C_N<1>
IN
1
D
C9304
DP_EXTA_ML_C_P<2>
IN
C9305
DP_EXTA_ML_C_N<2>
IN
1
IN
DP_EXTA_ML_C_P<3>
C9306
81 8
IN
DP_EXTA_ML_C_N<3>
C9307
1
C9308
BI
C9309
DP_EXTA_AUXCH_C_N
BI
DP_EXTA_ML_N<1>
OUT
1
0.47UF
DP_EXTA_ML_P<2>
75 81
IN
C9372
83 33
IN
T29_R2D_C_N<0>
T29_R2D_C_P<0>
DP_EXTA_ML_N<2>
2
2
75 81
DP_EXTA_ML_P<3>
75 81
DP_EXTA_ML_N<3>
75 81
10% 16V
X5R-CERM
0201
1
2
10% 16V
X5R-CERM
0201
1
R9309
1
C9373
=PP3V3_S0_DPSDRVA
1
DP_EXTA_AUXCH_N
2
R9308
83 33
OUT
83 33
OUT
1
81 75
81 75
81 75
Note: Other Parade
devices use 96/B6,
so only 94/B4 are
used for this part.
81 75
81 75
81 75
81 75
NO STUFF
81 75
1
R9310
1K
5%
1/16W
MF-LF
2 402
8
IN
8
BI
1
C9311
1
0.1UF
10%
16V
2 X5R-CERM
0201
83 33
IN
83 33
IN
C9382
T29_R2D_C_N<1>
T29_R2D_C_P<1>
0.47UF
C9383
R9312
8
1K
10%
16V
2 X5R-CERM
0201
R9355
30
1
30
2
1
30
5%
MF
1/20W
201
5%
MF
1/20W
201
1
5%
MF
1/20W
201
5%
MF
1/20W
201
DP_EXTA_ML_P<1>
DP_EXTA_ML_N<1>
2
1
OUT_D1P
OUT_D1N
28
27
DP_EXTA_ML_P<2>
DP_EXTA_ML_N<2>
7 IN_D2P
8 IN_D2N
OUT_D2P
OUT_D2N
25
24
DP_EXTA_ML_P<3>
DP_EXTA_ML_N<3>
9 IN_D3P
10 IN_D3N
OUT_D3P
OUT_D3N
23
22
DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
14 IN_SCL
13 IN_SDA
AC_AUXP
AC_AUXN
20
19
DPSDRVA_I2C_CTL_EN
48
IN
48
BI
B
23 16
IN
2
83
83
83
83
83
83
83
83
1
R9353
C9363
DP_SDRVA_ML_C_P<1>
DP_SDRVA_ML_C_N<1>
1
0.1UF
C9362
DP_SDRVA_ML_C_P<2>
DP_SDRVA_ML_C_N<2>
1
0.1UF
C9367
DP_SDRVA_ML_C_P<3>
DP_SDRVA_ML_C_N<3>
1
0.1UF
C9366
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
1
0.1UF
(IPD) OUT_HPD
31
(DP_SDRVA_HPD)
C9369
32
DP_A_CA_DET
CEXT
11
DPSDRVA_CEXT
1
0.1UF
IN
C9368
75
1
0.1UF
DPSDRVA_REXT
12 REXT
DP_AUXCH_ISOL
39 AUXDDC_OFF (IPD)
1
33
OUT
33
OUT
=I2C_T29AMCU_SCL
=I2C_T29AMCU_SDA
T29DPA_HPD
T29_A_BIAS_R
T29_LSOE<0>
T29_LSOE<1>
OUT
TBT_PWR_REQ_L
48
=TBT_WAKE_L:
Desktops use PCIe WAKE#
Mobiles use S4 WAKE#
=TBT_WAKE_L
OMIT
OUT
R93301
BI
76
IN
76
OUT
18
22
2
SWCLK
5%
1/20W
MF
201
IN
76
IN
76
75
76 8
1
10K
46 75
TBT_A_HV_EN
2
OUT
1K
5%
1/16W
MF-LF
2 402
5
R9362
1
R9336
10K
R9339
5%
1/20W
MF
2 201
R9363
51
5%
1/20W
MF
201 2
C9358
0.1UF
DIN1_1+
DIN1_1-
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
19
18
AUX1+
AUX1-
DP_SDRVA_HPD
17
HPD_1
2
T29_D2R1_BIASP
T29_D2R1_BIASN
15
14
AUX2+
AUX2-
13
HPD_2
10
32
11
GPU_SEL
AUX_SEL
NC
DP_A_PWRDWN
T29_A_BIAS
20%
10V
2 CERM
402
5%
1/20W
MF
2 201
U9390
CBTL04DP081
HVQFN
DOUT_0+ 1
DOUT_0- 2
T29DPA_ML_N<3>
T29DPA_ML_P<3>
T29: Unused
OUT
76 83
76 83
BI
T29DPA_ML_N<1>
BI 76 83
T29DPA_ML_P<1>
OUT 76 83
T29: LSX_A_R2P/P2R (P/N)
DIN2_0+
DIN2_0DIN2_1+
DIN2_1-
C9391
0.1UF
20%
10V
2 CERM
402
100K
VDD
DOUT_1+ 4
DOUT_1- 5
23
22
1
0.1UF
CRITICAL
(T29_A_LSX_P2R)
(T29_A_LSX_R2P)
C9390
AUX+ 6
AUX- 7
DP_A_EXT_AUXCH_P BI
DP_A_EXT_AUXCH_N BI
T29: RX_1 Bias Sink
HPD_IN 8
DP_A_EXT_HPD
IN
B
76 83
76 83
46 75
1
R9398
100K
5%
1/20W
MF
2 201
LO=Port A
HI=Port B
THMPAD GND
SIGNAL_MODEL=T29DP_MUX
Note: U9390 ML/HPD defaults to T29 mode so that DP/T29
Display can detect host T29 support using I2C
pull-ups on ML<3>. U9390 AUX defaults to DP mode
because 100-ohm pull-downs would defeat DP Sink’s
detection of DP Source.
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
DRAWING NUMBER
1M
5%
1/16W
MF-LF
2 402
Apple Inc.
051-9058
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
SIZE
D
REVISION
R
5%
1/16W
MF-LF
2 402
4
C
51
1
DisplayPort/T29 A MUXing
T29_A_UC_ADDR
R9330 provides pads for programming/debug of MCU, please make accessible.
If project has space for 10-pin programming header it should be used.
6
27
26
P2R = Plug to Receptacle
R2P = Receptacle to Plug
33
SWDIO
7
DP_SDRVA_ML_N<1>
DP_SDRVA_ML_P<1>
35 76
75
8
DIN1_0+
DIN1_0-
5%
1/16W
MF-LF
402
75
1
R9335
1/20W
201
1/20W
201
1
VOLTAGE=3.3V
R9399
DP_SDRVA_ML_N<3>
DP_SDRVA_ML_P<3>
R9334
I2C Addr:
0x26/0x27 (Wr/Rd)
1
5%
MF
5%
MF
DP_A_BIAS2
8
1
31
30
CBTL04DP081 (353S3151) and
PI3vEDP212 (353S3055) are
footprint-compatible parts with
similar pinouts. NXP uses pin
10 for ML and HPD, Pericom uses
pin 10 for ML and pin 11 for HPD.
5%
1/16W
MF-LF
402 2
IN
1/20W
201
1
NC
1K
10K
20%
10V
2 CERM
402
T29_A_LSX_P2R
T29_A_LSX_R2P
T29_LSEO<1>
PIO0_6/SCK
PIO1_6/RXD 23
PIO0_7/CTS#
PIO1_7/TXD 24
PIO0_8/MISO/CT16B0_MAT0
PIO1_8/CT16B1_CAP0 6
PIO0_9/MOSI/CT16B0_MAT1
SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD)
R/PIO0_11/AD0 (OD)
THRM
XTALIN 4
VSS
PAD
5%
MF
PP3V3_SW_TBTAPWR
76 75
Must be 3.3V DP A port power
R9397
R9338
76 83
DP/T29 A Low-Speed MUX
5%
1/20W
MF
2 201
0.1UF
76 83
OUT
10%
16V
X7R-CERM
0402
51
C9331
OUT
VOLTAGE=3.3V
DP_A_BIAS
4
R9393
1
T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC
TBT_A_HV_EN_R
T29_A_UC_ADDR
DP_A_EXT_HPD
16
17
18
19
20
2
76 83
DP_A_BIAS0
8
2
1
76 83
IN
(D9360.2)
U9359
74LVC1G04DBDCK
1
1
20%
10V
2 CERM
402
1.5K
1
CRITICAL
5
83
2
10
11
12
13
14
15
0
5%
1/16W
MF-LF
402 2
1
1.5K
IN
Both R’s must connect
to C in star topology.
DP Path Biasing
2
R9361 1.5K 1
5% 1/20W
MF
201
R9360 1.5K 1
2
R9365
R9364
1K
OMIT_TABLE
HVQFN25
1 RESET#/PIO0_0
R/PIO1_0/AD1
2 PIO0_1/CLKOUT
R/PIO1_1/AD2
7 PIO0_2/SSEL/CT16B0_CAP0
R/PIO1_2/AD3
(IPU) SWDIO/PIO1_3/AD4
8 PIO0_4/SCL (OD)
PIO1_4/AD5/WAKEUP
9 PIO0_5/SDA (OD)
3
17
T29_LSEO<0>
DP_SDRVA_ML_P<2>
DP_SDRVA_ML_N<2>
83
Must be 3.3V DP A port power
VDD
2
1/20W
201
1/20W
201
R9384
R9385
(D9360/D9361)
83
83
5%
1/20W
MF
201
0.1UF
K
(D9382/D9383)
6.3V
0201
R9396
C9330
A
76 83
GND_VOID=TRUE (D9382/D9383)
GND_VOID=TRUE (D9361.2)
GND_VOID=TRUE
1.5K 1
2
GND_VOID=TRUE
5% 1/20W
201
1.5K 1
2 MF
5% 1/20W
MF
201
SIGNAL_MODEL=T29PIN
CKPLUS_WAIVE=NdifPr_badTerm
25
T29_A_RSVD_N
24
T29_A_RSVD_P
1
TSLP-2-7
SIGNAL_MODEL=EMPTY
1
25
IN
6.3V
0201
K
TSLP-2-7
BAR90-02LRH
CRITICAL
(All 4 D’s)
6.3V
0201
2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201
5%
1/20W
MF
201 2
21
IN
83
D9361
5% 1/20W
MF 201
DP_SDRVA_ML_P<0>
DP_SDRVA_ML_N<0>
83
U9330
48
83
83
LPC1112A
33
R9383
TSLP-2-7
BAR90-02LRH
2
83
51
CRITICAL
DP_A_PWRDWN
2
20%
X5R
2
20%
X5R
6.3V
0201
1
83
1
5%
MF
5%
MF
T29: TX_1
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>
K
A
OMIT_TABLE
R93921
PP3V3_SW_TBTAPWR
1
1
THMPAD
5
76 75
DP_A_CA_DET
2
20%
X5R
2
20%
X5R
DP_A_PWRDWN
Port A MCU
75
1.5K
GND_VOID=TRUE
TSLP-2-7
A
D9383
GND_VOID=TRUE
IC supports input
high while Vcc = 0V.
34 PD (IPD)
GND
D9382
76 83
OUT
2
GND_VOID=TRUE
K
BAR90-02LRH
OUT
D
1
3
41
4.22K
83
A
BAR90-02LRH
T29_R2D_P<1>
T29_R2D_N<1>
83
20%
6.3V
CERM 2
402-LF
PS8301 has internal
~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).
R9382
1
2
2
20% 4V
CERM-X5R-1
201
2
2.2UF
6
33
R9319
1.5K
D9360
5% 1/20W
MF 201
76 83
GND_VOID=TRUE
R9374 1.5K
R9375 1.5K
D9372/D9373: SIGNAL_MODEL=T29PIN
D9364/D9365: SIGNAL_MODEL=EMPTY
T29_D2R_C_P<1>
T29_D2R_C_N<1>
GND_VOID=TRUE
20% 4V
CERM-X5R-1
201
PLACE_NEAR=U9310.11:2 mm
C9319
K
TSLP-2-7
BAR90-02LRH
CRITICAL
(All 4 D’s)
76 83
IN
(D9372/D9373)
(D9365.2)
SC70
2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201
3 IN_HPD
CA_DET
75
A
GND_VOID=TRUE
GND_VOID=TRUE
20% 4V
CERM-X5R-1
201
2
C9359
2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201
TSLP-2-7
2
10%
16V
X7R-CERM 2
0402
2
1
1
DP_SDRVA_ML_C_P<0>
DP_SDRVA_ML_C_N<0>
(DP_SDRVA_AUXCH_P)
(DP_SDRVA_AUXCH_N)
=I2C_DPSDRVA_SCL
=I2C_DPSDRVA_SDA
0.22UF
C9361
K
BAR90-02LRH
0.1UF
18
17
38 SCL_CTL
37 SDA_CTL
1
5%
1/20W
MF
2 201
OUT_AUXP_SCL
OUT_AUXN_SDA
36 I2C_ADDR0 (IPD)
35 I2C_ADDR1 (IPD)
C9360
TSLP-2-7
IN
(D9364.2)
T29: TX_0
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>
K
A
D9365
GND_VOID=TRUE
TSLP-2-7
A
D9373
=PP3V3_S0_DPSDRVA
75 7
270
16 IN_AUXP
15 IN_AUXN
26 I2C_CTL_EN (IPU)
1
0.22UF
AUXCH Snoop Port,
used by PS8301
during training.
DPSDRVA_I2C_ADDR0
DPSDRVA_I2C_ADDR1
DP_A_PWRDWN_R
SDRV_PD
83
83
C9365
DP_SDRVA_ML_R_P<2>
DP_SDRVA_ML_R_N<2>
5%
1/20W
MF
201 2
4 IN_D1P
5 IN_D1N
OUT
83
270
30
29
1
0.22UF
0.22UF
83
30
C9364
DP_SDRVA_ML_R_P<0>
DP_SDRVA_ML_R_N<0>
R93521
OUT_D0P
OUT_D0N
DP_EXTA_HPD
83
83
2
VDD
CRITICAL
1
D9372
R9373
T29 Path
Biasing
K
BAR90-02LRH
GND_VOID=TRUE
1.5K 1
2
5% 1/20W
MF 201
20% 4V
CERM-X5R-1
GND_VOID=TRUE201
R9351
0.1UF
1 IN_D0P
2 IN_D0N
81 75
5%
1/16W
MF-LF
2 402
A
83
A
BAR90-02LRH
T29_R2D_P<0>
T29_R2D_N<0>
83
0.47UF
R9308/R9309 maintain bias on C9308/C9309
to prevent spikes when U9310 AUXDDC_OFF
transitions from high to low.
C9312
1
D9364
5% 1/20W
MF 201
2
20% 4V
CERM-X5R-1
201
2
GND_VOID=TRUE
1/20W
201
DP_EXTA_ML_P<0>
DP_EXTA_ML_N<0>
1
0.47UF
75 81
5%
MF
1
0.47UF
21
40
1
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
81 75
1
75
1.5K R9372
1
2
T29_A_BIAS_R2DP1
T29_A_BIAS_R2DN1
C9381
QFN
1%
1/16W
MF-LF
2 402
1
C9380
PS8301TQFN40GTR-A2
0
T29_D2R_C_P<0>
T29_D2R_C_N<0>
GND_VOID=TRUE
20% 4V
CERM-X5R-1
201
GND_VOID=TRUE
U9310
5%
1/20W
MF
201
IN
1/20W
201
81
2
1M
20%
6.3V
CERM 2
402-LF
R9318
8
T29_D2R_N<1>
T29_D2R_P<1>
DP A Super-Driver
Addr (W/R)
0x96/0x97
0xB6/0xB7
0x94/0x95
0xB4/0xB5
1K
IN
7 75
10% 16V
X5R-CERM
0201
PS8301 I2C Addresses:
5%
1/16W
MF-LF
402 2
8
2
5%
1M
MF
DP_EXTA_AUXCH_P 75
2
2.2UF
R9311
T29 A High-Speed Signals
2
(C9380/C9381)
1
C9310
1
1
0.47UF
T29 signals are
P/N-swapped after AC
caps to improve layout.
75 81
10% 16V
X5R-CERM
0201
=PP3V3_S0_DPSDRVA
A0
0
1
0
1
1
1
20% 4V
CERM-X5R-1
201
2
GND_VOID=TRUE
83 33
R9350
A1
0
0
1
1
1
C9371
R9354
C
C9370
20% 4V
CERM-X5R-1
GND_VOID=TRUE
201
10% 16V
0.1UF
X5R-CERM
0201
If GPU uses common pins for AUX_CH
and DDC, alias nets together at GPU.
75 7
IN
0.47UF
2
0.1UF
81 8
83 33
8
(C9370/C9371)
T29_D2R_N<0>
T29_D2R_P<0>
2
T29_A_BIAS_R2DP0
T29_A_BIAS_R2DN0
75 81
10% 16V
X5R-CERM
0201
0.1UF
DP_EXTA_AUXCH_C_P
OUT
10% 16V
X5R-CERM
0201
0.1UF
81 8
DP_EXTA_ML_P<1>
2
0.1UF
81 8
83 33
IN
0.47UF
2
0.1UF
81 8
75 81
10% 16V
X5R-CERM
0201
0.1UF
81 8
DP_EXTA_ML_N<0>
2
0.1UF
81 8
GND_VOID=TRUE
75 81
10% 16V
X5R-CERM
0201
0.1UF
3
8
28
21
81 8
DP_EXTA_ML_P<0>
2
10% 16V
X5R-CERM
0201
0.1UF
4
29
20
16
12
9
3
1
5
2
C9300
DP_EXTA_ML_C_P<0>
IN
6
1
81 8
7
33
8
6.0.0
BRANCH
PAGE
93 OF 109
SHEET
75 OF 86
1
A
8
7
6
5
4
3
2
1
3.3V/HV Power MUX
V3P3 must be S4 to support
wake from Thunderbolt devices.
=PP3V3_S4_TBTAPWRSW
7
CRITICAL
D
CRITICAL
C9487 1
C9480 1
20%
6.3V
POLY-TANT 2
CASE-B2-SM
20%
6.3V
X5R-CERM-1 2
603
1
22UF
100UF
C9481
0.1UF
19
20
1200mA
830mA
930mA (assumes 15V, 12W minimum)
IHVS3
890mA
830mA
930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
V3P3OUT 18
OUT
CRITICAL
0.1UF
U9410
10%
50V 2
X7R
603-1
10%
25V
X5R-CERM 2
0603
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
C9485 1
1
0.1UF
QFN
C9486
10UF
20%
2 6.3V
X5R
603
20%
10V
CERM 2
402
CD3210A0RGP
16 RSVD
C9411
1
0.1UF
10%
2 50V
X7R
603-1
RSVD 15
IN
=TBTAPWRSW_EN
75 35
IN
TBT_A_HV_EN
11 HV_EN
ISET_S0 10
TBTAPWRSW_ISET_S0
8
IN
=TBT_S0_EN
17 S0
ISET_S3 9
TBTAPWRSW_ISET_S3
TBTHV:P15V
73
75
PPHV_SW_TBTAPWR
12
14
VHV
C9410 1
4.7UF
D
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
V3P3
6
7
1
Max
1030mA
890mA
PP3V3_SW_TBTAPWR
20V Max
C9415
Min
1100mA
IHVS0
20%
10V
2 CERM
402
=PPHV_SW_TBTAPWRSW
7
Nominal
IV3P3
5 EN
TBTAPWRSW_ISET_V3P3
ISET_V3P3 8
THRM
PAD
R9411
22.6K
1%
1/20W
MF
201 2
22.6K
1%
1/20W
MF
201 2
<RHVS3>
1
R9412
36.5K
1%
1/20W
MF
2 201
TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0_R
TBTHV:P15V
R94131
For 12V systems:
1
22.6K
below
TBTHV:P15V
C
TBTHV:P15V
R94101
12V: See
21
1
2
3
4
13
GND
1%
1/20W
MF
2 201
<RV3P3>
1
R9414
22.6K
1%
1/20W
MF
201
2
<RHVS0>
Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.
C
ILIM = 40000 / RISET
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
114S0338
2
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
R9410,R9413
CRITICAL
BOM OPTION
TBTHV:P12V
114S0338
2
RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF
R9411,R9414
TBTHV:P12V
1
IHVS0/S3
Nominal
1120mA
Min
1090mA
Max
1170mA (12W minimum)
Thunderbolt Connector A
L9400
FERR-120-OHM-3A
2
PP3V3RHV_SW_DPAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
0603
C9400 1
C9405
0.01UF
C9490
75
IN
T29_A_BIAS_R 0.1UF
1
0.01UF
10%
50V 2
X7R
402
For J9400 T29 SMT pads
(3, 5, 17 & 19):
GND_VOID=TRUE
2
T29 Dir
10%
16V
X7R-CERM
0402
83 75
OUT
83 75
OUT
1K
5%
1/20W
MF
201
VOLTAGE=3.3V
2
SIGNAL_MODEL=EMPTY
8 75
83 75
B
8
IN
8
IN
83 75
T29_A_BIAS_D2RN1
T29_A_BIAS_D2RP1
2.2K
5%
1/20W
MF
201
GND_VOID=TRUE 2
1K
5%
1/20W
MF
201
2
4
6
8
10
12
14
16
18
20
2
SIGNAL_MODEL=EMPTY
T29DPA_ML_P<3>
T29DPA_ML_N<3>
T29: Unused
BI
BI
83 75
83 75
OUT
OUT
L9498
1
650NH-5%-0.430MA-0.52OHM
2.2K
5%
1/20W
MF
2 201
GND_VOID=TRUE
T29_D2R_C_P<1>
T29_D2R_C_N<1>
A
BAR90-02LRH
D9499
A
K
TSLP-2-7
83
83
K
TSLP-2-7
BAR90-02LRH
CRITICAL
83 75
BI
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
OUT
T29DPA_HPD
OUT
T29DPA_CONFIG1_RC
75
OUT
T29DPA_CONFIG2_RC
R94521
1M
5%
1/16W
MF-LF
402 2
8
7
1
R9451 C9494 1
1M
5%
1/16W
MF-LF
2 402
330PF
10%
50V
X7R-CERM 2
0402
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
1
C9495
330PF
10%
50V
2 X7R-CERM
0402
0.01UF
T29DPA_ML_P<2>
T29DPA_ML_N<2>
T29: TX_1
C9471
R9470
IN
75 83
IN
75 83
IN
75 83
R9471
470K
470K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
T29DPA_ML_P<1>
T29DPA_ML_N<1>
BI
B
75 83
2
T29DPA_ML_C_P<2>
20% 4V
CERM-X5R-1
T29DPA_ML_C_N<2>
201
2
4V
0.47UF 20%
CERM-X5R-1
201
GND_VOID=TRUE GND_VOID=TRUE
1
1
C9473
470K
5%
1/20W
MF
2 201
R9401
1
10%
10V
X5R-CERM 2
0201
1
C9401
1
12
2
5%
1/20W
MF
201
1
0.47UF
R9472
1
IN
75 83
IN
75 83
R9473
470K
5%
1/20W
MF
2 201
470k R’s for ESD protection
on AC-coupled signals.
0.01UF
10%
2 50V
X7R
402
SYNC_MASTER=K90I_MLB
1
SYNC_DATE=02/15/2011
PAGE TITLE
R9441
Thunderbolt Connector A
100K
5%
1/16W
MF-LF
2 402
DRAWING NUMBER
Apple Inc.
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
6
1
(Both C’s)
83
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
C9402
10%
25V
X5R-CERM
0201
2
T29DPA_ML_C_P<0>
20% 4V
CERM-X5R-1
T29DPA_ML_C_N<0>
201
1
2
4V
0.47UF 20%
CERM-X5R-1
201
GND_VOID=TRUE GND_VOID=TRUE
1
1
C9472
83
C9499
5%
50V
2 CERM
402
2
(Both C’s)
0.47UF
T29: LSX_R2P/P2R (P/N)
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
CRITICAL
30PF
1
22 21
DPACONN_20_RC
1
5%
50V
CERM 2
402
75
0.01UF
GND_DPACONN_7_C
SHIELD PINS
1
GND_VOID=TRUE
0603
SIGNAL_MODEL=EMPTY
30PF
75
C9406
1
3
5
7
9
11
13
15
17
19
2
C9498 1
A
SM PINS
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN
650NH-5%-0.430MA-0.52OHM
(Both L’s)
BI
TOP ROW
TH PINS
L9499
GND_VOID=TRUE
SIGNAL_MODEL=T29PIN
83 75
BOT ROW
GND_VOID=TRUE
C9470
GND_VOID=TRUE
1 GND_VOID=TRUE
0603
SIGNAL_MODEL=EMPTY
2
D9498
83
T29DPA_ML_P<0>
T29DPA_ML_N<0>
T29: TX_0
R9495
R9499
T29 Dir
83
2
10%
25V
X5R-CERM
0201
F-RT-THSM
GND_VOID=TRUE
1
CRITICAL
R94981
DP Dir
DSPLYPRT-M97-1
R9494
51
5%
1/20W
MF
201 2
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
J9400
GND_VOID=TRUE
1
OUT
CRITICAL
T29_D2R_C_P<0>
T29_D2R_C_N<0>
R94911
T29_A_BIAS
DP Dir
GND_DPACONN_1_C
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
94 OF 109
SHEET
76 OF 86
1
A
8
7
6
5
4
3
2
1
PPBUS S0 LCDBkLT FET
MOSFET
CRITICAL
Q9706
FDC638APZ
CHANNEL
P-TYPE
RDS(ON)
43 mOhm @4.5V
LOADING
0.715 A (EDP)
FDC638APZ_SBMS001
SSOT6-HF
5
R9788
BOTTOM
AND PPBUS_SW_BKL
ON THE SENSOR PAGE
10%
16V
X7R-CERM
0402
1%
1/16W
MF-LF
402
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
7
PLACE_NEAR=L9701.2:3mm
=PP5V_S0_BKL
CRITICAL
2
CRITICAL
L9701
D9701
33UH-1.8A-110MOHM
LCDBKLT_EN_DIV
8
1
D
*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
1
0.1UF
301K
2
C9782
2
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
603-HF
1
=PPBUS_S0_LCDBKLT
8 77
THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
3
7
2
4
D
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
6
F9700
3AMP-32V-467
1
PPBUS_SW_LCDBKLT_PWR
1
=PPBUS_SW_BKL
CRITICAL
C9712
R9789
1
1
10%
25V
X5R
805
2
2
PLACE_NEAR=L9701.1:4mm
SOD-123
C9713
0.1UF
SWITCH_NODE=TRUE
DIDT=TRUE
10%
25V
X5R
402
A
PPBUS_SW_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
1217AS-2SM
10UF
147K
1%
1/16W
MF-LF
2 402
2
K
PLACE_NEAR=U9701.A5:3mm
PPVOUT_SW_LCDBKLT
CRITICAL
RB160M-60G
1
C9796
1
220PF
2
PLACE_NEAR=L9701.1:3mm
CRITICAL
C9797
1
10UF
10%
50V
X7R-CERM
0402
2
C9799
6 74
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
10UF
10%
50V
X5R
1210-1
2
10%
50V
X5R
1210-1
PLACE_NEAR=D9701.2:5mm
LCDBKLT_EN_L
PLACE_NEAR=D9701.2:3mm
Q9707
D 3
SSM6N15AFE
SOT563
PLACE_NEAR=U9701.D1:5mm
PLACE_NEAR=U9701.D1:3mm
C9710
5
8
IN
G
S 4
LCD_BKLT_EN
LCDBKLT_DISABLE
Q9707
1
1
0.01UF
10%
25V
X5R
603-1
10%
16V
X7R-CERM
0402
2
2
XW9720
C9714
1UF
SM
PPVOUT_SW_LCDBKLT_FB
VOLTAGE=40V
MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM
1
2
PLACE_NEAR=C9797.1:5mm
D 6
7
SSM6N15AFE
=PP3V3_S0_BKL_VDDIO
SOT563
PLACE_NEAR=U9701.C4:4mm
C
C9711
C
1
0.1UF
IN
10%
16V
X7R-CERM
0402
S 1
BKLT_PLT_RST_L
2
10K
C4
R9755
1
C1
24
G
D1
2
2
VIN
VDDIO VLDO
5%
1/16W
MF-LF
402
U9701
25-BUMP-MICRO
10K
1
5%
1/16W
MF-LF
402
R9753
IN
BI
=I2C_BKL_1_SDA
1
BKL_FSET
2
5%
1/16W
MF-LF
402
B4
ISET
FSET
B1
BKLT:PROD
B2
R9717
FB
PLACE_NEAR=U9701.E5:10mm
A5
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
2
R9731
301K
B
1%
1/16W
MF-LF
402
R9704
1
33
2
5%
1/16W
MF-LF
402
1
BKL_PWM
BKL_EN
A4
PWM
A3
EN
C3
TP_BKL_FAULT
R9715
D4
SCLK
SDA
FAULT
CRITICAL
PLACE_SIDE=BOTTOM
100K
1%
1/16W
MF-LF
1 402
B5
LCD_BKLT_PWM
2
D3
C9704
OUT1
E5
OUT2
OUT3
D5
OUT4
OUT5
E3
OUT6
E1
C5
E2
BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
BOTTOM
1
90.9K
Fpwm=9.62kHz
see spec for others
1%
1/16W
MF-LF
402
2
6 74
0
LED_RETURN_2
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
OUT
6 74
OUT
6 74
OUT
6 74
OUT
6 74
OUT
6 74
B
R9719
PLACE_NEAR=U9701.C5:10mm
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0
LED_RETURN_3
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
BKLT:PROD
R9714
R9720
16.2K
2
OUT
BKLT:PROD
I_LED=22.7mA
R9716 1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
BOTTOM
5%
50V
C0G-CERM
0402
LED_RETURN_1
2
R9718
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
33PF
2
0
5%
1/16W
MF-LF
402
BKLT:PROD
PLACE_NEAR=U9701.D5:10mm
GND_SW
GND_SW
1
BKL_SCL
BKL_SDA
A2
2
GND_L
0
PPBUS_SW_LCDBKLT_PWR
IN
B3
SW_0
SW_1
A1
1
5%
1/16W
MF-LF
402
8
FILTER
E4
R9757
77 8
C2
BOTTOM
Addr: 0x58(Wr)/0x59(Rd)
48
0
BKL_ISET
VSYNC
GND_S
48
=I2C_BKL_1_SCL
BKL_FLTR
2
D2
LP8550
BKL_VSYNC_R
R9741
0
PLACE_NEAR=U9701.E3:10mm
1%
1/16W
MF-LF
402
1
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
XW9710
SM
GND_BKL_SGND
1
BOTTOM
LED_RETURN_4
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
2
BKLT:PROD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
R9721
0
PLACE_NEAR=U9701.E2:10mm
I_LED=369/Riset
(EEPROM should set EN_I_RES=1)
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM
LED_RETURN_5
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
BKLT:PROD
R9722
0
PLACE_NEAR=U9701.E1:10mm
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM
A
PART NUMBER
103S0198
103S0198
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719
BKLT:ENG
3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722
BKLT:ENG
LED_RETURN_6
2
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
SYNC_MASTER=J31_MLB
10.2 ohm resistors for current
measurement on LED strings.
SYNC_DATE=07/08/2011
PAGE TITLE
LCD Backlight Driver
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
97 OF 109
SHEET
77 OF 86
1
A
8
7
6
5
CPU Signal Constraints
4
3
2
1
CPU Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
CPU_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
PCIE_85D
PCIE_PCH_TX
DMI_S2N
PCIE_85D
PCIE_PCH_TX
DMI_N2S
PCIE_85D
PCIE_PCH_RX
DMI_N2S
PCIE_85D
PCIE_PCH_RX
FDI_DATA
PCIE_85D
PCIE_PCH_RX
FDI_DATA
PCIE_85D
PCIE_PCH_RX
CPU_50S
CPU_AGTL
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>
CPU_50S
CPU_AGTL
FDI_LSYNC<1..0>
9 17
CPU_50S
CPU_AGTL
FDI_INT
9 17
CPU_PECI
CPU_50S
CPU_COMP
CPU_PECI
10 19 46
PM_SYNC
CPU_50S
CPU_AGTL
PM_MEM_PWRGD
CPU_50S
CPU_AGTL
PM_SYNC
PM_MEM_PWRGD
CPU_50S
CPU_ITP
XDP_DBRESET_L
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_50S
CPU_AGTL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
D
CPU_AGTL
*
=STANDARD
DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
DMI_S2N
TABLE_PHYSICAL_RULE_ITEM
9 17
9 17
9 17
9 17
9 17
9 17
9 17
TABLE_SPACING_RULE_ITEM
?
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
D
TABLE_SPACING_RULE_ITEM
CPU_8MIL
*
8 MIL
?
TABLE_SPACING_RULE_ITEM
CPU_COMP
*
20 MIL
?
CPU_ITP
*
=2:1_SPACING
?
CPU_VCCSENSE
*
25 MIL
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
10 17
10 17 26
Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
10 23 24
SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7
PCI-Express
10 23
10 23
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCIE_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
CPU_50S
CPU_AGTL
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
CPU_SM_RCOMP
CPU_27P4S
CPU_COMP
TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
20 MIL
?
LINE-TO-LINE SPACING
WEIGHT
CPU_50S
CPU_ITP
CPU_50S
CPU_AGTL
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
PM_THRMTRIP_L
DMI_CLK100M
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
CPU_CATERR_L
TABLE_SPACING_RULE_ITEM
CLK_PCIE
*
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
C
*
=3X_DIELECTRIC
LAYER
LINE-TO-LINE SPACING
WEIGHT
PCIE_PCH_TX2TX
TOP,BOTTOM
=4X_DIELECTRIC
*
=4X_DIELECTRIC
?
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PCIE_PCH_TX2RX
TOP,BOTTOM
=5X_DIELECTRIC
?
PCIE_PCH_RX2RX
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PCIE_PCH_RX2TX
*
=4x_DIELECTRIC
?
*
=3x_DIELECTRIC
?
CLK_PCIE_90D
CLK_PCIE
DMI_CLK100M
CLK_PCIE_90D
CLK_PCIE
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PCIE_PCH_2OTHER
TABLE_SPACING_RULE_ITEM
PCIE_PCH_RX2TX
TOP,BOTTOM
=4x_DIELECTRIC
?
PCIE_PCH_2OTHER
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
I125
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
I126
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
I127
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
I128
ITPCPU_CLK100M
CLK_PCIE_90D
CLK_PCIE
CPU_27P4S
CPU_COMP
CPU_27P4S
CPU_COMP
XDP_TDI
CPU_50S
CPU_ITP
XDP_TDO
CPU_50S
CPU_ITP
XDP_TMS
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PCIE_PCH_TX
*_PCH_TX
*
PCIE_PCH_TX2TX
9 23
10 45
8 12
10 45 46 68
10 19 23
10 19 46
?
TABLE_SPACING_RULE_ITEM
PCIE_PCH_RX2RX
10
TABLE_SPACING_RULE_ITEM
?
PCIE_PCH_TX2RX
10
10
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
PCIE_PCH_TX2TX
PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
CPU_CFG<11..0>
CPU_CATERR_L
CPU_VCCIO_SEL
I121
EDP_COMP
CPU_PEG_COMP
C
10 16
10 16
10 16
10 16
16 23
16 23
23
23
9
9
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_PCH_RX
*
PCIE_PCH_TX2RX
PCIE_PCH_RX
*_PCH_RX
*
PCIE_PCH_RX2RX
PCIE_PCH_RX
*_PCH_TX
*
PCIE_PCH_RX2TX
PCIE_PCH_TX
*
*
PCIE_PCH_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_RX
*
*
PCIE_PCH_2OTHER
XDP_TRST_L
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
B
CPU_50S
CPU_ITP
XDP_BPM_L
CPU_50S
CPU_ITP
XDP_BPM_R_L
CPU_50S
CPU_ITP
(FSB_CPURST_L)
CPU_50S
CPU_ITP
CPU_VCCAXG_SENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCAXG_SENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCAXG_SENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCAXG_SENSE
CPU_27P4S
CPU_VCCSENSE
I115
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I116
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I117
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I118
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I119
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I120
CPU_VALSENSE
CPU_27P4S
CPU_VCCSENSE
I122
CPU_SVIDALERT_L
CPU_50S
CPU_COMP
I123
CPU_SVIDSCLK
CPU_50S
CPU_COMP
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L<3..0>
CPU_CFG<15..12>
XDP_CPURST_L
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
10 23
10 23
10 23
10 23
10 23
10 23
9 23
23
12 68
CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>
B
12 68
12 70
12 70
12 68
12 68
12
12
9
9
9
9
CPU_VIDALERT_L
I124
CPU_SVIDSOUT
CPU_50S
CPU_COMP
12 68
CPU_VIDSCLK
12 68
CPU_VIDSOUT
12 68
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
CPU Constraints
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
100 OF 109
SHEET
78 OF 86
1
A
8
7
6
5
Memory Bus Constraints
4
3
2
1
Memory Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_37S
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK
MEM_72D
MEM_CLK
MEM_A_CLK
MEM_72D
MEM_CLK
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CMD
MEM_40S
MEM_CMD
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>
11 27
11 27
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
*
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
MEM_50S
TOP,BOTTOM
Y
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>
11 27
11 27
11 27
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
TOP,BOTTOM
=85_OHM_DIFF
Y
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
MEM_50S
D
ISL10
N
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_A_DQS0
MEM_85D
MEM_DQS
MEM_A_DQS0
MEM_85D
MEM_DQS
MEM_A_DQS1
MEM_85D
MEM_DQS
MEM_A_DQS1
MEM_85D
MEM_DQS
MEM_A_DQS2
MEM_85D
MEM_DQS
MEM_A_DQS2
MEM_85D
MEM_DQS
MEM_A_DQS3
MEM_85D
MEM_DQS
MEM_A_DQS3
MEM_85D
MEM_DQS
MEM_A_DQS4
MEM_85D
MEM_DQS
MEM_A_DQS4
MEM_85D
MEM_DQS
MEM_A_DQS5
MEM_85D
MEM_DQS
MEM_A_DQS5
MEM_85D
MEM_DQS
MEM_A_DQS6
MEM_85D
MEM_DQS
MEM_A_DQS6
MEM_85D
MEM_DQS
MEM_A_DQS7
MEM_85D
MEM_DQS
MEM_A_DQS7
MEM_85D
MEM_DQS
MEM_B_CLK
MEM_72D
MEM_CLK
TABLE_SPACING_RULE_ITEM
MEM_B_CLK
MEM_72D
MEM_CLK
TABLE_SPACING_RULE_ITEM
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CMD
MEM_40S
MEM_CMD
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
ISL10
N
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
MEM_50S
ISL3,ISL4,ISL9
Y
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
MEM_85D
ISL3,ISL4,ISL9
Y
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
11 27
11 27
D
11 27
11 27
11 27
TABLE_PHYSICAL_RULE_ITEM
C
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
=4:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=3:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
C
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=1.5:1_SPACING
?
MEM_CMD2MEM
*
=3:1_SPACING
?
MEM_DATA2DATA
*
=1.5:1_SPACING
?
MEM_DATA2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>
11 29
11 29
11 29
11 29
11 29
TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_2OTHER
*
25 MILS
?
TABLE_SPACING_RULE_ITEM
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_CLK
*
MEM_CLK2MEM
MEM_CLK
MEM_CTRL
*
MEM_CLK2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_CLK
*
MEM_CMD2MEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CMD
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_DATA
*
MEM_CLK2MEM
MEM_CLK
MEM_DQS
*
MEM_CLK2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
*
MEM_CMD2MEM
MEM_CMD
MEM_DQS
*
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DATA
MEM_CLK
*
MEM_DATA2MEM
MEM_DATA
MEM_CTRL
*
MEM_DATA2MEM
MEM_DATA
MEM_CMD
*
MEM_DATA2MEM
MEM_DATA
MEM_DATA
*
MEM_DATA2DATA
MEM_DATA
MEM_DQS
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL2MEM
MEM_CTRL
*
MEM_CTRL2CTRL
MEM_CMD
*
MEM_CTRL2MEM
MEM_CTRL
MEM_DATA
*
MEM_CTRL2MEM
MEM_DQS
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
*
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
MEM_CTRL
*
MEM_DQS2MEM
MEM_CLK
*
*
MEM_CMD
*
MEM_DQS2MEM
MEM_CTRL
*
*
MEM_DATA
*
MEM_DQS2MEM
MEM_CMD
*
*
A
MEM_DQS
*
MEM_DQS2MEM
MEM_2OTHER
7
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_B_DQS0
MEM_85D
MEM_DQS
MEM_B_DQS0
MEM_85D
MEM_DQS
MEM_B_DQS1
MEM_85D
MEM_DQS
MEM_B_DQS1
MEM_85D
MEM_DQS
MEM_B_DQS2
MEM_85D
MEM_DQS
MEM_B_DQS2
MEM_85D
MEM_DQS
MEM_B_DQS3
MEM_85D
MEM_DQS
MEM_B_DQS3
MEM_85D
MEM_DQS
MEM_B_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS5
MEM_85D
MEM_DQS
MEM_B_DQS5
MEM_85D
MEM_DQS
MEM_B_DQS6
MEM_85D
MEM_DQS
MEM_B_DQS6
MEM_85D
MEM_DQS
MEM_B_DQS7
MEM_85D
MEM_DQS
MEM_B_DQS7
MEM_85D
MEM_DQS
MEM_2OTHER
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
*
*
MEM_2OTHER
Need to support MEM_*-style wildcards!
DDR3: Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines
per Huron River SFF DG rev1.0 (#438297).
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQ to DQS matching per byte lane should be within 0.127mm.
DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm.
SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5
8
MEM_B_DQ_BYTE1
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_DATA
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_50S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_B_DQ_BYTE0
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_CMD
11 29
MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>
11 29
11 28
11 28
11 28
11 28
B
11 28
11 28
11 28
11 28
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
MEM_40S
11 29
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_B_CMD
11 29
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CMD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_40S
11 29
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
*
MEM_B_CMD
MEM_CMD2CMD
MEM_CMD
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_CLK
MEM_CMD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CMD
MEM_40S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_40S
MEM_B_CMD
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
B
MEM_B_CMD
MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
6
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
SYNC_MASTER=K90I_MLB
11 28
SYNC_DATE=02/15/2011
PAGE TITLE
Memory Constraints
11 28
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
101 OF 109
SHEET
79 OF 86
1
A
8
7
6
5
Digital Video Signal Constraints
4
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
DP_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LVDS_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SPACING_RULE_SET
LAYER
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_ITEM
DP_PCH
*
=3x_DIELECTRIC
?
DP_PCH_TX
*
=3x_DIELECTRIC
?
TOP,BOTTOM
=4x_DIELECTRIC
?
DP_PCH_TX
TOP,BOTTOM
=4x_DIELECTRIC
?
D
=3x_DIELECTRIC
LVDS_PCH_TX
LVDS_90D
LVDS_PCH_TX
LVDS_90D
LVDS_PCH_TX
LVDS_90D
LVDS_PCH_TX
LVDS_PCH_TX
TOP,BOTTOM
=4x_DIELECTRIC
?
LVDS_90D
LVDS_PCH_TX
LVDS_IG_A_DATA
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
LVDS_90D
LVDS_IG_A_CLK
TABLE_SPACING_RULE_ITEM
DP_PCH
TABLE_SPACING_RULE_ITEM
LVDS_PCH_TX
LVDS_IG_A_CLK
LVDS_IG_A_DATA
WEIGHT
LVDS_90D
LVDS_PCH_TX
I213
LVDS_90D
LVDS_PCH_TX
I214
LVDS_90D
LVDS_PCH_TX
I215
LVDS_90D
LVDS_PCH_TX
I216
LVDS_90D
LVDS_PCH_TX
SATA_HDD_R2D
SATA_90D
SATA3_PCH_TX
TABLE_SPACING_RULE_ITEM
?
SATA Interface Constraints
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_DATA_P<3..0>
LVDS_IG_B_DATA_N<3..0>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
17 74
17 74
6 17 74
6 17 74
8 17
8 17
D
8 17
8 17
8 17
8 17
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SATA_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
*
LINE-TO-LINE SPACING
WEIGHT
=3x_DIELECTRIC
?
SPACING_RULE_SET
*
=3x_DIELECTRIC
?
SATA_ICOMP
*
8 MIL
?
SATA3_PCH_TX
SATA_90D
SATA3_PCH_TX
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
SATA_HDD_R2D_CONN
SATA_90D
SATA3_PCH_TX
SATA_HDD_D2R
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_CONN
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_CONN
SATA_90D
SATA3_PCH_RX
SATA_ODD_R2D
SATA_90D
SATA_PCH_TX
SATA_ODD_R2D
SATA_90D
SATA_PCH_TX
SATA_ODD_R2D
SATA_90D
SATA_PCH_TX
SATA_ODD_R2D
SATA_90D
SATA_PCH_TX
SATA_ODD_D2R
SATA_90D
SATA_PCH_RX
SATA_ODD_D2R
SATA_90D
SATA_PCH_RX
SATA_HDD_R2D_CONN
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_CONN
SATA_90D
SATA3_PCH_TX
SATA_HDD_D2R_CONN
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_CONN
SATA_90D
SATA3_PCH_RX
USB_85D
USB
USB_85D
USB
USB_EXTA
USB_85D
USB
USB_EXTA
USB_85D
USB
USB_EXTB
USB_85D
USB
USB_85D
USB
I219
USB_85D
USB
I220
USB_85D
USB
I221
USB_85D
USB
I222
USB_85D
USB
I223
USB_85D
USB
I224
USB_85D
USB
I225
USB_85D
USB
I226
USB_85D
USB
I247
USB_85D
USB
I248
USB_85D
USB
I250
USB_85D
USB
I249
USB_85D
USB
USB_85D
USB3_PCH_RX
USB_85D
USB3_PCH_RX
USB_85D
USB3_PCH_TX
USB_85D
USB3_PCH_TX
USB_85D
USB3_PCH_RX
USB_85D
USB3_PCH_RX
USB_85D
USB3_PCH_TX
I233
USB_85D
USB3_PCH_TX
I235
USB_85D
USB3_PCH_RX
I236
USB_85D
USB3_PCH_RX
I238
USB_85D
USB3_PCH_TX
I237
USB_85D
USB3_PCH_TX
I240
USB_85D
USB3_PCH_RX
I239
USB_85D
USB3_PCH_RX
I241
USB_85D
USB3_PCH_TX
I242
USB_85D
USB3_PCH_TX
I244
USB_85D
USB3_PCH_TX
I243
USB_85D
USB3_PCH_TX
I246
USB_85D
USB3_PCH_TX
I245
USB_85D
USB3_PCH_TX
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
TABLE_SPACING_RULE_ITEM
SATA_PCH_TX
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
SATA_PCH_RX
SATA_90D
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
SATA_PCH_TX
SATA_HDD_R2D
SATA_HDD_R2D_CONN
TABLE_SPACING_RULE_ITEM
SATA_PCH_RX
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4X_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA3_PCH_TX2TX
*
TABLE_SPACING_RULE_ITEM
SATA3_PCH_TX2TX
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
SATA3_PCH_TX2RX
*
=5X_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
SATA3_PCH_TX2RX
TOP,BOTTOM
=6X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA3_PCH_RX2RX
*
=4x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
SATA3_PCH_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA3_PCH_RX2TX
*
=5x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
SATA3_PCH_RX2TX
TOP,BOTTOM
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA3_PCH_2OTHER
*
=4x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
SATA3_PCH_2OTHER
TOP,BOTTOM
=5x_DIELECTRIC
PCH_SATA_ICOMP
SATA_ICOMP
?
USB_HUB1_UP
C
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_TX
*_PCH_TX
*
SATA3_PCH_TX2TX
SATA3_PCH_TX
*_PCH_RX
*
SATA3_PCH_TX2RX
SATA3_PCH_RX
*_PCH_RX
*
SATA3_PCH_RX2RX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_RX
*_PCH_TX
*
SATA3_PCH_RX2TX
SATA3_PCH_TX
*
*
SATA3_PCH_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SATA3_PCH_RX
*
*
SATA3_PCH_2OTHER
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
I228
USB3_EXT_RX
I227
USB 2.0 Interface Constraints
I229
USB3_EXT_TX
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
I230
DIFFPAIR NECK GAP
I231
TABLE_PHYSICAL_RULE_ITEM
PCH_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
I232
TABLE_PHYSICAL_RULE_ITEM
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
B
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB
*
I234
=85_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
USB3_EXT_RX
USB3_EXT_TX
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
USB 3.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
USB3_PCH_TX2TX
LAYER
*
=4X_DIELECTRIC
?
USB3_PCH_TX2RX
*
=5X_DIELECTRIC
?
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
USB3_PCH_TX2TX
TOP,BOTTOM
LAYER
=5X_DIELECTRIC
?
USB3_PCH_TX2RX
TOP,BOTTOM
=6X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
=4x_DIELECTRIC
?
*
=5x_DIELECTRIC
?
I252
USB_EXTC
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
USB3_PCH_RX2RX
USB_EXTA
USB3_PCH_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
?
USB3_PCH_RX2TX
TOP,BOTTOM
=6x_DIELECTRIC
?
USB_CAMERA
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
=4x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
USB3_PCH_2OTHER
TOP,BOTTOM
=5x_DIELECTRIC
USB_CAMERA
?
USB_85D
USB
USB_BT
USB_85D
USB
USB_BT
USB_85D
USB
I253
USB_BT
USB_85D
USB
I254
USB_BT
USB_85D
USB
USB_TPAD
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
USB3_PCH_TX
*_PCH_TX
*
USB3_PCH_TX2TX
TABLE_SPACING_ASSIGNMENT_ITEM
A
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
*_PCH_RX
*
USB3_PCH_TX2RX
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*_PCH_RX
*
USB_IR
USB3_PCH_RX2RX
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*_PCH_TX
*
USB3_PCH_RX2TX
USB3_PCH_TX
*
*
USB3_PCH_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
PCH_USB_RBIAS
PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*
*
USB3_PCH_2OTHER
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
PCH_DIFFCLK_UNUSED_
CLK_PCIE_90D
CLK_PCIE
CPU_50S
CLK_PCIE
CPU_50S
CLK_PCIE
LPC_CLK33M
8
USB_SMC_P
USB_SMC_N
16 41
6 41
16 41
16 41
6 41
6 41
16 41
16 41
6 41
6 41
16 41
16 41
41
41
41
41
16
18 25
18 25
18 42
C
18 42
25 43
25 43
42
42
43
43
42
42
8 18
8 18
18 25
18 25
18 25
18 25
18 42
18 42
18 42
18 42
18 43
18 43
18 43
18 43
42
42
B
42
42
43
43
43
43
42
42
43
43
8 45
8 45
USB_EXTC_P
USB_EXTC_N
8 18
8 18
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
USB3_PCH_2OTHER
USB3_EXTA_RX_P
USB3_EXTA_RX_N
USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_F_P
USB3_EXTA_TX_F_N
USB3_EXTB_RX_F_P
USB3_EXTB_RX_F_N
USB3_EXTB_TX_F_P
USB3_EXTB_TX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N
16 41
6 41
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
USB3_PCH_RX2TX
I251
TABLE_SPACING_RULE_HEAD
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_HDD_R2D_RC_P
SATA_HDD_R2D_RC_N
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N
PCH_SATAICOMP
USB_HUB_UP_P
USB_HUB_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_MUX_P
USB_EXTB_MUX_N
USB_EXTA_MUXED_F_P
USB_EXTA_MUXED_F_N
USB_EXTB_F_P
USB_EXTB_F_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_EXTD_XHCI_P
USB_EXTD_XHCI_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
7
6
5
4
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
PCH_USB_RBIAS
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
3
18 32
18 32
6 32
6 32
8 32
8 32
6 32
6 32
8 53
8 53
SYNC_MASTER=K90I_MLB
8 44
SYNC_DATE=02/15/2011
PAGE TITLE
PCH Constraints 1
8 44
18
DRAWING NUMBER
16
Apple Inc.
16
16
16
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
REVISION
6.0.0
BRANCH
16
16
16
16 24
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
PAGE
102 OF 109
SHEET
80 OF 86
1
A
8
7
6
5
LPC Bus Constraints
4
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
3
2
1
PCH Net Properties
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
Chipset Net Properties
NET_TYPE
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
CLK_LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
LPC_AD
LPC_50S
LPC
LPC_FRAME_L
LPC_50S
LPC
LPC_RESET_L
LPC_50S
LPC
LPC_CLK33M
CLK_LPC_50S
CLK_LPC
LPC_CLK33M
CLK_LPC_50S
CLK_LPC
=STANDARD
LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
LPC
*
6 MIL
?
TABLE_SPACING_RULE_ITEM
CLK_LPC
D
*
8 MIL
LPC_CLK33M
CLK_LPC_50S
CLK_LPC
SMBUS_PCH_CLK
SMB_50S
SMB
DP_EXTA_ML
DP_85D
DP_PCH_TX
I251
DP_EXTA_ML
DP_85D
DP_PCH_TX
24
SMBus Interface Constraints
SMBUS_PCH_DATA
SMB_50S
SMB
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SMB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
SMBUS_PCH_0_CLK
SMB_50S
SMB
SMB_50S
SMB
SMBUS_SMC_B_S0_SCL
SMB_50S
SMB
SMBUS_SMC_B_S0_SDA
SMB_50S
SMB
HDA_BIT_CLK
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
CLK_SLOW_55S
CLK_SLOW
PM_CLK32K_SUSCLK
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
HDA_SYNC
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
?
HDA_RST_L
HDA_SDIN0
HD Audio Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
HDA_SDOUT
TABLE_PHYSICAL_RULE_ITEM
HDA_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
SMBUS_PCH_0_DATA
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
I253
DP_85D
DP_PCH_TX
18 24
I255
DP_85D
DP_PCH_TX
24 45
I254
DP_EXTA_AUXCH
DP_85D
DP_PCH
6 24 47
I256
DP_EXTA_AUXCH
?
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SPACING_RULE_SET
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
LAYER
LINE-TO-LINE SPACING
WEIGHT
SPI_CLK
TABLE_SPACING_RULE_ITEM
HDA
*
=2x_DIELECTRIC
SPI_MOSI
SPI_MISO
SIO Signal Constraints
SPI_CS0
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
C
*
=55_OHM_SE
SPACING_RULE_SET
LAYER
=55_OHM_SE
LINE-TO-LINE SPACING
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
WEIGHT
TABLE_SPACING_RULE_ITEM
*
8 MIL
SPI
SPI_50S
SPI
SPI
I288
SPI_50S
SPI
I289
SPI_50S
SPI
I290
SPI_50S
SPI
I291
SPI_50S
SPI
I292
SPI_50S
SPI
?
I293
SPI_50S
SPI
I294
SPI_50S
SPI
I295
SPI_50S
SPI
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE
ON LAYER?
LAYER
SPI
SPI_50S
SPI
SPI Interface Constraints
PHYSICAL_RULE_SET
SPI_50S
SPI_50S
TABLE_SPACING_RULE_HEAD
CLK_SLOW
SPI
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
CLK_SLOW_55S
SPI_50S
SPI_50S
TABLE_PHYSICAL_RULE_HEAD
LAYER
SPI
?
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
PHYSICAL_RULE_SET
SPI_50S
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
DIFFPAIR NECK GAP
PCIE_ENET_R2D
PCIE_85D
PCIE_PCH_TX
TABLE_PHYSICAL_RULE_ITEM
SPI_50S
*
=50_OHM_SE
SPACING_RULE_SET
LAYER
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_TX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
PCIE_85D
PCIE_PCH_RX
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
I235
CPU_27P4S
CPU_COMP
I236
CPU_27P4S
CPU_COMP
I237
CPU_27P4S
CPU_COMP
I238
CPU_27P4S
CPU_COMP
I239
CPU_27P4S
CPU_COMP
I240
CPU_27P4S
CPU_COMP
I241
CPU_27P4S
CPU_COMP
I242
CPU_27P4S
CPU_COMP
I243
CPU_27P4S
CPU_COMP
I244
CPU_27P4S
CPU_COMP
I245
CPU_27P4S
CPU_COMP
I246
CPU_27P4S
CPU_COMP
I247
CPU_27P4S
CPU_COMP
I248
CPU_27P4S
CPU_COMP
I249
CPU_27P4S
CPU_COMP
I250
CPU_27P4S
CPU_COMP
PCIE_ENET_D2R
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SPI
*
8 MIL
?
PCIE_AP_R2D
PCIE_AP_D2R
PCIE_FW_R2D
B
PCI-Express Signal Constraints
PCIE_FW_D2R
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCIE_T29_TX2TX
*
=3X_DIELECTRIC
?
PCIE_T29_TX2RX
*
=4X_DIELECTRIC
?
PCIE_T29_RX2RX
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PCIE_T29_TX2TX
TOP,BOTTOM
=4X_DIELECTRIC
?
PCIE_T29_TX2RX
TOP,BOTTOM
=5X_DIELECTRIC
?
PCIE_T29_RX2RX
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PCIE_T29_RX2TX
*
=4x_DIELECTRIC
?
PCIE_T29_2OTHER
*
=3x_DIELECTRIC
?
PCIE_AP_D2R
PCIE_AP_R2D
TABLE_SPACING_RULE_ITEM
PCIE_T29_RX2TX
TOP,BOTTOM
=4x_DIELECTRIC
?
PCIE_T29_2OTHER
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PCIE_CLK100M_ENET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MCP_PE1_REFCLK
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_TX
*_TX
*
PCIE_T29_TX2TX
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_TX
*_RX
*
MCP_PE2_REFCLK
PCIE_T29_TX2RX
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_RX
*_RX
*
PCIE_T29_RX2RX
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_T29_RX
*_TX
*
PCIE_T29_RX2TX
PCIE_T29_TX
*
*
PCIE_T29_2OTHER
PCIE_T29_RX
*
*
PCIE_T29_2OTHER
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
SPI_MLB_CLK
SPI_MLB_CS_L
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
DP_PCH
DP_85D
DP_PCH
I258
DP_85D
DP_PCH
DP_EXTA_ML_C_P<3..0>
DP_EXTA_ML_C_N<3..0>
DP_EXTA_ML_P<3..0>
DP_EXTA_ML_N<3..0>
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
8 75
8 75
75
75
8 75
8 75
75
D
75
16 48
16 48
16 48
16 48
16 48
16 57
16
16 57
16
16
16 57
16 57
57
16 57
16 24
I271
PCIE_T29_R2D
PCIE_85D
PCIE_T29_RX
I273
PCIE_T29_R2D
PCIE_85D
PCIE_T29_RX
PCIE_85D
PCIE_T29_RX
I272
PCIE_T29_R2D
16 47
I274
PCIE_T29_R2D
PCIE_85D
PCIE_T29_RX
47
I276
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
16 47
I275
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
47
I277
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
16 47
I278
PCIE_T29_D2R
PCIE_85D
PCIE_T29_TX
I279
PCIE_CLK100M_T29
CLK_PCIE_90D
CLK_PCIE
I280
PCIE_CLK100M_T29
CLK_PCIE_90D
CLK_PCIE
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
DP_85D
I257
16 48
=STANDARD
PM_SUS_CLK
SPACING
I252
6 16 45 47
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
PHYSICAL
6 16 45 47
16 47
47
PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_R2D_P<3..0>
PCIE_T29_R2D_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
PCIE_T29_D2R_C_P<3..0>
PCIE_T29_D2R_C_N<3..0>
8 33
8 33
33
33
8 33
8 33
33
33
PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N
16 33
16 33
46 47 56
46 47 56
C
46 47 56
46 47 56
Clock Net Properties
NET_TYPE
45 46
45 46
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
45 46
I281
SYSCLK_CLK32K_RTC
CLK_SLOW_55S
CLK_SLOW
SYSCLK_CLK32K_RTC
I282
SYSCLK_CLK25M_SB
CLK_25M_55S
CLK_25M
I283
CLK_25M_55S
CLK_25M
I284
CLK_25M_55S
CLK_25M
I285
CLK_25M_55S
CLK_25M
CLK_25M_55S
CLK_25M
CLK_25M_55S
CLK_25M
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_T29
SYSCLK_CLK25M_T29_R
16 24
45 46
36
36
16 36
16 36
I286
SYSCLK_CLK25M_T29
16 36
I287
16 24
16
24 36
24 33
33
16 36
36
36
6 32
6 32
16 32
16 32
16 32
16 32
38
38
16 38
16 38
16 38
B
16 38
38
38
6 32
6 32
8 16
8 16
16 36
16 36
16 32
16 32
16 38
16 38
8 16
8 16
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
A
System Clock Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CLK_SLOW_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
CLK_25M_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<22>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>
6
6
6
6 81
6 81
6
6
SYNC_MASTER=K90I_MLB
6
PCH Constraints 2
6
DRAWING NUMBER
6
Apple Inc.
6
*
=2x_DIELECTRIC
?
CLK_25M
*
=5x_DIELECTRIC
?
6
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
NOTE: 25MHz system clocks very sensitive to noise.
7
6
5
4
SIZE
D
6.0.0
BRANCH
6
TABLE_SPACING_RULE_ITEM
8
051-9058
REVISION
R
TABLE_SPACING_RULE_ITEM
CLK_SLOW
SYNC_DATE=02/15/2011
PAGE TITLE
6
3
2
PAGE
103 OF 109
SHEET
81 OF 86
1
A
8
7
6
5
CAESAR IV (Ethernet) Constraints
4
3
2
1
Ethernet Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
ENET_50S
ENET_3X
ENET_50S
ENET_3X
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=3:1_SPACING
?
ENET_50S
ENET_3X
ENET_100D
ENET_MDI
ENET_100D
ENET_MDI
BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
ENET_RESET_L
30 36
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
36 37
TABLE_SPACING_RULE_ITEM
ENET_3X
*
ENET_MDI
36 37
SOURCE: Broadcom 5764-DS04-RDS Page 38
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
D
LAYER
LINE-TO-LINE SPACING
WEIGHT
8MIL
?
I166
CR_DATA
ENET_50S
ENET_CR_DATA
I167
CR_DATA
ENET_50S
ENET_CR_DATA
I168
CR_CLK
ENET_50S
ENET_CR_DATA
I169
CR_DATA
ENET_50S
ENET_CR_DATA
I170
CR_DATA
ENET_50S
ENET_CR_DATA
I171
CR_CLK
ENET_50S
ENET_CR_DATA
I172
CR_CLK
ENET_50S
ENET_CR_DATA
TABLE_SPACING_RULE_ITEM
ENET_CR_DATA
*
CAESAR IV (Ethernet PHY) Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
ENET_100D
*
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_CR_DATA<7..0>
ENET_CR_CMD
ENET_CR_CLK
SDCONN_DATA<7..0>
SDCONN_CMD
SDCONN_CLK
SDCONN_CLK_L
D
30 36
30 36
30 36
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
0.6 MM
?
TABLE_SPACING_RULE_ITEM
*
ENET_MDI
SOURCE: Broadcom 5764-DS04-RDS Page 38
C
FireWire Interface Constraints
C
FireWire Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
FW_110D
*
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
I158
FW_P0_TPA
FW_110D
FW_TP
I159
FW_P0_TPA
FW_110D
FW_TP
I160
FW_P0_TPB
FW_110D
FW_TP
I161
FW_P0_TPB
FW_110D
FW_TP
I162
FW_P1_TPA
FW_110D
FW_TP
I163
FW_P1_TPA
FW_110D
FW_TP
I164
FW_P1_TPB
FW_110D
FW_TP
I165
FW_P1_TPB
FW_110D
FW_TP
TABLE_SPACING_RULE_ITEM
FW_TP
*
=3:1_SPACING
?
FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N
38 40
38 40
38 40
38 40
38 40
38 40
38 40
38 40
Port 2 Not Used
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Ethernet/FW Constraints
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
104 OF 109
SHEET
82 OF 86
1
A
8
7
6
5
DisplayPort Signal Constraints
4
ELECTRICAL_CONSTRAINT_SET
T29 I2C Signal Constraints
I1
TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I2
TABLE_PHYSICAL_RULE_ITEM
T29_I2C_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=55_OHM_SE
I3
=STANDARD
I4
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
I7
TABLE_SPACING_RULE_ITEM
T29_I2C
*
T29_R2D0
T29_R2D0
T29_R2D1
T29_R2D1
I5
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
I6
I8
D T29 SPI Signal Constraints
I9
I10
T29_D2R0
T29_D2R0
T29_D2R1
T29_D2R1
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
T29_SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
I11
I12
TABLE_PHYSICAL_RULE_ITEM
I13
I15
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
I14
TABLE_SPACING_RULE_ITEM
T29_SPI
*
I17
?
=2x_DIELECTRIC
I16
I18
T29/DP Connector Signal Constraints
I19
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
T29DP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
I20
I21
TABLE_PHYSICAL_RULE_ITEM
I22
DP_SDRVA_ML_EVEN
DP_SDRVA_ML_EVEN
DP_SDRVA_ML_ODD
DP_SDRVA_ML_ODD
DP_SDRVA_AUXCH
DP_SDRVA_AUXCH
TABLE_PHYSICAL_RULE_ITEM
T29DP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
I23
=100_OHM_DIFF
I24
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
*
=5x_DIELECTRIC
I25
WEIGHT
TABLE_SPACING_RULE_ITEM
T29DP
I26
TABLE_SPACING_RULE_ITEM
?
T29DP
TOP,BOTTOM
=7x_DIELECTRIC
?
I27
I28
I30
I29
SOURCE: Bill Cornelius’s T29 Routing Notes
I31
I32
C
I34
I33
T29_R2D2
T29_R2D2
T29_R2D3
T29_R2D3
I35
I36
I37
I39
I38
I40
T29_D2R2
T29_D2R2
T29_D2R3
T29_D2R3
I41
I42
I43
I44
I46
I45
I47
I48
I49
I50
I51
I52
DP_SDRVB_ML_EVEN
DP_SDRVB_ML_EVEN
DP_SDRVB_ML_ODD
DP_SDRVB_ML_ODD
DP_SDRVB_AUXCH
DP_SDRVB_AUXCH
I53
I54
I55
I56
I57
B T29 IC Net Properties
ELECTRICAL_CONSTRAINT_SET
I62
I61
I63
I64
DP_T29SNK0_ML
DP_T29SNK0_ML
I65
I66
I67
I68
DP_T29SNK0_AUXCH
DP_T29SNK0_AUXCH
I69
I70
I71
I72
DP_T29SNK1_ML
DP_T29SNK1_ML
I74
I73
I75
I76
DP_T29SNK1_AUXCH
DP_T29SNK1_AUXCH
I77
I78
I79
I80
A
I81
I82
I83
I84
I85
I86
T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
I87
I88
I89
I90
8
I58
I59
NET_TYPE
PHYSICAL
SPACING
I60
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH
DP_PCH
DP_PCH
DP_PCH
DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_ML_P<3..0>
DP_T29SNK0_ML_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH_TX
DP_PCH
DP_PCH
DP_PCH
DP_PCH
DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_ML_P<3..0>
DP_T29SNK1_ML_N<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N
DP_85D
DP_85D
DP_85D
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_T29SRC_ML_C_P<3..0>
DP_T29SRC_ML_C_N<3..0>
DP_T29SRC_AUXCH_C_P
DP_T29SRC_AUXCH_C_N
T29_I2C_55S
T29_I2C_55S
T29_I2C
T29_I2C
I2C_T29_SCL
I2C_T29_SDA
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI
T29_SPI
T29_SPI
T29_SPI
T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP
T29DP
T29DP
T29DP
T29_R2D_C_P<3..0>
T29_R2D_C_N<3..0>
T29_D2R_P<3..0>
T29_D2R_N<3..0>
7
2
1
T29/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
3
NET_TYPE
PHYSICAL
SPACING
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29_R2D_P<0>
T29_R2D_N<0>
T29_R2D_P<1>
T29_R2D_N<1>
T29_R2D_C_F_P<1..0>
T29_R2D_C_F_N<1..0>
T29_D2R_C_P<0>
T29_D2R_C_N<0>
T29_D2R_C_P<1>
T29_D2R_C_N<1>
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
DP_SDRVA_ML_C_P<3..0>
DP_SDRVA_ML_C_N<3..0>
DP_SDRVA_ML_R_P<3..0>
DP_SDRVA_ML_R_N<3..0>
DP_SDRVA_ML_P<2..0:2>
DP_SDRVA_ML_N<2..0:2>
DP_SDRVA_ML_P<3..1:2>
DP_SDRVA_ML_N<3..1:2>
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DPA_ML_P<3..0>
T29DPA_ML_N<3..0>
T29DPA_ML_C_P<3..0>
T29DPA_ML_C_N<3..0>
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29_R2D_P<2>
T29_R2D_N<2>
T29_R2D_P<3>
T29_R2D_N<3>
T29_R2D_C_F_P<3..2>
T29_R2D_C_F_N<3..2>
T29_D2R_C_P<2>
T29_D2R_C_N<2>
T29_D2R_C_P<3>
T29_D2R_C_N<3>
T29DPB_D2R3_AUXCH_P
T29DPB_D2R3_AUXCH_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
DP_SDRVB_ML_C_P<3..0>
DP_SDRVB_ML_C_N<3..0>
DP_SDRVB_ML_R_P<3..0>
DP_SDRVB_ML_R_N<3..0>
DP_SDRVB_ML_P<2..0:2>
DP_SDRVB_ML_N<2..0:2>
DP_SDRVB_ML_P<3..1:2>
DP_SDRVB_ML_N<3..1:2>
DP_SDRVB_AUXCH_P
DP_SDRVB_AUXCH_N
DP_SDRVB_AUXCH_C_P
DP_SDRVB_AUXCH_C_N
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DPB_ML_P<3..0>
T29DPB_ML_N<3..0>
T29DPB_ML_C_P<3..0>
T29DPB_ML_C_N<3..0>
DP_B_EXT_AUXCH_P
DP_B_EXT_AUXCH_N
75
75
75
75
75 76
75 76
D
75 76
75 76
76
76
75
75
75
75
75 83
75 83
75
75
75
75
75
75
75 76
75 76
75 76
75 76
75 76
75 76
C
Only used on dual-port hosts.
83
83
B
8 33
8 33
33
33
8 33
8 33
33
33
8 33
8 33
33
33
8 33
8 33
33
33
Only used on hosts supporting T29 video-in
33 48
SYNC_MASTER=K90I_MLB
33 48
SYNC_DATE=02/15/2011
PAGE TITLE
T29 Constraints
33
DRAWING NUMBER
33
Apple Inc.
33
33
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
REVISION
6.0.0
BRANCH
8 33 75
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 33 75
8 33 75
8 33 75
6
5
4
3
2
PAGE
105 OF 109
SHEET
83 OF 86
1
A
8
7
6
5
4
3
2
1
SMC SMBus Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
D
SMBUS_SMC_A_S3_SCL
SMB_50S
SMB
SMBUS_SMC_A_S3_SDA
SMB_50S
SMB
SMBUS_SMC_B_S0_SCL
SMB_50S
SMB
SMBUS_SMC_B_S0_SDA
SMB_50S
SMB
SMBUS_SMC_0_S0_SCL
SMB_50S
SMB
SMBUS_SMC_0_S0_SDA
SMB_50S
SMB
SMBUS_SMC_BSA_SCL
SMB_50S
SMB
SMBUS_SMC_BSA_SDA
SMB_50S
SMB
SMBUS_SMC_MGMT_SCL
SMB_50S
SMB
SMBUS_SMC_MGMT_SDA
SMB_50S
SMB
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
6 45 48
6 45 48
45 48
45 48
45 48
45 48
6 45 48
6 45 48
D
45 48
45 48
SMBus Charger Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
64
64
CHGR_CSO_P
CHGR_CSO_N
64
64
C
C
B
B
A
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
6.0.0
BRANCH
PAGE
106 OF 109
SHEET
84 OF 86
1
A
8
7
6
5
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
4
3
J30 Specific Net Properties
2
1
J30 Specific Net Properties
NET_TYPE
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
SENSE_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
THERM_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
ENET_100D
ENETCONN
ENETCONN_P<3..0>
37
ENET_100D
ENETCONN
ENETCONN_N<3..0>
37
SATA_90D
SATA_PCH_RX
SATA_ODD_D2R_C_P
6 41
SATA_90D
SATA_PCH_RX
SATA_ODD_D2R_C_N
6 41
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_RDROUT_P
41
SATA_90D
SATA3_PCH_RX
SATA_HDD_D2R_RDROUT_N
41
SATA3_PCH_TX
SATA_HDD_R2D_RDRIN_P
41
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL
SPACING
=1:1_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
PCIE_CLK100M_AP
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
WEIGHT
SATA_90D
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
D
SENSE
*
=2:1_SPACING
?
THERM
*
=2:1_SPACING
?
CPU_COMP
GND
*
SATA_90D
GND_P2MM
GND
*
SATA_HDD_R2D_RDRIN_N
CLK_PCIE
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
41
SATA_90D
SATA3_PCH_TX
SATA_HDD_D2R_RDRIN_P
41
I298
SATA_90D
SATA3_PCH_TX
SATA_HDD_D2R_RDRIN_N
41
I297
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_RDROUT_P
41
SATA_90D
SATA3_PCH_TX
SATA_HDD_R2D_RDROUT_N
THERM_1TO1_55S
THERM
THMSNS_D1_P
51
THERM_1TO1_55S
THERM
THMSNS_D1_N
51
THERM_1TO1_55S
THERM
THMSNS_D2_P
51
THERM_1TO1_55S
THERM
THMSNS_D2_N
51
T29_THERMD_P
51
51
1TO1_DIFFPAIR
GND_P2MM
?
=2:1_SPACING
SATA3_PCH_TX
I295
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_VCCSENSE
TABLE_SPACING_RULE_ITEM
*
CLK_PCIE
CLK_PCIE_90D
1TO1_DIFFPAIR
TABLE_SPACING_RULE_ITEM
AUDIO
CLK_PCIE_90D
1TO1_DIFFPAIR
I296
SENSE_DIFFPAIR
1TO1_DIFFPAIR
6 32
6 32
64
D
64
64
64
41
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
25 MILS
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
TABLE_SPACING_RULE_ITEM
ENETCONN
*
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I287
I288
TABLE_SPACING_ASSIGNMENT_ITEM
ENET_MDI
GND
*
SENSE_DIFFPAIR
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
THERM_1TO1_55S
THERM
T29_THERMD_N
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
T29THMSNS_D2_P
THERM_1TO1_55S
THERM
T29THMSNS_D2_N
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
GND_P2MM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
GND
*
=STANDARD
TABLE_SPACING_ASSIGNMENT_HEAD
?
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
CLK_PCIE
*
GND_P2MM
GND
PCIE*
*
GND_P2MM
GND
SATA*
*
GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
GND_P2MM
*
0.20 MM
TABLE_SPACING_ASSIGNMENT_ITEM
1000
GND
USB*
*
GND_P2MM
TABLE_SPACING_RULE_ITEM
PWR_P2MM
*
0.20 MM
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
50
50
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
1000
SB_POWER
CLK_PCIE
*
PWR_P2MM
SENSE_1TO1_55S
SENSE
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P
50
50
SPK_OUT
DIFFPAIR
AUDIO
49 70
SPK_OUT
DIFFPAIR
AUDIO
49 70
SPK_OUT
DIFFPAIR
AUDIO
SPK_OUT
DIFFPAIR
AUDIO
SPK_OUT
DIFFPAIR
AUDIO
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SB_POWER
SATA*
*
SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
SSM2315_SUB_N
SSM2315_SUB_P
SSM2315_L_N
SSM2315_L_P
SSM2315_R_N
SSM2315_R_P
AUD_LO2_N_R
AUD_LO2_P_R
AUD_LO1_N_R
AUD_LO1_P_R
AUD_LO2_N_L
AUD_LO2_P_L
SPKRAMP_INL_P
SPKRAMP_INL_N
SPKRAMP_INR_P
SPKRAMP_INR_N
SPKRAMP_INSUB_P
SPKRAMP_INSUB_N
PWR_P2MM
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
GND
*
GND_P2MM
MEM_CMD
GND
*
GND_P2MM
SB_POWER
SATA*
*
PWR_P2MM
MEM_CTRL
GND
*
GND_P2MM
GND
*
GND_P2MM
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1_P
49 68 69
SENSE_1TO1_55S
SENSE
I299
SENSE
CPUIMVP_ISNS1_N
CPUIMVP_ISNS2_P
49 69
SENSE_1TO1_55S
49 68 69
I300
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS2_N
49 69
SENSE_1TO1_55S
SENSE
SENSE
CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N
49 69
SENSE_1TO1_55S
49 69
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS2G_P
49 69
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUM_R_N
CPUIMVP_ISUMG_R_P
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUMG_R_N
49
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNSG_P
49
I309
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNSG_N
49
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS_P
49
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS_N
49
I313
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_P
65
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_N
65
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUMG_P
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUMG_N
68 69
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_THERMD_P
SENSE_1TO1_55S
SENSE
USB
USB_TPAD_R_P
USB_TPAD_R_N
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_1TO1_55S
SENSE
ISNS_5V_S0_HDD_P
49
SB_POWER
PP3V3_S5
6 7
SENSE_1TO1_55S
SENSE
ISNS_5V_S0_HDD_R_N
49
SB_POWER
PP3V3_S0
6 7
SENSE_1TO1_55S
SENSE
ISNS_5V_S0_HDD_R_P
49
SB_POWER
PP1V5_S3RS0
6 7
SENSE_1TO1_55S
SENSE
ISNS_LCDBKLT_N
SENSE_1TO1_55S
SENSE
ISNS_LCDBKLT_P
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_P
49
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_N
49
49
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
GND
*
TABLE_SPACING_ASSIGNMENT_ITEM
GND_P2MM
GND
LVDS*
*
GND_P2MM
I317
SENSE_DIFFPAIR
I318
SENSE_DIFFPAIR
SENSE_DIFFPAIR
I322
SENSE_DIFFPAIR
I321
SENSE_DIFFPAIR
I249
SENSE_DIFFPAIR
I250
I252
SENSE_DIFFPAIR
I251
I253
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I254
I256
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
OVERRIDE
OVERRIDE
MEM_72D
*
OVERRIDE
OVERRIDE
0.09 MM
400 MIL
OVERRIDE
OVERRIDE
0.09 MM
400 MIL
I255
OVERRIDE
OVERRIDE
I281
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I282
OVERRIDE
OVERRIDE
I283
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
MEM_37S
*
OVERRIDE
OVERRIDE
MEM_85D
*
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
400 MIL
OVERRIDE
OVERRIDE
0.09 MM
400 MIL
OVERRIDE
I284
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
6 60 61
6 60 61
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
6 60 61
6 60 61
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
C
6 60 61
SPK_OUT
DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I302
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I301
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I304
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I303
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
49 69
I305
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
49
I307
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
49
I306
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
49
I310
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I308
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I311
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I312
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I314
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
I315
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
AUD_DIFF
1TO1_DIFFPAIR
AUDIO
8 9
USB_85D
USB
CPU_THERMD_N
8 9
USB_85D
ISNS_5V_S0_HDD_N
49
CPUIMVP_ISNS2G_N
CPUIMVP_ISUM_R_P
I316
6 60 61
60
60
60
C
60
60
60
57 60
57 60
57 60
57 60
57 60
57 60
60
60
60
60
60
60
53
53
GND
GND
TABLE_PHYSICAL_RULE_ITEM
B
OVERRIDE
OVERRIDE
OVERRIDE
0.076 MM
10 mm
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
PCIE_85D
*
OVERRIDE
OVERRIDE
TOP
OVERRIDE
SENSE_DIFFPAIR
I291
TABLE_PHYSICAL_RULE_ITEM
USB_85D
OVERRIDE
I292
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_R_P
I320
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_R_N
49
I293
LVDS_90D
LVDS_PCH_TX
LVDS_CONN_A_CLK_F_N
6 74
I294
LVDS_90D
LVDS_PCH_TX
LVDS_CONN_A_CLK_F_P
6 74
I319
SENSE_DIFFPAIR
B
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
TOP
OVERRIDE
OVERRIDE
CLK_PCIE_90D
TOP
OVERRIDE
OVERRIDE
0.09 MM
400 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
A
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
400 MIL
OVERRIDE
OVERRIDE
Memory Constraint Relaxations
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.
Project Specific Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
MEM_72D
BOTTOM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.127 MM
6.35 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DRAWING NUMBER
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
TOP
0.1 MM
R
NOTICE OF PROPRIETARY PROPERTY:
7
6
5
4
3
2
SIZE
D
6.0.0
6.35 MM
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
051-9058
REVISION
BRANCH
PAGE
108 OF 109
SHEET
85 OF 86
1
A
8
7
6
5
4
3
2
1
K90i Board-Specific Spacing & Physical Constraints
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
ALLEGRO
VERSION
16.2
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
DEFAULT
*
Y
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
STANDARD
*
Y
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
BGA
BGA_P1MM
MEM_CLK
*
BGA
BGA_P2MM
CLK_PCIE
*
BGA
BGA_P2MM
CLK_SLOW
*
BGA
BGA_P2MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
DEFAULT
*
0.1 MM
TABLE_SPACING_ASSIGNMENT_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
D
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
Y
0.110 MM
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TOP,BOTTOM
*
=DEFAULT
TABLE_SPACING_ASSIGNMENT_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
STANDARD
DIFFPAIR NECK GAP
BGA_P1MM
*
=DEFAULT
TABLE_SPACING_ASSIGNMENT_ITEM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
*
Y
0.080 MM
0.080 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
BGA_P2MM
*
=DEFAULT
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_HEAD
TOP,BOTTOM
Y
0.165 MM
0.165 MM
LAYER
ISL10
N
0.126 MM
0.126 MM
1.5:1_SPACING
=STANDARD
=STANDARD
=STANDARD
*
0.15 MM
ISL3,ISL4,ISL9
Y
0.126 MM
0.126 MM
=STANDARD
=STANDARD
*
0.2 MM
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
2X_DIELECTRIC
*
0.140 MM
?
3X_DIELECTRIC
*
0.210 MM
?
4X_DIELECTRIC
*
0.280 MM
?
TABLE_SPACING_RULE_ITEM
2.5:1_SPACING
=STANDARD
WEIGHT
TABLE_SPACING_RULE_ITEM
?
*
0.25 MM
TABLE_SPACING_RULE_ITEM
?
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_ITEM
2:1_SPACING
=STANDARD
LAYER
TABLE_SPACING_RULE_ITEM
?
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TABLE_SPACING_RULE_ITEM
3:1_SPACING
*
0.3 MM
TABLE_SPACING_RULE_ITEM
?
5X_DIELECTRIC
*
0.350 MM
?
6X_DIELECTRIC
*
0.420 MM
?
7X_DIELECTRIC
*
0.490 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
D
0.090 MM
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
4:1_SPACING
*
0.4 MM
TABLE_SPACING_RULE_ITEM
?
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
37_OHM_SE
TOP,BOTTOM
Y
0.190 MM
0.1 MM
37_OHM_SE
ISL10
N
0.145 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
37_OHM_SE
ISL3,ISL4,ISL9
Y
0.145 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
37_OHM_SE
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
www.qdzbwx.com
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.2 MM
27P4_OHM_SE
*
Y
0.235 MM
0.2 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
55_OHM_SE
*
Y
0.070 MM
0.070 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_ITEM
72_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
72_OHM_DIFF
ISL3,ISL4,ISL9
Y
0.140 MM
0.140 MM
=STANDARD
0.190 MM
0.190 MM
72_OHM_DIFF
ISL10
N
0.140MM
0.140 MM
0.190 MM
0.190 MM
72_OHM_DIFF
TOP,BOTTOM
Y
0.175 MM
0.175 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
MAXIMUM NECK LENGTH
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_DIFF_BGA
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
85_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
85_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
ISL3,ISL4
Y
0.101 MM
0.1 MM
0.170 MM
0.170 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
ISL9,ISL10
Y
0.101 MM
0.1 MM
0.170 MM
0.170 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
TOP,BOTTOM
Y
0.125 MM
0.1 MM
0.190 MM
NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.
0.190 MM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_DIFF_BGA
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
90_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
90_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
B
90_OHM_DIFF
ISL3,ISL4
Y
0.091 MM
0.091 MM
0.180 MM
0.180 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL9,ISL10
Y
0.091 MM
0.091 MM
0.180 MM
0.180 MM
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
TOP,BOTTOM
Y
0.111 MM
0.111 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.
0.200 MM
0.200 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD
MAXIMUM NECK LENGTH
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_DIFF_BGA
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
ISL3,ISL4
Y
0.076 MM
0.076 MM
0.250 MM
0.250 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
ISL9,ISL10
Y
0.076 MM
0.076 MM
0.250 MM
0.250 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
TOP,BOTTOM
Y
0.085 MM
0.085 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4
Y
0.068 MM
110_OHM_DIFF
ISL9,ISL10
Y
110_OHM_DIFF
TOP,BOTTOM
Y
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
0.200 MM
0.200 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
=STANDARD
=STANDARD
0.068 MM
0.250 MM
0.250 MM
0.068 MM
0.068 MM
0.250 MM
0.250 MM
0.081 MM
0.081 MM
0.250 MM
0.250 MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
NOTE: These are Intel recommended impedances for PEG, unused on K90i.
TABLE_PHYSICAL_RULE_HEAD
A
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
48_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.165 MM
48_OHM_SE
*
Y
0.090 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MAXIMUM NECK LENGTH
TABLE_PHYSICAL_RULE_ITEM
SYNC_MASTER=K90I_MLB
SYNC_DATE=02/15/2011
PAGE TITLE
TABLE_PHYSICAL_RULE_ITEM
PCB Rule Definitions
DRAWING NUMBER
TABLE_PHYSICAL_RULE_HEAD
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
80_OHM_DIFF
*
N
=STANDARD
=STANDARD
80_OHM_DIFF
ISL3,ISL4
Y
0.115 MM
80_OHM_DIFF
ISL9,ISL10
Y
0.115 MM
80_OHM_DIFF
TOP,BOTTOM
Y
0.140 MM
=STANDARD
=STANDARD
=STANDARD
0.115 MM
0.180 MM
0.180 MM
0.115 MM
0.180 MM
0.180 MM
0.140 MM
0.190 MM
0.190 MM
051-9058
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TABLE_PHYSICAL_RULE_ITEM
8
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D
6.0.0
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SIZE
REVISION
BRANCH
PAGE
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