Introduction to
VHDL
ECE 200- Digital Logic Design
Fall 2016
Instructor: Prof. Baris Taskin
Introduction
qHardware
description languages (HDL)
q Language
to describe hardware used in electronic design automation in digital
and mixed signal systems.
q Two popular languages
q
VHDL: VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware Description
Language)
q
q
q
q
Developed by DOD from 1983
IEEE Standard 1076-1987/1993/200x
Based on the ADA language
Verilog
q
q
IEEE Standard 1364-1995/2001/2005
Based on the C language
ECE 200, Digital Logic Design
Applications
qModel
and document digital systems
q Different
q
levels of abstraction
Behavioral, structural, register-transfer level and gate-level.
qVerify
design
qSynthesize circuits
q Convert
from higher abstraction levels to lower abstraction levels
ECE 200, Digital Logic Design
Inputs and Outputs Specification
q
q
A
B
AND2
C
Example: AND2
q Inputs: A, B
q Outputs: C
VHDL description:
entity and_gate is
port (
A: in bit;
B: in bit;
C: out bit);
end and_gate;
ECE 200, Digital Logic Design
VHDL entity
entity and_gate is
port (
A: in bit;
Port names
B: in bit;
C: out bit);
end and_gate;
Direction of port
3 main types:
§in: Input
§out: Output
§inout: Bidirectional
ECE 200, Digital Logic Design
Name of the circuit
User-defined
Example:
Circuit name: AND2
File name: AND2.vhd
A
B
Datatypes:
§In-built
§User-defined
AND2
C
Built-in datatypes
• Scalar (single valued) types:
• bit
• boolean
• integer
• Examples:
• A: in bit;
• G: out boolean;
• Aggregate (collection) types:
• bit_vector: array of bits representing binary numbers
• signed: array of bits representing signed binary numbers
• Examples:
• D: in bit_vector(0 to 7);
• E: in bit_vector(7 downto 0);
• M: in signed (4 downto 0);
--signed 5 bit_vector binary number
ECE 200, Digital Logic Design
User-defined datatypes
qConstruct
datatypes
qExamples:
datatypes arbitrarily or using built-in
type temperature is (high, medium, low);
q type byte is array(0 to 7) of bit;
q
ECE 200, Digital Logic Design
VHDL Architecture
qVHDL description:
entity and_gate is
port (
A
A: in bit;
B: in bit;
C: out bit);
end and_gate ;
B
architecture beh of and_gate is
begin
C <= A and B;
end beh;
ECE 200, Digital Logic Design
AND2
C
Simulation
q Simulation
is modeling the output response of a circuit to
given input stimuli.
A
q For
our example circuit:
q Given the values of A and B
q Determine the values of Y
B
q Many
types of simulators used
q Event driven simulator is used popularly
q Simulation tool we shall use: ModelSim
ECE 200, Digital Logic Design
AND2
C
Thank You
ECE 200, Digital Logic Design