ModelSim Tutorial

ECE 200
Digital Logic Design - LAB
Tutorial: ModelSim
Lab Instructor: Prof. Baris Taskin
ModelSim Simulation and Environment
1. Start the ModelSim application:
Go to – All Programs -> ModelSim SE-64 10.1c (or any other version) and launch ModelSim.
2. New Project:
2.1 Create a new project : File -> New - > Project
2.2 Enter the Project name and the Project Location -> Click ‘OK’ :
2.3 Select ‘Create New File’ : Enter a File Name -> Click ‘OK’
Ensure the file type is VHDL
2.4 To edit the file : Right click on the and_gate.vhd file and select
2.5 Edit the File and save the changes.
3. Simulation using ModelSim
Example: Simulate a 2–input AND gate.
Port Name
Input operand 1
Input operand 2
Output - Anded inputs
4. Compilation: To compile the code click on the ‘Compile’ pull-down and select Compile All.
Error or success messages can be read in the Transcript Window.
5. Simulation
5.1 Start Simulation : After a successful compilation ->
Click on the ‘Simulate’ pull-down and select the Start Simulation button.
5.2 Design Architecture to Simulate: Expand the work library and select the respective architecture
5.4 Click on the ‘View’ drop down and ensure that Objects, Project, Transcripts, and Wave have been selected.
5.5 Click on the Add drop-down -> To Wave -> Signals in Design
6. Wave window :
Wave windows pops up as shown below.
Add the Input and Output signals to the Wave window as shown below:
6.1 Setting Signal Values:
Right click on a signal and ‘Force’ its value as required:
Assign a value to the signal in the ‘Value’ tab:
7. Single step run :
• Set the run period to 100 ns and click on the run icon. It is the first icon to the right of the 100 ns
• Adjust the zoom scale to correctly view the waves.
Complete Simulation:
Force the value of A to ‘0’ and B to ‘0’ -> Click the ‘Run’ button (Simulate tab).
The computed value of C (output) can be seen in the waveform
Validate the functionality of the 2 input AND gate by simulating all the other combinations of A and B.
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