Design and simulation of low power CMOS
compatible pH-ISFET readout circuit, with low
thermal sensitivity
A. HARRAK, S. E. NAIMI
SDMN Team, National School of Applied Sciences, Mohammed First University, Oujda, Morocco
Email: !!!@!!!
Abstract—A readout circuit for a CMOS compatible pH-ISFET
sensors is proposed in this paper, which carries out a temperature
compensation and high linearity by using a compact analog
circuit. The circuit was designed for a generic sensor structure,
which was modeled in Verilog-A and HSPICE, using the AMI
1µm CMOS process provided by MOSIS. The proposed scheme
reduces temperature sensibility and provide a linear circuit
output response. .
II. T HE READOUT CIRCUIT DESIGN METHODOLOGY
In this section, we will show the methodologies followed to
design a readout circuit.
A. pH-ISFET modeling
Keywords–component; ISFET; Readout Circuit; CMOS;
Temperature
I. I NTRODUCTION
The low cost Ion-Sensitive Field Effect Transistors (ISFET)
has been receiving more attention especially in areas of environmental monitoring applications and biomedical analysis.
Investigations on several fabrication processes of an ISFET
devices, have demonstrated that the pH-ISFET sensor can
be fabricated using a CMOS technologies [1]–[5]. However,
the monolithic implementation of pH-ISFET sensors on-chip
together with signal processing electronics would require
more investigation!!. The temperature sensitivity, the body
effect concerns and the device mismatch, due to the process
variation, are the greater problem for precision circuit design.
Thus, only few interfaces are suitable for integration in a
standard CMOS technology. Moreover, it is needed to simultaneously address precision, stability, power and reliability
constraints, while ensuring a reasonable yield. In particular,
thermal dependencies can lead to unacceptable results in
critical measurements. A lot of temperature compensation
techniques have been reported in the literature in order to
improve the pH-ISFETs stability [6]. The best of these circuit
are based on very complex architecture. The development
of simple analog circuit that can support all the constraints
mentioned previously is essential.
The solution presented in this work consists in a relatively
simple analog readout-circuit operating in differential mode
that provide an improved thermal insensitivity with a linear
response for a large variation of the pH. We show that the
idea of the designed circuit can be robust enough to consider
a industrial production.
Fig. 1.
Macro model
As the thermal characteristics of the ISFET are very important for the circuit design, the need for accurate component
modeling taking into account the temperature dependence of
the sensor is obvious. Lot of literature shows that the temperature dependence of a pH-ISFET is complicated and strongly
dependent of variable environmental conditions [7]. MOSFET
part of the pH-ISFET as well as the reference electrode or the
electrolyte temperature influence have been subject to many
research [8]. The combination of the well-known site binding
model and the MOSFET model to describe the behaviour of an
ISFET sensor provide an accurate representation of measured
DC component performance [9]. Figure 1 shows a behavioural
representation of the pH-ISFET sensor, in the macro-model
represented schematically the double capacitance of Helmotz
and Stern double layers are added, based on already existing
theories [10]. In summary, the flat-band voltage shift has a
standard expression (for an Ag/AgCl reference electrode) [11]:
∆VF B = Eref (
Ag
dEref
)+(
)(T − 298.16) + Eref
AgCl
dT
z
+χ
ψ0
}|
{
KT
+ ∆φ − 2.303
S(pHpzc − pH) (1)
BSIM3
q
G’
sol∆VFB
D
lj
G
B
Eref
Verilog-A
CGouy
CHelm
ψ0
Spice
S
(
)
[
0
exp( −2ψ
q
UT ) − exp(log(ka × kb) + 4.6pH)
ψ0 =
Nsil
+
−ψ0
0
Ceq
exp( −2ψ
UT ) + exp(log(ka) + 2.3pH)exp( UT ) + exp(log(ka × kb) + 4.6pH)
(
)]
0
exp( −ψ
UT )
qNnit
(2)
Kn
0
exp( −ψ
UT ) + Ka exp(log(ka) + 2.3pH)
(i.e Vout = (V3 − V4 )/T ). The basic equation of the circuit is
(assuming α1 = α2 ):
(α1 V1 + α1′ ) − (α2 V2 + α2′ )
T
α1 (V1 − V2 ) + α1′ − α2′
α1 ∆VF B + α1′ − α2′
=
=
T
T
Vout =
(3)
While Eq. (1) can be rewritten as:
Fig. 2.
schema bloc
Ag
dEref
) + −298.16
+ Eref + χsol
AgCl
dT
[
]
K
dEref
lj
+ ∆φ − T 2.303 S(pHpzc − pH) +
(4)
q
dT
∆VF B = Eref (
α2B.
, α2′
V 4 = α V + α′
Division by the
Temperature ( T1 )
∆VFB
where T is the temperature of the system, K is the
Boltzmann’s constant, q the electron charge, pHpzc is the non
zero pH, and S is the sensitivity factor of the gate insulator
and Eref (Ag/AgCl) is the relative potential of the reference
electrode, this potential is independent of the temperature
(0.205V ), the temperature coefficient of AgCl/Solution junction is practically negligible, d(Eref )/dT is the temperature
coefficient equal to 140µV /K. ∆φlj is the potential drop between the reference electrode and the solution, which typically
has a value of 3mV, χsol is the electrolyte-insulator surface
dipole potential, with a typical value of 50mV. Both ∆φlj and
χsol are pH independent.
In Eq. (1), ψ0 is the only parameter responsible for ISFET
pH sensitivity, as explained by the site binding theory. The
expression of the surface potential ψ0 is obtained for mono-site
sensitive material, in case of Si3 N4 membrane with two sites
the expression is more complicated as shown in Eq. (2) [12]–
[15]. To consider the second order phenomena, the expression
of the surface potential from Eq. (2) have been implemented
in Verilog-A. While the expression in Eq. (1), was used in all
steps of analysis and design of the readout-circuit.
In equation 2, q is the electron charge, Nsil the density
Attenuators
&
of silanol sites, Nnit the density of amine sites, UT the
Level Shifter
thermal voltage, ′ka-kb-kn are the dissociation constants for
V 3 = α 1 V1 + α1
α1the
, α1′ chemical
reactions at the Vinsulator
interface and Ceq =
4
= 3−V
T).
CGouy CHelm /(CGouy +VCoutHelm
2 1
2
The design
principle
of the readout-circuit
The basic representation of the readout circuit is given in
Fig. 2. The first bloc replicate the equivalent voltage ∆VF B
Polarization
bloc two floating nodes (∆V
across
F B = V1 − V2 ). Then the two
components of a differential potential are passed through two
attenuators in the second bloc. Actually each element in the
second bloc, act as a attenuator as well as a level shifter
yielding V3 = α1 V1 + α1′ and V4 = α2 V2 + α2′ . The third bloc
allows a division of the differential output by the temperature
And that finally:
dEref
K
Sα1 (pHpzc − pH) +
α1
q
dT
[
dE
Ag
α1′ Eref ( AgCl
) + −298.16 dTref + Eref + ...
Vout =2.303
+
]
T
χsol + ∆φlj + α1′ − α2′
T
(5)
α1′
α2′ ,
Note that with the appropriate choice of
and
the
third term of the sum can be easily eliminated. The final
simplifacation leads to :
Vout =2.303
dEref
K
Sα1 (pHpzc − pH) +
α1
q
dT
(6)
With the reasonable assumption that α, pHpzc and
dEref /dT present extremely low variations with the temperature, and under the restriction that α1 is a temperature
independent, the output voltage of the readout circuit can be
insensitive to the temperature. As it can be seen in Eq. (5,6)
the role of the two attenuators is dominating the accuracy
of the output. This stage requires a particular care for its
development.
The proposed strategy is evaluated through the readout
circuit presented in Fig. 3, which include, as threshold extractor, the caprio’s quad (M2, M3, M4 and the ISFET) and a
differential pair, operating in subthreshold region, as a circuit
to provide a division per T (Differential pair: M11-M12,
Active load: M13-M14). The polarization bloc is composed
by a cascode current mirrors (M20 to M27) and include
Caprio’s quad
Current mirror
M5
M2
Differential pair
Attenuators
ISFET
M13
M9
M14
M7
Vout
V1
M6
M10
R2
V3
Vcc
M18
M17
M19
M3
M4
Vcc
M11
V4
M12
M8
Vee
Vcc
M5a
M9a
M7a
V2
M6a
M15
M16
M20
M22
Vcc
M24
M10a
M26
M8a
Vee
R1
Fig. 3.M21Readout circuit: Vcc=-Vee=3V, R=30kΩ, R1=220kΩ (TC1=1.5e-3 TC2=5e-7)
M27
M23
M25
Vee
a basic reference source (M15 to M19), in addition to a
resistance R1 (which was, actually, modeled with the two
standard temperature coefficients TC1 (the linear temperature
coefficient) and TC2 (the quadratic temperature coefficient).
Two sub-circuits act as a attenuators and level shifters (M5 to
M10 and M5a to M10a). The proposed attenuators and level
shifters are presented in Fig. 4 as separated blocs.
Figure 4 (b) shows the classical attenuator, where the
transistors M7-M8 are used as an attenuator circuit, while
M9-M10 are clearly responsible for the shift of the resulting
voltage. However this circuit is not robust enough to overcome
the requirement like the linearity or the temperature sensitivity.
Actually the temperature sensitivity of this circuit can be
written, formally, as:
(a)
(
Vcc
dVT H7
β7 (2Voutb − Vcc − Vee )
− 2β6 (Vinb −
dT
M5
dVT H6
Vouta
Vinb
2Voutb + Vcc − VT H6 )
− 2β8 (Vcc − Voutb + VT H8M7)
dT
Vina
M6
)/(
dVT H8
×
2β7 (Vcc − Vee − VT H7 ) + 4β6 (Vinb − 2Voutb +
dT
Vcc
) M8
Vcc − VT H6 ) + 2β8 (Vcc − Voutb
(7)
Vee + VT H8 )
dVoutb
=
dT
i
Where βi = µCox W
Li for a transistor Mi. It can be easily
verified that, with appropriate choice of the device geometries,
the two members of the fraction in Eq. (7) can be negative
and so the variation of he output Voutb with the temperature
is positive. At the same time, the temperature sensitivity of
the circuit (a) is completely opposed, indeed:
dVouta
=
dT
(
dVT H1
(2β1 Vcc − 2β1 Vouta − 2β1 VT H1 )
+
dT
Fig. 4.
(a) first bloc attenuator, (b) second bloc attenuator and shifter
(Vee β2 − β2 Vouta )
(b)
Vcc
dVT H2
dT
)/(
(2Vouta (β1 + β2 ) − 2β1 Vcc
)
2β1 VT H1 β2 Vina + β2 Vee + β2 VT H2
(8)
M9
Finally,
Voutb the use of the two circuits can enhance the thermal
stability.
M10
C. Body effect
As the pH-ISFET has to be associated with an analog
circuit,
Vee the body effect in n-channel sensors is limiting the
possibilities of an ISFET source biasing. In a classical expression of the threshold voltage as in Eq. (9), the substrate bias
effect can causes an error in estimating the surface potential.
VT H = VF B + 2ϕB +
1 √
2ϵSi ϵ0 qNA (2ϕB − VBS ) (9)
Cox
The readout circuit, especially the caprio’s quad and the
ISFET, must be insensitive to any change of source to substrate
voltage variation. The body effect in the caprio’s quad is
usually considered as a second order effect [16]. We will
0.4
0.34
0.32
1.6
-0.2
-0.1
0.3
0
1.5
0.2
1.4
0.1
20°C
120°C
1.3
-3
-2.5
Output Voltage (V)
(a)
-2
-1.5
-1
-0.5
0.08
0
0
Input Voltage (V)
0.07
0.06
Output Voltage (V)
Output of Stage 1 (V)
0.09
0.36
Output of Stage 2 (V)
Stage 2
1.7
0.05
0.04
0.03
6
6.2
T=80°C
6.4
T=20°C
pH
0.05
0.04
0.03
0.02
(b)
0.8
0.01
Vout (V)
0
-0.01
0.75
0
2
4
6
8
10
12
pH
0.7
Fig. 6.
-3
-2.5
-2
-1.5
-1
-0.5
Simulation Results (T = 20◦ C and 80◦ C)
0
V (V)
in
Fig. 5.
CaraAtt
verify by simulation that the proposed circuit meets these
requirements using the modified caprio’s quad circuit.
III. S IMULATION R ESULTS AND DISCUSSION
Following a discussion of various phenomena (temperature
sensitivity and body effect), we will consider how the proposed
circuit meet our objectif!!!. In order to prove the effectiveness
of the proposed attenuator circuit and to show an improvement
of the temperature independent output, we simulate this circuit.
The parameters employed in the simulation will be shown
further in this section. As shown in the Fig. 5, the approach
suggested is able to eliminate the temperature insensitivity of
the bloc attenuators-shifter and to improve the linearity of the
circuit response. The sensitivity of the attenuator is around
!!µV /◦ C in the linear region and the residual error is estimated
to R2 =!!! at T = 20◦ C (R2 =!!! at T = 20◦ C).
The simulation results of the readout circuit is shown
in Fig. 6. As illustrated by the figure the output signal is
linear with pH and the design technique permits improving
temperature insensitivity. Indeed, the circuit output presents a
maximum temperature sensitivity, around !!µV /◦ C for pH=!!!.
The residual error is estimated to R2 =!!! at T = 20◦ C
(R2 =!!! at T = 20◦ C). The circuit sizing results are shown
in Table I. Despite body effects, our simulations confirm that
this phenomena can be neglected.
IV. C ONCLUSIONS
A novel readout circuit for a CMOS compatible ISFET
sensor type is proposed. In this study, the Verilog-A language,
have been used to describe the behaviour of the electrodeelectrolyte-sensitive membrane structure of the pH-ISFET.
While a standard model (BSIM3v3) was used in conjunction
with HSPICE for the MOSFET part of the sensor. The readout
circuit responds linearly with the pH variation from 1 to 12 and
for a temperature range from 20◦ C to 80◦ C. The residual error
is estimated to !!!. The linearity of the response is estimated
TABLE I
C ANAL WIDTH / LENGTH (µm/µm) OF ALL CIRCUIT TRANSISTORS
Device
W/L
Device
W/L
Device
W/L
ISFET
M2
M3
M4
M5
M6
M7
M8
M9
M10
M5a
20/4
20/4
19/4
19/4
8/4
20/10
14.5/2
6/2
9.5/8
9.5/8
8/4
M6a
M7a
M8a
M9a
M10a
M11
M12
M13
M14
M15
M16
20/10
14.5/2
6/2
9.5/8
9.5/8
10/2
10/2
20/2
20/2
8/2
40/2
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
4/2
4/2
8/4
8/4
8/4
180/2
180/2
180/2
180/2
5/40
5/40
with residual error which have a standard deviation σ 2 of !!!
with a mean m of !!! at 20◦ C and σ 2 =!! and m =!!! at 80◦ C.
The temperature sensitivity of the output is around !!! at !!!◦ C.
The results demonstrate the correct operation of the circuit.
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