Recent Development Work in IC Bond Pad Structure and Circuit Under Pad. Stevan Hunter

1

Recent Development Work in IC

Bond Pad Structure and Circuit

Under Pad

Stevan Hunter

Presented to IMAPS Student Chapter , UI, 29 SEP 2011

• Stevan Hunter

Who did the work ?

– Principal Reliability Engineer, ON Semiconductor , Pocatello, ID

– PhD Student, ISU ; IMAPS member

– (Project started in late 2008, early work constituted MS project, May

2010)

• Steven Sheffield , Cesar Salas , Jason Schofield , Jose

Martinez , Kyle Wilkins , Marco Salas

– Undergraduate student interns, Brigham Young University Idaho

– 1 per trimester starting in Fall 2009

– (Work is contuing with Jonathan Clark , Fall 2011)

2

• Bryce Rasmussen, Troy Ruud, many others...

– ON Semiconductor

** Work supported by ON Semiconductor **

Stevan Hunter Recent Development Work in IC CUP 29 Sep 2011

Scope of Today’s Presentation

Summarizing 3 presentations / publications in 2011, relating to

0.18µm CMOS IC Technology, and other CMOS with Al metallizations

1.

Hunter , et al, “ Use of Harsh Wafer Probe to Evaluate Various Bond

Pad Structures ”, IEEE SWTW, Jun 2011

2.

Hunter, et al, “ Use of Harsh Wire Bonding to Evaluate Various IC

Bond Pad Structures ”, IMAPS EMPC2011, Sep 2011

3.

Hunter, et al, “ Physically Robust Interconnect Design in Bond Over

Active Circuitry for Cu Wire Bonding ”, IMAPS / SEMI Wirebonding

Workshop, Jul 2011

3

(Two new papers to be presented at IMAPS 2011 in Oct)

• Martinez , et al, “ IC Bond Pad Structural Study by Ripple Effect ”,

IMAPS 2011, Oct 2011

• Hunter, et al, “ Bond Over Active Circuitry Design for Reliability ”,

IMAPS 2011, Oct 2011


Outline

• Traditional IC Bond Pads

• Wafer Probe

• Wirebonding

• The Cratering Test

• Mechanism of metals deformation and SiO

2 cracking

• Need for improved bond pad structures, BOAC / CUP

• Findings from harsh probing experiments

• Findings from harsh bonding experiments

• Design methodology for robust BOAC pad structures

• Pad Design Solution examples

• Summary

4 Stevan Hunter Recent Development Work in IC CUP 29 Sep 2011

Integrated Circuit Bond Pads

5

Example packaged

IC’s (from internet)

IC die example (photo: USC)


Wafer Probe (Electrical Test)

6

• Probe needles simultaneously touch all bond pads of the die in order to perform electrical testing of the die.

• Each touch damages the pad Al surface, leaving a “probe mark”


Simplistic View of Probing

(Cantilever probe tips)

Wafer comes into contact with the Probe Tip wafer: bond pad wafer Z-up


Wafer moves up into

Overdrive position for test, scraping the pad Al and causing a Probe Mark

8

Probed Pad Reliability Concerns

• Electrical OverStress (EOS) or Electrostatic Discharge (ESD)

– receives much attention and is usually eliminated in manufacturing

• Probe mark interferes with bondability

– probe mark area too large

– probe mark “gouge” too deep (too little Al remaining)

• Top intermetal dielectric (top IMD) cracks beneath pad Al

– crack weakens films adhesion and intermetallic bond strength

– crack in IMD causes crack in TiN barrier

• allows Al, Au, Cu diffusion into the circuitry

– crack may propagate during use (latent defect)

• physical weakening of pad and bond structure

– crack may extend to another metal feature

• electrical leakage or short

– crack is visible to a customer who does die analysis

• “obvious” reliability issue to customer


1 TD 2 TDs

2 Mils Overdrive

3 TDs 4 TDs 5 TDs 6 TDs

Pad #2 SLM Pads

1 TD 2 TDs

4 Mils Overdrive

3 TDs 4 TDs 5 TDs 6 TDs

Pad #2 SLM Pads


Probe Mark Analysis by AFM & Cratering Test

pad 8 pad 9

8 9


Probe Mark Analysis by FIB Cross Section

FIB through the probe mark center reveals gross cracking, with breakage of the top IMD and deformation of TM(-1)


Bond Pads and Wirebonding

It is typical for 25µ Au wire or 20µm Cu wire to be

“bonded” to each pad, and the wire connects to a lead on the package

Illustrations of ball bonds on bond pad structures (from ASE, Sep2011)


Wirebonding

A ball is formed at the end of a Au or Cu wire, then the ball is squished onto the Al pad surface and welded by ultrasonic energy


Upper photos: www.kns.com

Wirebonding / Pad Reliability Concerns

• Bond ball poor adhesion

• Bond stability against corrosion and diffusion

– Au-Al IMC issues

– Resistance increase over time

– Loss of adhesion over time

• IMD cracks (critical if BOAC / CUP pad)

• Bending and deformation of BOAC / CUP metal circuitry

• ESD protection (circuitry under pad in BOAC / CUP)

• Bond wire adhesion to package lead

• Bond wire integrity against corrosion or oxidation

• Bond wire stiffness to combat bending during plastic molding


15

Bonded Pad Issues and Analysis Methods

1. Bond Pull Strength test (BPS)

– Hook the wire loop and pull up until breakage

– Record the breaking force and failure mode (accepted spec limits)

– Ball may come off the pad at a low force due to poor adhesion

– Ball may pull out a chunk of the pad as it pulls off (pad divot or crater)

2. Ball Shear test (BS)

– Shear (bulldoze) the ball off the pad

– Record the breaking force and failure mode (accepted spec limits)

– Ball may come off the pad at a low force due to poor adhesion

– Ball may pull out a chunk of the pad as it pulls off (pad divot or crater)

–

Note that when the films adhesion is strong and the ball is stiff, BS test will break something in the structure – interpretation of results may be difficult

3. Cratering Test

– Etch away the ball and pad Al, then optically inspect for damage

• Cracks, lifting barrier film, divots and craters, and ripple effect

– SEM inspection, FIB or cross section polish SEM


Traditional bond pad: 4-level metal example

A 4-level metal pad structure within the

“pad window” is illustrated in concept:

Al metallization: TiN / Al(0.5%Cu) / TiN ,

W vias , SiO

2 dielectric

• sheets of metallization at all levels

• via arrays connecting the metals

• SiO

2 dielectric surrounding

(Periphery of pad structure, passivation, Si devices, etc. are not shown)

Pad Al (MT)

Top Vias

Vias

MT(-1)

MT(-2)

Vias

MT(-3)


Pad Cracking: Process Flow

Wafer probe

(electrical test)

Wirebond Packaging Operation

1.

Compressive stress from probe force

2.

Lateral stress from scrub

3.

Multiple touchdowns

1.

Compressive stress from

C/V + downforce

2.

Lateral stress from ultrasonic

1.

Thermal cycling

2.

Stresses from packaging

1.

Use conditions

2.

Thermal cycling

Cracks initiate, then propagate

(crack)


“Cratering Test” (1)

• Cratering Test

(removal of bond ball and pad Al, then visual inspect)

– Etch to dissolve or undercut the bond ball, and etch away the pad Al, but purposely leave some of the

TiN barrier film if possible

– visually observe top SiO

2 cracking

– visually observe other damage:

• “lifting barrier”

• other loss of adhesion

• divots in top IMD

• craters


Wafer Probe Cratering Test

• Cratering test removes the pad Al and the probe mark

• Usually etch only the Al to leave TiN barrier

– easier to see the cracks (highlighted in red below)

• Can also overetch the TiN to reveal etch damage in the underlying metal layer

Pad 1 Pad 2 Pad 3 Pad 4 Pad 5 Pad 6

Probe

Mark

Normal

Etched

Over

Etched



• Enables comparison between standard and harsh wirebond, and various pad structures

Top Vias No Top Vias

Au ball bond

Harsh Au ball bond



• optical “ripple effect”

– deformation in underlying metal interconnect (verify by FIB or XSEM)

Au ball bond Harsh Au ball bond

FIB cross section of “traditional” bonded pad test structure

Al

Top SiO

2

SiO

2

Al



• Not all issues can be seen in cratering test

– cannot detect weakened locations

– may not see cracks in SiO

2 if the TiN barrier is not broken

– cannot detect partially cracked locations on the bottom of the SiO

2


Damage relating to top vias

• top vias participate in SiO

2 cracking, giving traditional pads with top vias the worst record for cracking

• lifting TiN, SiO

2 with top vias divots, and craters are much more likely cracks propagate from via to via an example of “lifting barrier”, relating to top vias


Al Deformation & SiO

2

Cracking

Basic issue with traditional pad designs :

• Large mechanical stress into brittle SiO

2 ductile Al film film over

• Underlying Al deforms into local “hills” and “valleys”, which bends the SiO

2 which cracks when its tensile fracture strength is exceeded

– Cracks may initiate in the top of the SiO

2 above deformed Al hill

– Cracks may initiate in the bottom of the SiO

2 in deformed Al valley

• Significant stress may be applied in wafer probing

• Significant stress may be applied in wirebond, especially Cu

• Additional stress may be applied in packaging

• Cracks and weak regions in the SiO

2 but remain a reliability concern may go undetected,


Pad Stack Design Leads to Pad Cracking

Pad Window (probe and bond stresses here)

Al

SiO

2

Al

SiO

2

Al

SiO

2

Al

SiO

2

Si

2.) SiO

1.) Al film deforms into hills and valleys

2 bends and cracks

(TiN barrier layers not shown, for simplification)


Pad Stack Design Leads to Pad Cracking (2)

Pad Window (probe and bond stresses here)

Al

SiO

2

Al

SiO

2

Al

SiO

2

Al

SiO

2

Si

2.) SiO

1.) Al film deforms into hills and valleys

2 bends and cracks

(TiN barrier layers not shown, for simplification)


Examples of Cratering Test Results

Pad crack from ball bonding

Latent damage from wafer probe “revealed” from bonding

Barrier lifting, and divot in top IMD

27

Pad “ripple” from ball bonding

FIB cross section of divot.

Sublayer Al “ripple” caused the crack


Needs for Al – SiO

2

Bond Pad Structures

Need a methodology to accomplish the following together:

28

• Bond-over-active-circuitry (BOAC) , 2 – 7 levels of metal

• Maximum pad design flexibility for small die size,

• Interconnect circuitry in all levels below the pad metal, (& ESD protection)

• “pad anywhere” is desirable

• Up to 6 wafer probe touchdowns

• Cu wirebond to replace Au wirebond

• Higher reliability

– No bending or deformation in sub-layers

– No cracks

– No other bonding issues

• Often cannot use thick top metal (MT)

• Decreased cost


Engineering Tradeoffs / Issues

• Metal bending and deformation in interconnects is not acceptable in BOAC / CUP

• Pad cracks are not acceptable in BOAC / CUP

• Traditional pad structure cracks easily from wafer probing

• Traditional pad structure cracks easily from wire bonding

• Thin top metal increases stress to reach underlying films

• Cu wirebond increases stress on the pad Al

• High number of probe touchdowns increases pad cracks

• Cannot add new layers or process steps

• Cannot introduce new materials or layer alterations

• No existing methods to solve these simultaneously

• …Need methodology for more robust pads


Available Methods for Al – SiO

2

Pads (1)

1. reduce the mechanical stress to the bond pad Al

– minimize touchdowns and force at wafer probe

– minimize stress at wirebond but, Cu wirebond still requires more mechanical stress than Au wirebond

2. modify the top of the pad to reduce the stress reaching the underlying pad structure

– thicker pad Al

– alter the barrier film

– add films to the pad top but, the above add cost and complexity, and adverse engineering tradeoffs; deformation and cracking are reduced but are not necessarily prevented in Cu wirebond


Available Methods for Al – SiO

2

Pads (2)

3. modify pad structure features for a specific purpose

– change the pad metal topology to improve Au wirebond adhesion

– modify the top via pattern in or around the pad to prevent cracks or to contain the cracks within the pad window location

– eliminate top vias in the pad window to reduce cracking

– use vias in combination with specific metal patterns to “strengthen”

– remove metal features to reduce stress to devices beneath

– place dummy metal features for damping of bonding stress

– use specific connected bus structures suitable for BOAC

– use certain metal patterns to reduce pad capacitance

– use metal features to dampen the bonding stress

But, no method or combination of these methods meets the needs for freeform design of BOAC with Al-based interconnects in all metal levels beneath the pad window, especially not for achieving pad structures robust enough for the increased mechanical stress of Cu wire bonding.


Findings from Harsh Probing Experiments

• Optimize probing parameters for reduced force as required

– Multiple touchdowns still pose some risk for cracking

• Presence of a full sheet of Al metallization beneath the pad dominates cracking behavior

• Top vias weaken the SiO

2

• Thick pad Al reduces interconnect metal deformation and SiO

2 cracking

• Prevent pad cracks at wafer probe by preventing bending of top SiO

2

; i.e. prevent deformation in underlying Al film

– Lower metal pattern density of interconnect layers, especially MT(-1)

– In particular, ensure small metal width between spaces, slots, or holes in

MT(-1)

– (Cracks tend to occur where probe force is above MT(-1) areas)

– (Cracks tend to occur where probe scrub path transitions from MT(-1) space to MT(-1) metal in the pattern)


MT(-1) experimental design examples

• After cratering test, cracks are visible in the TiN barrier

• MT(-1) patterns can be seen, after removal of pad Al and

TiN barrier film

Examples of metal test patterns in MT(-1) full sheet, no vias under full sheet, no top vias, but dense vias under

33

[ref: Hunter, et al; IEEE SWTW JUN 2011]


Harsh Probe

Data

Experimental Bond Pads

Fraction of cracked pads vs metal pattern density in MT(-1)


Harsh Probing: Pads cracked vs MT(-1) pattern


Findings from Harsh Bonding Experiments

(1)

Harsh Bonding results are very similar to harsh probing results

• Pad structures crack due to high bonding stress, so we optimize for low stress in manufacturing

– Cu bonding stress is “harsh” regardless

– Simulate the same high stress by un-optimized Au ball bond recipe

• Presence of a full sheet of Al metallization in pad sub-layers dominates cracking behavior

• Top vias weaken the SiO

2

• Thick pad Al reduces sub-layer interconnect metal deformation and SiO

2 cracking


Pad Al Thickness Reduces Sub-layer Deformation

Cratering test ripple: Au ball bond on traditional pad structure

1µm pad Al

7% pads cracked

1.5µm pad Al

4% pads cracked

3µm pad Al

0% pads cracked


Findings from Harsh Bonding Experiments

(2)

• Prevent pad cracks at bonding by preventing bending of top

SiO

2

; i.e. prevent deformation in underlying Al film

– Lower metal pattern density of interconnect layers, especially MT(-1)

– Presence of MT(-1) features and vias beneath may be beneficial, unless high pattern density

– Reduce metal width between spaces, slots, or holes

• Other

– Bonding cracks don’t tend to interact with interconnect patterns

– Removal of metal in all layers beneath pad is unacceptable due to potential harsh bonding strain on devices beneath and increased cracking outside pad window

– Traditional reliability testing is not likely to reveal cracking issues


Summary: Bond Pad Structure Cracking Results

Harsh Probing and Harsh Au Wirebonding

Traditional

Weakest

No top Vias

Slight improvement

Missing MT(-1)

More improvement

Slotted MT(-1)

Better

Waffle MT(-1)

Better

Missing MT(-1) and MT(-2)

Very good

39

Missing MT(-1) Slotted MT(-2)

Best

Missing MT(-1) waffle MT(-2)

Best


Missing MT(-1, -2,-3)

Strongest

“Harsh” Au Wire Ball Bonding Results

10206 pads analyzed in this experiment

Pad test structure examples. These pads have Top Metal removed

40

Indicates Pad Designs with TM(-1) Missing.


Au(1%Pd) 1 mil Wire Bond

(Non-optimized Recipe, 2000 pads)

Crater Test & Ball Shear Results for Different MT(-1) Pad Structures

Only traditional pads exhibited consistent cracking for AuPd ball bond.


Cu 1 mil Wire Bond

(2000 pads)

Crater Test & Ball Shear Results for Different TM(-1) Pad Structures

Only traditional pads exhibited consistent cracking for Cu ball bond.


43

Au & Cu Wirebond Reliability Test Results

• 1mil Au wirebond, and 1mil Cu wirebond rel tested in parallel,

• 3 different robust pad BOAC designs, electrically test I

L

• 1 assembly lot (300 plastic packaged parts) each

BPS

BS

2

• 0.8um Pad Al thickness on robust pad

• Au bonds : large IMC growth, some voiding

• Cu bonds : Al remaining under bond, very little IMC, no weakening or resistance increase – more reliable for high temperature applications, don’t need thick pad Al


44

Design of Physically Robust Pads

>>> don’t let the SiO

2

“bend” significantly during pad stress <<<

Do this by preventing Al deformation beneath the SiO

2

• Prevent Al “hills” and “valleys”, prevent plastic deformation

– Do this by lowering the metal pattern density in the metal sub-layers beneath the pad window, predominantly in MT(-1)

– Limit the maximum allowed metal width (or distance) between spaces, slots or holes in the metal sub-layers beneath the pad window, with the most restriction imposed in MT(-1)

– Vias beneath MT(-1) and MT(-2) features are encouraged

Below: Example of how robust pad design guidelines may be specified

(actual values are technology-specific)

MT Very thin nominal THICK

MT(-1) density

MT(-1) width

MT(-2) density

MT(-2) width

0-50% dense, very narrow

25 –75% dense wide

0-75% dense narrow

15-90% dense wider

0-85% dense not as narrow

15-95% dense widest


Examples of Robust Pad Design Solutions

1. 3LM BOAC, Au wirebond

2. 3LM Power Device, Cu wirebond

3. 4LM standard pad for design library, Au or Cu wirebond


Pad Design Challenge 1

3LM BOAC

• 3-level Metal, older CMOS technology,

• Very thin top metal

• Die area limit requires BOAC pads

– Freeform interconnect circuitry in M1 and M2

– Some top vias required

– Need ESD protection circuitry under pad

• Traditional bond pads historically had issues with cracks in non-optimized probing and bonding processes, partly due to the very thin top metal


Pad Design Solution 1

3LM BOAC

• M1 and below for ESD protection circuitry under pad

– 93% M1 pattern density, mostly due to the natural spaces

• M2 sparse with only about 5% pattern density

• Top vias connect M2 to pad

• Pad electrical node conduction through dense vias outside pad window

47

• Successful product qualification, including extended reliability testing followed by wire pull, ball shear, and cratering tests

• No cracking found in harsh probing and harsh bonding tests with Au wire

• Issues with Cu wirebonding due to such thin top metal



3LM Power Device, Cu wirebond

• 3-level metal power device

• Thick top metal

• Cu wire bond

• “Pad anywhere” style BOAC

• Product failed qualification:

• Certain pads were having electrical shorts

– Caused by cracks in the top SiO

2

– Pads with large area M2 features in the pad window had the cracks



3LM Power Device, Cu wirebond

• DOE with a number of variations in lower metal density

– Various arrays of holes in M2 and M1

– Or selected slotting in M2 and M1

– And various via density changes between M2 and M1

• Arrays of holes in M2 were most successful at preventing cracks

– Don’t need holes in M1, only M2

– Via placement had no effect

– Lowered M2 pattern density to 80% on large area features

– Uniform lower density in the pattern is a benefit of arrayed holes

• Completed full reliability qualification without issues

• (Other products, including 2LM and 3LM, have been improved by the same method, both Au and Cu wire)



Reduced area pad for design library

• Well established CMOS technology

• Nominal top metal thickness

• At least 4-levels of metal

• Standard robust pad design for no MT(-1) in pad window, and full ESD protection under the pad

• Provide options for designers:

– Ability for designer to add MT(-1) interconnects for BOAC

– Permit use of ESD protection devices outside the pad instead


51


4LM standard pad for design library

• No MT(-1) in pad window

– MT(-1) and dense top vias for pad connection are outside pad window only

• Option for MT(-1) interconnect

– Simulated by bus structures with arrays of holes (75% pattern density in bus)

– Vias connecting MT(-1) to MT(-2)

• 4um wide bus structures traverse the pad window in MT(-2) for the various electrical nodes, about 50% pattern density

• ESD protection circuitry under pad, including the M1 circuitry

– Option to replace ESD circuitry under pad and use other qualified ESD protection circuitry as desired

• 3 pad designs qualified together

– Harsh probing, followed by harsh bonding tests with multiple wire types

– Standard and extended reliability qualification testing, with extra wire pull, ball shear, and cratering tests following the reliability stresses

• 1mil Au wirebonding

• 1mil Cu wirebonding


52

Summary

• Pad design challenges include various engineering tradeoffs

• Prior design methods for Al – SiO

2 provide the needed solutions pad structures don’t

• Basic BOAC / CUP pad design guidelines were developed based on extensive data:

– Various pad test structures

– Harsh probing

– Harsh Au wirebonding, AuPd, and Cu wirebonding

– Extended reliability testing, with physical pad tests following

• “Ripple” effect in the cratering test is valuable in assessing pad robustness

• Pad Al thickness is a less important parameter on a robust pad structure

• Examples of improved pad design in product solutions


Future Work

• Harsh Probing experiments are continuing

– More test structures in more CMOS technologies

– Different style probe cards

• Harsh Bonding experiments are continuing

– More test structures in more CMOS technologies

• Reliability testing Au and Cu wirebonded parts with new pad structures

• Implementing improved pads and Cu wirebonding on products

• Finite element modeling (FEM) to investigate robust pad physical principles

• Seeking to refine bond pad Design Rules for BOAC / CUP


W stud pressing on Al over SiO2

Basic 3D model

Von Mises

Stress after downforce


3LM Bond Pad with W probe touching it.

Films, top to bottom, are:

1um pad Al, 1um SiO2, 0.5um Al M2, 1um SiO2 IMD1, 0.5um

Al M1, 1um SiO2 ILD, 600um Si


Equivalent strain for 1E-5 uN probe force on 3LM bond pad.

High strain points at the edge of the probe, with strain continuing down through the layers.


Probed Bond Pad FIB Cross Section


2D Surfaces Sketch (YZ & ZX symmetry) with 5um radius flat tip


5u radius flat probe tip

100GPa pressure (all hidden except top SiO2 and MT(-1) Al)


Bonding “Ripple” in bond pad layers


Al “splash” in Cu ball bonding


2D Surfaces Sketch (YZ & ZX symmetry) with 60um radius “bond ball”


Hiding everything but the top SiO2 and

MT(-1)


Recent Development Work in IC Bond Pad Structure and Circuit Under Pad. Stevan Hunter

Recent Development Work in IC

Bond Pad Structure and Circuit

Under Pad

Who did the work ?

Scope of Today’s Presentation

Outline

Integrated Circuit Bond Pads

Wafer Probe (Electrical Test)

Simplistic View of Probing

Probed Pad Reliability Concerns

Probe Mark Analysis by AFM & Cratering Test

Probe Mark Analysis by FIB Cross Section

Bond Pads and Wirebonding

Wirebonding

Wirebonding / Pad Reliability Concerns

Bonded Pad Issues and Analysis Methods

Traditional bond pad: 4-level metal example

Pad Cracking: Process Flow

“Cratering Test” (1)

Wafer Probe Cratering Test

“Cratering Test” (2)

“Cratering Test” (3)

“Cratering Test” (4)

Damage relating to top vias

Al Deformation & SiO

Cracking

Pad Stack Design Leads to Pad Cracking

Pad Stack Design Leads to Pad Cracking (2)

Examples of Cratering Test Results

Needs for Al – SiO

Bond Pad Structures

Engineering Tradeoffs / Issues

Available Methods for Al – SiO

Pads (1)

Available Methods for Al – SiO

Pads (2)

Findings from Harsh Probing Experiments

MT(-1) experimental design examples

Harsh Probe

Experimental Bond Pads

Harsh Probing: Pads cracked vs MT(-1) pattern

Findings from Harsh Bonding Experiments

Pad Al Thickness Reduces Sub-layer Deformation

Findings from Harsh Bonding Experiments

Summary: Bond Pad Structure Cracking Results

Harsh Probing and Harsh Au Wirebonding

“Harsh” Au Wire Ball Bonding Results

Au(1%Pd) 1 mil Wire Bond

Cu 1 mil Wire Bond

Au & Cu Wirebond Reliability Test Results

Design of Physically Robust Pads

Examples of Robust Pad Design Solutions

Pad Design Challenge 1

Pad Design Solution 1

Pad Design Challenge 2

Pad Design Solution 2

Pad Design Challenge 3

Pad Design Solution 3

Summary

Future Work

W stud pressing on Al over SiO2

3LM Bond Pad with W probe touching it.

Equivalent strain for 1E-5 uN probe force on 3LM bond pad.

Probed Bond Pad FIB Cross Section

2D Surfaces Sketch (YZ & ZX symmetry) with 5um radius flat tip

5u radius flat probe tip

100GPa pressure (all hidden except top SiO2 and MT(-1) Al)

Bonding “Ripple” in bond pad layers

Al “splash” in Cu ball bonding

2D Surfaces Sketch (YZ & ZX symmetry) with 60um radius “bond ball”

Hiding everything but the top SiO2 and

MT(-1)

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