This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1 Integrated Design of a Class-J Power Amplifier Saeed Rezaei, Student Member, IEEE, Leonid Belostotski, Member, IEEE, Fadhel M. Ghannouchi, Fellow, IEEE, and Pouya Aflaki, Member, IEEE Abstract—This paper discusses the design of a monolithic microwave integrated circuit (MMIC) class-J GaN power amplifier (PA). Theoretical derivations of optimum load impedances, output power, and efficiency are presented to demonstrate their dependence on the quality factor of the integrated inductor used in the output matching network. A group of design curves are obtained to select the optimum transistor size and impedance according to the required output power and efficiency for a given inductor loss. An analytical-based design methodology using the design curves is proposed. To verify the accuracy of this analytical design approach, an integrated 0.5-W 15-V monolithic microwave integrated circuit PA is fabricated in 0.8- m GaN technology. The PA exhibits greater than 50% drain efficiency over 825 MHz, from 2.25 to 3.075 GHz. Index Terms—Broadband, class-J, design space, GaN HFET, inductor quality factor, monolithic microwave integrated circuit (MMIC), optimum resistance, power amplifier (PA). Fig. 1. Comparison of GaN, GaAs, and Si figures of merit . I. INTRODUCTION H IGH output power, high efficiency, and, recently, wide bandwidth are three desirable factors for RF/microwave power amplifiers (PAs). Higher circuit power efficiency leads to lower dc power consumption, therefore increasing the battery life and relaxing the heat dissipation requirements. Monolithic microwave integrated circuits (MMICs) are of great interest in RF/microwave applications due to their smaller sizes compared with that of hybrid circuits. Among the existing microwave device technologies, AlGaN–GaN semiconductor technologies are particularly suitable for MMIC power amplifier (PA) applications due to their superior performances to other semiconductor technologies such as GaAs and Si . Fig. 1 shows GaN figures of merit compared with GaAs and Si. As can be seen, GaN has significantly greater bandgap energy and breakdown field intensity, which translate into higher operating voltages. In addition to higher output power, higher closer drain voltages move the optimum load resistance to the center of the Smith chart. This provides the opportunity to minimize losses of the output matching network through requiring matching networks with low loaded quality factors. The low-quality-factor matching network is also relatively more Manuscript received September 11, 2012; revised January 02, 2013; accepted January 06, 2013. This work was supported in part by Alberta Innovative Future Technologies (AITF), the Natural Sciences and Engineering Research Council of Canada (NSERC), and the Canada Research Chairs (CRC) Program. S. Rezaei, F. M. Ghannouchi, and P. Aflaki are with the iRadio Laboratory, Department of Electrical and Computer Engineering, University of Calgary, Calgary AB Canada T2N1N4 (e-mail: [email protected]). L. Belostotski is with Micro/Nano Technologies (MiNT) Laboratory, Department of Electrical and Computer Engineering, University of Calgary, Calgary AB Canada T2N1N4 (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2013.2247618 broadband thus implying the possibility of wider bandwidth PA designs. These advantages make GaN device a strong option for broadband, high-power, and high-efficiency PAs , . Broadband PAs are of great interest as there is strong consumer desire to increase the functionality of their wireless devices. The availability of broadband PAs would reduce the need for multiple amplifiers inside of such devices, thus saving the development costs and speeding up the implementation cycles. While a particular semiconductor technology may be amenable to implement broadband PAs, a selection of a suitable PA type is perhaps even more important for wide bandwidth designs. Among the previously proposed PAs, switching-mode PAs ,  rely on the specific and precise multi-harmonic impedance terminations such as short and open circuits. These PAs normally exhibit narrowband frequency performance (less than 10%) and make switching-mode PAs less appealing for broadband applications. On the other hand, linear mode amplifiers such as classes A, AB, and B are less efficient than switching-mode PAs. Nevertheless, harmonically tuned class-B PAs can theoretically achieve peak efficiencies as high as 78.5%. However, the bandwidth of those PAs is also limited due to the difficulty in the realization of their low impedance harmonic load terminations over a wide bandwidth , . A recently proposed linear class-J mode of operation , with proper fundamental and second harmonic impedances has shown the theoretical efficiencies as high as those of class“deep” AB and class-B PAs –. However, since class-J PAs do not require harmonic resonators to achieve the maximum efficiency, there is a potential of increasing PA efficiency bandwidth compared with other linear amplifiers. On the other hand, in the integrated realization of power amplifiers, the inherent loss of inductors in the output matching 0018-9480/$31.00 © 2013 IEEE This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES network has a significant impact on the integrated PA performance and is not normally accounted for in the theoretical derivations of achievable output power and efficiency in the literature. Taking the advantages of the class-J PA and considering to the impact of the inductor loss in a PA design parameters, an implementation of an integrated 0.5-W GaN class-J PA through the proposed design methodology is the focus of this manuscript. This paper starts with a brief review on class-J PAs in Section II. Impedance locations of class-J on the Smith chart are illustrated in Section III and a simple two-element output-matching network is introduced to translate output load to the nearly class-J impedances. The dependence of 50 of the PA optimum resistance and efficiency on losses of an integrated inductor in the output matching network is analyzed and a design methodology to select the proper transistor size and the optimum impedance is presented in Section IV. Using the proposed methodology in Section IV, a MMIC PA is designed in Section V. Finally, the measurement results of the amplifier are presented in Section VI to show the broadband performance of the designed PA and confirm the simple and intuitive theoretical equations presented in Section IV. Fig. 2. Ideal class-J intrinsic drain voltage and current waveforms normalized and respectively, . to where and are the dc supply and the transistor knee voltages, respectively. The maximum and minimum drain voltages are calculated as II. CLASS-J PAS (3) In class-J mode of operation, both intrinsic drain voltage and current waveforms are theoretically composed of even harmonic components and thus are half sine waves. Moreover, in contrast to the class-B mode, where real fundamental load and short-circuit harmonic terminations are used; the class-J mode of operation is defined by an inductive/capacitive fundamental and capacitive/inductive second harmonic load terminations. A class-J amplifier is biased as a conventional “deep” class-AB PA that will be considered hereafter in the analytical development as class-B. Thus, a class-J PA demonstrates very similar drain current waveform to its class-B counterpart. Taking only second harmonic and neglecting other higher order even harmonics, the intrinsic half-cosine drain–current waveform as a function of the angular phase can be expressed as (4) (1) where is the transistor maximum drain current. The class-J drain voltage is engineered to satisfy two conditions. First, as for class-B or deep class-AB PAs, the drain voltage must be above zero to avoid clipping and to maintain the linear behavior of the amplifier. Second, no power must be delivered to the load at the harmonics. An intrinsic drain voltage waveform which satisfies the above conditions can be written as The intrinsic ideal class-J drain voltage and current waveforms normalized to and , respectively, are shown in Fig. 2. For simplicity in illustration, the knee voltage is assumed to be zero. The fundamental sine term along with the secondharmonic voltage term keep the voltage waveform above zero. The reactive components in the fundamental and second-harmonic manifest themselves as both a 45 shift between waveforms and as an increase in the maximum drain voltage to nearly . From Fig. 2, the overlap between the drain voltage and cur, where , disrent waveforms over the range of sipates power and results in the same theoretical efficiency and delivered power at fundamental as for a class-B amplifier; i.e., % and , respectively. In general, by rearranging (2), a set of intrinsic drain voltage expressions represents a family of class-J drain voltage waveforms that meet the class-J voltage requirements (5) where is a constant parameter bounded in the range of . Using (1) and (5), the required set of optimum intrinsic fundamental and second harmonic loading impedances presented to the transistor in class-J PA, under the assumption of the maximum drain voltage swing, are extracted as follows: (6) (2) (7) This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. REZAEI et al.: INTEGRATED DESIGN OF A CLASS-J POWER AMPLIFIER Fig. 3. Fundamental (solid line) and second-harmonic (dashed line) design spaces from class-J through class-B to class-J*. In the above expressions, represents the phasor of the flowing current into the optimum load, whereas the optimum for the maximum output voltage swing is equal to load . The set of impedances given by (6) and (7) are located on “design spaces” on the Smith chart as shown in Fig. 3, starting through class-B and ending up from class-J in class-J* . All fundamental and second-harmonic impedances in Fig. 3 result in the same output power, gain, and efficiency. This family of impedances provides the flexibility of choosing the design space amendable for a particular PA implementation. In addition, it is also important to note that, theoretically, no third-harmonic component exists in the class-J intrinsic current waveform, and, hence, the third harmonic is assumed to be opened. III. SELECTED DESIGN AREA FOR CLASS-J PA In general, the optimum intrinsic resistance of a class-J PA, , can be located in two distinct areas on the Smith chart: higher than 50 and lower than 50 . In relatively high-power PAs with high drain currents, the optimum resistance value would fall inside the resistance area that is lower than 50 . However, to design a medium output power PA, such as designed in this work, the optimum resistance should fall within the resistance area that is higher than 50 . Also, selecting higher has the advantage of reducing the dissipated power in the drain parasitic resistance, which is an extra power loss on top of the matching network loss and degrades the PA performance. The fundamental and second-harmonic impedance loci of and class-J* for 50 are class-J shown on the Smith chart in Fig. 4. From this figure, to reach any fundamental impedance on the class-J and J* loci from the center of the Smith chart, using only a two-lumped-element matching network suitable for - and -band integrated amplifiers, two possible configurations, identified as (a) and (b) in Fig. 4, can be used. Configuration (b) is attractive to simultaneously act as a matching network and a dc supply network. However, in configuration (b), the second harmonic impedance presented to the transistor is located far from the edge of the Smith chart and the impedance seen by the third harmonic is 3 Fig. 4. Fundamental and second-harmonic optimum intrinsic impedance loci 50 in class-J, (solid line) and class-J*, (dashed for line). Fig. 5. Schematic of the designed class-J amplifier. far from open, which is theoretically required in class-J PAs. Therefore, configuration (a) is selected in this work. Configuration (a) has the advantage of absorbing the intrinsic drain–source capacitance of the transistor into its shunt capacitor and, hence, reducing the required matching capacitance value. The circuit schematic, which uses configuration (a) for the output matching network and will be discussed in more detail later in Section V, is shown in Fig. 5. In this design, the output and parmatching network is built with series spiral inductor allel metal–insulator–metal (MIM) capacitor , which nearly synthesize the required fundamental and second-harmonic loads at the transistor drain. Taking into account that the output matching network is capable of presenting nearly equal impedances at fundamental and second-harmonic frequencies for the PA in Fig. 5, the study of on the amplifier output power and efthe impact of losses in ficiency is discussed in detail in Section IV. IV. STUDY OF INDUCTOR QUALITY FACTOR ON PA PERFORMANCE AND PROPOSED DESIGN METHODOLOGY Since the output matching network significantly affects the MMIC PA efficiency and output power delivered to the load, here we study the impact of the output matching network losses at the fundamental frequency on the PA performance and present a methodology to determine the design parameters of the PA presented in Fig. 5. As the capacitors have significantly are ignored. higher quality factors than inductors, losses in To investigate the impact of the inductor losses on the MMIC This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES PA performance, the inductor with the finite quality factor is modeled as a lossless inductor in series with a resistor . Using this representation, the next part of this section will derive design expressions, which directly relate the inductor quality factor to the transistor width and optimum . The usefulness of this relationintrinsic load resistance ship is then demonstrated through the design of an integrated class-J PA with the schematic illustrated in Fig. 5. Note that the intrinsic output capacitance of the transistor is absorbed , and the following theoretical expressions are in capacitor derived at the fundamental frequency. as the impedance looking into the matching Considering network and and as currents flowing into the transistor drain and output load, respectively, the power delivered to the is obtained as and to the output load matching network , The optimum intrinsic load impedance in a class-J PA, as a function of the inductor is derived by substituting (12) to yield into (14) The above expression is a function of inductor , which makes the design procedure dependent on a specific inductor value. To eliminate this dependence, another expression relating to is required. From Fig. 5, the admittance looking into the matching network at node 1, , is equal to the class-J optimum intrinsic admittance presented to the transistor, i.e., . Therefore, equating the real parts of and results in the following expression: (15) (8) (9) where , which is the series loss resistance of the inductor , can be substituted into (15) with and yields where the inductor loss is included in . Then, the amplifier power and efficiency reduction ratio due to the inductor loss from the transistor drain to the output load is calculated as (16) (10) Then, using (14) and (16) to eliminate expression relating to the inductor and is derived as: , a second-order , output power and are the PA efficiencies at the load and the tranwhere sistor drain reference planes, respectively. From (10), the reduction ratio of the PA output power and efficiency is derived as (11) As expected, (11) shows that series low-quality inductors in the output matching network can significantly degrade the PA delivered power and efficiency to the load. Thus, an integrated PA design procedure should not only focus on presenting the optimum load impedance to the transistor but also on optimizing the losses in the matching network. Taking into account the inductor , a procedure to choose the circuit design parameters, to achieve the desired output such as transistor size and power and efficiency is discussed next. By substituting from (11) into , the transistor maximum drain current can be derived as (12) Considering a hypothetical reference transistor with width and generating the maximum allowed current , the current density can be used with (12) to determine the required transistor width from the following expression: (13) (17) Solving (17) results in two roots and (with positive and negative signs in the numerator, respectively): (18) where and are coefficients related to parameters, which are given as and (19) (20) Since, for small values of , optimum resistance results in negative values and are unacceptable, is the meaningful solution of (17) and is used to determine the reduction ratio and the optimum transistor width. Similarly, using (14) in (11) to eliminate , the new expression for the PA output power and efficiency reduction ratio is yielded as (21) where inductor is the acceptable solution of (17) for a given and delivered power to the load . The drop of the This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. REZAEI et al.: INTEGRATED DESIGN OF A CLASS-J POWER AMPLIFIER 5 Fig. 6. Transistor optimum intrinsic resistance as function of the inductor for different and , using technology parameters of 0.75 A/mm 2.2 V. and PA efficiency from transistor drain to the output load due to the output matching network is calculated as Fig. 7. Efficiency drop (left vertical axis) and PA output power and efficiency reduction ratio (right vertical axis), as functions of the inductor for different and , using technology parameters of 0.75 A/mm and 2.2 V. (22) where is the dc power, which is obtained from , and is deduced from . Finally, the modified expression for the total transistor width by eliminating from (13) is derived as (23) Expressions (18), (21), (22), and (23) are design equations, which relate the important PA parameters, i.e., the efficiency and the output power, to the transistor width, technology-limited inductor , and the current density . Fig. 6 demonstrates the optimum resistance from (18) as a function of the inductor for the used GaN technology 60 mA/80 m, knee voltage of 2.2 V and for parameters dc supply voltages of 15, 12, and 9 V. For each dc supply voltage, acceptable optimum intrinsic reranging from 26.5 sistances are plotted for the output power to 27.5 dBm. From Fig. 6, for a given output power and value, lower inductor requires a lower . Also, decreasing reduces toward 50 , which could make the output matching network design much simpler. The drawback of lowering , when is fixed, associates with an increase in and, consequently, an increase in the transistor width the with its associated larger parasitic capacitances. Similarly, Fig. 7 illustrates the PA output power and the efficiency reduction ratio obtained from (21) and the efficiency Fig. 8. Total transistor width as function of the inductor for different and , using technology parameters of 0.75 A/mm and 2.2 V. drop from (22), whereas Fig. 8 shows the transistor optimal widths determined from (23) as functions of the inductor for the same range of and used in Fig. 6. As can be seen from Figs. 7 and 8, lowering dc supply voltage and minimizes the reduction ratio for a given inductor and the efficiency drop, respectively, while maximizing the total transistor width. An algorithmic design methodology has been developed for a PA shown in Fig. 5 to determine the amplifier design parameters. Based on the design requirements, the following steps are used and transistor width to achieve the to select the proper desired output power and efficiency. values from Fig. 6 over dc Step 1) Determine possible range for given parameters: 1) supply voltage PA output power and 2) technology’s inductor quality factor . This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES Step 2) Determine the total transistor widths corresponding to the selected range of values from Fig. 8. and , determine from Step 3) For the given parameters Fig. 7 the efficiency drop as well as the output power and efficiency reduction ratio , and then select the optimal dc supply value . Step 4) For the value, use Figs. 6 and 8 to select and to obtain the minimum efficiency drop due to the output matching network. Step 5) Design the output matching network to translate load to class-J impedances given in (6) impedance and (7). V. CLASS-J AMPLIFIER DESIGN To verify the theoretical expectations of class-J behavior, the proposed design procedure in Section IV can be used to determine the design parameters of a PA delivering 27 dBm of power at 2.5 GHz to a 50- load. The technology used in this work is 0.8- m GaN process on SiC substrate. The preliminary version of the provided GaN design kit, at the time of the PA design, included a limited number of transistor widths and fingers to provide the desired output power. Also, the existing integrated inductors in the design kit had the maximum quality factor of nearly 10 at 2.5 GHz. Taking into account those two restrictions, we start the amplifier design according to the proposed design steps. From Fig. 6, for output power 27 dBm and inductor 10, three intrinsic optimum resistances of 43, 83, and 135 corresponding to dc supply voltages of 9, 12, and 15 V are read. Using Fig. 8, the transistor widths for those optimum resistances are determined as 425, 315, and 253 m, respectively. From Fig. 7, the efficiency drop due to the lossy matching network for the determined optimum resistances are obtained as 4.7%, 9%, and 12.3% respectively. Therefore, from the efficiency perspective for the monolithic technology used and 27-dBm output power targeted, the optimum set of design parameters that should have been selected are 9 V leading to 43 and 425 m. Since the designed and fabricated PA preceded the development of the design methodology, we selected initially and unfortunately the 15 V suboptimal design with the following parameters: 135 and 253 m for the output leading to power 27 dBm and inductor 10. The closest total transistor width in the provided GaN design kit to the determined width of 253 m is 240 m. Based on the available number of fingers and widths in the design kit, it can be constructed either with four 60- m or six 40- m gate fingers. Due to the lower parasitic capacitances in smaller gate widths, we choose six 40- m gate fingers to construct the GaN HFET in this work. The HFET’s dc drain current and the transconductance as functions of the gate voltage are demonstrated in Fig. 9. 3.8 V when the The device is completely pinched off at drain is biased at 15 V. The drain current at 0 V is 160 mA, and the maximum drain current at 0.8 V is ob180 mA. According to the class-J bias tained at nearly condition of 5% , the device is biased at 3.4 V 7 mA. to draw the quiescent drain current of almost Fig. 9. DC transfer characteristics for 6 15 V. 40 m GaN HFET in bias point of Fig. 10. (a) Output fundamental and (b) second-harmonic load-pulling contours with de-embedded drain–source capacitance at 15-V dc supply, 17-dBm input power, and 2.5-GHz. PAE contours (solid lines) and output power contours (dotted lines). The selected transistor is first unconditionally stabilized by an on-chip stabilization network shown in Fig. 5. The stabilization 20 and the largest network consists of a series resistor available inductor in the design kit of 8.82 nH, which is used to provide a constant dc current and resonate at 2.5 GHz with the combination of the gate node capacitance and an external 0.36 pF. capacitor, To verify the theoretically determined intrinsic load impedances for the designed PA, transistor load-pulling simulation in Advanced Design System (ADS) simulator to achieve the maximum output power in the presence of the stability network is performed. In the transistor load pulling, the parasitic drain–source capacitance of 10 fF is de-embedded to obtain the intrinsic impedances presented at the intrinsic transistor drain plane. The output power and power-added efficiency (PAE) contours at the fundamental and second-harmonic frequencies for an input power of 17 dBm and center frequency 2.5 GHz are shown in Fig. 10(a) and (b), respectively. From Fig. 10(a), the transistor load pulling shows the maximum output power at a transistor drain plane of 27.5 dBm and PAE of 57%, which corresponds to a drain efficiency of almost 72%. The intrinsic output load impedances corresponding to the maximum output power and PAE obtained from load pulling This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. REZAEI et al.: INTEGRATED DESIGN OF A CLASS-J POWER AMPLIFIER 7 TABLE I INTRINSIC CLASS-J FUNDAMENTAL, SECOND-HARMONIC, AND SOURCE IMPEDANCES TO ACHIEVE THE MAXIMUM OUTPUT POWER AT 2.5 GHZ Fig. 12. Class-J PA scattering parameters. Fig. 11. Class-J amplifier intrinsic drain voltage and current waveforms. and class-J design theory are shown in Table I. As can be seen, the theoretical results are in good agreement with those from transistor load pulling. from transistor Table I also provides the source impedance source pulling at 2.5 GHz, which is used to design the input matching network. This value cannot be estimated with the relatively simple analytical device model used to derive the design methodology. The input matching network to translate 50 to in Fig. 5 consists of a series capacitor 0.36 pF, a shunt inductor 5.28 nH, and a series capacitor 6 pF, which blocks the dc path through inductor to the ground. In order to design an output matching network to translate 50 to the determined theoretical class-J load impedances, a 7.1 nH, with of nearly 10 at series spiral inductor 0.21 pF are used. 2.5 GHz and a MIM shunt capacitor The simulated intrinsic drain voltage and current waveforms of the designed class-J amplifier after de-embedding of the drain source capacitance is shown in Fig. 11. The simulation is performed with 17 dBm CW input signal at 2.5 GHz. The minimum and maximum intrinsic drain voltages are read as 2.2 and 37.5 V, respectively. With almost 50-ps time difference between the maximum voltage and zero current points in one RF cycle, the simulated PA demonstrates a nearly 45 phase shift at 2.5 GHz between the current and voltage waveforms at the drain of the field-effect transistor (FET), as was theoretically expected in Fig. 2. The quiescent drain bias current is maintained at 7 mA, which corresponds to a “deep” class-AB mode of operation. The simulated amplifier scattering parameters are demonstrated in Fig. 12. The maximum small signal gain is achieved 17 dB at 2.4 GHz whereas the isolation is simulated better than Fig. 13. Die photograph of the GaN MMIC amplifier. 23 dB in whole range of 2 GHz to 3.2 GHz. The minimum return loss is obtained 10 dB at about 2.4 GHz. VI. LAYOUT AND EXPERIMENTAL RESULTS To verify the accuracy of the proposed design procedure and the theoretical results obtained in Section IV, a MMIC PA was fabricated and its die photograph is shown in Fig. 13. In the fabricated 2 2 mm PA, circuit components are connected through 52- m-wide CPW lines with nearly 50- characteristic impedance. As the maximum current-carrying capacity for the interconnect layers in the integrated circuit technology in this work is 6 mA/ m for a single-layer interconnect, then a 52- m-wide CPW line, providing 50- characteristic impedance, can also carry the maximum drain current 180 mA, which was obtained from Fig. 9. Five 18- m-wide bridges depicted in Fig. 13 are employed to connect ground planes on the top layer. Out of two gold metal layers provided by the foundry, the amplifier layout is mostly realized on the This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 8 Fig. 14. Amplifier output power, drain efficiency, and PAE at the output load plane as functions of the input power at 2.5 GHz. Fig. 15. Amplifier output power and drain efficiency at the load plane as functions of the frequency at 17-dBm CW input power. first gold layer with the exception of the spiral inductors and the MIM capacitors, which are fabricated on both metal layers. The fabricated chip was mounted on a ceramic laminate. The power supply bond pad was wire-bonded to a printed circuit board (PCB) trace on the laminate. All measurements were conducted on wafer, using ground–signal–ground (GSG) probes. Fig. 14 shows the measurement and simulation results for the output power and efficiency at the load plane as functions of the input power swept from 0 to 20 dBm at a center frequency of is measured 2.5 GHz. Input 1-dB gain compression point as 12.5 dBm. At the input power of 17 dBm, the output power is measured as 26.8 dBm, which corresponds to the drain efficiency of 57%. At this point, the amplifier gain is compressed to about 3.2 dB. The maximum drain efficiency of nearly 59% at the saturation output power is achieved. In 10-dB input power back-off from the output power saturation point, the drain efficiency of greater than 44% is also measured. Fig. 15 demonstrates measured and simulated output power and drain efficiency as functions of the frequency at 17-dBm IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES Fig. 16. Amplifier simulated drain efficiency at the transistor drain plane in comparison with the measured efficiency at the output load plane as functions of the frequency at 17-dBm CW input power. input power. To generate this input power and apply to the amplifier, a signal generator along with a driver amplifier and an isolator are utilized. The isolator is used between the driver amplifier and the MMIC PA to avoid any potential instability and damage. As can be seen, the drain efficiency is measured greater than 50% over 825 MHz from 2.25 to 3.075 GHz, whereas the output power varies almost 1.5 dB over 625 MHz from 2.225 to 2.85 GHz. Fig. 16 represents the simulated drain efficiency at the transistor drain and the measured drain efficiency at the output load planes as functions of the frequency. Due to the inductor loss, a nearly 12.5% drop from the simulated efficiency at the transistor drain to the measured efficiency at the output load plane is observed, which is in good agreement with the theoretical value of almost 12% shown in Fig. 7. To investigate the linearity performance of the realized amplifier, inter-modulation distortion (IMD) measurement is performed using a two-tone signal. The resultant third-order IMD (IMD3) performance, obtained with 1-MHz tone spacing at a center frequency of 2.5 GHz, is depicted in Fig. 17, in which the IMD3 is plotted as function of the output back-off (OPB). As can be seen, the amplifier presents a minimum IMD3 of 32 dBc at 5-dB OPB. The IMD3 characteristic of the amplifier agrees with the predicted IMD3 patterns normally encountered on class-B PAs . for given inductor and Based on Fig. 7, lowering decreases the efficiency drop in the output output power matching network. To validate this, we carried on two additional class-J PA designs in ADS using dc supply voltages of 12 V 27 dBm (design 2) and 9 V (design 3) that can deliver at 2.5 GHz to the output load 50 . Their design led to series inductors in the output matching network with of nearly 10 at 2.5 GHz in both cases. Total transistor width is increased from 240 m in the original design, i.e., 15 V, to the realizable sizes of 320 m (8 40 m) and 420 m (6 70 m) in designs 2 and 3, respectively, while the optimum intrinsic resistance presented to the new transistors is decreased from 135 in the original design to 83 and 43 , respectively. The theoretical, from Fig. 7, and ADS simulation efficiency drop values for This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. REZAEI et al.: INTEGRATED DESIGN OF A CLASS-J POWER AMPLIFIER 9 the comparison difficult against those discrete PAs reported in the literature in terms of the efficiency and output power however; in terms of the bandwidth, it is among the best reported results of the class-J PAs. VII. CONCLUSION Fig. 17. Amplifier measured IMD3 as function of the output power back-off at a center frequency of 2.5 GHz. TABLE II EFFICIENCY DROP VALUES IN THREE DESIGNS WITH NOMINAL FREQUENCY 12 AND 9 V AT This paper presented a design methodology for an integrated 0.5-W GaN MMIC class-J PA along with an analytical study and quantitative analysis of the power-efficiency design paradigm. In this design, the losses in the output matching network are accounted to come up with an optimal design for a given output power. It is also shown that the output matching network, which does not require harmonic terminations such as short for harmonic tuned class-B, allows a class-J PA to achieve the broadband frequency of operation. A class-J PA was fabricated in a GaN technology to verify the accuracy of the theoretical design procedure and the simulation results. The fabricated broadband GaN MMIC class-J amplifier in 15-V dc supply voltage, experimentally demonstrated the drain efficiency of at least 50% in more than 800-MHz bandwidth from 2.25 to 3.075 GHz. Finally, two additional class-J PA designs were simulated to verify the theoretical approach to PA efficiency drop optimization by lowering the dc supply voltage. ACKNOWLEDGMENT The authors would like to thank CMC Corporation for supplying the GaN design kit and Agilent Technologies for providing Educational license of ADS software. - AND TABLE III -BAND CLASS-J PAS designs 2 and 3 are compared in Table II. As expected from the theory, the simulation results also verify the efficiency drop reduction from the original design to designs 2 and 3, when the dc supply voltages are decreased. The slight discrepancies between the drop in the efficiency values predicted by the theory and ADS simulation are likely due to the fact that the intrinsic losses in the transistor are not accounted in the simple model used to develop the analytical designed methodology in Section IV. A summary of the results presented in this paper and class-J PA results in the - and -band reported in the literature can be seen in Table III in terms of bandwidth, efficiency, gain, output power and the gain comparison points. Except of our work, all the other designs use 10 W packaged GaN transistor connected to the off-chip matching circuits. The technology limitation and the low Q on-chip matching circuit loss in our MMIC PA make REFERENCES  R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, and W. L. 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He is currently working toward the Ph.D. degree at the University of Calgary, Calgary, AB, Canada. From 2004 to 2009, he worked in the telecommunication industry in Tehran, Iran, where he served as Senior Research Engineer with the RF Group for GSM900, DCS1800, WCDMA, MMDS and LMDS Base Transceiver Station (BTS) projects. He is currently with the Intelligent RF Radio Laboratory (iRadio Laboratory), University of Calgary, Calgary, AB, Canada. His research interests include high-efficiency broadband RF power amplifier design, advanced transceivers circuit and system design, and monolithic microwave integrated circuit and analog radio frequency integrated circuit design. Mr. Rezaei was the recipient of the Teledyne DALSA Corporation Award in the Componentware category at the TEXPO competition, held by Canadian Microsystem Corporation (CMC) in Ottawa, ON, Canada, in October 2011. He was also the recipient of the Analog Devices Inc. Outstanding Student Designer Award in 2012. He also achieved Alberta Innovates Technology Futures (AITF) and Izaac Walton Killam Scholarships in 2012. Leonid Belostotski (S’97–M’01) received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Alberta, Edmonton, AB, Canada, in 1997 and 2000, respectively, and the Ph.D. degree from the University of Calgary, Calgary, AB, Canada, in 2007. A large portion of his M.Sc. thesis program was spent with the Dominion Radio Astrophysical Observatory, National Research Council (NRC), Penticton, BC, Canada, where he designed and prototyped a distance measurement and phase synchronization system for the Canadian Large Adaptive Reflector telescope. Following his graduation, he was with Murandi Communications Ltd., as an RF Engineer, during which time he designed devices for high-volume consumer applications and low-volume high-performance devices for the James Clerk Maxwell Telescope, Mauna Kea, HI, USA. He is currently an Associate Professor with the University of Calgary, the Director of the Micro/Nano Technologies (MiNT) Laboratory, University of Calgary, Calgary, AB, Canada, and the President of his own engineering consulting firm. His research interests include RF and mixed-signal ICs, high-sensitivity receiver systems and antenna arrays, and terahertz systems. Dr. Belostotski was the recipient of the IEEE Microwave Theory and Techniques 2008 MTT-11 Contest on “Creativity and Originality in Microwave Measurements” and the Analog Devices Inc. Outstanding Student Designer Award in 2007. Fadhel M. Ghannouchi (S’84–M’88–SM’93–F’07) received the B.Sc. and M.Sc. degrees from École Polytechnique de Montréal, Montréal, QC Canada, in 1983 and 1984, respectively, and the Ph.D. degree from the University of Montréal, Montréal, QC, Canada, in 1987. He is currently a Professor, Alberta Innovates Technology Futures/Canada Research Chair, and Director of iRadio Laboratory, Electrical and Computer Engineering Department, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada. He has held several invited positions at several academic and research institutions in Europe, North America, and Japan. He has provided consulting services to a number of microwave and wireless communications companies. He has authored and coauthored over 500 publications. He authored and coauthored 3 books. He holds 12 U.S. patents with five pending. His research interests are in the areas of microwave instrumentation and measurements, nonlinear modeling of microwave devices and communications systems, design of power- and spectrum-efficient microwave amplification systems, and design of intelligent RF transceivers for wireless and satellite communications. Prof. Ghannouchi is a Fellow of the Institution of Engineering and Technology (IET). He is a Distinguished Microwave Lecturer of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). Pouya Aflaki (M’12) received the M.Sc. degree in electrical engineering from Amirkabir University of Technology (Tehran Polyphonic), Tehran, Iran, in 2006, and the Ph.D. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada, in 2011. In September 2006, he joined the iRadio Laboratory, University of Calgary, Calgary, AB, Canada, as a Ph.D. student and Research Assistant. From October 2011 to April 2012, he was a Post-Doctoral Fellow with LACIME Laboratory, Ecole de technologie superieure (ETS), Montreal, QC, Canada, where he was involved with designing a laser diode driver for medical applications. Since May 2012, he has been a Post-Doctoral Fellow with the iRadio Laboratory, University of Calgary, working on wideband switching-mode power amplifier and advanced wireless transmitter design. His research interests include linear and switching-mode microwave power amplifiers, microwave passive circuits design, advanced transmitter architectures, linearization techniques, and large-signal device modeling.