5.1 General Register Organization
Type of CPU
1) Single Accumulator Org -> basic computer design
2) General R Org -> Set of general R to store data
-2 R & 1 W port
-R 0 contains an implied constant value “0”
3) Stack Org ( (-)up & (+)down )
-Stack -> M unit w an addr R that can count only
-Stack Pointer -> R that holds the addr for the stack
-SP always on top - LIFO - Data items don’t move in memory
-Push w Overflow Detection
-Pop w Underflow Detection
5.3 Instrc Format
Op Code -> Tell CPU what to do
Operand -> Tell CPU the content of this doing action (D/S)
1) 3/2 Addr instr. F (General Purpose R) = ADD AL, BL, CL
2) 1 A Addr instr. F ( Acc-based ) = PUSH AX
3) 0 A Addr instr. F (Stack ) = DAA
0
0
0
ADD opcode
REG 8
16
000 al ax
001 cl
cx
010 dl dx
011 bl bx
100 ah sp
101 ch bp
110 dh si
111 bh di
0
32
eax
ecx
edx
ebx
esp
ebp
esi
edi
0
0
d
d=0 R->M
d=1 M->R
s=0 8-bit
s=1 16/32 bit
MOD Meaning
00
R indirect A mode/SIB w no Disp
(R/M=100) or Disp only A
mode(R/M=101)
01
1 byte signed Disp (8disp)
10
4 byte signed Disp (32disp)
11
R addressing mode
s
Scale
00
01
10
11
In*S
*1
*2
*4
*8
Index
000
001
010
011
100
101
110
111
R
EAX
ECX
EDX
EBX
Illegal
EBP
ESI
EDI
Base
000
001
010
011
100
101
110
111
R
EAX
ECX
EDX
EBX
ESP
***
ESI
EDI
***DIS only if MOD=00, EBP if MOD=01/10
5.4 Addressing Modes
-To know EA -BA->implicit
R direct A
-MOV BX,DX
-MOV EAX, BX (X)
-MOV AL, AX (X)
Immediate A
-MOV BX, 1234H
-MOV 13H, AL (X)
-Don’t have EA
-X related to M
-data=operand
M Direct A
-MOV AL, [2400]
-MOV BX, ES:[1234H] (Override)
R Indirect A
-MOV AL, [BX]
-DX:BS (PA-20 bit)
-MOV CL, [SI]
-MOV [D1], AH
DISP A
-MOV CX, [BX+10]
-MOV CX,10[BX]
-MOV AL, [BP]+5
Indexed A
-MOV CL, [BX][DI] -DS:BX+DI
Scaled A (Base Index DISP)
-MOV AX, 4*BX
-ADD ECX, [EDI*4]
-ADD ECX, [EBX + EDI*4 + 1234H]
5.5 Program control
Branch group of instr.
= Conditional jumps / Unconditional jump / Iteration instr. / CALL instr. / Return Instr.
Subroutine (CS:IP)
-special segment of program that can be called for execution from any point in a program.
-To branch a subR, the value in IP/CS must be modified.
-Ori IP/CS must be preserved
Intra Segment
-A new 16-bit value which is specified
by instr. operand is loaded into IP
Direct call (PUSH)
-CALL S；SP←(SP)-2，SS:[SP]
←IP；IP←(IP)+16-bit offset
Indirect call
-CALL BX；SP←(SP)-2，SS:[SP]
←IP；IP←BX=offset
Return
 Return without operand
 RET
；IP←SS：[SP]，
SP←(SP)+2
 Return with operand
 RET n
；IP←SS：[SP]，
SP←(SP)+2，SP←(SP)+n
JMP (Short/Near/Word)
Direct jump
◼ Direct jump
Inter Segment
-At starting CS and IP placed in a stack.
-New values are loaded in to CS and IP given by the
operand.
Direct call
-CALL FAR PTR SUB2 ；SP←(SP)-2，SS:[SP]←CS；
SP←(SP)-2, SS:[SP] ←IP，IP← Offset of SUB2，CS←
Base address of SUB2
Indirect call
-CALL FAR PTR [SI] ；SP←(SP)-2，SS：[SP]←CS；
SP←(SP)-2, SS：[SP] ←IP，IP←[SI，CS←[SI+2]
 Return without operand
 RET
；IP←SS：[SP]，SP←(SP)+2，
CS←SS：[SP]，SP←(SP)+2
 Return with operand
 RET n
；IP←SS：[SP]，SP←(SP)+2，
CS←SS：[SP]，SP←(SP)+2， SP←(SP)＋n
(FAR/DWORD)
Direct jump
◼ JMP 1200H
；
◼ JMP FAR PTR NEXT
；CS：IP← New base
IP←1200H
address and new offset of NEXT
◼ Short jump
◼ JMP SHORT LOOP ；
IP←(IP)+8-bit offset
◼ Near jump
◼ JMP NEAR PTR L2 ；
Indirect jump
IP←(IP)+16-bit offset
◼ JMP DWORD PTR [DI] ；(IP) ←(DS：DI)，(CS)
Indirect jump
←(DS：DI+2)
◼ JMP CX
；IP←(CX)
◼ JMP [BX+SI]
；IP←[BX+SI]
◼ JMP WORD PTR [SI] ；IP←(SI)
mem16
Conditional Jump(JCC)
-Above and Below are used for comparing Unsigned numbers.
-Greater than and less than are used with signed numbers
Near jump
-Short jump (-128 to +127)
-Backward J
-Forward J
-Long jump (-32768 to +32767)
Loop Instr.
Format : LOOP Short-Label
 Operation: (CX)=(CX)-1
Interrupt Instr. ( Flag+IP+CS ) INT n 0~255
Method of creat’g a temporary halt during program execution & allows peripheral devices to
access the microP
Interrupt instr. w type number
 Its execution includes the following steps
◼ Flag register value is pushed on to the stack.
◼ CS value of the return address and IP value of the return address are pushed on to the
stack.
◼ IP is loaded from the contents of the word location ‘type number’ × 4
◼ CS is loaded from the contents of the next word location.
◼ Interrupt Flag and Trap Flag are reset to 0
 The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H
similarly for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt
pointers. i.e. −
◼ TYPE 0 -> division by zero situation.
◼ TYPE 1 -> single-step execution during the debugging of a program.
◼ TYPE 2 -> non-maskable NMI interrupt.
◼ TYPE 3 -> break-point interrupt.
◼ TYPE 4 -> overflow interrupt.
 The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors,
and interrupts from 32 to Type 255 are available for hardware and software interrupts.
INTO - Interrupt on overflow instruction
5.6 Characteristics and fn of instrc. set
General purpose data transfers = (MOV / PUSH / POP / XCHG / XLAT)
MOV
PUSH
MOV DST, SRC
 PUSH SRC
(DST)  (SRC)
 (SP)  (SP) – 2
 ( (SP)+1, (SP) )  (SRC)
XCHG
POP
 XCHG OPR1, OPR2
 POP DEST
 (OPR1)  (OPR2)
 (DST)  (SP)+1, (SP))
(SP)  (SP) + 2
XLAT (Translate byte)
 XLAT OPR
 ((AL)+(BX)+(DS)0)->(AL)
Address object transfers
LEA(Load Effective Address)
LES (Load Pointer Into ES)
◼ LEA REG, SRC
◼ LES REG, SRC
◼ (REG)  SRC
◼ (REG)  (SRC)
(ES)  (SRC+2)
LDS (Load Pointer Into DS)
◼ Before: (DS）=C000H
◼ LDS REG, SRC
(C0010H)=0180H
◼ (REG)  (SRC)
(C0012H)=2000H
(DS)  (SRC+2)
After:（SI）= 0180H (DS/ES)=2000H
IN instructions Port 0~255/DX 256~65535
Out instructions
-IN AL, PORT ; (AL)  (PORT)
-OUT PORT, AL ;(PORT)  (AL)
-IN AX, PORT ; (AX)  (PORT+1, PORT)
-OUT PORT, AX ;(PORT+1, PORT)  (AX)
** MOV DX, 3FCH
IN AX, DX
(X) IN AX, 03FCH
Arithmetic instructions
ADD
ADC
 ADD DEST, SRC
 ADC DEST，SRC
 (DST)  (DST) +(SRC)
 (DST)  (DST) +(SRC)+CF
INC
SUB
 INC DEST
 SUB DST, SRC
; (DST)  (DST) - (SRC)
 (DEST) (DEST)+1
 SBB DST, SRC
;(DST)  (DST) - (SRC) - CF
 DEC OPR
;(OPR)  (OPR) - 1
 NEG OPR
;(OPR)  0 - (OPR)
 CMP OPR1, OPR2 ;(OPR1) - (OPR2)
MUL
IMUL
 MUL SRC
 IMUL SRC
 (AX)  (AL) * (SRC)
 (AX)  (AL) * (SRC)
(DX, AX)  (AX) * (SRC)
(DX, AX)  (AX) * (SRC)
DIV and IDIV
CBW
 DIV SRC
 AL → AX
 (AL)  (AX) / (SRC)
if MSB of AL = 1 then AH = 255 (0FFh), else AH = 0
CWD
(AH)  (AX) % (SRC)
 AX → (DX,AX)
 (AX)  (DX, AX) / (SRC)
if MSB of AX = 1 then DX = 65535 (0FFFFh), else
(DX)  (DX, AX) % (SRC)
DX (DX)= 0000H
 IDIV SRC
Adjusting instruction of BCD code
 Packed BCD
(59)10 ＝(0101 1001)BCD
 AAA(‘+’), AAS(‘-’ )
◼ If (AL)0~3=0~9，and AF=0，
then (AL)4~7 = 0，AF → CF＝0
◼ If (AL)0~3=A~F，or AF=1，
then (AL)  (AL)±6，(AL)4~7＝0
(AH)  (AH)±1，AF → CF＝1
 Unpacked BCD
(59)10 ＝(0000 0101 0000 1001)BCD
 DAA(‘+’), DAS(‘-’ )
◼ If AF＝1 or (AL)0~3＝A~F，
then (AL)  (AL)  06H，AF＝1
◼ If CF＝1 or (AL)4~7＝A~F，
then (AL)  (AL)  60H，CF＝1
Logical Instructions
 NOT OPR
 (OPR)   (OPR)
 AND DST, SRC
 (DST)  (DST)  (SRC)
 OR DST, SRC
 (DST)  (DST)  (SRC)
 XOR DST, SRC
 (DST)  (DST)  (SRC)
 TEST OPR1, OPR2
(OPR1)  (OPR2)
 Shift and Rotate Instructions
 SHR/SAL: shift logical left/shift
arithmetic left
 SHR: shift logical right
 SAR: shift arithmetic right
 ROL: rotate left
 ROR: rotate right
 RCL: rotate left through carry
 RCR: rotate right through carry
 AND
 Used in clearing certain bits (masking)
 OR
 Used in setting certain bits
 XOR
 Used in Inverting bits
 Used to compare if two numbers are
equal
SHL OPR, CNT
SAL OPR, CNT
SHR OPR, CNT
SAR OPR, CNT
ROL OPR, CNT
ROR OPR, CNT
RCL OPR, CNT
RCR OPR, CNT
String Instruction
 Source DS:SI, Destination ES:DI
◼ You must ensure DS and ES are correct
◼ You must ensure SI and DI are offsets into DS and ES respectively
 Direction Flag (0 = Up, 1 = Down)
◼ CLD - Increment addresses (left to right)
◼ STD - Decrement addresses (right to left)
MOV BX,AL ;operand types must match
MOV BX,AX
;MOV 100, CL ;illegal immediate mode
;MOV SS,2400H ;illegal immediate mode
;MOV AX,IP ;symbol not defined: IP
;MOV CS,AX ;illegal use of CS
register
;MOV [BX],[SI] ;improper operand
type;X M to M
;MOV AX,[BX+BP] ;multiple base
registers
;MOV AX,[SI+DI] ;multiple index
registers
MOV AX, [SI+BX] ;base + index R
;MOV AX,[BX-SI] ;illegal use of
register
MOV AX, [BX+SI];
;MOV AX,[DX] ;must be index or base
register
MOV AX,[BX] ;SI/DI/BX
;IN
AX,2100H ;value put of range
MOV
DX,2100H;
IN
AX,DX;
;LDS AX,BX ;illegal use of register
LDS BX, [SI]
LEA BX, [SI]
;PUSH IP ;symbol not defined: IP
PUSH SI
;POP CS ; Illegal use of CS register
;ADD AX,DS ;improper use of segment
register
ADD AX, SI ;AX/BX/CX/DX/SP/BP/SI/DI
;INC [BX] ;operand must have size
INC BYTE PTR[DI+100H];
;MUL 20H ;immediate mode illegal
MOV AL, 01H
MOV CL, 20H
MUL CL
;SHL AX,4 ;Improper operand type
MOV CL,4;
SHL DL,CL;