Chapter 3 : Data Transfer and Microoperations 3.1 Bus system Bus Adv -shared comm. link (Data Transfer) -Versatility (New devices added easily/ -use 1 set of wires to connect mult Peripherals can be moved btw C system) subsystems** -Low Cost ** -Parallel & series connect’n Disadv -Be wired in Multidrop or Daisy Chain -Create comm. bottleneck (Bandwidth limit topology max I/O throughout) -Max bus speed is limited by (Length/No of devices/The need to support a range of devices) Types of Buses (Components of C) a) Internal (PCI/AGP/PCMCIA) -Int. data/M/System bus -Connect all int. CMPT of C (CPU & M -> Motherboard) -quick -Independent of the rest of C op. Data Bus -Allow data to travel (carry data) btw MicroP(CPU) & M(RAM) or I/O devices -Bi-directional (out-Read / In-Write) -8,16,32,64 lines -No of lines = width/wordsize -Signal names (D0,D1,D2,D3,etc) = D0~D15 b) External (USB/FireWire) -Expansion bus -Connect dif external devices Address Bus -Carry an Addr(info about locat’n of data) from CPU to M or I/O -Unidirectional -16, 20, 24, 32 lines -Width of Addr Bus = Max M capacity -Addr supplied by CPU -Signal Names (A0,A1,A2,A3,etc) Control Bus -Control signal that ensure EV is flowing smoothly from Place to Place -Collect’n of signal -> Coordinate CPU acts -Each Signal has a uniq purpose (M R/W, I/O R/W, Bus Rq, interrupt R, interrupt Ack, Reset, Clock, ) -10-20 lines -Signal = O, I, bi-directional Types of Buses(Org) = Point-to-point/Multipoint/Daisy chain Type of Buses (Fn) a) Dedicated b) Time Multiplexed (AD0 ~ AD15) -Separate D&A lines -Shared lines -Addr valid/ Data valid control line -Adv = Faster -Adv = Fewer lines -Disadv = Physically larger -Disadv = More complex control = Degradat’n of performance Bus Design Issues 1) Bus Width (D&A buses) 2) Bus Type (Dedicated/Multiplexed) 3) Bus Arbitrat’n (Centralised/Distributed)/ Priority -Obtain Access to the Bus (Problem=How is bus reserved by a devices that wishes to use it?) -Chaos is avoided by master-slave arrangem’t -Only Bus Master (CPU) control access to bus (Initiates & control all Bus Rq) ***DRAWBACK = involve in every transact’n -Slave (M) = respond to R/W Rq -Arb Sigal (Bus Rq/Bus Grant/Bus Priority) Multiple Potential Bus Masters need Arb ◼ Bus arbi scheme: ◼ Bus M wanting to use the bus asserts the bus request ◼ Bus M X use the bus until its Rq is granted ◼ Bus M must signal to the arbiter after finish using the bus ◼ Try to balance : ◼ Bus priority: Higher priority service first ◼ Fairness: No Rq is locked out a) Self Selection -Many Rq lines -The one w highest priority self decides to take bus b) Collision Detect’n (Ethernet) -1 Rq line – Try to access bus, -If collision device back off -Try again in random + exponential time c) Daisy Chain Arb -grant line runs thru all device, highest priority device 1st Disadv = X assure fairness ( low-priority device locked out) = Limit Bus speed d) Centralized Arb Simple Implementation of a Bus Arbiter 4) Bus timing a) Synchronous (simple) -Include a clock in control lines -A fixed protocol for C’m’n’c’t’n Adv =very little logic & fast Disadv = Device on bus run at same clock rate = X be long if fast (avoid clock skew) = Mixture of Fast & Slow devices, wait for the slowest device ( Fast X run at their capacity) b) Asynchronous -X clocked -Accommodate a wide range of devices -It can be long w/o worry clock skew -It requires a handshaking protocol Synchronous Timing Diagram Read Operation Timing Asynchronous Timing Diagram 5) Data Transmis’n a) Parallel -Carry data words in parallel on multiple wires b) Serial -Carry data in bit-serial form -D, A, and C are sequentially sent down single wire -There may be additional control lines 6) Bus Operat’n (R, W, block transfer, interrupt) 7) Bus Transact’n -perform 1> bus Operat’n -sequence of actions to complete a well-defined act (M R, M W, I/O R, Burst R) **2 parts -send Addr -Receive/send data -Master = initiates the transact’n (send Addr) -Slave =Responds to Addr by a) Send data to Master if master ask for data b) Receive data from Master if master wants to send data 8) Bus cycle ( Each Operat’n may take several bus cycles) 3.2 CPU-memory transfer Read Machine Cycle Place on the address bus ,the address of the location whose content is to be read .Done by the processor. Assert the read control signal which is part of the control bus. Wait until the content of the addressed location appears on the data bus. Transfer the data on the data bus to the processor De-activate the read control signal .The read operation is over and the address on the address bus is not relevant anymore. Write Machine Cycle Place on the address bus , the address of the location to which data is to be written. On the data bus, place the data to be written. Assert the write control signal which is part of the control bus. Wait until the data is stored in the addressed location. De-activate the memory write signal. This ends the memory write operation 3.3 I/O transfer I/O (Input/Output) ports (I/O addresses) Unique locat’n in M reserved for c’m’n’c’t’n btw the CPU & hardware D Be commonly associated with specific devices and should not be shared. How is I/O differentiated from memory? a) M-mapped I/O b) I/O-mapped I/O -reside in the same “space” -Occupy Dif “space” -access in the same manner (diff by Addr) -access by unique instr (dif by instr) -M instr = reference M -I/O instr ◼ move data to/from a specified I/O address (“port”) and a CPU register (e.g., the accumulator) ◼ IN port – inputs data from a device ◼ OUT port – outputs data to a device Implementation of I/O-Mapped I/O ◼ same Addr & data bus ◼ A dedicated Control bus signal differentiates a “memory cycle” from an “I/O cycle” ◼ On Intel’s Pentium CPU, this control bus signal is named M/IO ◼ M/IO = 0 → memory cycle ◼ M/IO = 1 → input/output cycle 3.4 Micro-operations Micro-operations (micro-ops or μops) Be detailed low-level instr used in some designs to implement complex machine instr(macro-instr). Perform basic operat’ns on data stored in one or more R, including transf’g data btw R or btw Rs & external buses of the CPU, and perform’g arithmetic or logical operat’s on R. In a typical fetch-decode-execute cycle, each step of a macro-instruction is decomposed during its execution so the CPU determines and steps through a series of microoperations. The execution of micro-operations is performed under control of the CPU's control unit, which decides on their execution while performing various optimizations such as reordering, fusion and caching.