OFC2013Burst-modeReceiverTechnologyforShortSynchronization

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[OFC 2013 Tutorial OW3G.4] Burst-mode Receiver Technology for Short
Synchronization
Conference Paper · January 2013
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[OFC 2013 Tutorial OW3G.4]
Burst-mode Receiver Technology for
Short Synchronization
Xing-Zhi Qiu ([email protected])
Ghent University – Information Technology Department (INTEC),
Interuniversity MicroElectronics Center (IMEC), Belgium
INTEC
X.Z. Qiu,http://
OFC’13,www.intec.ugent.be
OW3G.4 1
Outline
‰
Introduction
¾ Evolution of PONs (IEEE and ITU-T)
‰
OLT BM-RX Requirements
¾ High Optical Power Budget
¾ Short Burst Synchronization
¾ BM-RX Figure of Merit
‰
Overview of Fast Synchronization BM-RXs
¾ AC-Coupled & DC-Coupled BM-RX Configurations
¾ 3R Fast Synchronization BM-RX Architectures
¾ Dual-Rate BM-RXs
‰
Prototypes of IEEE/ITU-T BM-RXs/Sub-Systems
¾ IEEE 10G-EPON BM-RXs & System Performance
¾ 10G-PON Fast Synchronization BM-RXs Performance
‰
Summary
PON: passive optical network, OLT: optical line terminal, BM-RX: burst-mode receiver
X.Z. Qiu, OFC’13, OW3G.4
2
978-1-55752-962-6/13/$31.00 ©2013 Optical Society of America
1
Access Network Bandwidth Trends
‰
Technology Bandwidth Growth: 10x every 6 years
Source: Ronald Heron, Alcatel-Lucent ECOC’10 WS5
DS: downstream, US: upstream, BW: bandwidth
X.Z. Qiu, OFC’13, OW3G.4
3
ITU-T/IEEE TDM-PON Standards
‰
PON Standardization Organization for Optical Access
‰
ITU-T Recommendations [1]
¾ ITU-T FSAN Study Group 15 - Question2 “Optical systems for fibre access networks”
¾ IEEE 802.3 working group “CSMA/CD (ETHERNET)”: 802.3ah-EFM & 802.3av-10G PHY
¾ APON/BPON G.983.1,2,3,4,5
o
155/622Mb/s DS, 155Mb/s US
¾ G-PON G.984.1,2,3,4,5,6,7
o
o
o
o
2.5Gb/s DS, 1.25Gb/s US
G984.5: GPON Enhancement band
G984.6: GPON Reach extension
G984.7: GPON Long reach
¾ XG-PON G.987.1,2,3,4
o
o
(10Gb/s DS, 2.5Gb/s US)
Evolutionary growth of the existing GPON standard, and coexist with G-PON ODN
¾ NG-PON2 G.989.1,2,3 - 40-Gigabit-capable passive optical networks (NG-PON2): general
requirements, PMD layer specification / TC layer specification framework) – under study
o
‰
Revolutionary change of the existing GPON standard
IEEE Standards [2]
¾ 1G-EPON IEEE 802.3ah (1Gb/s DS, 1Gb/s US)
¾ 10G-EPON IEEE 802.3av (asymmetric 10/1G-EPON, symmetric 10/10G-EPON)
[1] ITU-T Recommendation G.983-987, [2] IEEE P802.3av 10GEPON Task Force, http://www.802.org/3/av/index.html, 2009
[3] Masaki Noda et al., OFC’12, OTh4G.6, [4] http://www.itu.int/itu-t/workprog/wp_search.aspx?sg=15
EFM: Ethernet in the first mile, ODN: optical distribution network
X.Z. Qiu, OFC’13, OW3G.4 4
2
Evolution of TDM-PONs
Data rate (bit/s)
10G chips reused
by 4x10G TWDM
40G
ITU-T standardization
Possibility of ITU-T/IEEE
synergies – 10G-PON optics
IEEE standardization
10G
ITU-T G.989 consented
NG-PON2 G.989
40G
ITU-T XG-PON G.987 completed in 2010
10/2.5GÆ10/10G
XG-PON G.987
Japan (10/1GÆ10/10G)
IEEE 802.3av
ITU-T PON deployment
10G-EPON 802.3av completed in Sept 2009
IEEE PON deployment
Milestone
G-PON 1st Interop Event in Jan 2006, wide scale
deploy 4Q 2007, G.984.1-6 amendments till 2008
G.984.x
2.5
G
G-PON: NA, EMEA
G-PON G.984 completed in June 2004
E-PON: Japan, China
IEEE 802.3ah
1G
EPON 802.3ah published in 2004
G.983.x published
Revised
622
M BPON G.983 completed in 2000, revised till 2002
BPON: NTT, Verizon
BPON 1st Interop. Event in March 2004
APON
155 FSAN founded in 1995
M APON G983.1 in 1998
1998
Year
2000
2005
2010
[1] Rob Bond, Telcordia, FTTH Council Webinar, July 30, 2008, [2] P. Vetter ECOC’12 Tutorial, Tu.3.G.1
TDM: time division multiplexing, TWDM: time/wavelength division multiplexing
X.Z. Qiu, OFC’13, OW3G.4
2013
5
FSAN 40G PON – ITU-T G.989
‰
NG-PON2 Initial Requirements
¾ One solution serving all markets (e.g. cost-effective high BW for residential users, 10G
symmetric for business users, multiple 10G links for mobile backhaul at low power
consumption)
¾ Min. 40Gb/s capacity, 40km reach at 64 split, no need for backward compatibility with
existing G-PON on same ODN and video overlay
¾ Technology options: TDM/WDM hybrid (TWDM), WDM-PON, OFDM-PON
‰
40-80G TWDM-PON: Preferred Pragmatic Choice by FSAN
[1]
¾ Basic configuration: min. 4 wavelengths (4x10G DS, 4x2.5/10G US)
¾ ODN and video overlay compatibility considered, XG-PON compatibility optional [2]
¾ Optical amplifiers at OLT for higher power budget than XG-PON [2]
¾ Wavelength plan pending (under discussion)
¾ Timetable: TWDM-PON selected in April 2012, NG-PON2 standard G.989.x study period:
(2013-2016)
[1] http://www.gazettabyte.com/home/2012/4/4/fsan-close-to-choosing-the-next-generation-of-pon.html, “FSAN close to choosing the next
generation of PON”
[2] Frank Effenberger, “XG-PON1 versus NG-PON2: Which One Will Win?”, ECOC’12, Tu.4.B.1
[3] Martin Carroll, “FTTx Access in North America, Europe, and Other Regions – Status and Perspectives”, Joint ITU/IEEE Workshop on
Ethernet - Emerging Applications and Technologies Geneva, 22 Sept. 2012
NG-PON: next generation PON, OFDM: orthogonal frequency-division multiplexing
X.Z. Qiu, OFC’13, OW3G.4 6
3
IEEE 10G-EPON based Access Networks
‰
‰
Symmetric 10G/10G & Asymmetric 10G/1G PONs
Coexistence with Deployed 1G-EPON
Source: Glen Kramer, ECOC’09 Symposium NG Optical Access
X.Z. Qiu, OFC’13, OW3G.4
7
TDM-PON Burst-Mode PMD Components
‰
Three BM Physical Medium Dependent (BM-PMD) Components [1]
¾ OLT 2R burst-mode receiver (BM-RX) – key component of PONs
¾ OLT burst-mode clock data recovery (BM-CDR)
¾ ONT burst-mode transmitter (BM-TX)
Verizon XG-PON
BM-TX
1270nm US
2R BM-RX & BM-CDR
Æ OLT 3R BM-RX
Source: Link Hoewing, “FiOS: An Ultra Broadband Case Study”, Verizon, October 15, 2010
[1]X.Z. Qiu et al., "Development of GPON upstream physical-media-dependent prototypes", JLT, Vol. 22, 2004, pp. 2498-2507
ONT: optical network terminal
X.Z. Qiu, OFC’13, OW3G.4 8
4
Outline
‰
Introduction
¾ Evolution of PONs (IEEE and ITU-T)
‰
OLT BM-RX Requirements
¾ High Optical Power Budget
¾ Short Burst Synchronization
¾ BM-RX Figure of Merit
‰
Overview of Fast Synchronization BM-RXs
¾ AC-Coupled & DC-Coupled BM-RX Configurations
¾ 3R Fast Synchronization BM-RX Architectures
¾ Dual-Rate BM-RXs
‰
Prototypes of IEEE/ITU-T BM-RXs/Sub-Systems
¾ IEEE 10G-EPON BM-RXs & System Performance
¾ 10G-PON Fast Synchronization BM-RXs Performance
‰
Summary
X.Z. Qiu, OFC’13, OW3G.4
9
US TDMA Scheme & OLT 3R BM-RX
‰
PON Transmission Scheme & US TDMA Bursty Nature
‰
OLT 3R BM-RX
¾ Downstream TDM: Continuous wave-mode (same amplitude and synchronous phase)
¾ Upstream TDMA: Burst-mode (differential amplitude & phase on burst by burst basis)
¾ Re-amplification & re-shaping: BM-TIA & BM-LA gain control & decision threshold extraction
¾ Retiming: BM-CDR data recovery/phase alignment
1
3 2 2 1
¾ BM-RX settling time/preamble required
ONT1
1
OLT at Central Office
(Synchronous
PON system with
OLT master clock)
3
OLT
3R
BM-RX
2
2
DS TDM
(broadcast)
1
3
2 2
1
2
ONT2
2
2
3
US TDMA
(Burst)
1
Passive
splitters
3
3
1 3
OLT US-PMD (3R BM-RX)
BMCDR
BMLA
APD
BM-TIA
2
3
1
US ONU bursts
aligned after ranging
3
ONT3
Unsynchronized opticalpower-varied bursts
2
ONTx extracts
its own DS
frames
ONU DS PMD (3R CW-RX)
3
2 2
1
APD
-TIA
TDMA: time division multiple access, CDR: clock & data recovery, TIA: transimpedance amplifier,
BM-LA: burst-mode limiting amplifier, CW: continuous wave-mode, MAC: medium access control X.Z. Qiu, OFC’13, OW3G.4
CW
-LA
CWCDR
3
10
5
IEEE 10G-EPON Upstream Burst
‰
Burst Composition [1][2]
¾ 10Gb/s Burst overhead (variable):
- Guard time: max. 512ns laser Ton + max. 512ns laser Toff
- Sync time: max. 800ns 2R RX settling + max. 400ns CDR lock + 64/66 bits burst delimiter
¾ FEC protected data payload (64B66B line coding) followed by EOB
Æ
Short burst OH required for
network throughput efficiency
IEEE 802.3av 10GE-PON burst signal format
EOB
400+400ns
FEC unprotected
End_Burst_
Delimiter
laserOnTime
(Ton)
Toff
E-PON burst signal format
Sync time
CDR
lock
2R BM-RX
settling
FEC protected data payload EOB
Burst Delimiter
(code group align)
Sync pattern
(Preamble)
End of
burst
Dead zone
laserOffTime
(Toff)
Idle
Data Payload
Overhead (OH)
[1] Naoto Yoshimoto, “Smooth migration Technology from GE-PON to NG-PON towards NGN era in Japan”, Computex Taipei Forum - NGN2009
[2] IEEE P802.3av 10GEPON Task Force, http://www.802.org/3/av/index.html
OH: overhead, EOB: end of burst, Ton: laser turn-on, Toff: laser turn-off
X.Z. Qiu, OFC’13, OW3G.4 11
FEC: forward error correction, EOB: end of burst, OH: overhead
ITU-T XG-PON Upstream PHY Layer Overhead
‰
G.987.2 Upstream Physical (PHY) Layer Burst Overhead (Tplo) [1]
¾ Guard time Tg: 64-128 bit time @2.5Gb/s (25.6-51.2ns) for burst overlap prevention
- laser turn-on time Ton+Tu (32bit time) and laser turn-off time Toff+Tu (32 bit time)
¾ Upstream physical synchronization block PSBu:
- preamble time Tp: 160-1856 bit time @2.5Gb/s (64-742ns) for 2R RX settling and CDR lock
- burst delimiter time Td: 32-64 bit time
¾ XG-PON OLT burst mode overhead time: objective 256 bit time (102ns), worst case
2048 bit time (819ns)
XG-PON1 burst overhead
Tplo
(physical layer overhead time)
Start time
Tg
G-PON burst overhead time
PSBu
FEC-protected data
Start of upstream
PHY frame
Tu
End of previous
burst, ONU i
[1] ITU-T Recommendation G.987.2 & G.987.3, 2010
Toff
Ton
Tu
Tg
(Guard
time)
2R BMRX
settling
Tp
(Preamble
time)
CDR
lock
Beginning of next burst ONU j
(scrambled PHY payload)
Td (Burst delimiter)
PHY: physical layer, OH: overhead, PSBu: upstream physical synchronization block, Tplo: physical layer overhead time,
Tg: guard time, Tu: timing uncertainty, Tp: preamble time, Td: delimiter time
X.Z. Qiu, OFC’13, OW3G.4
12
6
IEEE 10G-EPON 3R BM-RX Requirements
‰
IEEE 802.3av OLT 10GBASE-PR-D3 Spec
¾
¾
¾
¾
‰
Line rate: 10.3125 Gb/s, Line code: 64B/66B data encoding
Average RX power: max. -6dBm
RX sensitivity: -28 dBm @BER=1E-3 (Pre-FEC)
Sync time: max. 800ns for RX settling plus max. 400ns for CDR lock
Mandatory 1G/10G Dual-Rate TDMA Technique
¾
Support coexistence of 10G–EPON and 1G–EPON ONUs on the same outside plant
Main difference between ITU-T
and IEEE BM-RXs:
- ITU-T WDM wavelength plan:
2.5/10G XG-PON Up (12601280nm), 1.25G G-PON Up
(1290-1310/1330 nm), no
need for dual-rate operation
- wavelength overlap of IEEE
GE-PON Up (1260-1360nm)
with 10G-EPON Up (12601280nm) signals, requiring
1G/10G dual-rate mode at
BM-RX
Up: upstream
Source: Paolo Solina, ECOC’10, We.8.B.1
X.Z. Qiu, OFC’13, OW3G.4
13
ITU-T G-PON / XG-PON BM-RX Requirements
‰
ITU-T ODN Loss Spec [1]
¾ G-PON ODN loss:
(G.984.2, G.984.7)
¾ XG-PON ODN loss:
(G.987.2, with FEC)
‰
ODN
Class A
Class B
Class B+
Class C
Class C+
Loss (dB)
5-20
10-25
13-28
15-30
17-32 (FEC)
ODN
N1 Class
N2 Class
E1 Class
E2 Class
Loss (dB)
14-29
16-31
18-33 (OA)
20-35 (OA)
High ODN Loss Requires High Optical Power Budget [2]
¾ High TX optical output power and high RX Sensitivity
¾
¾
‰
1.25Gb/s G-PON OLT BM-Rx sensitivity: < -28 dBm (Class B+) @BER=1E-10
2.5Gb/s XG-PON OLT BM-Rx sensitivity: < -27.5 dBm (N1), -29.5 dBm (N2) @BER=1E-4
(Pre-FEC)
G. 987 OLT BM-RX Other Spec
¾
¾
¾
¾
¾
Line rate: 2.48832 Gb/s, line code: NRZ
RX overload: max. -7dBm (N1 class), -9 dBm (N2 class)
Wide dynamic range: min. 20.5 dB incl. max. 15dB 'ODN + max. 4dB 'TX_PO
Overhead/preamble time: min. 102/64ns, max. 819/742ns
Consecutive identical digits immunity (CID): 72 bits for scrambled NRZ
[1] ITU-T Recommendation G.987.1 & G.987.2, 2010,
[2] Fabrice BOURGART, ”ITU-T Standardization: from G-PON to 10G XG-PON”, FTTH 2010
N1: Nominal 1 class, N2: Nominal 2 class, OA: optical amplifier, 'ODN: differential loss of
ODN, CID: consecutive identical digit, 'TX_PO: differential launch power of TX
X.Z. Qiu, OFC’13, OW3G.4
14
7
BM-RX with Short Sync Time - Specific Issues
‰
Transients During Guard Time and Burst Preamble [1]
¾ Issue 1: DC drift due to loud/soft packets resulting in long tail effect (~1us)
Æ “RESET” signal within guard time to erase DC wander caused by preceding loud packet
¾ Issue 2: high RX sensitivity resulting in spurious output during guard period, and invalid
output during preamble / RX settling
Æ a blanking signal to ignore OLT false transition until valid data is received
‰
Penalty Caused by Inaccurate Decision Threshold Extraction [2]
GPON
OLT Rx
output
Invalid output
during preamble
1.224us
RESET
DC drift issue
Æ long tail after loud
packet
Guard time
(10ns/div)
High RX sensitivity
Æ spurious output
Preamble
Lesson Learned from G-PON Deployment [1]
[1] Rich Baca, “Technological challenges to G-PON operation”, OFC/NFOEC’08, NMD1
[2] P. Ossieur et al., JLT, Vol. 24, No. 3, 2006, pp.1543-1550.
X.Z. Qiu, OFC’13, OW3G.4
15
New Feature of OLT BM-RX
‰
Reliable GPON Operation Needs Two Feedback Signals [1]
¾ A time-critical RESET pulse from the MAC to the OLT transceiver (BM-RX)
¾ A time-critical blanking/CDR reset signal from the MAC to the BM-CDR
‰
New Feature Eliminates Two Time-Critical Signaling [2]
¾ On-chip auto-RESET generated inside BM-LA replaces external RESET pulse from MAC
¾ Self-detected burst activity signal generated inside BM-LA replaces a blanking signal from
MAC to BM-CDR
Blanking/CDR reset signal
Burst activity detected
OLT
transceiver
On-chip
auto-RESET
CDR
SerDes
DC-coupled
MAC
RESET signal
OLT Line Card
New feature allows no time-critical control signals / interfaces cross the
boundary between PHY & MAC layer for better system interoperability
[1] Rich Baca, “Technological challenges to G-PON operation”, OFC/NFOEC’08, NMD1
[2] X. Z. Qiu et al., "Evolution of burst mode receivers", ECOC’09, 7.5.1
BM-LA: burst-mode limiting amplifier, SerDes: serializer/deserializer,
PHY: physical layer, MAC: medium access control
X.Z. Qiu, OFC’13, OW3G.4
16
8
10G BM-RX Figure of Merit
‰
Generic 10G BM-RX Design Guidelines with Advanced Features
¾ ITU-T/IEEE 10G-PON optics synergy (high volume production and low cost)
¾ Symmetric 10G-PON BM-RX for G.989 TWDM business users (coexistence with deployed
outside fiber plan)
¾ Trade-off between cost effectiveness (die size, packaging) and good enough performance
¾ Compromise of short burst overhead for high network transmission efficiency and relaxed
OLT timing parameters for simpler implementation with low power consumption
¾ Elimination of time-critical control signaling form MAC to PHY for system interoperability
¾ Multi-rate operation for supporting network scalability and upgradeability
¾ Robust design for high yield manufacture
‰
Challenging 10G BM-RX Performance Spec
¾ High Rx sensitivity: < [email protected] BER=10-3 (G-PON Class B+ and XG-PON N1 Class
compliant, optical amplifiers used for higher power budget than N1 Class)
¾ Wide dynamic range: > 22dB (IEEE 10GBASE-PR-D3)
¾ Short burst overhead: 100-400ns (fast sync time of 50-250ns)
TWDM: time/wavelength division multiplexing
X.Z. Qiu, OFC’13, OW3G.4
17
Outline
‰
Introduction
‰
OLT BM-RX Requirements
‰
Overview of Fast Synchronization BM-RXs
¾ AC-Coupled & DC-coupled BM-RX Configurations
¾ 3R Fast Synchronization BM-RX Architectures
- AC-coupled 2R BM-RXs
- DC-coupled 2R BM-RXs
- BM-CDRs
¾ Dual-Rate BM-RXs
‰
Prototypes of IEEE/ITU-T BM-RXs/Sub-Systems
¾ IEEE 10G-EPON BM-RXs & System Performance
¾ 10G-PON Fast Synchronization BM-RXs Performance
‰
Summary
X.Z. Qiu, OFC’13, OW3G.4
18
9
OLT AC-Coupled BM-RX Configuration
‰
3R BM-RX Key Techniques [1]
¾ BM-TIA: converting current from photodiode into a differential output voltage with variable gain (handle
> 22dB optical input power in tens of ns scale) and DC offset control
¾ BM-LA: amplification, offset removal / decision threshold extraction (time constant critical, optimal low
frequency cut-off for low baseline DC droop & low pattern dependent jitter)
¾ BM-CDR: timing and data recovery (fast clock phase extraction)
“no light”
AC or DC
Coupling
Coupling
capacitors
“1”
PD
“0”
Optical input
BMTIA
BMCDR
BM-LA
Waveform
distorted
BM-TIA:
gain control
Decision
threshold
Phase
mismatched
BM-LA: offset
cancellation &
constant amplitude
Optical input
BM-CDR: clock
extraction &
data recovery
t
Loud burst followed by soft burst
ÆDC component decays with time t
[1] Masafumi Nogawa, NTT Technical Review, Mar. 2011
[2] Haim Ben-Amram, www.ieee802.org/3/av/public/2008.../3av_0801_benamram_2.pdf
PD: photodiode, G1/G2: gain 1 / gain 2
X.Z. Qiu, OFC’13, OW3G.4
19
OLT DC-Coupled BM-RX Configuration
‰
‰
DC-Coupled BM-RX Preferred over AC-Coupling for Fast Sync.
Dedicated BM-TIA with Fast AGC
¾ Step AGC: very short response time in nanosecond, but RESET needed
¾ Continuous AGC: gain adjusting continuously without RESET, slow response > 250ns if 65bits CID
‰
Dedicated BM-LA with Fast Offset Cancellation
¾ Peak/bottom detection with RESET
¾ Feed-forward average detection without RESET
¾ Feedback offset cancelation with RESET or without RESET
APD
BM-TIA
Loud burst
level ”1”
Soft burst at sensitivity level
RESET
BM-LA
BM-CDR
RESET
signal(s)
Extinction
ratio
Level ”0”
DC-coupled 3R BM-RX
Guard
Preamble
Long CID
Loud
burst
Soft burst
Vth1
Decision
threshold
[1] Yusuke Ohtomo et al, “High-speed circuit technology for 10-Gb/s optical burst-mode transmission” OFC’10, OWX1
AGC: automatic gain control
X.Z. Qiu, OFC’13, OW3G.4
Vth2
20
10
10G AC-Coupled BM-RX Time Constant Issue
‰
Deterioration in Response Time [1]
¾ Time constant of average detector - small time
constant required for short preamble
¾ Max. 65bits CID – DC droop during long CID (<5%) large time constant required
¾ Tradeoff between short preamble and baseline DC
droop Æ RX preamble: 250~360ns (10.3Gb/s,
64b66b) [2] ÅÆ IEEE BM-RX settling time: 800ns
Average
detector
Transient response after AC-coupling
Preamble
Waveform distortion by duty fluctuation
Output of TIA & Vth
(Vth)
B(Vth) - small AD time constant
t
Preamble
[1] Kazutaka Hara et al., JLT ,Vol 28, No 19, 2010 , pp. 2775-2782
[2] Rujian Lin, www.ieee802.org/3/av/public/2008_03/3av_0803_lin_1.pdf
CID: consecutive identical digit, Vth: threshold voltage, AD: average detector
B(Vth) - large time constant
X.Z. Qiu, OFC’13, OW3G.4
21
10G AC-Coupled BM-RX (Transient-Cancellation)
‰
NTT Baseline Wander Common Mode Rejection (BLW-CMR) &
Inverted Distortion Technique [1]
¾
¾
¾
¾
AD1 - small RC time constant – VA1 - baseline wander (BLW)
Transient response cancellation using BLW-CMR technique [2]
Inverted distortion technique – less duty-cycle distortion
Small time constant
Shorter preamble and high tolerance to CIDs
for short preamble
[1] Kazutaka Hara et al., JLT ,Vol 28, No 19, 2010 , pp. 2775-2782
[2] Hirotaka Nakamura et al., JLT Vol. 27, NO. 3, 2009, pp. 336-342
AD: average detector, BLW-CMR: baseline wander common mode rejection
DC droop during long CID “0”
large time constant required
X.Z. Qiu, OFC’13, OW3G.4
22
11
BM-TIA with 2-Step AGC & Coarse/Fine AOC
‰
NTT PIN-TIA with 2-Step AGC and AOC
[1]
¾ Fast high / low 2-step transimpedance Rf switching (10 ns)
¾ Fast coarse / fine AOC, allowing AC-coupled with a simple BM-LA
¾ Decision threshold level = common mode voltage – duty cycle distortion minimal
RESET
[1] M. Nakamura et al., “A 10G burst-mode PIN-TIA with 10-nsec response for PON systems”, LEOS’07, MH2, pp. 67-68,
X.Z. Qiu, OFC’13, OW3G.4
AOC: automatic offset control
23
BM-TIA with 3-Step AGC & Coarse AOC
‰
UGENT APD-TIA with 3-Step AGC and Coarse Offset Control [1]
¾
¾
¾
¾
Fast High / Medium / Low 3-step transimpedance Rf switching (<10 ns)
Fast coarse offset control (fine offset cancellation/decision threshold extraction done at BM-LA)
RESET detection via common-mode signaling
DC-coupled with dedicated BM-LA Æ Short preamble
VTIA
Reset
Gain
switching/lock
Vdummy
RF
GS1
Lock
Common-mode
signaling
VCM
GS2
Output buffer
APD
DC-coupled between
BM-TIA & BM-LA
Vout+
Input
TIA core
Vout-
S2D
GS1 (High/Medium gain)
BM-LA
RLoad
GS2 (Medium/Low gain)
RF
VCC
BM-TIA
output
Dynamic range
3
TIA dummy
Idummy
Low gain
2
1
Medium gain
GND
GS1 (High/Medium gain)
High gain
BM-TIA input
BM-TIA
[1] X. Yin et al., "DC-coupled burst-mode receiver with high sensitivity, wide dynamic range and short settling time for
symmetric 10G-GPONs”, ECOC’11, Mo.1.C.5
GS1/GS2: gain control signal, S2D: single to differential converter, VCM: common-mode voltage
X.Z. Qiu, OFC’13, OW3G.4
24
12
Step / Continuous AGC / ATC BM-RXs
‰
Mitsubishi BM-RX with Continuous AGC and Continuous ATC [1]
¾ Continuous gain adaptation within burst without RESET
¾ Continuous threshold varying
based on detected average power
¾ Tracking power fluctuation in burst
¾ Longer response time (a few hundred ns)
for high tolerance to CIDs
BM-RX with continuous AGC/ATC
BM-RX with
step AGC/peak detect ATC
[1] M. Noda et al., “Technology progress of high-speed burst-mode 3R receiver for PON applications”, OFC’12, OTh4G.6
[2] Masaki Noda et al., ECOC’10, Mo2.B.2
ATC: automatic threshold control,
X.Z. Qiu, OFC’13, OW3G.4
25
DC-Coupled BM-LA (Feedforward Type)
‰
UGENT Feed-forward Peak/Bottom Detection with RESET [1]
¾ Ž
4 successive amplifier stages with 4 peak/bottom detectors (TH 1-TH4) - critical timing
¾ Relative decision threshold error (to signal amplitude) decreased along BM-LA stages
¾ 17.8 ns for complete threshold extraction – 2R RX settling time: 25 ns with auto-RESET
BM-TIA
PIN
DC-coupled BM-LA
Peak/bottom threshold extraction
+
Peak
detector
High/low
gain
Gain
switching
& locking
TH1
Coarse
threshold
extraction
TH1
TH4
A1
A4
+
Burst
detect
Reset
logic
Burst detected
RESET
A3 output
A1 output
+
TIA
RESET
A4 output
%07,$RXWSXW
3UHDPEOH
VHWJDLQWKUHVKROGH[WUDFW
A2 output
TH2
TH3
TH4
[1] P. Ossieur et al., "A 10 Gb/s burst-mode receiver with automatic reset generation
and burst detection for extended reach PONs", OFC’09, OWH3
[2] X.Z. Qiu et al., “Evolution of Burst Mode Receivers ”, ECOC’09, 7.5.1
%0/$RXWSXW
5(6(7
JHQHUDWHG
%XUVWGHWHFWHG
X.Z. Qiu, OFC’13, OW3G.4
26
10 ns/div
13
DC-Coupled BM-LA (Feedback Type)
‰
NTT Feedback Offset Cancelation without RESET [1]
¾ Ž
Two-stage amplifiers with active feedback
¾ Automatic voltage offset cancellation (AOC) in 200 ns without RESET
Two-stage feedback AOC
RX settling time (1-stage vs 2-stage feedback AOC)
Conventional 1-stage feedback AOC
[1] M. Nogawa et al., “A 10-Gb/s burst-mode limiting amplifier using a two-stage active feedback
circuit”, Symposium on VLSI Circuits 2009, 2-5, pp. 18-19.
X.Z. Qiu, OFC’13, OW3G.4
27
BM-LA (Switched Bandwidth Feedback Type)
‰
UGENT Feedback Type BM-RX with Switched Loop Bandwidth [1]
¾ Feedback-type BM-RX with switchable AOC loop BW without external RESET
¾ Programmable two time-constants (fast response during preamble, large time
constant during payload)
¾ Additional features: on-chip auto-RESET generation, 2.5G/5G/10Gb/s operation
Wide dynamic range
10G APD-basedDC-coupled
BM-RX ICsBM-LA
TIA output
VAPD
High
Low gain
APD
External reset
Auto-reset
generation
Offset
Off
ffset integrator with
switchable BW
Medium gain
TIA input
TIAc
Medium
/Low
GS2 gain
GS1
TIAd
GS1
A1
S2D
High/
Medium
gain
Gain switch
& lock
GS1
Output
buffer
Reset
Lock
A2
A3
A4
Data
Buffer output
Activity
detection
Reset
detection
GS2
10G BM-LA
10G BM APD-TIA
BM-TIA
[1] X. Yin et al.,"Experiments on 10Gb/s fast settling high sensitivity burst-mode receiver
with on-chip auto-reset for 10G-GPONs", OFC’12, NTu1J.4
BW: bandwidth
X.Z. Qiu, OFC’13, OW3G.4
28
14
AC-Coupled versus DC-Coupled BM-RXs
‰
AC-Coupled “GE-PON like” BM-RXs
- Higher sensitivity (DC offset removal via AC coupling)
- Easier design for low power consumption, flexible use of different components w/o RESET
/ Longer RX settling time, not efficient for short packets (baseline DC droop Æ pattern
dependent jitter)
/ Not directly scaled for different data rates (AC-coupling critical time constants and CID
tolerance contradicting)
/ Lower data throughput (line coding 8b10b for GE-PON, 64b66b for 10GE-PON)
‰
DC-Coupled “G-PON like” BM-RXs
- Shorter burst overhead (less time constant constraint)
- Simultaneous multi-rate operation possible (no line coding, less time constant and CID
tolerance contradicting)
/ Sensitivity penalty (DC offset & decision threshold error due to very short Rx settling time)
/ Not very friendly for component replacement from different vendors (dedicated BM-LA)
/ Difficult to design (RESET signal required)
‰
DC-Coupled method Preferable for Fast Burst Synchronization
NRZ: non-return-to-zero, CID: consecutive identical digit
X.Z. Qiu, OFC’13, OW3G.4
29
Pros & Cons of BM-RX Design Types
‰
UGENT 10Gb/s APD BM-RX combines both advantages of AC- and
DC-coupled approaches
AC-coupled BM-RX
DC-coupled BM-RX
UGENT DC-coupled New Approach
- Higher sensitivity
/ Sensitivity penalty (DC offset - Higher sensitivity (less time constant
(DC offset removal via & decision threshold error using tradeoff for settling time as payload
AC coupling)
FF peak/bottom detection)
tracking with low AOC BW)
/ Slow settling (AC-
- Faster RX settling (less time - Shorter RX settling time (Feedback
coupling time constant constant constraint)
type with switchable AOC loop BW for
constraint)
faster threshold extraction)
/ Line coding (limit
- No line coding (scrambled
number of CIDs)
NRZ, large CID tolerance)
- Simultaneous multiple rate XGPON
operation (2.5G/5G/10G, NRZ)
- Easier design for
/ Not friendly for network
low power
consumption, friendly
use of components
interoperability (dedicated BMLA with external RESET signal
required)
- Relative friendly for network
interoperability (on-chip auto-RESET, no
timing-critical signaling cross PHY-MAC
layer)
/ Need dedicated BM-LA
FF: feedforward, AOC: automatic offset control, BW: banwidth, CID: consecutive identical digit,
NRZ: non-return-to-zero, PHY: physical layer, MAC: medium access control
X.Z. Qiu, OFC’13, OW3G.4
30
15
BM-CDR Configurations
‰
Three Main Types of BM-CDR Techniques [1,2]
¾ Fast-lock PLL based CDR: acquisition time limit +/- 130 ns with 0.1 UI of peak-to-peak
output jitter, sub-100 ns locking time demonstrated [3]
¾ Gated-VCO based CDR: very fast response in 1 bit, but larger output clock jitter & narrow
tolerance to pulse-width distortion [4]
¾ Over-sampling based CDR: fast response in a few ns, low jitter, large tolerance to pulsewidth distortion, but high power consumption and large chip area [5]
1) Fast-lock PLL based BM-CDR
2) Gated-VCO based BM-CDR
3) Over-sampling based BM-CDR
[1] M. Noda et al., “Technology progress of high-speed burst-mode 3R receiver for PON applications”, OFC 2012, OTh4G.6
[2] Yusuke Ohtomo et al, OFC’10, OWX1, [3] Y. Chang, ECOC’09, P6.29, [4] J. Terada et al., ISSCC’09, 5.8, pp.104-105,
[5] C, Mélange et al., JLT, Vol. 27, Nr. 17, 2009, pp. 3837-3844.
PLL: phase-locked loop, VCO: voltage-controlled oscillator, DEC: decision circuit
X.Z. Qiu, OFC’13, OW3G.4 31
GVCO Based BM-CDRs
‰
NTT GVCO CDRs [1-3]
1) 2 GVCOs
(PLL with 20MHz
frequency difference)
2) Single GVCO
(FLL with 2MHz
frequency difference)
3) Cascaded GVCOs
(Sync time:14 bits, better jitter performance & tolerance to long CIDs
by jitter-reduction and PWD-compensation circuits)
[1] J. Terada et al., “Jitter-Reduction and Pulse-Width-Distortion Compensation Circuits for a 10Gb/s Burst-Mode CDR Circuit ”
ISSCC’09, 5.8, pp.104-105, [2] M. Nogawa et al., ISSCC’05, pp. 228-229, [3] J. Terada et al., ISSCC’08, pp. 226-227.
X.Z. Qiu, OFC’13, OW3G.4 32
GVCO: gated VCO, FLL: frequency-locked loop
16
Over-Sampling Based BM-CDRs
‰
Mitsubishi Over-Sampling CDRs [1-3]
VCO
8-phase
clock
1) GE-PON
bit sync IC
2) 10GE-PON quadrate sampling
• 4-phase PLL: 4x10.3G 90-degree phaseshifted CLK#0-CLK #3 synchronized with
system clock
• Quad-rate sampler: D-FF array samples
data at >40 GSa/s equivalent rate (D0-D3)
• Data edge counter: number of rising/falling
edges from D0-D3 at 64-bit intervals
• Data phase decider: data-phase decisionalgorithm for optimum recovery phase
[1] Hitoyuki Tagami et al., JSSC, Vol. 41, NO. 11, 2006, pp. 2555-2565, [2] N. Suzuki et al., ECOC’08, P.6.3,
X.Z. Qiu, OFC’13, OW3G.4
[3] N. Suzuki et al., EL, Vol. 45 No. 24, 2009, pp. 1261-1263
33
Dual-Rate G-PON 10x Over-Sampling BM-CDR
‰
UGENT 622/1244Mb/s GPON BM-CDR IC in 0.13um CMOS [1]
10x replica delay lines (800/1600ps)
Freq / 2
Charge
Pump
Delay element
control
Phase
Detector
Reference DLL
Reference
DLL
(delay locked
loop)
10x data
delay lines
Data
Data
D0
1.24G/622M
D1
D8
Sampled
data in
100
D
Q
D9
10-tap (80/160ps)
Sampler
Reference clock (sync
with OLT master clock)
• Two matched delay lines (10x master data delay lines & 10x
replica delay lines), both controlled by slave DLL
• Reference delay locked loop (DLL) sets replica delay lines to
data bit period (800ps @1.25Gb/s or 1600ps @622Mb/s)
• Data sampler: 10x oversampling – 80ps per tap, 10x taps
• Middle bit detection: search for middle of “010” pattern
• Optimum tap selected via majority voting algorithm (averaging)
• Low power digital processing at 1/8 data rate (155/77MHz)
• Payload tracking mode: +/-1 extra bit shift in worst case
• Sync time: 20bits (16ns) incl. phase averaging algorithm
Data sampler
Q<0:9>
10
0
To tap
selection
D
10
Q
D
Q
D
Q
Data
out
8
Clock
1.24G/622M
Middle
Middle
of bit
bit
detection
detector
Low speed clock
155M/77M
Dual-rate (622Mb/s or 1244Mb/s)
bit synchronization (analog part –
reference DLL & data sampler)
Optimum phase
selection algorithm
Tap
selector
Tap Selection
Data recovery with fast optimum decision phase
(digital part – middle bit detect & tap select algorithm)
[1] P. Ossieur et al., “A dual-rate burst-mode bit synchronization and data recovery circuit
with fast optimum decision phase calculation", AEU, Vol. 63, Nr. 11, 2008, pp. 931-938.
X.Z. Qiu, OFC’13, OW3G.4
34
17
10Gb/s 4x Over-Sampling BM-CDR
‰
UGENT 10G Over-Sampling BM-CDR [1-3]
¾
¾
¾
¾
¾
¾
¾
¾
Reference DLL
4x oversampling (40 Gbit/s equivalent sample rate)
Fast locking (1.6 ns)
4:64 DeSer: timing jitter averaging (group of 16 data bits)
Low power phase picking algorithm with 622MHz clock
Output synchronous to system clock
Robust against pulse width distortion (100ps +/- 20%, 72 CIDs)
1.5 W @ 2.5V power consumption with built-in phase selection
Die size: 2.75 x 2.25 mm2
Replica delay lines
Data delay lines
Data sampler
[1] C. Mélange et al., EL Vol. 45, 2009, pp.694-695,
[2] C, Mélange et al., JLT, Vol. 27, Nr. 17, 2009, pp. 3837-3844
[3] C, Mélange et al., OFC’10, OWX2
X.Z. Qiu, OFC’13, OW3G.4
35
10GE-PON / 1GE-PON Coexistence
‰
Backward Compatibility with ODNs & Deployed GE-PON Systems
Wavelength
overlap
OLT data paths operating in dual-rate
mode (1G/1 G, 10G/1G, 10G/10G with
a single optical input)
MAC: medium access control
RS: reconciliation sublayer
XGMII: 10Gb/s media independent interface
PCS: physical coding sublayer
PMA: physical media attachment
PMD: physical medium dependent
[1] Keiji Tanaka et al, “IEEE 802.3av 10G-EPON
Standardization and Its Research and Development
Status”, JLT Vol. 28, No. 4, 2010, pp. 651-661
Dual-rate PMD configuration: 1) optical domain split, 2) electrical
domain split (preferred)
X.Z. Qiu, OFC’13, OW3G.4
36
18
Dual-Rate BM-RX with Bit-Rate Discrimination
‰ NTT IEEE 10G/1G Dual-Rate 2R BM-RX with Bit-Rate Discrimination Circuit [1]
BDC: Bit-rate
discrimination
circuit
GC: gate circuit
2R RX settling time: <250 ns incl. BDC
[1] Hara, Kazutaka et al, “1.25/10.3-Gbit/s dual-rate burst-mode receiver with automatic
bit-rate discrimination circuit for coexisting PON systems” COIN’10, pp.1-3
X.Z. Qiu, OFC’13, OW3G.4
37
Dual-Rate BM-RX with External Rate Select Signal
‰ Mitsubishi IEEE 10G/1G Dual-Rate 3R BM-RX with Rate Select Signal [1]
Burst overhead
-
Ton/Toff: 48ns
RX_settling: 800ns
CDR_settling: 37ns
BD: 6.4ns
EOB: 6.4ns
Grant cycle: 1ms
[1] M. Noda et al., OFC 2012, OTh4G.6
X.Z. Qiu, OFC’13, OW3G.4
38
19
Multi-Rate BM-RX with On-Chip Auto-RESET
‰ UGENT XG-PON 10G/5G/2.5G Multi-Rate 2R BM-RX with ON-Chip Auto-RESET [1]
¾ 2R RX settling time: 75 ns for simultaneous 10G/5G/2.5G operation
¾ Tracking mode with slow time constant - large tolerance to > 72 CIDs at 10G/5G/2.5Gb/s
VAPD
VTIA
VDUMMY
BM-TIA IC
APD
R2
BM-LA IC
Reset
Gain
Switching
Lock
CM
Signaling
Sig
gnaling
g
M1
VOOS+
S+
VOOS-S-
VDD
R1
GS1 GS2
RF
V11++
TIA core
GS1
TIA dummy
VCM
Buffer
V22++
V22--
Auto Reset
Generation
V33++
V33--
-
Vout+
A1
Buffer
Buff
f er
Vtia-
GS2
RF
Dummy
current
S2D
V11--
Activityy
-
Vtia+
Iin
Reset
Off
Offset
ffset Integrator with
Switchable Loop BW
GS1
R4
R4
R3
R3
RE
GS2
Activity
Detection
RE
Auto reset
generation
Decision
threshold
extracted
GS1
GS2
Gain steps
1
1
High-gain
Small Iin,pp
0
0
1
1
0
0
Medium-gain
Low-gain
-
Large Iin,pp
[1] X. Yin et al., ISSCC’12, pp. 416-417
7
[2] J. Put et al., EL, Vol. 47, 2011, pp.
970-972
Vout-
Pre-Amp with
CM signaling
GS2
5x faster
Activity
detection
Fast threshold
Slow threshold
extraction
tracking
Incoming
burst
Guard time
Reset
Preamble
Payload
Activity
Common-mode VCM
X.Z. Qiu, OFC’13, OW3G.4
39
Outline
‰
Introduction
‰
OLT BM-RX Requirements
‰
Overview of Fast Synchronization BM-RXs
¾ AC-Coupled & DC-Coupled BM-RX Configurations
¾ 3R Fast Synchronization BM-RX Architectures
¾ Dual-Rate BM-RXs
‰
Prototypes of IEEE/ITU-T BM-RXs/Sub-Systems
¾ IEEE 10G-EPON BM-RXs & System Performance
¾ 10G-PON Fast Synchronization BM-RXs Performance
‰
Summary
X.Z. Qiu, OFC’13, OW3G.4
40
20
BM-RX Specifications in PON Systems
ATM-PON
GE-PON
G-PON
10G-EPON
10G-EPON
XG-PON
NG-PON2
Standard
ITU-T
G.983
(Class C)
IEEE
802.3ah
(PX20-D)
ITU-T
G.984
(Class C)
IEEE
802.3av
(PR-D3)
IEEE
802.3av
(PRX-D3)
ITU-T
G.987
(N2)
ITU-T
G.989.2
(FFS)
US data rate
155 Mb/s
1.25 Gb/s
1.25 Gb/s
10.3 Gb/s
1.25 Gb/s
2.5 Gb/s
10 Gb/s
Response time
< 24 bits
< 400 ns
< 76 bits
< 800 ns
< 400 ns
< 224 bits
< 200 ns
Sensitivity
/ Overload
-33 dBm
/ -11
-27 dBm
/ -6 dBm
-29 dBm
/ -8 dBm
-28 dBm
/ -6 dBm
-29.78/ 9.38dBm
-29.5 dBm
/ -9 dBm
-28 dBm
/ -6 dBm
Dynamic range
22 dB
21 dB
21 dB
22 dB
20.4 dB
20.5 dB
22 dB
BER condition
1E-10
1E-12
1E-10
1E-3 (FEC)
1E-12
1E-4 (FEC)
1E-3 (FEC)
* Response time: guard time + preamble
ITU-T G.989.2 “40-Gigabit-capable passive
optical networks (NG-PON2): Physical media
dependent (PMD) layer specification” study
period 2013-2016
6.4dB FEC gain after 20km with
Reed–Solomon code (255, 223)
[1] M. Nakamura et al., BCTM’10, .pp.21-28
[2] Keiji Tanaka et al, JLT Vol. 28, No. 4, 2010, pp. 651-661
FSS: for further study
X.Z. Qiu, OFC’13, OW3G.4
41
NTT IEEE 3R BM-RX Performance
1.7 mm x 1.7 mm
210 mW
B-CDR
1.05mm x 0.9 mm
180 mW
RESET
-29.5dBm 3R BM-RX
sensitivity
B-TIA
B-LA
[1] Masafumi Nogawa et al, NTT Technical Review, Vol. 9 No. 3 Mar. 2011, pp. 1-7
X.Z. Qiu, OFC’13, OW3G.4
42
21
Dual-Rate Triplexer for 10G-EPON OLT XFP TRX
‰ NTT Small and Low-Cost Dual-Rate Optical Triplexer [1]
¾ Full-duplex operation (10.3Gb/s and 1.25Gb/s TX ON).
10.3-Gb/s and 1.25-Gb/s
TX eye diagrams
[1] A. Kanda et al, OECC’12, 3D2-2, pp. 77-78
X.Z. Qiu, OFC’13, OW3G.4
43
Mitsubishi Dual-Rate 3R BM-RX Performance
480 mW
280 mW
3W
RX_settling:
800ns
Experimental
test-up
[1] Junichi Nakagawa et al., PTL, Vol. 22, No. 24, Dec. 2010, pp. 1841-1843
X.Z. Qiu, OFC’13, OW3G.4
44
22
Latest Progress BM Transceivers (Mitsubishi)
Demo set-up
RX_settling:
240ns
OLT XFP / ONU
SFP+ TRXs
US optical burst-packets
& US / DS loss budgets
[1] Junichi Nakagawa et al., PTL,
Vol. 22, No. 24, Dec. 2010, pp.
1841-1843
X.Z. Qiu, OFC’13, OW3G.4
45
10G-GPON Multi-Rate 2R BM-RX
‰ UGENT 10G/5G/2.5G Fast Settling 2R BM-RX without External RESET
¾
¾
¾
¾
Common-mode signaling Æ standard package (5-pin TO-CAN) to reduce cost
Feedback-type limiting amplifier with switchable time-constant Æ multi-rate operation (fast sync: ~75 ns)
Auto-Reset generation (miss Resets in case FEC used) - tolerant to high pre-FEC BER (1E-3) scenario
Robust Auto-Reset generation: count more bits (n) and allow errors (f) with programmable n and f.
External reset
VAPD
APD
Biasing
Test circuit
TIA core/
dummy
Output
buffer
Gain
switching
S2D
Common-mode
signaling
TIAc
High/
Medium
gain
Lock
Auto-reset
generation
A3
Output
buffer
Reset
Gain switch
& lock
GS1
A2
A1
Medium
/Low
GS2 gain
TIAd
BM-TIA
S2D
GS1
GS1
1.28mm x 1.02mm
200 mW
Off
Offset
ffset integrator with
switchable
switchab
a le BW
A4
Reset
detection
BM-LA
GS2
Auto-RESET generation under Pre-FEC BER case [1-2]
V
Offset
integrator
SIGNAL
Guard time ( = noise)
with
Pre-amp
decision level: 1
...
...
...
Test
circuit
1.21mm x 1.26mm
430 mW
EoB detected
Æ reset generated
...
(k-n)
Output
buffer
t
EoB detection threshold (n)
...
Limiting stages
Biasing
...
counter
restarts
EoB counter
COUNTER
Reset
generation
Burst 2
0
...
...
counter
restarts
...
Activity
detection
erroneously received 1-bit
Burst 1
counter
restarts
Missing end-of-burst (EOB)
Reset probability vs guard time
Data
outp
t ut
output
Buffer
Buff
ffer
Activity
detection
...
k
t (1/bitrate)
[1] J. Put et al, Optics Express, Vol. 19, Nr. 26, 2011, pp. B604-B610, [2] X. Yin et al., ISSCC’12, pp. 416-417
X.Z. Qiu, OFC’13, OW3G.4
[3] X. Yin et al., JOCN, Vol. 4, Nr. 11, Oct. 2012, pp. B68-B76
46
23
10G-GPON 3R BM-RX Performance
‰ Combined High Performance 10Gb/s BM-RX Experiments [1-2]
-31.9dBm RX sensitivity (BM-static, BER=1E-3), error free at -5dBm
-2
-31.3dBm Rx sensitivity (loud/soft ratio = 26.3dB, BER=1E-3)
75 ns 2R RX settling time, 25 ns guard time, with on-chip RESET
-3
80ns fast-lock PLL based BM-CDR (Vitesse sample)
BM-TX1
Data 1 BM-EAM
EML
driver
.
.
.
TX2
TX#1
TX1
TX2
10Gb/s upstream bursts
Att1
BM-TX2
ONUs
ONU
BM-laser
driver DFB
Data 2
TX1
1310nm
upstream
Att2
APD
BM-TIA
t
10G-GPON OLT
BM-LA
BM-RX
BM-CDR
Data output
Log10(BER)
¾
¾
¾
¾
-4
-5
≥ 26.3 dB dynamic range
-31.9
dBm
-6
-26.8
dBm
-7
-8
-9
-10
-11
-12
-40
BM-B2B
BM-2TX
-31.3 dBm
-35
-30
APD M=9,
10G NRZ PRBS 231-1
plus 72-bit CID,
guard time 25.6ns,
-26.2 settling time 76.8ns
dBm
-25
-20
-15
-10
≥ -5
dBm
-5
0
Input optical power (dBm)
Measured 2R BM-RX Performance
Att1
BMTX#1
25km
fiber
EAM
driver
BM-TIA IC
BM-LA IC
EML
BM-TX#2
2x2
splitter
Att2
DFB TOSA
BM-CDR
APD-TIA
test board
BM-LA test
board
BM-RX
Measured 3R BM-RX Performance
[1] X. Yin et al., OFC’12, NTu1J.4
X.Z. Qiu, OFC’13, OW3G.4
47
10G-GPON 2R BM-RX for Multi-Rate Operation
‰ 10G/5G/2.5Gb/s BM-RX Experiments with On-Chip Auto-RESET
[1-2]
¾
¾
¾
¾
¾
100 ns 2R RX settling time for 10G/5G/2.5G
50 ns guard time (longer guard time for Auto-Reset @ BER=1E-3)
Data payload: NRZ PRBS31 plus 72-bit CIDs
-31dBm @ 10Gb/s Rx sensitivity (BER=1E-3, loud/soft ratio>26dB)
-28.9dBm @ 5G & 2.5Gb/s (BER=1E-10) (** input power < -31 dBm is too weak for on-chip Auto-Reset
circuit in current design)
¾ Superior CID tolerance up to 512-bit CIDs
Measured BER &
total jitter
[1] X. Yin et al., OFC’12, NTu1J.4
X.Z. Qiu, OFC’13, OW3G.4
48
24
Future Work
‰
EU FP7-Funded ICT DISCUS IP Project [1]
¾ Project start/end date: 01/11/2012 - 31/10/2015
¾ 12 partners (TCD, ALUD, NSN, TID, TI, ASTON, IMEC, III-V, Tyndall+UCC, Polatis, ATE,
KTH)
‰
LR-PON Physical Hardware to be Implemented within DISCUS
¾ 10Gb/s burst-mode electronic dispersion compensation [2] supported by a linear BM-RX [3-4]
(Tyndall)
¾ 40Gb/s downstream PMD components (IMEC, III-V)
¾ 10/40Gb/s power-efficient bit-interleaved CDR / decimator (IMEC) [5]
‰
System Integration and Proof Concept Test Bed
[1] FP7 ICT DISCUS IP Project http://www.discus-fp7.eu/,
[2] P. Ossieur et al., PTL, Vol., Vol. 20, Nr. 20, 2008, pp. 1706-170
706-170
[3] P. Ossieur et al., OPEX, 2011, pp. B604–B610,
[4] X. Yin et al., OPEX, 2012, B462-B469,
[5] C. Van Praet et al., OPEX, 2012, B7-B14.
X.Z. Qiu, OFC’13, OW3G.4
49
Summary
‰
Review of OLT BM-RX Requirements / Design Guidelines
¾ Optical power budget and network coexistance with deployed PONs
¾ Relaxed timing parameters but still shorter burst overhead for robust design and high yield manufacture
¾ Trade-off between cost effectiveness (die size, packaging, power consumption) and good enough
performance
¾ No external time-critical control signals cross PHY & MAC layer for better system interoperability
‰
Overview of IEEE & ITU-T Fast Synchronization BM-RX Development
¾ AC-coupled & DC-coupled BM-RX Configurations
¾ Various 2R / 3R BM-RX Architectures
¾ Dual-rate and multi-rate operation
‰
(Sub)-System Integration and Demonstration
¾ Technology for IEEE 10G-EPON BM-Rx is ready for production, need low cost-engineering work and
volume (10G-PON optics synergy with ITU-T NG-PON2 TDMA-BM-RXs)
¾ 10G/5G/2.5Gb/s upstream burst-mode transmission demonstrated with excellent performance (elimination
of external reset, fast synchronization with fully programmable short overhead, and low power
consumption).
BM-RX design challenge: the combined requirements of high RX sensitivity, wide
dynamic range, short burst overhead, multi-rate operation, without external signaling
from MAC - Successfully demonstrated!
X.Z. Qiu, OFC’13, OW3G.4
50
25
Acknowledgements
‰
EU-Funded Projects: PIEMAN, MARISE, EUROFOS
‰
INTEC_design Colleagues of INTEC Dept., Ghent University / IMEC
‰
Bell Labs Alcatel-Lucent (Stuttgart, Murray Hill) for Bilateral Funding
‰
III-V Lab (Marcoussis) Collaboration within MARISE
‰
STMicroelectronics for Technical Support and Chip Fabrication
‰
Sumitomo Electric Devices Innovations, Inc for 10Gb/s APD-TIA
Assembly
‰
Vitesse Semiconductor for Providing 10Gb/s BM-CDR and DFB TOSA
X.Z. Qiu, OFC’13, OW3G.4
51
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Optical Receiver Using Transient-Phenomena Cancellation Techniques for 10 Gbit/s-Class High-Speed TDM-PON Systems”, JLT ,Vol 28,
No 19, 2010 , pp. 2775-2782
[Slide21-2]
Rujian Lin, “10GEPON Burst Timing in Coexistence Situation”, www.ieee802.org/3/av/public/2008_03/3av_0803_lin_1.pdf
[Slide22-2]
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Yoshimoto, Kazutoshi Kato, “A 10G burst-mode PIN-TIA with 10-nsec response for PON systems”, LEOS’07, MH2, pp. 67-68
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X. Yin, X.Z. Qiu, J. Gillis, J. Put, J. Verbrugghe, J. Bauwelinck, J. Vandewege, F. Blache, D. Lanteri, M. Achouche, H. Krimmel, D. van
Veen and P. Vetter, "DC-coupled burst-mode receiver with high sensitivity, wide dynamic range and short settling time for symmetric 10GGPONs”, ECOC’11, Mo.1.C.5
[Slide25-1]
Masaki Noda, Naoki Suzuki, Satoshi Yoshima, Masamichi Nogami, and Junichi Nakagawa, “Technology progress of high-speed burstmode 3R receiver for PON applications”, OFC’12, OTh4G.6
[Slide25-2]
Masaki Noda, Satoshi Yoshima, Kenji Ishii, Satoshi Shirai, Masamichi Nogami, and Junichi Nakagawa, “Dual-rate Optical Transceiver
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[Slide26-1]
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[Slide26-2]
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[Slide27-1]
M. Nogawa Kazuyoshi Nishimura, Jun Terada, Makoto Nakamura, Susumu Nishihara and Yusuke Ohtomo, “A 10-Gb/s burst-mode
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[Slide28-1]
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"Experiments on 10Gb/s fast settling high sensitivity burst-mode receiver with on-chip auto-reset for 10G-GPONs", OFC’12, NTu1J.4
[Slide31-1]
Masaki Noda, Naoki Suzuki, Satoshi Yoshima, Masamichi Nogami, and Junichi Nakagawa, “Technology progress of high-speed burstmode 3R receiver for PON applications”, OFC’12, OTh4G.6
[Slide31-2]
Yusuke Ohtomo,,Hideki Kamitsuna, Hiroaki Katsurai, Kazuyoshi Nishimura, Masafumi Nogawa, Makoto Nakamura, Susumu Nishihara,
Takeshi Kurosaki, Tsuyoshi Ito, Akira Okada, “High-speed circuit technology for 10-Gb/s optical burst-mode transmission” OFC’10, OWX1
[Slide31-3]
Y. (Frank) Chang, “First Demonstration of a Fast Response/Locking Burst-mode Physical-layer Chipset for Emerging 10G PON
Standards”, ECOC’09, P6.29
X.Z. Qiu, OFC’13, OW3G.4
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[Slide31-4, Slide32-1] Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto, “Jitter-Reduction and
Pulse-Width-Distortion Compensation Circuits for a 10Gb/s Burst-Mode CDR Circuit”. ISSCC’09, 5.8, pp.104-105
[Slide31-5]
C, Mélange, B. Baekelandt, J. Bauwelinck, P. Ossieur, T. De Ridder, X.Z. Qiu and J. Vandewege, "Burst-mode CDR performance
evaluation in long-reach high-split passive optical networks", JLT, Vol. 27, Nr. 17, 2009, pp. 3837-3844.
[Slide32-2]
Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru, Togashi, Kiyomi
Kumozaki, Yusuke Ohtomo, “A 10Gb/s Burst-Mode CDR IC in 0.13µm CMOS”, ISSCC’05, pp. 228-229
[Slide32-3]
Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo, “A 10.3125Gb/s Burst-Mode CDR
Circuit using a ΔΣ DAC”, ISSCC’08, pp. 226-227
[Slide33-1]
Hitoyuki Tagami, Seiji Kozaki, Kenich Nakura, Shigeki Kohama, Masamichi Nogami, and Kuniaki Motoshima, “A Burst-Mode BitSynchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON”, JSSC, Vol. 41, No. 11, 2006, pp. 25552565
[Slide33-2]
Naoki Suzuki, Kenichi Nakura, Mayumi Ishikawa, Satoshi Yoshima, Satoshi Shirai, Seiji Kozaki, Hitoyuki Tagami, Masamichi Nogami,
Akira Takahashi and Junichi Nakagawa, “Demonstration of 10.3-Gbit/s Burst-mode CDR employing 0.13 um SiGe BiCMOS Quad-rate
sampling IC and Data-phase decision-algorithm for 10Gbps-based PON Systems ”, ECOC’08, P.6.3
[Slide33-3]
N. Suzuki, K. Nakura, S. Kozaki, H. Tagami, M. Nogami and J. Nakagawa, “82.5 Gsample/s (10.3125 GHz 3 8 phase clocks) burst-mode
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P. Ossieur, J. Bauwelinck, X. Yin, C. Mélange, T. De Ridder, B. Baekelandt, X.Z. Qiu and J. Vandewege, “A dual-rate burst-mode bit
synchronization and data recovery circuit with fast optimum decision phase calculation", AEU, Vol. 63, Nr. 11, 2008, pp. 931-938
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[Slide35-2]
C, Mélange, B. Baekelandt, J. Bauwelinck, P. Ossieur, T. De Ridder, X.Z. Qiu and J. Vandewege, "Burst-mode CDR performance
evaluation in long-reach high-split passive optical networks", JLT, Vol. 27, Nr. 17, 2009, pp. 3837-3844.
[Slide35-3]
C, Mélange, X. Yin, B. Baekelandt, T. De Ridder, X.Z. Qiu, J. Bauwelinck, J. Gillis, P. Demuytere and J. Vandewege, "Fully DC-coupled
10Gb/s burst-mode PON prototypes and upstream experiments with 58ns overhead", OFC’10, OWX2
[Slide36-1]
Keiji Tanaka, Akira Agata, and Yukio Horiuchi, “IEEE 802.3av 10G-EPON Standardization and Its Research and Development Status”,
JLT Vol. 28, No. 4, 2010, pp. 651-661
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Kazutaka Hara, Shunji Kimura, Hirotaka Nakamura, Naoto Yoshimoto, and Hisaya Hadama, “1.25/10.3-Gbit/s dual-rate burst-mode
receiver with automatic bit-rate discrimination circuit for coexisting PON systems” COIN’10, pp.1-3
[Slide38-1]
Masaki Noda, Naoki Suzuki, Satoshi Yoshima, Masamichi Nogami, and Junichi Nakagawa, “Technology progress of high-speed burstmode 3R receiver for PON applications”, OFC’12, OTh4G.6
[Slide39-1]
X. Yin, J. Put, J. Verbrugghe, J. Gillis, X.Z. Qiu, J. Bauwelinck, J. Vandewege, H.G. Krimmel and M. Achouche, "A 10Gb/s burst-mode
TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time", ISSCC’12, pp. 416-417
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J. Put, X. Yin, J. Gillis, X.Z. Qiu, J. Bauwelinck, J. Vandewege, H.-G. Krimmel and P. Vetter, "10 Gbit/s burst-mode limiting amplifier with
switched time constants for fast settling and large CID tolerance", Vol. 47, 2011, pp. 970-972
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Networks”, BCTM’10, .pp.21-28
[Slide41-2]
Keiji Tanaka, Akira Agata, and Yukio Horiuchi, “IEEE 802.3av 10G-EPON Standardization and Its Research and Development Status”,
JLT Vol. 28, No. 4, 2010, pp. 651-661
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Masafumi Nogawa, Hiroaki Katsurai, Makoto Nakamura, Hideki Kamitsuna, and Yusuke Ohtomol, “10-Gbit/s Burst-mode Receiver
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J. Put, X. Yin, X.Z. Qiu, J. Gillis, J. Verbrugghe, J. Bauwelinck, J. Vandewege, F. Blache, D. Lanteri, M. Achouche, H.G. Krimmel, D. van
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X. Yin J. Put, J. Verbrugghe, J. Gillis, X.Z. Qiu, J. Bauwelinck, J. Vandewege, H.G. Krimmel and M. Achouche, "A 10Gb/s burst-mode TIA
with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time", ISSCC’12, pp. 416-417
[Slide46-3]
X. Yin, X.Z. Qiu, J. Gillis, J. Put, J. Verbrugghe, J. Bauwelinck, J. Vandewege, H. Krimmel, D. van Veen, P. Vetter and F. Chang,
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and F. C. Chang, "Experiments on 10Gb/s fast settling high sensitivity burst-mode receiver with on-chip auto-reset for 10G-GPONs",
OFC’12, NTu1J.4
[Slide49-1]
FP7 ICT DISCUS IP Project http://www.discus-fp7.eu/
[Slide49-2]
P. Ossieur, C. Mélange, B. Baekelandt, T. De Ridder, J. Bauwelinck, X.Z. Qiu and J. Vandewege, "Burst-mode electronic equalization for
10-Gb/s passive optical networks”, PTL, Vol. 20, Nr. 20, 2008, pp. 1706-1708
[Slide49-3]
Peter Ossieur, Nasir A. Quadir, Stefano Porto, Marc Rensing, Cleitus Antony, Wei Han, Peter O’Brien, Y. Chang, and Paul D. Townsend,
“A 10G linear burst-mode receiver supporting electronic dispersion compensation for extended-reach optical links”, OPEX, 2011, pp.
B604–B610
[Slide49-4]
X. Yin, B. Moeneclaey, X. Z. Qiu, J. Verbrugghe, K. Verheyen, J. Bauwelinck, J. Vandewege, M. Achouche, F. Y. Chang, "A 10Gb/s APDBased Linear Burst-Mode Receiver with 31dB Dynamic Range for Reach-Extended PON Systems”OPEX, 2012, B462-B469,
[Slide49-5]
C. Van Praet, H. Chow, D. Suvakovic, D. Van Veen, A. Dupas, R. Boislaigue, R. Farah, M. F. Lau, J. Galaro, G. Qua, N. P.
Anthapadmanabhan, G. Torfs, X. Yin and P. Vetter, "Demonstration of low-power bit-interleaving TDM PON", OPEX, 2012, B7-B14
[Slide41-1]
X.Z. Qiu, OFC’13, OW3G.4
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