Cascode

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Chapter 4
CMOS Cascode Amplifiers
4.1 Introduction
A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and
transconductance. The voltage gain can be made to attain higher value by using active load
like current source. A single stage CS amplifier can offer infinite input resistance,
moderate output resistance and moderate dc gain even with current source load. To achieve
desired performance two or more stages of MOS devices are cascaded to form a single
device called cascode amplifier [49]. This cascode amplifier can give desired performance
parameters as per stages selected for cascading.
4.2 CMOS Cascode Amplifiers
Amplification is an essential function in many analog circuits. The cascode amplifier
consists of common source (CS) and common gate (CG) configuration to achieve higher
gain. The analysis and design of cascode amplifier hence will start with the MOS device
physics, analysis and design CS stage.
4.2.1 MOS Device Physics
Assuming the basic concepts of doping, mobility, and pn junctions, the physics of
MOSFETs at elementary level is dealt here. Fig, 4.1 shows a physical structure of an ntype MOS (NMOS) device. The device consists of two heavily doped n-type regions
indicated in the figure as source (S) and drain (D) terminals, a heavily doped (conductive)
piece of polysilicon indicated as a gate (G) and a thin layer of silicon dioxide(SiO2) of
thickness tox (2-50nm) insulating gate from p-type substrate on which the device is
fabricated. Metal contacts are made to the gate on the top of oxide layer, the source region,
the drain region, and the substrate; which is also known as the body (B). The structure is
symmetric with respect to S and D and the useful action occurs in the substrate region
under the gate oxide [44].
The length L is a dimension of the gate along the source-drain path and perpendicular to
that is width W. The actual distance between source and drain (Leff) is slightly less as S/D
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Figure 4.1. Physical structure of NMOS device
junctions side diffuse. These Leff and tox play important role in the performance of the
device. Hereafter L denotes effective length.
Actually, the substrate potential also greatly affects the device characteristics. As in typical
MOS operation, the S/D junctions must be reverse- biased; the substrate of NMOS is
connected to the most negative supply in the system. In CMOS technologies, both NMOS
and PMOS devices are available. Usually NMOS and PMOS devices must be fabricated on
the same substrate and for this reason PMOS device is placed in a local substrate called a
well as shown in Fig.4.2. Here to keep the S/D junctions reverse-biased, the n-well must be
connected to the most positive voltage. An interesting fact can be seen from Fig.4.2, all
NMOS devices share same substrate but PMOS devices can have an independent n-well.
Figure 4.2. PMOS device inside n-well
MOS I/V Characteristics
To raise the abstraction from physics level to circuit level the equations for I/V
characteristics need to be studied. I/V characteristics, some of the terms and secondary
effects will be dealt in this section.
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Threshold Voltage
When a positive voltage is applied to the drain with respect to source, as the voltage at gate
with respect to source increases, the width of depletion region and the potential at oxide
silicon interface also increase. As soon as the gate potential reaches a sufficient high value,
electron flow from source to drain starts. The value of gate potential for which this current
flow occurs is called the threshold voltage VTH. The choice of VTH depends on the device
performance in typical circuit applications. The upper limit is roughly equal to V DD/4 and
lower bound determined by the variation with temperature and process, and the channel
length. Typical value of VTH is adjusted by implantation of dopants into the channel area
during fabrication.
I/V characteristics
The NMOS with gate and drain voltages applied with the normal directions of the currents
is indicated in Fig.4.3 (a). The ID versus VDS characteristics are plotted as a family of
curves, each measured at a constant VGS as shown in Fig. 4.3 (b). The shape of ID-VDS
characteristics can be expected from physical operation of the device [43].
The characteristic curves indicate clearly three distinct regions of operation: the cut off
region, the triode region, and the saturation region. The MOSFET operates as an amplifier
in the saturation region and it operates as a switch in the cut off and triode regions. The
device is in cut off when VGS<VTH whereas to operate in triode region VDS<(VGS-VTH).
The ID-VDS characteristic in the triode region can be described using physics and the
process of the device as,
Figure 4.3. (a) An n-channel enhancement type MOSFET. (b) Output characteristics
(4.1)
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where, µn is the mobility of charge carriers of N-MOSFET, Cox the gate oxide capacitance,
W the width and L the length of channel of the MOSFET.
If VDS is sufficiently small, the term of its square can be neglected from (4.1) and we
obtain,
(4.2)
The (4.2) shows that ID is a linear function of VDS, which is also seen from the
characteristic curves. This linear relationship implies that the path from source to drain can
be represented by a linear resistor as,
(4.3)
The term in the bracket is called as gate to source overdrive voltage VOD and given as,
(4.4)
When the drain-source voltage exceeds VOD, as seen ID becomes relatively constant and we
say the device operates in the saturation region. The boundary between the triode and
saturation region is characterized by,
(4.5)
Substituting this in (4.1) gives the saturation value of ID as,
(4.6)
A saturated MOSFET can be used as a current source connected between the drain and the
source.
Second-Order Effects
The analysis of MOSFET carried out so far involved various assumptions, which are not
valid for many analog circuits. Three such essential second-order effects are discussed
here.
Body Effect
In the analysis so far, it was assumed that the body and source of MOSFET were tied to the
ground. If body voltage of NMOS drops below the source voltage, the S/D junctions
remain reverse-biased but certain characteristics may change. To elaborate this effect,
assume VS=VD=0, and VG is somewhat less than VTH such that a depletion region is
formed under the gate but no inversion layer exists. Since VB becomes more negative,
more holes are attracted to the substrate, leaving behind a large negative charge widening
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the depletion region. The threshold voltage is a function of the total charge in the depletion
region because the enough gate charge must be supplied to form an inversion layer. Hence,
as VB drops, VTH increases and this is called the ―body effect‖ or the ―backgate effect‖. It
is proved that with body effect:
(4.7)
Where VSB is the source-body potential difference, VTH0 the threshold voltage without
body effect that is with VSB=0, γ denotes the body effect coefficient and ΦF the difference
between the work functions of the polysilicon gate and the silicon substrate. The value of γ
typically lies in the range of 0.3 to 0.4 V1/2.
Body effect is generally unwanted. The change in the threshold voltage complicates the
design of analog as well as digital circuits.
Channel-Length Modulation
In the analysis of I/V characteristics, it was noted that the actual length of the inverted
channel gradually decreases with increase in the potential difference between gate and
drain. Thus, effective length L` is actually a function of VDS. This effect is known as
―channel-length modulation‖. Let us write,
Then,
Figure 4.4. Effect of channel length on characteristics in saturation region
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Assuming a first order relationship between ΔL/L and VDS, that is ΔL/L=λVDS, the
equation for drain current in saturation gets modified as,
(4.8)
where, λ is the channel-length modulation coefficient. As shown in Fig. 4.4, this
phenomenon results in a nonzero slope in I/V characteristic and hence non-ideal current
source between drain and source in saturation. The parameter λ represents the relative
variation in length for a given increment in VDS. Hence, for longer length channels, λ is
smaller.
In short channel MOSFETs, the linear approximation ΔL/L α VDS becomes less accurate
resulting into a variable slope in the saturated I/V characteristics. The V DS can be used to
set ID offering more flexibility to VOD. However as dependence of ID on VDS is much
weaker, it is not used to set ID. The variation of ID with VDS is usually considered an error.
Subthreshold Conduction
In analysis of the MOSFET, the assumption was that the device turns off abruptly as V GS
drops below VTH. Actually, for VGS≈VTH, a weak inversion layer still exists and some
current flows from D to S. Even ID is finite for VGS<VTH, but the dependence is
exponential. This effect known as subthreshold conduction can be expressed by formula
for VDS greater than roughly 0.2 volts as,
(4.9)
Where δ > 1 is a nonlinearity factor and VT the thermal voltage given by VT = kT/q with k
the Boltzmann‘s constant, T the absolute temperature in kelvins and q the magnitude of
electronic charge. With VGS<VTH, it is said that the device operates in a week inversion.
Except for δ, the (4.9) is similar to the IC/VBE characteristics of the bipolar transistor. The
important point here is that as VGS falls below VTH, the ID drops at finite rate. With typical
values of δ and at room temperature, VGS decreases by approximately 80 mV for onedecade decrease in ID. Thus for example if a threshold voltage is selected 0.3V to allow
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low voltage operation, then as VGS is reduced to zero, the ID decreases by a factor of 103.75.
Subthreshold conduction can result in significant power dissipation, especially in large
circuits like memories.
The exponential variation of ID with VGS in subthreshold region can lead to achieve a
higher gain. Since only a large device width or low ID meets these conditions, the speed of
circuit is severely limited.
4.2.2 Common Source (CS) Amplifier
Consider the single stage CS amplifier with an ideal current source load shown in Fig. 4.5.
A small signal input voltage (vin) is applied to the gate and output is taken at drain (vo).
The drain current of MOSFET depends on its gate voltage (Vg) and drain voltage (Vd).
Thus, the drain current can be expressed as,
Figure 4.5. A single stage CS amplifier
(4.10)
As per the definition
is nothing but the transconductance (gm) of the MOSFET and
its output conductance. For small signals, we can write the quantities in above equation as
small case vg, vd and id. Here vg is same as the input signal vi and vd is the output of
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amplifier vo. As the MOSFET is fed by a current source, it does not allow any variation in
the drain current. Hence,
. Therefore,
(4.11)
The voltage gain (Av) of CS stage becomes
(4.12)
Where ro, the output resistance of MOSFET is defined to be 1/go.
Assuming MOSFET to be in saturation and using approximate model, drain current ( )
can be given by (4.6) as,
(4.13)
As per definition gm can be expressed as,
(4.14)
Substituting Id from (4.13) for right hand side, we get,
(4.15)
Substituting for Vg - VTH from (4.15) in (4.14)
(4.16)
The above three equations show different proportions of gm with parameters (Vg – VTH),
W/L, and Id. This is because three parameters are not independent of each other. Which
equation should be used for gm depends on which parameters have been fixed by design
and biased conditions. For example, if size and gate bias is fixed, the (4.14) should be used
for gm. On the other hand, if the current bias is fixed (4.16) is appropriate. Finally, if both
gate voltage and drain current have been fixed by the design, (4.15) should be used to
evaluate gm.
The output conductance (go) is evaluated as the slope of drain characteristics in the
saturation region. With simple Early effect like model and using (4.8), go comes out to be,
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(4.17)
Where, λ is the channel-length modulation coefficient. In terms of geometry and (Vg –
VTH) we can write,
(4.18)
The voltage gain can be written in terms of geometry and (Vg – VTH) as,
(4.19)
In terms of drain current and geometry the voltage gain is given by
(4.20)
Thus if MOSFET is biased at constant current, the DC gain is determined by the square
root of gate area, as λ α 1/L.
AC behavior of CS stage
The AC equivalent circuit of MOSFET can be drawn as shown in Fig. 4.6, including the
number of inter electrode capacitances.
Figure 4.6. AC equivalent circuit
Applying KCL at drain terminal (D), we get,
(4.21)
Separating the terms of vi and vo, we get,
(4.22)
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AC gain Avf can now be written as,
(4.23)
Let, Ctot = Cgd + Co also recognizing ωCgd/gm << 1
Then high frequency gain of CS amplifier is given by
(4.24)
This describes the frequency response of CS amplifier with one dominant pole. The
bandwidth is given by 1/roCtot. The gain bandwidth product is given by,
(4.25)
It is seen that the gain bandwidth product is independent of ro. The maximum possible
cutoff frequency occurs at unloaded amplifier, where capacitive load is device capacitance
itself. The total capacitance Ctot is directly proportional to W and technological parameter
λ, and gm is proportional to W. Thus, gain-bandwidth product depends only on
technological parameter and is independent of geometry and operating point of MOSFET.
Thus, DC gain and cutoff frequency cannot be set independently.
The above CS amplifier circuit is analyzed with an ideal current source load. In practice,
different types of loads are possible, even a practical current source is implemented by
operating MOSFET in saturation and will not offer infinite output resistance as assumed
earlier. Thus, it is needed to analyze CS stage with different loads.
CS Stage with Resistive Load
With transconductance, a MOSFET converts variations in its gate-source voltage to a small
signal current, which after passing through a resistor generates an output voltage. Now the
output current will pass through not only the output resistance of MOSFET ro, but also
externally connected load resistance RD, coming in parallel. Thus, output voltage can be
given as,
Normally ro is larger compared to external load resistor RD,
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(4.26)
The voltage gain depends on device parameter gm which itself is a function of input voltage
and aspect ratio W/L. The important observation here is that gain varies with the signal
swing, and this leads to nonlinearity. The gain can be increased by increasing aspect ratio
W/L and/or external load resistor RD. By increasing W/L, the device becomes larger
leading to greater device capacitances thus limiting high frequency response. If R D is
increased, the maximum voltage swing at the output gets limited. As seen in the analog
design octagon Fig. 1.3, the circuit exhibits trade- offs among gain, bandwidth, and voltage
swings.
CS stage with Diode-connected load
It is difficult to fabricate resistors with accurate values in many CMOS technologies.
Hence, it is desirable to replace a resistive load with a MOS transistor. A MOSFET
operates as a small signal resistor if gate and drain are shorted, called a diode-connected
Figure 4.7 (a) Diode connected NMOS and PMOS devices (b) Small signal equivalent circuit.
device as depicted in Fig.4.7(a). Here MOSFET is always in saturation as the drain and
gate have same potential. With small-signal equivalent circuit shown in Fig. 4.7(b), the
output impedance can be obtained as 1/gm ro≈1/gm. Considering body effect, it becomes
1/(gm+gmb) where gmb is the body transconductance. The impedance offered by diodeconnected load is lower when body effect is included.
Now let us consider CS stage with diode-connected load shown in Fig. 4.8. Neglecting
channel length modulation effect, the voltage gain becomes,
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Figure 4.8. CS stage with diode-connected load
(4.27)
(4.28)
Where ε=gmb2/gm2. Using (4.16) to express gm in terms of device dimensions and bias
currents, Av becomes,
(4.29)
But ID1=ID2,
(4.30)
This equation reveals an important fact that if variation of ε is negligible with output
voltage, the gain is independent of the bias currents and voltages.
The diode load can be implemented with a PMOS device also. If body terminal is tied to
the source, the circuit is free from body effect, and the small signal voltage gain becomes,
(4.31)
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Equations (4.30) and (4.31) show that the gain of the CS stage with diode-connected load
is a relatively weak function of the MOSFET dimensions. The high gain requires a strong
input device and a weak load device. This also reduces the allowable output voltage
swings.
CS stage with practical current source load
Equation (4.26) for voltage gain of the CS stage suggests that the voltage gain increases
with increase in load impedance. With resistive or diode-connected load, increase in the
load resistance limits the output voltage swing.
The load replaced with a current source load is a more practical approach as shown in Fig.
(4.9). Here the requirement is that both MOSFETs operate in saturation. The total
impedance at the output node is equal to ro1 ro2, and the gain becomes,
(4.32)
The output impedance of MOSFETs at given drain current is directly proportional to L. As
the gain is proportional to ro1 ro2, the longer MOSFETs yield a higher voltage gain, but at
the same time reducing bandwidth and requiring more overdrive voltage for M2 to
maintain it into saturation. The single stage CS amplifier cannot achieve high gain and
other configuration such as cascode amplifier must be used to achieve higher gain.
Figure 4.9. CS stage with current-source load
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4.2.3 Cascode Amplifiers
A cascode stage using CS and CG configurations is shown in Fig. 4.10. The input signal
goes to the gate of lower MOSFET (M1) arranged in CS configuration. The gate of upper
MOSFET (M2) is held at a fixed DC voltage Vr, such that both MOSFETs operate in
saturation all the time. The M2 acts as a common gate amplifier. The two MOSFETs
connected in series act as a single compound device with gate and source of M1 and drain
of M2. This compound device is evaluated to find its equivalent gm and go, denoted as gmeq
and goeq in a fashion analogous to the CS stage. Two MOSFETs are in series; hence, their
drain currents are equal.
(4.33)
Thus,
with dVd2 = 0
(4.34)
with dVg1 = 0
(4.35)
Figure 4.10. A CS-CG cascode amplifier
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gmeq of the cascode stage
To find gmeq of cascode stage, make dVd2 = 0 and evaluate the change of drain current with
changing gate voltage of M1.As the drain as well as the gate of M2 are held at fixed
voltages,
(4.36)
(4.37)
Using these equations, we can write for a small signal changing drain current,
(4.38)
(4.39)
Hence,
(4.40)
Note that the source of CG stage is not at substrate potential. Thus, as the drain voltage of
CS stage changes, the drain current of CG stage changes due to two identified reasons:
1) The gate source voltage of MOSFET changes the drain current. As the drain voltage of
M1 increases, the gate source voltage of M2 reduces thereby reducing its current.
2) Since the source voltage of M2 changes, its threshold voltage changes. This changes its
effective over voltage, and thus the current also. When the drain voltage of M 1
increases, the threshold voltage of M2 becomes higher, thereby reducing its current.
It is assumed that gm2 is defined to account for both M1 and M2. Vd1 can be eliminated from
(4.38) to get,
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Hence,
(4.41)
Commonly gm values are much higher than go values. Then (4.41) gets reduced to gmeq ≃
gm1. The value of gmeq will be slightly lower than gm1 due to feedback through the drain
voltage variation of M1.
goeq of the cascode stage
As seen from (4.33), we must make dVg1= 0 and solve for the change of drain current with
respect to change in drain voltage of M2 to evaluate goeq. With these conditions,
dVgs1 = 0
(4.42)
dVgs2 = 0 – dVs2 = - dVd1
(4.43)
dVds2 = dVd2 – dVd1
(4.44)
Using these equations, we can write small signal change in drain current,
(4.45)
(4.46)
Also from (4.45),
Then (4.46) becomes,
(4.47)
Thus we get equivalent go as,
(4.48)
Using the fact that gm values are much higher than go values,
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Hence, goeq is lower than go1 by a factor equal to the voltage gain of the upper MOSFET
M2.As seen earlier, the equivalent gm is practically the same as that for a single MOSFET
and the output resistance is higher (goeq lower), the DC gain is increased.
DC gain of the cascode stage
Once evaluated gmeq and goeq, now the DC gain of the cascode stage can be written as,
Once again using the fact that gm values are much higher than go values, we get,
It can be written as,
(4.49)
The individual DC gains of the two MOSFETs in CS and CG can be defined as,
and
Then,
Hence, DC gain of cascode amplifier is equal to the product of DC gain of individual CS
and CG stages.
AC behavior of cascode amplifier
As the gmeq of the cascode stage is about same as that of a single stage CS amplifier, the
gain bandwidth product also remains same. Due to higher output resistance, the DC gain is
higher and bandwidth gets reduced for a cascode stage.
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Figure 4.11. AC equivalent circuit of the cascode amplifier
The Fig 4.11 shows the AC equivalent circuit of the cascode amplifier. It can be seen that
vx is quite small. Due to this, the effect of the drain capacitance of M1 and gate capacitance
of M2 can be neglected. Then ro1 may be replaced by a parallel combination of ro1 and the
capacitance seen at the drain of M1. Applying KCL at output node, we get,
(4.50)
Simplifying
(4.51)
As A2 the gain of CG stage is quite large, vx is very small compared to vo.
Applying KCL at the drain of M1 gives,
(4.52)
Finally the gain becomes as,
(4.53)
Since sro1Cdg1 is small, the equation gets simplified as,
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(4.54)
As compared to CS stage the DC gain of cascode stage is multiplied by A 2 and bandwidth
reduced roughly by the same factor. Thus, the gain bandwidth product is the same as the
single CS amplifier.
Even if the DC gain is higher and gain bandwidth product remains unchanged, the design
of amplifier, which goes beyond technological limit, is possible.
Practical Cascode circuits:
The circuit of cascode amplifier analyzed has used an ideal current source as the load.
Actually, the current source load is implemented using MOS transistors. Then the output
resistance of the cascode stage comes in parallel with the output resistance of this current
source load. If single MOSFET current source is used, the output resistance becomes ro,
while that of cascode stage is A x ro. The lower resistance of current source load dominates
the final output resistance and the advantages of the cascode stage are lost [51]. Therefore,
the load also should be a cascode current source with high output resistance. This leads to
the circuit with four MOSFETs in series as shown in Fig. 4.12, often called as the
telescopic cascode amplifier. For this circuit all four MOSFETs are to be maintained in
saturation and hence consume larger voltage overdrive. However, this limits the swing in
output voltage for which all MOSFETs will be maintained in saturation.
Figure 4.12. Telescopic cascode amplifier
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The folded cascode amplifier is as shown in Fig. 4.13. Telescopic cascode limits the swing
in output voltage. The folded cascode gives increased output voltage swing but at the cost
of reduced voltage gain and increased device count [45].
Figure 4.13. Folded cascode amplifier
4.2.4 Design Examples
Statement: 1. Design single stage NMOS CS amplifier with load resistor 2 KΩ, small
signal gain 10, supply voltage 3 V, and Power dissipation not more than 3 mW. Assume
µnCox = 60 µA/ V2 and λ = 0.
Design Steps –
Power dissipation = VDD ID
Thus ID = 1 mA
As λ = 0, Av = - gmRD
Thus, gm = 5 mA/V
Now, using relation
Vod = 400 mV
To find dimensions of NMOS using equation of ID
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Figure 4.14. Schematic of CS amplifier with resistive load
Figure 4.15. Frequency and phase response of CS amplifier with resistive load
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W/L = 208, as λ is assumed zero, L cannot be taken too lower. Let L = 0.5µm, then W =
104 µm.
Simulated circuit is shown in Fig. 4.14 with Tanner schematic editor.
The frequency and phase response this design example shown in Fig. 4.15 indicates that
the voltage gain comes out to be 11.2 and bandwidth 100 MHz due to L taken of lower
value 0.5µm.
Statement: 2. Repeat above design example with diode connected load and small signal
voltage gain of 2.5, neglect body effect,
Design Steps –
The voltage gain with diode connected load neglecting body effect is given as,
(W/L)2 = (104/.5)/(2.5)2 = (20/0.5) µm/µm
Figure 4.16. Schematic of CS amplifier with diode connected load
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The circuit of diode connected CS amplifier simulated with EDA tool Tanner is shown in
Fig. 4.16. The simulation result in Fig. 4.17 shows the closely matching voltage gain with
theoretical value 2.2 and bandwidth of 450 MHz is measured.
Figure 4.17. Frequency and phase response of CS amplifier with diode connected load
Statement: 3. Design current source load CS amplifier to provide output voltage swings
2.2 V with bias current of 1mA and small signal voltage gain 50. Assume µnCox = 2µpCox =
60 µA/V2
Design Steps – Using circuit of Fig. 4.9
With supply voltage 3 V and output voltage swing 2.2 V, total overdrive available is 0.8 V.
Thus, overdrive of 0.4 V is allotted to both NMOS and PMOS device.
The dimensions can be calculated as,
W/L of NMOS = 104/0.5 µm/µm and W/L of PMOS = 208/0.5 µm/µm
Calculated gm of NMOS = 5mA/V and Gain = - gm1(ro1║ro2) = -50.
Thus required ro of both devices comes to be 20 kΩ giving us a λ = 0.05.
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The circuit is simulated with EDA tool Tanner as shown in Fig. 4.18. The phase and
frequency response simulation shown in Fig. 4.19 gives bandwidth 20 MHz much lower
Figure 4.18. Schematic of CS amplifier with current source load
Figure 4.19. Frequency and phase response of CS amplifier with current source load
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than that of resistive and diode connected load. This is due to additional junction
capacitance offered by current source. The advantage of this kind of load is the higher gain
offered by the circuit.
4.3 Current Mirror Sources
Current mirrors using MOSFETs have been widely used in analog integrated circuits both
as biasing elements and as active loads for amplifier stages. The current mirrors as biasing
circuits result in circuit performance insensitive to variations in power supply, temperature
and presence of common mode noise [36]. In MOS circuits the bias current is small, thus
the use of current mirrors become economical than resistors in terms of the die area
required. For low power supply amplifiers, high voltage gain is obtained using current
mirror as a load by offering high incremental resistance.
Figure 4.20. Current mirror block diagram with reference to ground and power supply.
A current mirror is an element with at least three terminals (IN, OUT, COMMON) as
shown in Fig.4.20. The power supply is applied to a common terminal and the input
current source to the input terminal. The output current comes out to be equal to the input
current multiplied by current gain. If this current gain is unity, the input current reflects at
output terminal and the circuit is named as current mirror. Ideally, the current mirror gain
is independent of input frequency, and the output current is independent of potential
between the output and common terminals. The voltage between input and common
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terminal is ideally required to be zero, as this allows the entire supply voltage to drop
across the input current source. Some times more than one input and or output terminals
are used.
Practical MOS current mirrors deviate from this ideal behavior. The deviations from ideal
conditions are as follows.
1. The variation of the current mirror output current with changes in voltage at the output
terminal is one of the most important deviations. The small signal output resistance, Ro
of the current mirror characterizes this effect. This resistance is included in Nortonequivalent model at the output. The Ro directly affects the performance of circuits that
use current mirrors. Higher value of Ro is achieved when the output current decreases.
This also decreases the maximum operating speed.
2. The gain error, which is deviation of gain of current mirror from its desired value, is
another error source. The gain error comprises of the systematic gain error and the
random gain error. The systematic gain error ‗ε‘ is the gain error caused even if all
matched elements in the mirror are perfectly matched. The unintended mismatches
between matched elements cause the random gain error.
3. The voltage available across the input current source is reduced due to a positive
voltage drop (VIN) created by current source connected to input. Low VIN simplifies the
design of input current source.
4. The output current depends mainly on the input current if the output voltage VOUT is
positive. This output voltage is limited to a minimum value (VOUTmin) that allows the
output device to operate in saturation. Minimizing VOUTmin maximizes the range of
output voltages for which the current mirror output resistance is almost constant.
The performances of various current mirrors are compared to each other for above four
parameters: Ro, ε, VIN and VOUTmin.
4.3.1 A Simple MOS Current Mirror
Figure 4.15 shows a simple current mirror using MOSFETs. The drain of M1 is shorted
with gate; therefore, the channel does not exist at the drain. Thus, M1 operates in the
saturation if threshold voltage is positive [7]. The M1 is said to diode connected. Let us
assume that M2 also operates in saturation region and both M1 and M2 have infinite output
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resistance. The drain current of M2 (ID2) is controlled by VGS2 that is equal to VGS1. The
gate source voltage of MOSFET is usually separated into the threshold voltage VTH and the
overdrive voltage Vod. The overdrive for M2 assuming square law behavior of MOSFET
becomes,
(4.55)
The mobility falls with increasing temperature. Hence, the overdrive rises with rising
temperature. Rearranging (4.55) and equating gate voltages of M1 and M2,
Figure 4.21. Simple current mirror
(4.56)
Thus, the overdrive of M2 is equal to that of M1.
(4.57)
If MOSFETs are identical, (W/L)2 = (W/L)1 and therefore,
(4.58)
This shows that the current flowing in the drain of M1 is mirrored to the current flowing in
the drain of M2. As for MOSFETs the forward current gain (βF) tends to ∞, applying KCL
at the drain of M1, (4.58) becomes,
56
(4.59)
Hence, the gain of the current mirror is unity, for identical devices operating in saturation
region with infinite output resistance. This result assumes that the gate currents are zero.
The result in (4.59) holds good for dc and low frequency ac currents. The gate currents of
M1 and M2 increase with increase in input frequency due to finite gate-source capacitance.
The part of the input current that flows through the gate does not flow into the drain of M 1.
This decreases the gain of current mirror as the frequency of input increases [10].
If the devices are not identical, then from (4.56) and (4.59),
(4.60)
The aspect ratio of MOSFETs changes the gain of the current mirror. To change the gain
of current mirror, width (W) is changed keeping length (L) constant.
The drain currents of MOSFETs are assumed independent of their drain-source voltages in
(4.56). In saturation region, the drain current actually increases slowly with drain-source
voltage. The output characteristic of M2 is as shown in Fig.4.16. The output resistance of
the current mirror at given operating point is the reciprocal of the slope of the output
characteristic at that point. Here,
(4.61)
where, VA is the early voltage and λ is the channel-length modulation parameter. At the
point shown on the characteristic curve VDS2=VDS1 and VGS2=VGS1. If the slope of
characteristic curve in saturation region is constant, a straight line passing through the
operating point predicts the variation in ID2 with VDS2. Therefore,
(4.62)
The ideal gain of current mirror is (W/L)2/(W/L)1. Then from (4.62) the systematic gain
error ε, is given as,
(4.63)
57
Thus the current mirror currents can differ by more than ε percent from values calculated
by assuming MOSFET output resistance to be infinite.
The input voltage for MOS current mirror (VIN) is given as,
(4.64)
According to square law behavior of MOSFET, the overdrive voltage is proportional to
square root of the input current.
The minimum output voltage required to keep M2 in saturation is,
(4.65)
VOUTmin can be made arbitrarily small as it depends on device geometry. If MOSFETs
operate in weak inversion, then VOUTmin becomes
(4.66)
Here VT is thermal voltage and at room temperature equals to 26 mV.
4.3.2 Cascode Current Mirror
One of the desirable characteristics for a current mirror is a very high output resistance that
cascode connection achieves. A MOSFET current mirror based on cascode connection is
shown in Fig. 4.17. The MOSFETs M1 and M3 form a simple current mirror. M2 acts as the
common gate part of the cascode and transfers the drain current of M 1 to the output
presenting a high output resistance. M4 acts as a diode level shifter and assures that M2 and
M1 always remain in saturation. The small signal output resistance of M2 in common gate
configuration, with ro1 as a source resistance is given in terms of small signal parameters
as,
(4.67)
For MOS cascode as dc current gain β0 → ∞, the number of stacked cascode devices can
be increased. This will be limited by the MOS substrate leakage current that creates a
resistive shunt dominating output resistance for VOUT>VOUTmin.
58
Applying KVL in Fig. 4.17,
(4.68)
As VDS3=VGS3, (4.68) shows that VDS1=VDS3 when VGS2=VGS4. With this condition, the
systematic current gain of the cascode current mirror is zero due to identical bias on M1
Figure 4.22. MOS cascode current mirror
and M2 and βF → ∞. Actually VGS2 is not exactly equal to VGS4 even with perfectly
matched MOSFETs unless VOUT=VIN. Thus, VDS1≃VDS3 and leads to,
(4.69)
The input voltage of this MOS cascode mirror is,
(4.70)
The input voltage here is composed of two gate-source drops, each including threshold and
overdrive components. Neglecting body effect and assuming that MOSFETs have got
equal overdrives,
(4.71)
59
Addition of further cascode levels increases the input voltage by another threshold and
another overdrive component per cascode. This fact increases the difficulty of designing
the input current source with low power supply voltages.
When both M1 and M2 operate in saturation region, VDS1≃VDS3=VGS3.To operate M2 in
saturation it is required that VDS2>VOV2. Hence, minimum output voltage for which M1 and
M2 operate in saturation region is,
If all MOSFETs have identical overdrives,
(4.72)
If VOUT < VOUTmin, M2 operates in the triode region and if VOUT < Vod1, both M1 and M2
operate in the triode region. Even if the overdrive is made small by using larger W, the
threshold term remains and represents significant loss of voltage swing. Thus the cascode
current mirror gives better output resistance but at cost of increased minimum output
voltage.
4.2.4 Wilson Current Mirror
The Wilson current mirror is as shown in Fig. 4.18. Let us consider the circuit without
M4.This circuit uses negative feedback through M1 and activates M3 to raise the output
resistance. A feedback path is formed that regulates ID3 so that it equals the input current.
To find the output resistance of the Wilson current mirror when all MOSFETs operate in
saturation, the small-signal model is used [43]. Applying a test mirror comes out to be,
(4.73)
60
The calculation of Ro ignores body effect. The body effect of M2 has little effect on Ro
because M1 is diode connected; the voltage from source of M2 to ground is almost
constant.
The systematic gain error here is not zero even if βF→∞, as the drain source voltage of M3
differs from that of M1 by the gate source voltage of M2. Thus without M4,
Figure 4.23. MOS Wilson current mirror
(4.74)
When M4 is inserted in series with M3, it equalizes the drain source voltages of M3 and M1.
Then, ε ≃ 0.
The output resistance is still given by (4.73), if all MOSFETs operate in saturation.
Insertion of M4 does not change the minimum output voltage or input voltage. The
minimum output voltage ignoring body effect and assuming equal overdrives is,
(4.75)
With this condition the input voltage is
61
(4.76)
4.3.5 Design Example
MOS current mirror
The proposed circuit of MOS current mirror is built selecting NMOS devices M1 and M2 of
same dimension of aspect ratio 10/0.5 µm/µm as shown in Fig. 4.24 (a). The
transconductance (gm) and output resistance (ro) of the MOSFETs used are found out using
simulation results as 1.2mA/V and 45.43kΩ. The response of all the current sources
discussed above depends on the current source IIN. The current source IIN used here is a
PMOS device maintained in saturation for all operating conditions, with the help of bias
Vb, applied on the gate. The current supplied by IIN is maintained 365µA with the help of
bias Vb on the gate of PMOS device M3. The PMOS device M3 is selected with aspect ratio
5/0.5 µm/µm and gate bias Vb required is 0.6639V. The supply voltage selected is 2.5V.
The gate bias 0.6639V is obtained from supply voltage 2.5V using voltage reference circuit
made up of one PMOS and one NMOS device of aspect ratio 3/0.5µm/µm and
18.85/0.5µm/µm respectively [60]. The similar reference voltage circuit is used in all
proposed circuits.
450
400
350
IOUT (µA)
300
250
200
150
100
50
0
0
1
2
3
VOUT(V)
Figure 4.24. (a) Schematic of CMOS current mirror source and (b) Output characteristics
The output characteristic of MOS current mirror source is as shown in Fig. 4.24 (b). The
MOSFET M2 is seen to be in triode region for VDS2 < 0.7V and enters saturation region
thereafter. The output resistance Ro calculated from output characteristic curve comes out
62
to be 47.34kΩ. The minimum output voltage for which M2 remains in saturation is 0.7V
approximately equal to overdrive of MOSFET. The load resistance RL is connected at the
drain of M2. The output voltage and output current readings are obtained by varying R L.
Cascode current source
The proposed cascode current mirror source is as shown in Fig. 4.25 (a). The aspect ratio
dimensions of NMOS devices M1-M4 is kept same to be 10/0.5µm/µm.
The dimension of current source PMOS device M5 is also kept same 5/0.5 µm/µm and to
get the current of 365µA, now the required Vb comes out to be 0.1996V. This required
voltage reference of 0.1996V is derived from 2.5V VDD using a voltage reference circuit as
shown in Fig. 4.25 (a). As the reference voltage is too lower, two PMOS and one NMOS
device is required. The PMOS device dimensions come out to be W/L=0.05/2 µm/µm and
NMOS device dimension comes out to be W/L = 61.12/0.5µm/µm. The PMOS devices
with small W and large L offer higher resistance and NMOS device with large W and
small L offer lower resistance required for generation of small Vb from large value of VDD.
400
350
IOUT (µA)
300
250
200
150
100
50
0
0
1
VOUT(V)
2
3
Figure 4.25. (a) Schematic of CMOS cascode current mirror source and (b) Output characteristics
The output resistance measured from the output characteristics curve in Fig. 4.25 (b)
comes out to be 1.622MΩ. When output voltage starts to built up, initially M 1 and M2
operate in triode region. As output voltage increases, M1 enters into saturation first. With
further increase in output voltage, both the devices operate in saturation region. The
63
minimum output voltage required to maintain both devices in saturation comes out to be
1.4V, which is approximately double of the overdrive required for single device.
Wilson current mirror source
If the three current sources are to be compared, they must be fed from identical current
source of 365µA. The aspect ratio dimensions of NMOS devices M1-M4 are selected to be
same 10/0.5µm/µm and the aspect ratio of current source PMOS device M 5 also selected
same 5/0.5 µm/µm. To get the current of 365µA from M5 the required gate drive voltage
Vb is 0.2135V. This once again is a lower reference voltage derived from higher VDD.
400
350
IOUT (µA)
300
250
200
150
100
50
0
0
1
2
3
VOUT(V)
Figure 4.26. (a) Schematic of CMOS Wilson current mirror source and (b) Output characteristics
The reference voltage circuit comes out to be similar as that of cascode current mirror
source with dimension of PMOS devices W/L = 0.05/2 µm/µm and dimension of NMOS
device W/L = 39.7/0.5 µm/µm as shown in Fig. 4.26 (a).
The output I-V characteristics of Wilson current mirror source is as shown in Fig. 4.26 (b).
As one of the NMOS device comes across output in diode configuration, the output does
not built from zero.
The output starts to build from 0.42V and M2 reaches saturation at 1.94V approximately.
The output resistance measured from I-V characteristics curve comes out to be 1.71MΩ.
The parameters of three current mirror sources are summarized in Table 1.
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Table 4.1: Summary of parameters measured from current source circuits
Circuits/
Simple current
Parameters
mirror
Ro
47.34 kΩ
Cascode current
mirror
1.622 MΩ
Wilson current
mirror
1.71 MΩ
ε
1.093
1.0045
1.0045
VIN
0.8644
1.8813
1.8734
VOUTmin
0.7V
1.4V
1.94V
The table 4.1 shows comparison of three current mirror sources based on their parameters.
From the table it is seen that highest output resistance is offered by Wilson current mirror
source but its VOUTmin is too larger which reduces its operating range. The simple current
mirror source offers comparatively low output resistance but operating range is wider than
other two sources. Thus simple current mirror source is suited as an active load whereas
other two would be suitable as tail current sources.
To conclude, the basic building block of IA, a gain stage is treated in detail in this chapter
with possible high gain stages; telescopic cascode and folded cascode. The behavior of
MOSFET with its physics is accomplished in detail. The basic circuit of CS amplifier is
designed and simulated with passive and active loads. The other building blocks required
frequently in monolithic form of IA are the current mirror sources. The current mirror
sources are analyzed and also the designing is carried in detail with simulation for
comparison.
*****
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