Sleep Mode Transistor Sizing Effect of MTCMOS Inverter Circuit on

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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
Sleep Mode Transistor Sizing Effect of MTCMOS Inverter Circuit on
Performance in Deep Submicron Technology
Hari Sarkar1, Binoy Bera2, Sudakshina Kundu3
1,2
Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India
Department of Computer Science and Engineering, West Bengal University of Technology, Kolkata, India
3
E-mail Id: [email protected], [email protected]
ABSTRACT: Multi Threshold CMOS (MTCMOS) circuit can be used to eliminate the trade-off between speed and
standby leakage current inherent in single threshold CMOS circuit. Low threshold voltage MOSFETs are used for high
speed of operation and High threshold voltage MOSFETs are used for low standby leakage current. As a result, the
standby power can be greatly reduced by this approach which is a key factor for battery operated devices. But the draw
back of MTCMOS circuit design is that the physical layout area of the circuit increases compared to conventional
inverter circuit. This paper shows how we can reduce the physical layout area of the MTCMOS circuit and its effect on
performance.
Keywords: CMOS inverter circuit, low and high Vth, MTCMOS, 90nm technology, HSPICE, insert.
I. INTRODUCTION
One of the most popular techniques to reduce power dissipation in CMOS logic circuit is by reducing supply voltage as power
dissipation is directly proportional to the square of the supply voltage (Pdyn α V2dd)[1]. But the price for reduction of only
supply voltage (Vth is fixed) is decrease in switching speed of the circuit or increase in logic gate delay which is inversely
proportional to the difference between supply voltage and threshold voltage [1]. So, to maintain high switching speed we have
to simultaneously reduce both supply voltage (Vdd) and threshold voltage (Vth). But in Deep Sub-micron Technology (gate
length less than 180nm) if we reduce threshold voltage the sub-threshold leakage current increases. This results in increase in
the standby leakage current which dominates over switching current. So, there has to be a trade off between switching speed
and standby leakage current (power dissipation). One probable solution to this problem is to use Multi Threshold CMOS
(MTCMOS) circuit. The simplest form of MTCMOS is the Dual Threshold CMOS (DTCMOS) circuit. DTCMOS circuit
uses two MOSFETs with different threshold voltages in the same circuit. Low threshold voltage MOSFETs are used to get
the desired speed of operation and high threshold voltage MOSFETs are used to reduce the standby leakage current.
Fig.1: Conventional Inverter Circuit
The Fig.1 is the conventional CMOS inverter circuit. To increase the speed of switchig threshold voltages of both the MP1
and MN2 transistors are low. Fig.2 is the MTCMOS inverter circuit of conventional inverter. To decrease the standby leakage
current one nmos transistor(MN2) with high threshold voltage is used. In the active mode of operation the MN2 transistor
should be ON and in the standby condition it should be OFF. But the physical layout area is increased in MTCMOS inverter
circuit as we have added one extra nmos(MN2) which will increase the physical layout area compared to conventional
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
inverter circuit if the physical dimension is same as MN1. But we can vary the width of MN1 and MN2 so that the total
physical layout area will be same as conventional inverter circuit. The performance of the MTCMOS circuit which is defined
by the ratio of Ion(max) to Ioff . This ratio should be maximum to get the better performance of the circuit in different
combination of width of
Fig. 2: MTCMOS Inverter Circuit
MN1 and MN2 transistors of MTCMOS inverter circuit. We have to vary the width of both MN1 and MN2 of Fig.2 so that
the total physical layout area will be same as physical layout area of Fig.1 and the ratio of Ion(max) to Ioff is maximum.
II. MATHEMATICAL ANALYSIS
Performance of conventional inverter circuit(Fig.1)[2]
The total physical layout area of Fig.1 is given by
Ain= Area of MP1+ Area of MN1
= LpWp + LnWn
As the technology is same for both MP1 and MN1 so the gate length L is same and the technology is taken as 90nm
Ain = LWp + LWn
We have taken Wp=400(nm) and Wn=250(nm)
The driving current Ion in BSIM4.6.0(Level 54) is given as [3]
Ion
which is a function of both Width and Length of the device.
The subthreshold current Ioff is given as
Ids = Ids0
Ids0 =
As other leakage current is small compared to subthreshold current we will take standby leakage current Ioff is same as
subthreshold current.
The performance factor which is given by
Pinverter =
Here, Ion means maximum driving current Ion(max) when Vds=Vdd
Performance of MTCMOS inverter circuit(Fig.2)
The total physical layout area of Fig.1 is given by
Amtcmos= Area of MP1+ Area of MN1+ Area of MN2
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
= LpWp + Ln1Wn1 + Ln2Wn2
As the technology is same for both MP1 and MN1 so the gate length L is same and the technology is taken as 90nm
Amtcmos = LWp + LWn1+ LWn2
The possible conditions of choosing Wn1 and Wn2 for better performance factor and same physical layout area as the
conventional inverter circuit
1) Wn1=Wn2 = Wn=250(nm)
In this case the total physical layout area will increase and the performance factor is given by
Pmtcmos1 =
2) (Wn1+Wn2)= Wn
In this case the total physical layout area will remain same as the conventional inverter circuit . The possible condition of
choosing Wn1 and Wn2 are
a) Wn1 = Wn2=
=125(nm)
Pmtcmos2 =
b) Wn1>Wn2
Wn1=150(nm)
Wn2=100(nm)
Pmtcmos3 =
c) Wn1<Wn2
Wn1=100(nm)
Wn2=150(nm)
Pmtcmos4 =
III. SIMULATION RESULT USING HSPICE
conventional inverter
Value
Ion(A)
10.8×10
-6
mtcmos inverter
case 1
Ion1(A)
Parameters
Ioff(A)
Pinverter
98.7×10 109
-9
Parameters
Ioff1(A)
Pmtcmos
1
Value
9.27×10
1.2×10-9
-6
mtcmos inverter
case 2(a)
Ion2(A)
7.7×10
3
Parameters
Ioff2(A)
Pmtcmos
2
Value
6.0×10-6
586×10-
10×10
12
3
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
mtcmos inverter
case 2(b)
Ion3(A)
Parameters
Ioff3(A)
Pmtcmos
3
Value
6.1×10-6
mtcmos inverter
case 2(c)
Ion4(A)
713×10-
8.5×10
12
3
Parameters
Ioff4(A)
Pmtcmos
4
Value
5.5×10-6
459×1012
11.9×1
03
IV. CONCLUSION
The conventional Inverter circuit with low threshold voltage MOS transistors has performance factor Pinverter=109 and the
MTCMOS inverter with Wn1=Wn2=Wn has the performance factor Pmtcmos=7.7×103 which is 70 times more than the
conventional inverter circuit but the physical layout area increases compared to conventional inverter circuit. The MTCMOS
inverter circuit having the same physical layout area Wn1=Wn2=125(nm) has the best performance factor Pmtcmos1=10×103.
Here, all the nmos and pmos has the same characteristic of Intel’s 90nm technology specification simulated in
BSIM4.6.0(Level 54) model[5].
ACKNOWLEDGMENT
H. Sarkar and Binoy Bera would like to thank Prof. Sudakshina Kundu West Bengal University of Technology, Kolkata for
her constant support and inspiration and guidance thanks to DST-FIST program.
REFERENCES
[1] K. Roy, S. C. Prasad, “ Low Power CMOS VLSI Circuit Design”, John Wiley & Sons, Inc, 2000, ISBN 0-47111488-X, ch.5, pp. 201-249
[2] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction
techniques in deep submicrometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327,Feb. 2003
[3] Mohan V. Dunga, Xuemei (Jane) Xi, Jin He, Weidong Liu, Kanyu M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun
Chan,Ali M. Niknejad, Chenming Hu, “BSIM4.6.0 MOSFET Model and Users’ Manual, University of California,”
[4] HSPICE User Guide,” Simulation and Analysis”, Version B-2008.09, September 2008
[5] T.Ghani,M.Armstrong,C.Auth,M.Bost,”An 90nm High Volume Manufacturing Logic Technology Featuring Novel
45nm Gate Length Strained Silicon CMOS Transistors”, proceedings of IEDM 2003.
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