E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Features
General Description
ÿÿ Automotive compatible input voltage range from 3.3V to 40V including load dump transients.
ÿÿ Resistor programmable output voltages from 3.3V to VBAT with integrated soft start.
ÿÿ Up to 200mA load current with digitally
programmable overcurrent- and open load levels.
ÿÿ Protection against supply over/under voltage,
overtemperature and overcurrent with
open-drain error flag.
ÿÿ Output for optional external bipolar NPN-transistor to reduce power dissipation.
ÿÿ Integrated I2C interface allows for programming of protection limits and voltage and current
monitoring.
ÿÿ Control interface with digital comparator for
additional functions.
ÿÿ Fast 8bit ADC samples relevant system voltages and currents.
The E522.40 is a dual phantom supply with I2C interface
for antennas in automotive environments. It affords
protection of the antenna lines against ESD, short to
ground and battery, as well as protection against thermal over-stress of the IC.
The I2C interface allows addressing of several devices
with only 2 interface lines. Various antenna voltages
from 3.3V to 18V can be programmed independently
using external voltage dividers.
A separate control line can be connected to an external bipolar NPN-transistor as a pre-regulator to reduce
power dissipation in the IC. An I2C interface in conjunction with a 8bit ADC allows monitoring of antenna voltages and currents. Overcurrent and open load limits
can be programmed for each antenna line separately,
and will lead to automatic shutoff if tripped.
An analog sense input and digital control line can be
used to interface with an additional phantom supply or
for other functions.
Applications
Ordering Information
ÿÿ Automotive Antenna Modules
ÿÿ Navigation and Radio Units
ÿÿ General Voltage Regulator Applications
Ordering No.:
Temp RangeAMB
Package
E52240A62C
-40°C to +125°C
QFN20L5
Typical Application Circuit
DSUP
VBAT
CSUP
optional
NPN for
power dissipation
CSUP,HF
Q1
CVC
SUP
VC
CIN
1 or 2 Antennas
FB[1,2]
VDD
CVDD
CVDD,HF
R1
Digital Enable
I2C Bus
{
CBYP
LOUT
A[1,2]
G1
3.3V
Dig. Sup
AC-Signal
IN[1,2]
RFBH
COUT
RFBL
Antenna
200mA
COUT,HF
RP
E522.40
EN
AIN
SDA
DO
SCL
NFLT
AD[1,2]
µC Interrupt
Analog Sense Input
Optional Digital
Control Output
GND
Ground Bus
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 1/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Functional Diagram
SUP
VC
IN[1,2]
Chargepump
RefG
+
G1
Ref
−
+
A[1,2]
−
FB[1,2]
EN
AN-MUX
VDD
8-Bit ADC
State Machine
I/V-Sense
AIN
Registers
SDA
SCL
System Control
System Error
Output Voltage
Output Current
Overcurrent Level
Open Load Level
I2C-Interface
AD1
DO
NFLT
AD2
GND
Pin Configuration
Bottom Side
AD2
VDD
AD1
FB2
A2
Top View
15 14 13 12 11
AIN
16
10
SCL
IN2
17
9
GND
n.c.
18
8
SDA
IN1
19
7
DO
VC
20
6
SUP
E522.40
2
3
4
5
A1
EN
NFLT
G1
Pin 1
1
FB1
EP
Note: Not to scale, EP Exposed die pad
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 2/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Pin Description
Pin
Name
Type 1)
Description
1
A1
HV_A_O
Output one. Needs to be bypassed with at least 10µF ceramic capacitor to GND.
2
FB1
A_I
Voltage feedback for output two. Internally connected to linear regulator error
amplifier. Reference voltage is 1.25V (typ).
3
EN
D_I
Digital enable, connect to micro-controller or to VDD.
4
NFLT
D_O
Open drain fault flag to be used as micro-controller interrupt. Asserts low if a
system fault has been detected.
5
G1
HV_A_O
Base connection for bipolar transistor. Leave this pin open if the optional bipolar
transistor is not used.
6
SUP
HV_S
Power Supply pin for battery sensing and charge pump, connect to VBAT supply
rail through diode. Bypass with 47µF capacitor.
7
DO
D_O
Digital control output for external circuitry.
8
SDA
D_IO
Digital I2C bus connection.
9
GND
S
Ground connection, needs to be connected to exposed die pad.
10
SCL
D_I
Digital I2C bus connection.
11
AD2
A_I
Address selector, selects I2C addresses for the IC. See I2C Bus section for details.
12
VDD
S
3.3V supply. Bypass with 47µF capacitor.
13
AD1
A_I
Address selector, selects I2C addresses for the IC. See I2C Bus section for details.
14
FB2
A_I
Voltage feedback for output two. Internally connected to linear regulator error
amplifier. Reference voltage is 1.25V (typ).
15
A2
HV_A_O
Output two. Needs to be bypassed with at least 10µF ceramic capacitor to GND.
16
AIN
A_I
Analog input signal for digital comparator. If the voltage on AIN exceeds the
level programmed into register AIN Toggle Level an error can be communicated
and/or DO can be toggled.
17
IN2
HV_S
Supply pin for output 2. Connect to reverse polarity protected vehicle supply,
or lower rail. If external bipolar transistor is used, connect to its emitter. Bypass
with 10µF capacitor.
18
n.c.
19
IN1
HV_S
Supply pin for output 1. Connect to reverse polarity protected vehicle supply,
or lower rail. If external bipolar transistor is used, connect to its emitter. Bypass
with 10µF capacitor.
20
VC
HV_A_O
Tank capacitor for internal charge-pump. Bypass with 1nF 20V rated ceramic capacitor to IN1
-
EP
S
Exposed Die Pad
Not Connected
1) A = Analog, D = Digital, S = Supply, I = Input, O = Output, IO = Bidirectional, HV = High Voltage
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 3/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
1Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages
with respect to ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative.
Description
Condition
Symbol
Min
Max
Unit
Supply voltage
VSUP
-0.3
40
V
Supply voltage for outputs A[1,2]
VINX
-0.3
40
V
Voltage at VC
V VC
-0.3
40
V
Output voltage
VAX
-0.3
28
V
Voltage at NFLT
VNFLT
-0.3
6
V
3.3V supply voltage
V VDD
-0.3
3.6
V
Voltage at all other low voltage IO-Pins
VLVIO
-0.3
V VDD+0.3
V
Max. Output current at outputs AN1,
AN2
IOUTANMAX
-400
0
mA
Max. junction temperature
TJMAX
150
°C
Storage temperature
TSTG
-40
150
°C
2ESD Protection
Description
Condition
Symbol
Min
Max
Unit
ESD HBM at all pins
HBM
VPINS
±2
-
kV
ESD CDM at edge pins
CDM 2)
V PINS EDGE
±0.75
-
kV
ESD CDM at all other pins
CDM
VPINS-OTHER
±0.5
-
kV
1)
2)
Note: Test point defined as tested pin to supply.
1) According to AEC-Q 100-002, Human Body Model, 1.5kΩ resistance, 100pF capacitance.
2) According to AEC-Q 100-011, Charged Device Model, pulse rise time (10% to 90%) <400ps, 1Ω resistance.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 4/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
3Recommended Operating Conditions
Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.
All voltages are referred to ground (0V).
Currents flowing into the circuit have positive values.
The first electrical potential connected to the IC must be GND. (If not specified specify timing sequence of electrical contacts.)
Description
Condition
Symbol
Min
Typ
Max
Unit
Supply voltage in run mode
Run mode
VSUP
4.5
12
26
V
Supply Voltage in standby mode
Standby mode
VSUP
3.3
12
40
V
Supply voltage in run mode
Run mode
VINX
4.5
12
26
V
Supply voltage for outputs in
standby mode
Standby mode
VINX
3.3
12
40
V
Supply Voltage for low voltage
part
VDD
3.0
3.3
3.6
V
Operating ambient temperature
TA
-40
125
°C
Output current
IOUTAN
-200
0
mA
AIN input voltage range
VAIN
0
V VDD
V
EN input high voltage
VENH
0.7*V VDD
V VDD+0.3 V
EN input LOW voltage
VENL
-0.3
0.3*V VDD
V
Input LOW voltage SDA,SCL
VI2CIL
-0.3
0.3*V VDD
V
Input HIGH voltage SDA,SCL
VI2CIH
0.7*V VDD
V VDD+0.3 V
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 5/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
4Electrical Characteristics
(V VSUP = +4.5V to +26V, TAMB = -40°C to +125°C, unless otherwise noted. Typical values are at V VSUP = +12V and TAMB =
+25°C. Positive currents flow into the device pins.)
Description
Condition
Symbol
Supply current into Pin SUP
Run mode
Supply current into Pin SUP
Min
Typ
Max
Unit
ISUPrun
0.21
2
mA
Standby mode
ISUPstb
0.19
0.22
mA
Supply current into Pin SUP
Sleep Mode
ISUPslp
5.8
10
μA
Supply current into Pin VDD
Run mode
IVDDrun
1.5
1.8
mA
Supply current into Pin VDD
Standby mode
IVDDstb
1.4
1.8
mA
TOT
165
°C
TOThyst
20
°C
Supply
Thermal error temperature
Thermal error hysteresis
1)
1)
VSUP undervoltage threshold
VSUPuv
3.3
3.9
4.5
V
VSUP overvoltage threshold
VSUPov
24
25.5
27
V
VVDD undervoltage threshold
V VDDuv
2
2.7
V
Error blanking time
Error retry time
terrb
Error latch not active
10
tRETRY
300
VA1, VA2
2
ms
500
800
ms
18
V
Internal linear regulators A1, A2
Output voltage Range
Line Regulation
V VSUP=6V to 16V
VA=5V
IA=10mA
dVAline
1.6
10
mV
Load regulation
ILoad=1mA to 150mA
V VSUP=6V
VA=5V
dVAload
7.5
30
mV
Power supply rejection ratio 2)
V VSUP=1Vpp@10kHz
PSRR
57
60
Voltage at FB-Inputs 3)
Ta=25°C
VFB25
1.243
1.256
Voltage at FB-Inputs 3)
-40°C≤Ta≤125°C
VFB
1.231
Overcurrent limit
VAX=0V
IAOC
200
Feedback input current
IINFB1, IINFB2
-1
Series resistance IN1,2 to A1,2
RDSA1, RDSA2
0.7
Start delay time
tSDT
200
μs
|TCVFB|
50
ppm
/K
2)
Feedback voltage temperature
coefficient 2)
dB
300
1.269
V
1.281
V
400
mA
1
μA
5
Ω
Pre-Regulator G1
Voltage at G1 in RUN-mode
IG1=-5mA
VG1RUN
Voltage at G1 in SLEEP-mode
SLEEP-mode
IG1=0.1mA
VG1SLP
8
8.73
9
V
200
mV
1) Test is done by correlation measurement
2) Parameter not subject to production test, Specified by design
3) Parameter defines the accuracy of the output voltage; ext. resistor divider can cause additional error
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 6/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Electrical Characteristics (continued)
(V VSUP = +4.5V to +26V, TAMB = -40°C to +125°C, unless otherwise noted. Typical values are at V VSUP = +12V and TAMB =
+25°C. Positive currents flow into the device pins.)
Description
Condition
Symbol
Min
Typ
Max
Unit
RAIN
70
100
130
KΩ
V VDD-0.4
Digital/Analog Interface
AIN input resistance
DO output HIGH voltage
IDO=-2mA
VDOOH
V
DO output LOW voltage
IDO=2mA
VDOOL
0.4
V
NFLT output LOW voltage
INFLT=1mA
VNFLTOL
0.4
V
NFLT leakage current
No system fault detected
INFLTLEAK
-1
1
μA
HINI2C
0.23
Digital Interface
I2C Interface
Hysteresis of I2C inputs SDA,SCL
SDA output LOW voltage
ISDA=4mA
VSDAOL
SDA leakage current
I2C input debounce time
V
1)
ISDALEAK
-10
tDEB
50
0.4
V
10
μA
ns
Address selection threshold low
V THADL
0.33*
V VDD
V
Address selection threshold high
V THADH
0.66*
V VDD
V
Input current AD1,AD2
IAD
-5
50
μA
400
kHz
I2C Timing
SCL Clock Frequency
fSCL
Low Time of SCL
tLOW
1.3
µs
High Time of SCL
tHigh
0.6
µs
Bus free time between a Start and
a Stop Condition
tBUF
1.3
µs
Hold time start condition
tHD_STA
0.6
µs
Data hold time
tHD_DAT
0.3
µs
Data setup time
tSU_DAT
0.3
Rise time of both SDA and SCL
tr
100
ns
Fall time of both SDA and SCL
tf
100
ns
Setup time for stop condition
tSU_STO
0.6
µs
µs
1) Parameter not subject to production test, Specified by design
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 7/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
5Typical Operating Characteristics
E522.40A Voltage Drop across the Regulator vs. Load Current in Switch Mode
200
Tamb=25°C
Tamb=125°C
Tamb=-40°C
180
160
140
Voltage Drop [mV]
120
100
80
60
40
20
0
0
20
40
60
80
100
120
140
160
180
200
Load Current [mA]
Figure 1. Voltage drop IN[n] A[n] vs. load current in switch mode.
E522.40A Output Voltage vs. Load Current in Regulator Mode
5.05
5.04
5.03
5.02
Output Voltage [V]
5.01
5
4.99
4.98
4.97
4.96
4.95
20
40
60
80
100
120
140
160
Load Current [mA]
Figure 2. Output voltage 5V vs. load current in regulator mode.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 8/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40 Current Limitation in Regulator Mode
5
4.95
4.9
4.85
Output Voltage [V]
4.8
4.75
4.7
4.65
4.6
4.55
4.5
200
210
220
230
240
250
260
270
280
290
300
Load Current [mA]
Figure 3. Output voltage 5V vs. load current in regulator mode.
E522.40A Output Voltage vs. Temperature in Regulator Mode
5.1
Load current=100mA
5.08
5.06
5.04
Output Voltage [V]
5.02
5
4.98
4.96
4.94
4.92
4.9
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 4. Output voltage 5V vs. temperature in regulator mode (load current 100mA).
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 9/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
Figure 5. Powerup 5V at load resistance of 25Ω with 1mH 10µF passive load. Ch1 shows the output voltage. Ch2 shows the
EN signal.
Figure 6. Powerdown 5V at load resistance of 25Ω with 1mH 10µF passive load. Ch1 shows the output voltage. Ch2 shows
the EN signal.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 10/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
6Functional Description
The E522.40 is a power supply for two antennas or other loads in automotive applications. It provides protection of the supply lines against ESD, short to ground and
battery. An integrated I2C interface allows for control
and diagnosis of up to four ICs with only two bus lines.
Various voltages from 3.3V to VBAT can be programmed
using the external voltage dividers. By tying FB[n] to
GND, the IC will act as a switch for that output with an
on resistance of 1.5Ω (typ). Alternatively the programmable digital output DO can be used in combination
with analog input AIN to control a third load. AIN can
be used to monitor the output of a discrete external
current amplifier and internal digital comparator levels
can be set up to switch an external transistor with DO
to disconnect the load in case of a current fault.
The IC must be powered by an external 3.3V digital supply rail at VDD. A separate digital enable EN line can be
either tied to 3.3V for always on operation, or allows
independent activation and shutoff if controlled by a
digital signal. Maximum load current per output is limited to 200mA. The actual load current is defined by the
overall power budget of the IC. It is possible to export
some of the power to an external NPN transistor placed
in the supply path of the outputs A[1-2]. G1 will regulate
the base of the external transistor to 8.73V (typ).
The I2C interface allows independent control of the
outputs and monitoring of
• Supply voltage
• Both voltages, and currents
• The analog input AIN
An integrated 8 bit analog digital converter automatically samples the output voltages and the load currents
and stores them in the respective registers. Overcurrent
and open load limits can be programmed for each outputs separately. If the overcurrent limit is tripped, the
output will be shut off. To monitor system status the
E522.40 can be read periodically via the I2C bus; alternatively the open drain fault output NFLT can be used
to trigger a microcontroller interrupt.
Depending on the setting in the status register fault
conditions can be triggered by:
• Overvoltage at SUP
• Overcurrent at any of the outputs.
• Open load at any of the outputs.
• Over and under voltage at any of the outputs
• Overtemperature
Tripping the comparator level at AIN.
The I2C addresses are defined by the state of AD[1,2] allowing up to four E522.40 to be connected to the same
I2C bus. For additional I2C address options contact your
Elmos sales representative.
6.1 Powerup and System States
The E522.40 knows five system states: SLEEP, STANDBY,
RUN, STARTDELAY, ERROR. With VDD below the undervoltage lockout level of V VDDUV the IC is in low-quiescent
current SLEEP mode.
At powerup of VDD (3.3V typ) the IC enters in STANDBY
mode. As long as EN is low the IC will remain in this
mode and can be configured via I2C interface.
If EN is switched to VDD, the E522.40 enters RUN mode.
In RUN mode all outputs go active. Until otherwise pro-
grammed the output overcurrent and open load levels
are at their default values.
Taking EN low will put the E522.40 back into STANDBY
mode. In STANDBY mode all outputs are off but memory contents are preserved. During STARTDELAY the Regulators are prepared to carry the full load. This includes
the startup of the internal chargepump. With a detected error the E522.40 enters the ERROR state.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 11/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
EN = Low
t< tSDT
EN = High
Standby
A[1,2] = off
DO = prog.
NFLT = Low until
first communication
Gl = actice
SDA = active
SCL = active
EN = Low
A[1,2] = off
DO = prog.
NFLT = Low until
first communication
Gl = actice
SDA = active
SCL = active
V DD< V DDUV
V DD>V DDUV
tretry=500ms
Error cleared
Error
Sleep
A[1,2] = erroe dep
DO = error dep
NFLT = Low
Gl = actice
SDA = active
SCL = active
tretry<500ms
t = tSDT
EN = Low
EN = Low
A[1,2] = off
DO = undef.
NFLT = HighZ
Gl = GND
SDA = HighZ
SCL = HighZ
Startdelay
Error
Run
A[1,2] = progr.
DO = programmed
NFLT = HghZ
Gl = actice
SDA = active
SCL = active
V DD< V DDUV
EN = High
V DD< V DDUV
Figure 7. System state diagram
6.2 Supply Voltage
The E522.40 is designed to operate in the automotive
environment and will tolerate supply voltages from
3.3V to 40V. Being a dual linear regulator, the device is
not capable of generating output voltages higher than
voltage applied to SUP and IN[1,2] minus the internal
voltage drop (for calculations, see next chapter).
The voltage at SUP is internally sampled by the AD converter and stored in the corresponding voltage register
SUP_Voltage (0x02). Full scale range 0xFF corresponds
to 25V resulting in a resolution of 100mV per LSB.
6.3 Overvoltage Shutoff
To limit the power dissipation in the E522.40 an overvoltage level can be programmed into the “SUP Overvoltage Level” register. Once the Supply voltage reading
exceeds the value stored in this register both outputs
are shut down and a supply overvoltage error is recorded in register Error (0x00). For more information on
power dissipation issues, see section „7.1 Thermal Considerations“.
6.4 Output Voltages at A1, A2
The voltages for outputs A[1-2] are generated by a pass
device that connects IN[n] to A[n]. Both IN1 and IN2 must
be connected to the same rail, which can be equal or
lower than SUP. If a lower voltage rail is used to supply
IN1/2, a reverse polarity diode is recommended to protect that internal rail against a short of A1 or A2 to the
battery supply.
The output voltage at A[n] is programmed with a resistor divider connected between the output and the the
corresponding FB[n] pin and is regulated to the reference
voltage at FB[n] = 1.25V (typ). It is possible to generate
output voltages as low as 1.25V but the internal current
measurement falls out of specifications below 2V(typ).
Each output voltage will need to be bypassed to GND
with a 10µF(min) capacitor. Enabling an output results
in a 200μs start delay after which the output ramps to
its programmed voltage. The output voltage in regulator
mode can be calculated by VOUT = VFB * (1 + RATIO), where
RATIO is the ratio of the external resistor divider.
If the voltage at IN[n] is simply to be switched to A[n]
without regulation, FB[n] must be connected to GND.
The corresponding pass switch is fully on and will pass
the input voltage IN[n] directly to the output minus a
current induced drop across the pass device which can be
calculated by VDROP = IA[n]·RDS,A with IA[n] = load current and
RDS,A = 1.5Ω (typ). Note that a voltage error is reported in
this case. In STANDBY and SLEEP mode all outputs A[1-2]
are switched to high impedance.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 12/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
6.5 Internal Voltage Readout
The voltages on outputs A[1,2] are internally sampled by the AD Converter and stored in the corresponding voltage
registers. Full scale range 0xFF corresponds to 18V resulting in a resolution of 70.6 mV per LSB with an accuracy of
±5%(max).
6.6 Output Currents
Output currents for the outputs are measured internally. The IC has a current limit of 300mA(typ.). Once the
load current reaches the current limit, the output voltage will be reduced. This feature prevents high inrush
currents.
In addition to the current limit, internal programmable
over-current and open-load levels exist. If the measured
current falls below the open-load level for longer than
10ms, an open load error is asserted. If the measured
current exceeds the over-current level for more than
10ms, the output is disabled and an over-current error
is asserted.
By default the over-current level is set to 200mA and
the open load level to 0mA. I2C programming allows
the levels to be programmed accordingly. Programming
0xFFinto the Over-current Level register and 0x00 into
the Open-load Level Register disables the detection
function.
6.7 Digital Readout of the Output Currents
The output currents on A[1,2] are internally sampled by the AD Converter and stored in the corresponding current
registers. Two current gain stages exist:
1. A Low Current Register with 50mA max current, trimmed at 10mA. One LSB corresponds to 0.196mA
Table 1. Output current readout low range
Register Value
0xFF
0x7F
0x33
Min
Typ
50
25
10
9
Max
11
Unit
mA
mA
mA
2. A High Current Register with 200mA max current, trimmed at 100mA. One LSB corresponds to 0.784mA
Table 2. Output current readout high range
Register Value
0xFF
0x7F
0x3F
Min
Typ
200
100
50
85
Max
115
Unit
mA
mA
mA
Note, that at voltages at A1, and A2 below 2V(typ) the current readings become inaccurate.
6.8 Pre-Regulator G1
For output voltages below 7V it is possible to export
some of the power dissipated by the E522.40 to an external NPN transistor connected with its collector to
SUP, its base to G1 and its emitter to IN1/IN2. Output
G1 regulates the base of this NPN to typ. 8.73V. The resulting emitter voltage of the external NPN is the input
voltage VIN[1,2] at IN[1,2].
The maximum power dissipated across this NPN is the
total maximum load current multiplied with the voltage drop across it.
In sleep mode G1 is at GND and the external transistor is off.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 13/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
6.9 Digital/Analog Interface DO, AIN
The E522.40 includes a separate digital output DO and
an analog input AIN. This interface can be used for various functions, but its primary purpose is control of an
additional discrete phantom supply through the I2C interface.
The analog input AIN is sampled by the ADC along with
the outputs A1 and A2 and its value is stored in Register
AIN. One bit corresponds to 0.012V.
DO can be controlled independently through register
Status or linked together with the AIN Level Register to
set up a digital comparator in the following way:
Whenever the value in Register AIN passes the level
programmed in Register AIN Level, an event is generated. Depending on the setting of the Status Register this
event can trigger a low on NFLT, a toggle of DO or both.
DO can be linked to the AIN comparator or switched
high or low independently. The Status Register is used
to set up this functionality.
The following figure shows an example of the interface
signals with AIN error trigger enabled and AIN linked
to DO:
AIN Input Voltage
AIN Threshold
NFLT Output
DO Output
Figure 8. D/A interface signal waveform
6.10 Error Handling
During RUN mode error detection is activated. All errors
will lead to a low on NFLT. All errors are cleared with a
write to the Error Register.
These following types of errors exist:
• Supply Overvoltage
If the digitally sampled supply voltage rises above
the value stored in register SUP Overvoltage Level
all outputs are shut off, to limit power dissipation.
Programming 0xFF disables over-voltage shutoff.
• Overtemperature
If the IC temperature rises above the thermal error
temperature 150°C(typ) all outputs are shut off.
• Voltage Errors
If the voltage on FB[1,2] leaves a ± 10% band
around 1.25V a voltage error is reported. The outputs remain active.
• Overcurrent
If the digitally sampled High Current of outputs
A[1,2] exceeds the value stored in register A(n)
Overcurrent Level, the corresponding output is
shut off and an overcurrent error is reported. Programming 0xFF into the register disables overcurrent detection.
• Open Load
If the digitally sampled Low Current of outputs
A[1,2] is below the value stored in register A(n)
Open Load Level, an open load error is reported,
the outputs remain active. Programming 0x00
into the register disables open load detection
• AIN Register triggered
If the digitally sampled voltage on AIN crosses the
threshold programmed into the AIN Level Register
and this error is activated in the status register an
AIN Trigger error is reported. This can also lead to
a toggle of the output DO depending on the setting in the System Register.
For all Voltage- and Current-Errors a 10ms blanking is
implemented. Blanking is not implemented for Overtemperatur-Error and AIN-Trigger.
If Auto Retry is enabled, all errors will be cleared at the
end of the retry time.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 14/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
6.11 Control Interface
Taking EN high after a VDD power up will bring up the
RUN mode of the E522.40 with its default settings:
- All outputs active at their pre-programmed setting.
- Overcurrent level of 200mA
- Open load level of 0mA
The I2C interface allows independent control of the
outputs and monitoring of output voltages and currents. An integrated 8 bit analog digital converter automatically samples the output voltage and the load current and stores them in the respective registers.
All monitored voltages and currents are sampled consecutively. A complete cycle takes about 0.5ms to update all monitor registers.
Overcurrent and open load limits can be programmed
for each output line separately, and will lead to automatic shutoff of the output if tripped. To monitor the
system status the E522.40 can be monitored periodically via the I2C bus, or the open drain fault output NFLT
can be used to trigger a micro-controller interrupt in
case of a fault.
Fault conditions can be triggered by:
• Over-voltage at SUP
• Over-current at any of the outputs.
• Open load at any of the outputs.
• Over and under voltage at any of the outputs
• Overtemperature
• AIN-Trigger
NFLT is also set to LOW in STANDBY-mode as long as
no successful communication has been detected at the
I2C-Interface.
It is possible to set up an auto retry mode or to latch
the fault condition until the fault is cleared by the I2Cinterface.
Table 3. Address map
Register Name
Address
Error
0x00
Status
SUP Voltage
SUP Overvoltage Level
A1 Voltage
A1 Low Current
A1 High Current
A1 Overcurrent Level
A1 Open Load Level
A2 Voltage
A2 Low Current
A2 High Current
A2 Overcurrent Level
A2 Open Load Level
AIN
AIN Level
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Description
Contains system error flags
Write access to the register clears all error flags
System setup and state
Voltage at pin SUP
Overvoltage error level at SUP
Output voltage at output A1
Load current at A1, 50mA range
Load current at A1, 200mA range
Overcurrent threshold A1
Open load threshold A1
Output voltage at output A2
Load current at A2, 50mA range
Load current at A2, 200mA range
Overcurrent threshold A2
Open load threshold A2
Voltage sampled at AIN
AIN trigger level
Table 4. Contains system error flags Write access to the register clears all error flags
Error (0x00)
MSB
Content
Reset Value
Access
AIN-TRIG A2-ER1
A2-ER0
A1-ER1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
AIN-TRIG : AIN Trigger
A2-ER1 : 01x - Voltage Error, 10x - Open Load
A2-ER0 : 11x Overcurrent
A1-ER1 : 01x - Voltage Error, 10x - Open Load
A1-ER0 : 11x Overcurrent
OT : Overtemperature
SUP-OV : Supply overvoltage
Bit Description
LSB
A1-ER0
0
R/W
OT
0
R/W
SUP-OV
0
R/W
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 15/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Table 5. System setup and state
Status (0x01)
MSB
Content
Reset Value
Access
POR
COM
AR/EL
EAINT
DOH
1
1
0
0
0
R
R
R/W
R/W
R/W
POR : Power On Reset
COM : reset after first successful I2C-communication
AR/EL : Auto Retry / Error Latch
EAINT : Enable AIN Error Trigger
DOH : Drive DO High
LDOAIN : Link DO and AIN
A2A : Output A2 active
A1A : Output A1 active
Bit Description
LSB
LDOAIN
0
R/W
A2A
1
R/W
A1A
1
R/W
Table 6. Voltage at pin SUP
SUP Voltage (0x02)
MSB
Content
Reset Value
Access
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
Bit Description
LSB
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Table 7. Overvoltage error level at SUP
SUP Overvoltage
Level (0x03)
Content
Reset Value
Access
Bit Description
MSB
LSB
OVL7
OVL6
OVL5
1
1
1
R/W
R/W
R/W
OVL7 : MSB Overvoltage level
OVL0 : LSB Overvoltage level
OVL4
1
R/W
OVL3
1
R/W
OVL2
1
R/W
OVL1
1
R/W
OVL0
1
R/W
Table 8. Output voltage at output A1
A1 Voltage (0x04)
MSB
Content
Reset Value
Access
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
Bit Description
LSB
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Table 9. Load current at A1, 50mA range
A1 Low Current
(0x05)
Content
Reset Value
Access
Bit Description
MSB
LSB
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 16/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Table 10. Load current at A1, 200mA range
A1 High Current
(0x06)
Content
Reset Value
Access
Bit Description
MSB
LSB
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Table 11. Overcurrent threshold A1
A1 Overcurrent Level
(0x07)
Content
Reset Value
Access
Bit Description
MSB
LSB
OCL7
OCL6
OCL5
OCL4
1
1
1
1
R/W
R/W
R/W
R/W
OCL7 : MSB of overcurrent level A1
OCL0 : LSB of overcurrent level A1
OCL3
1
R/W
OCL2
1
R/W
OCL1
1
R/W
OCL0
0
R/W
Table 12. Open load threshold A1
A1 Open Load Level
(0x08)
Content
Reset Value
Access
Bit Description
MSB
LSB
OLL7
OLL6
OLL5
OLL4
0
0
0
0
R/W
R/W
R/W
R/W
OCL7 : MSB of overcurrent level A1
OCL0 : LSB of overcurrent level A1
OLL3
0
R/W
OLL2
0
R/W
OLL1
0
R/W
OLL0
0
R/W
Table 13. Output voltage at output A2
A2 Voltage (0x09)
MSB
Content
Reset Value
Access
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
Bit Description
LSB
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Table 14. Load current at A2, 50mA range
A2 Low Current
(0x0A)
Content
Reset Value
Access
Bit Description
MSB
LSB
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Table 15. Load current at A2, 200mA range
A2 High Current
(0x0B)
Content
Reset Value
Access
Bit Description
MSB
LSB
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 17/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
Table 16. Overcurrent threshold A2
A2 Overcurrent Level
(0x0C)
Content
Reset Value
Access
Bit Description
MSB
LSB
OCL7
OCL6
OCL5
OCL4
1
1
1
1
R/W
R/W
R/W
R/W
OCL7 : MSB of overcurrent level A2
OCL0 : LSB of overcurrent level A2
OCL3
1
R/W
OCL2
1
R/W
OCL1
1
R/W
OCL0
0
R/W
Table 17. Open load threshold A2
A2 Open Load Level
(0x0D)
Content
Reset Value
Access
Bit Description
MSB
LSB
OLL7
OLL6
OLL5
OLL4
0
0
0
0
R/W
R/W
R/W
R/W
OLL7 : MSB of open load level A2
OLL0 : LSB of open load level A2
OLL3
0
R/W
OLL2
0
R/W
OLL1
0
R/W
OLL0
0
R/W
Table 18. Voltage sampled at AIN
AIN (0x0E)
MSB
Content
Reset Value
Access
ADC7
ADC6
ADC5
0
0
0
R
R
R
ADC7 : MSB of ADC value
ADC0 : LSB of ADC value
Bit Description
LSB
ADC4
0
R
ADC3
0
R
ADC2
0
R
ADC1
0
R
ADC0
0
R
Table 19. AIN trigger level
AIN Level (0x0F)
MSB
Content
Reset Value
Access
AINL7
AINL6
AINL5
AINL4
0
0
0
0
R/W
R/W
R/W
R/W
AINL7 : MSB of AIN trigger level
AINL0 : LSB of AIN trigger level
Bit Description
LSB
AINL3
0
R/W
AINL2
0
R/W
AINL1
0
R/W
AINL0
0
R/W
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 18/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
6.12 I2C Interface
The actual system configuration can be programmed
by the microcontroller via I2C interface. It is also possible to read the actual currents and voltages and reconfigure limits accordingly.
The I2C Interface implemented in this IC works in slave
mode only. The I2C bus uses Serial Clock Line [SCL] and
a bi-directional Serial Data Line [SDA].
At the physical layer, SDA line is of open-drain design,
thus, pull-up resistor is needed. Pulling the line to
ground is considered a logical zero while letting the line
float is a logical one.
Transitions for data bits are always performed while
the clock is low; transitions while it is high are "start"
and "stop" markers delimiting a bus transaction.
Data transfer is initiated with the START bit (S) when
SDA is pulled low while SCL stays high. Then, SDA sets
the transferred bit while SCL is low and the data is sampled (received) when SCL rises. When the transfer is
complete, a STOP bit (P) is sent by releasing the data line
to allow it to be pulled up while SCL is constantly high.
The complete write cycle consists of 3 Bytes delimited
by ACK's and terminated by the STOP Signal. The first
Byte contains the address of the device(7bit) and the
R/W bit. For transfer master -> slave ( write register) this
bit has to be 0.
The next Byte contains the address of the register
which shall be accessed followed by the data, which is
to be written.
A complete read cycle consists of 4Bytes. The first and
second are identical to the write cycle. After the second
byte one more start condition has to be sent followed
by a byte again containing the device address and the
R/W Bit. After that the device will send the contents
of the register and waits for an acknowledge from the
master.
The I2C addresses can be selected by connecting the
pins AD1 and AD2 to either GND, VDD/2 or VDD ( see.
Table below).
Figure 9. I2C Data Transfer
Figure 10. I2C Register Write Sequence
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 19/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
Figure 11. I2C Register Read Sequence
Table 20. I2C Addresses
VAD1
GND
VDD
GND
VDD
VAD2
GND
GND
VDD
VDD
ADR(3...0)
0x51
0x52
0x53
0x54
Figure 12. I2C Timing
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 20/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
7Typical Operating Circuit
DSUP
VBAT
CSUP
optional
NPN for
power dissipation
CSUP,HF
Q1
CVC
SUP
VC
CIN
1 or 2 Antennas
RFBH
FB[1,2]
VDD
CVDD
LOUT
A[1,2]
G1
3.3V
Dig. Sup
Antenna
200mA
RP
Digital Enable
I2C Bus
CBYP
COUT,HF
COUT
RFBL
CVDD,HF
R1
AC-Signal
IN[1,2]
{
E522.40
EN
AIN
SDA
DO
SCL
NFLT
AD[1,2]
µC Interrupt
Analog Sense Input
Optional Digital
Control Output
GND
Ground Bus
Figure 13. Typical Application Circuit
Symbol
Description
Type
Min
DSUP
Reverse Polarity Diode
Schottky
≤500mA
DIN 1)
Optional reverse polarity Diode
Schottky
≤500mA
CSUP
Input Filter Capacitor
Electrolytic 47
µF
35V
CSUP,HF
HF Capacitor
Ceramic
100
nF
35V
CIN
Input Capacitor
Ceramic
10
nF
35V
CVC
Charge-pump Tank Capacitor
Ceramic
nF
20V
Q1
Pre-regulator
NPN
RFBH
Top Voltage Prog. Resistor
Thinfilm
RFBHL
Bottom Voltage Prog. Resistor
Thinfilm
COUT
Output Filter Capacitor
COUT,HF
HF Filter Capacitor
CVDD
VDD Bypass Capacitance
CVDD,HF
VDD HF Capacitance
RP
I2C Pullup Resistor
R1
Interrupt Pullup Resistor
LOUT
Signal Filter Choke
Ferrite
2)
CBYP
Signal Coupling Capacitor
Ceramic
2)
Ceramic
Ceramic
Typ
Max
1
Unit
Rating
Example
500
mA
BD139
1
100
kΩ
1/8W
1%
1
100
kΩ
1/8W
1%
10
µF
100
nF
10
µF
6V
100
nF
6V
1) If an internal supply rail is used and output protection against VBAT is necessary.
2) Depends on customer application and antenna frequency.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 21/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
7.1 Thermal Considerations
The small footprint and high output current capability
of the E522.40 make power dissipation calculation very
important. The package has a thermal rating of RthJA =
35°C per watt according to:
• JESD 51-2 (method still air)
• JESD 51-5 (exposed pad soldered to PCB with
thermal vias)
• JESD 51-7 (4-layer PCB)
• JESD 51-12 (interpretation of Rth-values)
with IOUTmax being the maximum output current, VINmax
the maximum voltage on pin IN[1,2], and VOUTmin the
minimum output voltage to be expected on A.
Depending on configuration VINmax could either be SUP,
the output voltage of Q1, or a separate supply rail.
For an output to used as a switch the power dissipated
of this channel is calculated as
For more information on packages see Application
Note. 25AN0063E.xx “Thermal Considerations for IC
Packages”.
To calculate the maximum power PMAX in watts that
can safely be tolerated use the following formula:
with RDSAmax = 3Ω.
The total power PMAX must be higher than the sum of
PA1max and PA2max together, if not there are a number of
options:
1. Reconsidering the worst-case conditions: How likely is it that both outputs are drawing maximum
currents?
2. Can some of the power be dissipated by the external pre-regulator? - as described in section „6.8 PreRegulator G1“.
3. Since output voltage and currents can be read by
the microprocessor, the power actually dissipated can be monitored, allowing for power-limiting
measures. Such as disabling one antenna diversity
channel, etc.
As an additional safe-guard, the IC will shut down its
outputs if the internal junction temperature TJMAX exceeds 150C. This is reported to the micro-controller as
well.
P MAX =
T JMAX T AMB
RthJA
with TJMAX = 150°C, and TAMB the maximum ambient
temperature in Celsius which is present in the application during operation.
For an output to be used as a linear regulator The power
PAmax dissipated is calculated as follows:
P Amax = I OUTmax (V INmax V)OUTmin
2
P Amax = I OUTmax
RDSAmax
7.2 Layout Recommendations
• Make Supply-lines and Output-lines wide enough according to the max. current.
• Place blocking capacitors as close as possible to the IC.
• Thermal performance is strongly influenced by the board design. Use thermal vias to dissipate heat from the
exposed die pad to copper areas of the board.
• Avoid ground shift. Use large ground plane or separate the load ground from the regulator ground.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 22/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
PACKAGE
Date: 07.02.2013
OUTLINE SPECIFICATION
8Package Information
20 Lead Quad Flat Non Leaded Package
All devices
are available
to JEDEC
MO-220K, variAuthor:
ASto in a Pb free, RoHs compliant QFN20L5 plastic package according
QM-No.:
08SP0687.05
ant VHHC-2. The package is classified to Moisture(QFN20L5)
Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a
soldering peak temperature of (260+5)°C.
Package Outline and Dimensions are according JEDEC MO-220 K, variant VHHC-2
Description
Symbol
min
mm
typ
max
min
inch
typ
max
A
0.80
0.90
1.00
0.031
0.035
0.039
Stand off
A1
0.00
0.02
0.05
0.000
0.00079
0.002
Thickness of terminal leads, including lead finish
A3
--
0.20 REF
--
--
0.0079 REF
--
b
0.25
0.3
0.35
0.010
0.012
0.014
Package height
Width of terminal leads
D/E
--
5.00 BSC
--
--
0.197 BSC
--
D2 / E2
3.50
3.65
3.80
0.138
0.144
0.150
e
--
0.65 BSC
--
--
0.026 BSC
--
Length of terminal for soldering to substrate
L
0.35
0.40
0.45
0.014
0.016
0.018
Number of terminal positions
N
Package length / width
Length / width of exposed pad
Lead pitch
20
20
Note: the mm values are valid, the inch values contains rounding errors
Note 1: for assembler specific pin1 identification please see QM-document 08SP0363.xx (Pin 1 Specification)
Page 1 of 1
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 23/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
9Marking
9.1 Top Side
ÿÿ
ÿÿ
ÿÿ
ÿÿ
Elmos (Logo)
52240
YWW*#
XXXXU
Signature
52240
B
Y
WW
*
#
XXXX
U
Explanation
Elmos project number
Elmos project revision code
Year of assembly (e.g. 2014)
Week of assembly
Mask revision code
Elmos internal code
Production lot number (1 to 4 digits)
Assembler Code
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 24/26
QM-No.: 25DS0122E.02
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
E522.40
10 Record of Revision
Chapter
-
Revision
.00
.01
4
.02
6.12
.02
Change and Reason for Change
Initial revision
Product classification changed to Production Data
Page 6 - VSUPov values changed - Typ. from 25V to 25.5V
and Max. from 26V to 27V
Page 20 - Table 20 revised
Date
Released Elmos
Mar 24, 2014 AMIL/ZOE
Aug 20, 2014 AMIL/ZOE
Nov 10, 2014 AMIL/ZOE
Nov 10, 2014 AMIL/ZOE0
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 25/26
QM-No.: 25DS0122E.02
E522.40
DUAL LOW DROP OUT VOLTAGE REGULATOR WITH DIGITAL DIAGNOSIS
PRODUCTION DATA - NOV 10, 2014
WARNING – Life Support Applications Policy
Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing Elmos Semiconductor AG products,
to observe standards of safety, and to avoid situations in which malfunction or failure of an Elmos Semiconductor
AG Product could cause loss of human life, body injury or damage to property. In the development of your design,
please ensure that Elmos Semiconductor AG products are used within specified operating ranges as set forth in
the most recent product specifications.
General Disclaimer
Information furnished by Elmos Semiconductor AG is believed to be accurate and reliable. However, no responsibility is assumed by Elmos Semiconductor AG for its use, nor for any infringements of patents or other rights of third
parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Elmos Semiconductor AG. Elmos Semiconductor AG reserves the right to make changes to this document
or the products contained therein without prior notice, to improve performance, reliability, or manufacturability.
Application Disclaimer
Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as
means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed
to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does
not convey to the purchaser of the semiconductor devices described any license under the patent rights of Elmos
Semiconductor AG or others.
Contact Information
Headquarters
Elmos Semiconductor AG
Heinrich-Hertz-Str. 1 • D-44227 Dortmund (Germany)
: +492317549100
: sales-germany@elmos.com
Sales and Application Support Office North America
Elmos NA. Inc.
32255 Northwestern Highway • Suite 220 Farmington Hills
MI 48334 (USA)
: +12488653200
: sales-usa@elmos.com
Sales and Application Support Office China
Elmos Semiconductor Technology (Shanghai) Co., Ltd.
Unit 16B, 16F Zhao Feng World Trade Building,
No. 369 Jiang Su Road, Chang Ning District,
Shanghai, PR China, 200050
: +86216210 0908
: sales-china@elmos.com
Sales and Application Support Office Korea
Elmos Korea
B-1007, U-Space 2, #670 Daewangpangyo-ro,
Sampyoung-dong, Bunddang-gu, Sungnam-si
Kyounggi-do 463-400 Korea
: +82317141131
: sales-korea@elmos.com
Sales and Application Support Office Japan
Elmos Japan K.K.
BR Shibaura N Bldg. 7F
3-20-9 Shibaura, Minato-ku,
Tokyo 108-0023 Japan
: +81334517101
: sales-japan@elmos.com
Sales and Application Support Office Singapore
Elmos Semiconductor Singapore Pte Ltd.
3A International Business Park
#09-13 ICON@IBP • 609935 Singapore
: +65 6908 1261
: sales-singapore@elmos.com
 : www.elmos.com
© Elmos Semiconductor AG, 2014. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet 26/26
QM-No.: 25DS0122E.02