A Three-Phase Four-leg DVR Using Three Dimensional Space Vector
Modulation
Aziz Tashackori, Seyed Hossein Hosseini, Mehran Sabahi, and Tohid Nouri
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
E-mail: aziz.tashackori@yahoo.com, hosseini@tabrizu.ac.ir, sabahi@tabrizu.ac.ir,
thdnouri@gmail.com
Abstract: In this paper a three-phase four-wire Dynamic
Voltage Restorer (DVR) is proposed to inject required
compensating series voltage to the electric power system in
such a way that continuous sinusoidal voltage is seen at load
side ever at heavy fault occurrences at utility side. The
proposed DVR is composed of a three-phase four-leg inverter
and a three-phase high frequency harmonic filter that are
connected to the utility by three single-phase power
transformers. Three dimensional space vector modulation
(3DSVM) is applied to the proposed DVR to generate switching
pulses for power switches. Fourth added wire enables the DVR
to compensate unbalance voltage sag and swell that are custom
power quality problems in electrical utility. The performance of
the structure and applied switching scheme under both
balanced and unbalanced sag and swell are validated by
simulations in PSCAD-EMTDC software.
Keywords: DVR, 3DSVM, Balanced and Unbalanced
Disturbance, Power Quality.
1.
Introduction
The generated voltage by power plants has a sinusoidal
waveform with fixed frequency. Power quality problem is
one of the major concerns in power distribution system.
Voltage magnitude, waveform, and frequency are the
major factors that dictate the quality of a power supply.
Consumer’s equipment need pure balanced sinusoidal
voltage with constant root mean square (RMS) value to
have their satisfying operation. Any faults whether in
transmission or in distribution system causes transient
voltage sag or swell in whole or part of the grid. Any
voltage waveform disturbances may cause serious faults
in electrical equipment. Nowadays with advent of
advanced electrical and electronic equipment there has
been a progressive need to high quality electric power.
Voltage sag is widely recognized as one of the most
important power quality disturbances [1]. IEEE standard
1159-1995, defines voltage sags as a short reduction in
RMS value of the supplied voltage from its nominal
value with a magnitude between 10% up to 90% that is
happened in a short duration of time (half a cycle up to a
minute) [2]. It is often caused by faults in power systems
or by starting of large induction motors which draw very
high lagging current. Many mitigation alternatives have
been proposed in literatures. One of them is minimizing
short circuits that can be done in several ways such as
avoiding feeder or cable overloading by correct
configuration planning. Another alternative is using of
power electronic based converters such as dynamic
voltage restorer (DVR), distribution static compensator
(DSTATCOM) and uninterruptible power supply (UPS)
that are known as custom power devices.
In this paper, distributed DVR for load side protection
against balanced and unbalanced voltage sag and swell is
investigated in PSCAD/EMTDC simulation package [3].
DVR is a series compensator which is able to protect a
sensitive load from the distortion at the utility side during
fault or over load in power system [4-7]. The basic
principle of a series compensator is simple. The series
compensator can restore the load side voltage to the
desired amplitude and waveform, by injecting a
controlled series voltage, even when the source voltage is
unbalanced or distorted. In practical cases, the sags and
swells can be unbalanced. Therefore, the DVR should be
able to inject unbalanced three-phase voltages. These
voltages may be generated by the three-phase four-wire
converters with split capacitor [8] or H-bridge inverters
[9]. SPWM and Space Vector PWM control techniques
are used for controlling the DVR. Space Vector PWM
can utilize the dc voltage better and generates fewer
harmonic components in inverter output voltage [10].
Based on the afore mentioned discussions, this paper
proposes a three-phase four-wire DVR to inject required
compensating series voltage to the electric power system
in such a way that continuous sinusoidal voltage is seen
at load side ever at heavy fault occurrences at utility side.
The proposed DVR is composed of a three-phase four-leg
inverter and a three-phase high frequency harmonic filter
that are connected to the utility by three single-phase
power transformers. Three dimensional space vector
modulation (3DSVM) is applied to the proposed DVR to
generate switching pulses for power switches. Fourth
added wire enables the DVR to compensate unbalance
voltage sag and swell that are custom power quality
problems in electrical utility. The performance of the
structure and applied switching scheme under both
balanced and unbalanced sag and swell are validated by
simulations in PSCAD-EMTDC software.
2.
Three-Phase Four-wire DVR
DVR is connected in series to electrical utility in order
to mitigate voltage sag and swell and injects controlled
compensating voltage into the system to regulate the load
side voltage at desired value. The DVR was first installed
in 1996 [11]. It is normally installed in a distribution
system between the supply and the sensitive load. Its
primary function is to rapidly inject the proper voltage in
the event of a disturbance in order to avoid any power
disruption to the sensitive loads. There are various circuit
topologies and control schemes that can be used to
implement a DVR. In addition to voltage sags and swells
compensation, DVR can also perform other tasks such as:
line voltage harmonics compensation, reduction of
transients in voltage and fault current limitations.
The aim of this paper is propose a new approach
solution to maintain the voltage of sensitive load under
balanced and unbalanced distortion. This can be done by
a three-phase four-wire converter based on 3DSVM. This
technique has higher amplitude modulation indexes if
compared with convectional SPWM techniques. The
four-wire voltage source inverter topology of DVR is
shown in Fig. 1.
3.
Fig. 2: Control block diagram of DVR
Proposed Control Implementation
The purpose of control scheme is to maintain voltage
at a desired value. To control the three-phase four-leg
inverter, 3DSVM is used. 3DSVM has some advantages
such as more efficient and high DC link voltage
utilization, lower output voltage harmonic distortion, less
switching and conduction losses, wide linear modulation
range, more output voltage magnitude and its simple
digital implementation [10], [12]. The block diagram of
the control system used is shown in Fig. 2. This algorithm
is based on the representation of the natural coordinates a,
b and c in a new 3-D orthogonal frame, called α−β−γ
frame, that is as bellow:
⎡
⎢1
⎡Vα ⎤
⎢
⎢ ⎥ 2⎢
V
⎢ β ⎥ = 3 ⎢0
⎢Vγ ⎥
⎢1
⎣ ⎦
⎢
⎣⎢ 2
Fig. 1: Three-Phase Four-Wire DVR
1
2
3
2
1
2
−
1 ⎤
2 ⎥ ⎡V ⎤
⎥ a
3 ⎥⎢ ⎥
Vb
−
2 ⎥⎢ ⎥
1 ⎥ ⎢⎣Vc ⎥⎦
⎥
2 ⎦⎥
Fig. 3: Possible switching combinations
The line to neutral voltages for all sixteen switching
combinations in a−b−c coordinate and α−β−γ are shown
in TABLE I and TABLE II, respectively. Fig. 4
represents the general case of the four legs inverter
switching vectors in α−β−γ frame. There are two zero
switching vectors (ZSV) that located at the origin of the
α−β−γ coordinate and fourteen non-zero switching
vectors (NZSV). Seven vectors are located in the positive
part of the γ axis, while seven other vectors are found in
the negative part.
−
Vγ = Vg
(1)
The switching combinations can be represented by the
ordered sets [Sa , Sb , Sc , Sf ] that are shown in Fig. 3
where Sa=p denotes that the upper switch in phase A, Sap
is closed, and Sa=n denotes that the bottom switch in
phase A, San is closed. The same notation applies to phase
legs B and C and to the fourth neutral leg.
Vγ =
2
Vg
3
Vγ =
1
Vg
3
Vγ = 0
Vγ =
-1
Vg
3
Vγ =
-2
Vg
3
Vγ = -Vg
Fig. 4: Switching vectors in α−β−γ coordinate
TABLE I: The four-leg inverter switching network ac terminal voltages
pppp
nnnp
pnnp
ppnp
npnp
nppp
nnpp
pnpp
0
-Vg
0
0
-Vg
-Vg
-Vg
0
Vbf
0
-Vg
-Vg
0
0
0
-Vg
-Vg
Vcf
0
-Vg
-Vg
-Vg
-Vg
0
0
0
pppn
nnnn
pnnn
ppnn
npnn
nppn
nnpn
pnpn
Vaf
Vg
0
Vg
Vg
0
0
0
Vg
Vbf
Vg
0
0
0
Vg
Vg
0
0
Vcf
Vg
0
0
0
0
Vg
Vg
Vg
Vaf
Complete table for the corresponding NZSVs and
matrices to compute the duty ratios of all 24 tetrahedrons
is given in [10].
Vα Vβ
Vβ
3Vα ≥ Vβ
nnnp
pnnp
ppnp
npnp
nppp
nnpp
pnpp
1
Vg
3
−2
Vg
3
−1
Vg
3
−1
Vg
3
−1
Vg
3
−2
Vg
3
1
Vg
3
−1
Vg
3
Vα
0
0
2
Vg
3
Vβ
0
0
0
Vγ
0
-Vg
−2
Vg
3
−1
Vg
3
−1
Vg
3
1
Vg
3
−2
Vg
3
pppn
nnnn
pnnn
ppnn
npnn
nppn
nnpn
pnpn
1
Vg
3
1
Vg
3
−1
Vg
3
−2
Vg
3
−1
Vg
3
1
Vg
3
0
1
Vg
3
−1
Vg
3
2
Vg
3
1
Vg
3
2
Vg
3
Vα
0
0
2
Vg
3
Vβ
0
0
0
Vγ
Vg
0
1
Vg
3
1
3
Vg
0
−1
Vg
3
1
Vg
3
1 ⎤ ⎡V
⎤
⎥ ⎢ α_ref ⎥
− 1⎥ ⎢Vβ_ref ⎥
⎥⎢
⎥
0 ⎥⎦ ⎣Vγ_ref ⎦
3Vα ≥ Vβ
2
Vg
3
3.2
Projection of the Reference Vector
The time duration of the selected switching vector can
be easily computed by projecting the reference vector
onto the adjacent NSZVs. The corresponding duty ratios
of the switching vectors are given by:
⎡1
0
⎡ d1 ⎤
⎢d ⎥ = 1 ⎢ 1 − 3
⎢ 2⎥ V ⎢2
2
g ⎢
⎢⎣ d 3 ⎥⎦
⎢⎣ 0
3
d Z = 1 − d1 − d 2 − d 3
3Vα ≥ Vβ
−1
Vg
3
3.1
Selection of Switching Vectors
In order to minimize the circulating energy and to
reduce the current ripple, switching vectors adjacent to
the reference vector should be selected. This is because
that the adjacent switching vectors produce non
conflicting voltage pulses. The position of the reference
space vector can be determined in two steps:
1- Determination of the prism. Totally, there are six
prisms. The flowchart in Fig. 5 explains the prism
selection.
2- Determination of the tetrahedron in which the
reference vector is located. Each prism contains four
tetrahedrons that are shown in Fig. 6 (for prism 1). The
reference space vector is located based on the polarity of
the reference space vector components in a−b−c frame
that is given in TABLE III.
Vref = d1V1 + d 2V2 + d 3V3
3Vα ≥ Vβ
Fig. 5: Flowchart used to determine prism information
TABLE II: Inverter voltages in the α−β−γ coordinate
pppp
Vβ
Fig. 6: Presentation of the switching vector in the α-β-γ frame example
for the reference vector located in prism 1
TABLE III: Tetrahedron determination
Prism
P1
P2
P3
P4
(2)
(3)
(4)
For the reference vector in other tetrahedrons, only the
projection matrix should be changed in Equation (3).
P5
P6
Tetrahedron
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
Reference vector
component
Active Vector
V1
V2
V3
ppnp
pnnn
nnnp
pppn
npnn
ppnp
nnnp
pppn
nppp
npnn
pppn
nnnp
nnpn
nppp
pppn
nnnp
pnpp
nnpn
pppn
nnnp
pnpp
pnnn
pppn
nnnp
pnnp
ppnn
pnnp
ppnn
ppnn
npnp
npnp
ppnn
npnp
nppn
nppn
npnp
nppn
nnpp
nppn
nnpp
nnpp
pnpn
pnpn
nnpp
pnnp
pnpn
pnpn
pnnp
pnnn
ppnp
ppnp
pnnn
ppnp
npnn
ppnp
npnn
npnn
nppp
npnn
nppp
nppp
nnpn
nnpn
nppp
nnpn
pnpp
nnpn
pnpp
pnnn
pnpp
pnnn
pnpp
Vaf
≥
≥
≥
<
≥
<
≥
<
<
<
≥
<
<
<
≥
<
<
≥
≥
<
≥
≥
≥
<
Vbf
<
≥
≥
<
≥
≥
≥
<
≥
≥
≥
<
≥
<
≥
<
<
<
≥
<
<
<
≥
<
Vcf
<
<
≥
<
<
<
≥
<
<
≥
≥
<
≥
≥
≥
<
≥
≥
≥
<
<
≥
≥
<
Simulation Results
Vdvrc
In this section, the proposed system in Fig. 1 is
simulated in PSCAD-EMTDC. System parameters are
given TABLE IV. It should be noted that the series
transformers are operating in the linear region.
Fig. 7 shows the simulation results under unbalance
voltage sag condition with the values of 60%, 50% and
40% on phases a, b, and c, respectively. As can be seen,
under such conditions Fig. 7(a), the DVR injects
unbalance voltage Fig. 7(b) in such a way that the load
voltage Fig. 7(c) remains balanced and sinusoidal and
doesn’t sense the voltage sag.
Fig. 8 shows the simulation results under balance
voltage sag condition. It is clear that the load voltage is
restored to the nominal condition (before sag occurrence)
after a time lower than a half cycle.
Parameters
Value
Line Frequency
Switching frequency
Load voltage
dc bus voltage
Series transformer turns ratio
Filter Inductance
Filter capacitance
Load a phase
Load b phase
Load c phase
50Hz
10000Hz
230v rms
75v
1:4
1mh
25μf
45Ω, 40mh
60Ω, 30mh
90Ω, 70mh
0
-200
0.020
0.000
0.020
0.040
Va
400
300
200
100
0
-100
-200
-300
-400
0.000
0.080
0.100
0.120
0.140
600
400
200
0
-200
-400
-600
0.000
0.020
0.040
0.060
0.100
0.120
0.140
Load Voltage
(b)
400
300
200
100
0
-100
-200
-300
-400
Va
0.000
Vb
0.020
0.040
0.080
0.100
0.120
0.140
400
300
200
100
0
-100
-200
-300
-400
0.000
Vsb
0.020
0.040
(a)
0.080
0.100
0.040
0.140
0.120
0.140
Vc
0.060
0.080
Vsb
0.040
Vdvra
0.100
Vsc
0.060
0.080
400
300
200
100
0
-100
-200
-300
-400
Vdvrb
0.020
0.040
Va
0.060
0.100
0.120
0.140
0.120
0.140
0.040
0.120
0.140
0.120
0.140
0.120
0.140
Vdvrc
0.080
(b)
Vb
0.020
600
400
200
0
-200
-400
-600
200
0.120
0.140
Vsa
0.000
Vsc
0.060
0.020
0.020
0.000
Injected Voltage
Utility Voltage
(c)
Fig. 7: Unbalanced voltage sag, (a) utility voltages (b) injected voltages
(c) load voltages
Vsa
0.120
0.060
0.100
Vc
0.080
0.100
(c)
Fig. 9: Unbalanced swell (a) utility voltages (b) injected voltages (c)
load voltages
Vc
0.060
300
200
100
0
-100
-200
-300
-400
Vdvrc
0.080
Vb
Vsa
0.000
Load Voltage
Vdvrb
0.100
(a)
Utility Voltage
Injected Voltage
Vdvra
0.080
In another case, the DVR performance is investigated
under balanced and unbalanced voltage swell. The results
of unbalanced swell are shown in Fig. 9. In this case the
three-phase terminal voltages with unbalanced swell of
60%, 50% and 40% on phase a, b, and c are considered,
respectively. As can be seen, also under swell conditions,
the load voltage is restored to its nominal value. Fig. 10
shows the performance of DVR under 50% balance
voltage swell conditions. Utility voltage, injected voltage
and load voltage are shown.
(a)
300
200
100
0
-100
-200
-300
0.060
(c)
Fig. 8: Balanced sag (a) utility voltages (b) injected voltages (c) load
voltages
Vsc
0.060
0.040
(b)
Injected Voltage
Utility Voltage
Vsb
Vdvrb
-100
0.000
Vsa
400
300
200
100
0
-100
-200
-300
-400
Vdvra
100
0.000
Utility Voltage
TABLE IV: Simulation parameters
Injected Voltage
200
Load Voltage
4.
Vsb
0.020
0.040
Vdvrc
Vsc
0.060
(a)
0.080
Vdvra
0.100
Vdvrb
100
0
-100
-200
0.000
0.020
0.040
0.060
(b)
0.080
0.100
Load Voltage
400
300
200
100
0
-100
-200
-300
-400
0.000
Va
Vb
Vc
[9]
0.020
0.040
0.060
0.080
0.100
0.120
0.140
(c)
Fig. 10: Balance Swell (a) Utility voltages (b) Injected voltages (c) Load
voltages
As can be seen, the load voltage remains continuously
balanced and sinusoidal.
The THD values of load voltages compensated using
3DSVM are given in Table V. The THD of the load
voltage is less than 3%, that lays in the criterion reported
in IEEE standards 519-1992 [13].
Table V: THDs of Compensated Load Voltages
Type of Disturbance
THDa
THDb
THDc
Unbalanced Sag
%1.04
%0.87
%1.03
Balanced Sag
%1.35
%1.28
%1.41
Unbalanced Swell
%1.05
%0.83
%1.46
Balanced Swell
%1.53
%1.39
%1.43
5.
Conclusion
In this paper, a three-phase four-wire DVR is
presented to compensate the balanced and unbalanced sag
and swell voltage using three dimensional space vector
modulation. The performance of DVR is validated
through simulations in PSCAD/EMTDC and the results
verify the analysis. According to the results, DVR injects
appropriated series voltage during utility voltage
disturbance and maintains the load voltage at desired
value. Also the THD values of the load voltage are less
than the standard values.
References
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
H. Akagi, “New trends in active filters for power conditioning,”
IEEE Trans. Ind. Applicat., vol. 32, pp. 1312–1322, Nov./Dec.
1996.
IEEE Recommended Practice for Monitoring Electric Power
Quality, IEEE Std. 1159-2009 (Revision of IEEE Std. 11591995), 2009.
Manitoba HVDC research center Inc., “PSCAD/EMTDC Ver. 4”,
2005.
M. Gyugyi et al., “Apparatus and method for dynamic voltage
restoration of utility distribution networks,” U. S. Patent 5 329
222, July 12, 1994.
G. T. Heydt, W. Tan, T. LaRose, and M. Negley, “Simulation and
analysis of series voltage boost technology for power quality
enhancement,” IEEE Trans. Power Del., vol. 13, no. 4, pp. 1335–
1341, Oct. 1998.
J. G. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg,
“Control and testing of a dynamic voltage restorer (DVR) at
medium voltage level,” IEEE Trans. Power Electron., vol. 19, no.
3, pp. 806–813, May 2004.
S.H. Hosseni, M Sabahi, “Three-Phase DVR using a Single-Phase
Structure with Combined Hysteresis/Dead-band Control,” in
Proc. 2006 IEEE Power Electronic and Motion Control Conf.,
pp. 1-5.
A. Gosh and Gerard Ledwich, “Compensation of distribution
[10]
[11]
[12]
[13]
system voltage using DVR,” IEEE Trans. on Power Delivery, vol.
17, no. 4, pp. 1030-1036, Oct. 2002.
Changjiang Zhan, Atputharajah Arulampalam and Nicholas
Jenkins, “Four-wire Dynamic Voltage Restorer based on a threedimensional voltage space vector PWM algorithm,” IEEE Trans.
on Power Electronics, Vol. 18, No. 4, pp. 1093-1102, July. 2003.
Richard Zhang, “Three-Dimensional Space Vector Modulation
for Four-Leg Voltage Source Converters,” IEEE Trans. on power
electronics, vol. 17, no. 3, MAY 2002.
Li, B.H., S.S. Choi and D.M. Vilathgamuwa, “Design
considerations on the line-side filter used in the dynamic voltage
restorer,” IEE Proc. Generat. Transmission Distribut., vol. 148,
pp. 1-7, 2001.
R. Zhang, D. Boroyevich, H. Prasad, H. Mao, F. C. Lee, and S.
Dubovsky, “A three-phase inverter with a neutral leg with space
vector modulation,” in Proc. IEEE-APEC’97 Conf., pp. 857–863.
IEEE recommended practices and requirements for harmonic
control in electrical power systems, IEEE Standard 519-1992,
1993.