COURSEWORK, GRADING
AND END-OF-TERM TEST
DIGITAL TECHNICS
End-of-term test:
Time:
Venue:
Dr. Bálint Pődör
Óbuda University,
Microelectronics and Technology Institute
Thursday 5 May 15h20m
Bldg. G, lecture hall F19
The grading of the course will be based on the results of the
home assignments, and of the end-of-term test.
11. LECTURE (SEMICONDUCTOR MEMORIES)
Weighing will be the following:
1st homework (combinational logic)
2nd homework (sequential logic)
end-of-term test
Pass level:
20 %
30 %
50 %.
55 %
2nd (Spring) term 2010/2011
2
MEMORY HIERARCHY
11. LECTURE
SEMICONDUCTOR MEMORIES
Reg.
1. Classification of semiconductor memories
Cache
2. Elementary memory cells, operation mechanisms
3. Properties of selected important memory types
capacity/cost
Magnetic band Optical disk
CLASSIFICATION OF MEMORIES
MEMORY ACCESS
according to physical mechanism
semiconductor
capacity
Magnetic disk
4. Trends in memory developments
magnetic
access time
Central memory
”random” access (independent of address)
(RAM - Random Access Memory)
optic
stack memory
(LIFO - Last In First Out)
queuing system
(FIFO - First In First Out)
according to access
associative (contents addressable)
(CAM - Contents Addressable Memory)
address
contents
(associative)
5
6
CHANGEABILITY OF STOERED
INFORMATION
rewriteable (erasable)
RWM
Read Write Memory
MEMORY CLASSIFICATION: HARDWARE
addressable memory
readable only
ROM
Read Only Memory
ROM
In case of loss of supply voltage:
volatile / nonvolatile
RWM
Reading: destructive / non-destructive
masked PROM EPROM SRAM DRAM ferrite
static / dynamic (refreshment is necessary)
7
8
22 x 3 MEMORY
word select
address
word WE
22 x 3 MEMORY OPERATION
input
bits
write
enable
Decoder asserts one of the word select lines, based on
address.
Word select activates one of the output AND gates, which
drives the selected data to the output OR gate. (For a read,
this is basically a MUX -- decoder ANDed with signals, results
ORed together.)
When writing, the only WE bits for the proper word are
asserted (based on decoder again).
address
decoder
output bits
• This is a not the way actual memory is implemented.
– fewer transistors, much more dense,
relies on electrical properties
• But the logical structure is very similar.
– address decoder
– word select line
– word write enable
• Two basic kinds of RAM (Random Access Memory)
• Static RAM (SRAM)
– fast, maintains data as long as power applied
• Dynamic RAM (DRAM)
– slower but denser, bit storage decays – must be
periodically refreshed
ROM: FIRST LOOK ON MEMORY
Address
a0
a1
am – 1
m-to-2m decoder
MORE MEMORY DETAILS
Sel 0
(0/1)
(0/1)
(0/1)
Sel 1
(0/1)
(0/1)
(0/1)
Sel 2
(0/1)
(0/1)
(0/1)
(0/1)
(0/1)
Word lines
Sel 2 m – 1
(0/1)
Bit lines
Read
Data
dn – 1
dn – 2
d0
ROM: ORGANIZATIONAL STRUCTURE
decoder
DIODE AND BJT ROM
words
driver
An …A0 addressed word is available on the output when
CS and RD are simultaneously active (LOW).
MOSFET ROM
Read Only Memory; manufacturer programming
Usupply
1
Wo ....Wn - address/word line
Bo .... Bn - bit line
HIGH level on address line pulls up the potential of the
corresponding bit line.
PROM
Programmable Read Only Memory; can be ”programmed”
only once by the user.
Using an special equipment the fuses can be burned-out at
the appropriate places.
Selected line
fuse
NiCr fuse
0
1
The FET with connection in the selected word line pulls down
the voltage of the bit line.
PROGRAMABLE PERMANENT
MEMORIES
PROM Programable Read Only Memory
REPROGRAMMABLE ROM: EPROM
EPROM (Erasable PROM): circuit and technology: Si
MOSFET.
Mask-programmed PROM
Field programmable ROM
Floating gate MOSFET: Floating-gate avalanche MOS,
FAMOS
Relatively slow device, access time: 70-300 nsec.
REPROGRAMMABLE PROM: EPROM
REPROGRAMMABLE PROM: EEPROM
Programming:
electrical charge injection (typical voltages 12-21 V).
EEPROM Electrically Erasable PROM: can be erased
electrically.
Erasing:
ultra-violet light (not less than 5-10 minutes).
The stored charges are discharged.
After erasing the memory contains either full 0-s or 1-s.
MOS technology: floating gate MOSFET. The threshold
voltage can be set by the charge on the floating gate.
Typical parameters: programming, erasing
10 – 50 msec.
Cycle number: 1000-10000.
Number of programming cycles ca. 104 -106.
FLOATING GATE MOS TRANSISTOR (FAMOS)
FLASH MEMORY
Floating gate
MOSFET based device, two gates on top of each other.
Top electrode: direct electrical access (control gate).
Below it: control gate (floating), capacitively coupled to the
control gate and to the MOS channel.
Gate
D
Drain
Source
tox
G
tox
n
p
+
S
n+
Substrate
Device cross section
FLOATING GATE TRANSISTOR
PROGRAMMING
FLOTOX EEPROM
Floating gate
I
Gate
Drain
Source
20 V
0V
Schematic symbol
5V
VGD
−10 V
20-30 nm
10 V
n+
20 V
10 V→ 5 V
−5 V
0V
−2.5 V
5V
Substrate
p
n+
10 nm
(a) Flotox transistor
S
D
S
D
S
(b) Fowler-Nordheim I-V characteristic
BL
D
WL
Avalanche injection.
Removing programming voltage
leaves charge trapped.
Programming results in
higher VT.
VD D
(c) EEPROM cell during a read operation
CROSS-SECTIONS OF NON-VOLATILE
MEMORY CELLS
FLASH EEPROM
Control gate
Floating gate
Thin tunneling oxide
erasure
n+ source
programming
n+ drain
p-substrate
Flash
READ/WRITE MEMORY
EPROM
Courtesy Intel
6-TRANSISTOR CMOS SRAM CELL
WL
VDD
M2
M4
Q
M6
Q
M5
M1
M3
BL
STATIC MOS MEMORY: SRAM
• Static Random Acces Memory
• If supply voltage is permanently present, stores information
for very losg times
• One flip-flop in the emory cell
• Cell size grater than DRAM cell (lower integration level).
• Used in PCs to store Setup information (back-up battery is
necessary)
• Very fast operation: cache
BL
DYNAMIC MOS MEMORY: DRAM
DRAM: Dynamic Random Access Memory
One storing capacitor and a MOS transistor (connecting to
the bit-line).
Capacitor: appr. 0 V – logic 0 state,
appr. suply voltage – logic 1 state.
Periodic refreshment is necessary (charge leaking),
refreshment period typically few millisecs.
Cell capacitance: 0.03 – 0.05 pF.
Stored charge: 0.05 pF x 5 V = 0.25 pCb, appr. 1,5x106
electrons.
DYNAMIC RAM: DRAM
DRAM CELL
The memory cell consists of a MOSFET and of a MOS
capacitor
Stored bit1: capacitor charged, stored bit 0: capacitor
discharged
gating
After read operation the capacitor should be immediately
recharged
One bit storage
selection
The capacitor loses its charge rapidly (few millisec), should
be periodically refreshed
data
Access time 60-70 nsec
Cells arranged in a matrix
MOSFET STOTRAGE CELL
ASSOCIATIVE MEMORY/SEARCH
Charge storage on capacitor C
comparison
comparison
Read enable
T2
T1
Write line
key(k)
T3
C
Write enable
comparison
Read line
33
MEMORY SYSTEMS ORGANIZATION
mask
register
data (1)
key (2) data (2)
key (3) data (3)
...
comparison
Gnd
key(1)
...
key (n) data (n)
sought for data
data 34(k)
EXTENSION OF MEMORY WORD LENGTH
Parallel connection of address lines and of control lines.
Example: forming 16-bit word length RAM from two 8-bit
word length RAMs.
EXTENSION OF MEMORY CAPACITY
MEMORY: SHORT SUMMARY
Example: quadrupling of memory capacity
NEW TRENDS IN NON-VOLATILE
SEMICONDUCTOR MEMORIES
Non-volatile memories are those memories that hold the
information even after turning off a power supply. Nowadays
the most frequent non-volatile memories are flash memories
based mainly on floating gate FETs.
OVERVIEW
Scaling down the technology node of CMOS integrated
circuits yielded reliability problems in these memories. This
inspires research for new constructions and for new
operation principles of non-volatile memory elements and
arrays.
Another driving force for research for new solutions is the
permanent demand for creating faster and faster memories.
In the following slides a short summary of recent trends and
development are presented.
This part of the lecture is due to Professor Zsolt Horváth
and Dr. Péter Basa (Hungarian Academy of Sciences,
Research Institute for Technical Physics and Materials
Science).
Market trends for flash memories, DRAMs and SRAMs
Conventional non-volatile memory
transistors
Current
non-volatile
memories
(EEPROM, flash) use mainly floating
gate memory FETs.
Information storage is based on the
changing the threshold voltage of
FETs by charge injected to and
trapped in the floating gate.
Requirements for fast writing and
erasing with low pulse amplitudes is
in
contradiction
with
the
requirements for high memory
window width and good retention
behaviour.
MAIN LIMITATIONS
Main problem with floating gate
devices:
technology scale down (50 nm
gate length)
low operating voltages
low charging pulse amplitudes
very thin oxide under floating gate
Consequence: charge leakage
through defects.
Another problem: drain turn-on
effect – no saturation of drain
current due to capacitance
coupling among the drain, floating
gate, and source.
MAIN LIMITATIONS
As the space between word lines scales down to sub-50nm,
capacitance coupling via floating gate interference is
increased. Interference approaches 50 % of the total Vth shift
of the cell at the 20 nm node.
Number of electrons on the gate is small (about 80 for Vth of 1
V at 20 nm node).
Variations in channel conductivity due to discretness of
doping atoms,
line edge roughness, policrystallinity of the gate, 1/f noise,
etc.
SINGLE ELECTRON MEMORY TRANSISTOR
NANOCRYSTAL MEMORY TRANSISTORS
One of the possible solutions:
memories with embedded nanocrystals, floating gate is replaced by
semiconductor NCs, which store the
charge.
NCs are at 2-8 nm from the Si/SiO2
interface whole oxide thickness 8-30
nm, NC size 2-10 nm.
Advantages:
- the trapped charge cannot flow out
through local defects in the bottom
oxide layer
- drain turn-on effect is much lower
- floating gate interference is reduced
Freescale: 24 Mbit nanocrystal
memory array in production in 2005.
SILICON NITRIDE MEMORY TRANSISTORS
MNOS: Metal-Nitride-OxideSemiconductor SONOS: SiliconOxide-Nitride-Oxide-Silicon
SANOS, TANOS: Al2O3 upper
dielectric, TaN gate
Injected charge is stored in traps in
the Si3N4 layer, which are isolated
electrically.
Advantages:
- the trapped charge cannot flow out
through local defects in the bottom
oxide layer,
- drain turn-on effect is much lower
- floating gate interference is reduced
FERROELECTRIC MEMORY TRANSISTORS
FERROELECTRIC MEMORY TRANSISTORS
FET like structure
Memory effect connected to the electrical polarization of a
ferroelectric material
Mainly PbZrxTi1-xO3 (PZT) is used
Insulator layer is used for
passivation of Si interface
states, floating gate to enhance
device performance.
February 2009: Toshiba announced the prototype of a 128 Mbit
ferroelectric memory
PHASE CHANGE MEMORY ELEMENTS
Change of crystal phase and
conductivity by current pulses:
crystalline or amorphous.
GeSb and related compounds
GeSbTe phase-change
memory transistor
MAGNETORSISTIVE MEMORY ELEMENT
The essential part - magnetic tunnel junction: two magnetic
materials separated by a thin insulator layer.
One of the magnetic layers has a fixed, permanent
polarization, while the other can be polarized in parallel or
opposite direction .
The conductivity depends on the direction of polarization of the
free magnet.
February 2008: Intel and
StMicroelectronics distributed
the prototypes of the first phase change memory arrays.
MAGNETORSISTIVE MEMORY ELEMENT
MEMORY DEVELOPMENT SUMMARY
Writing by current applied to bit and digit lines
Scaling down the technology node resulted in reliability
problems in floating gate memories.
Nanocrystal, silicon nitride based, phase-change,
ferroelectric and magnetoresistive memories are some of
the possible alternatives to replace them.
July 2006: Freescale announced the prototype of a 512 Mbit
magnetoresistive memory array.
END OF LECTURE