DEPARTMENT OF TECHNOLOGY
A Study of LDMOS
Switched Mode Power Amplifiers
Ahmed Al Tanany
Sept, 2007
Master’s Thesis in Electronics/Telecommunication
Examiner: Olof Bengtsson
A Study of Switched Mode Power
Amplifiers using LDMOS
By
Ahmed Al Tanany
This work is done at Infineon Technologies, Sweden under supervision of :
Johan Sjöström
Hans Norström
Chen Qiang
The examiner from university of Gävle
Olof Bengtsson
A DISSERTATION
Submitted in partial fulfillment of the requirements
For the degree of
MASTER OF SCIENCE
(Electronics/Telecommunication Engineering)
UNIVERSITY OF GÄVLE
Sept, 2007
II
Abstract
This work focuses on different kinds of Switch Mode Power Amplifiers (SMPAs) using
LDMOS technologies. It involves a literature study of different SMPA concepts.
Choosing the suitable class that achieves the high efficiency was the base stone of this
work. A push-pull class J power amplifier (PA) was designed with an integrated LC
resonator inside the package using the bondwires and die capacitances. Analysis and
motivation of the chosen class is included. Designing the suitable Input/Output printed
circuit board (PCB) external circuits (i.e.; BALUN circuit, Matching network and DC
bias network) was part of the work. This work is done by ADS simulation and showed a
simulated result of about 70% drain efficiency for 34 W output power and 16 dB gain at
2.14 GHz. Study of the losses in each part of the design elements is also included.
Another design at lower frequency (i.e.; at 0.94 GHz) was also simulated and compared
to the previous design. The drain efficiency was 83% for 32 W output power and 15.4 dB
Gain.
III
IV
Acknowledgment
I would like to take the opportunity to acknowledge my indebtedness towards all the
people who have helped me in all my tasks and works.
My sincere gratitude is directed to my supervisor; Johan Sjöström. He actively involved
himself in the project and offered useful support at every stage of my project, reviewed
my schematics, answered my all questions and provided me with books and reading
material.
I am deeply grateful to my supervisors, Hans Norström and Chen Qiang for the support,
help and patience they have shown, that have provided a good basis for the present thesis.
I am grateful to Andreas Wiesbauer for his prompt interest and introducing me to the
Infineon branch in Sweden.
I would also like to thank Hans Brandberg, manager of the concept engineering, Infineon
Technologies, Sweden, for helping and encouraging during the time of preparing this
research.
My thanks are extended to all engineers at Infineon, especially; Tomas Åberg, Paul
Andersson, Reza Bagger and Ted Johansson for the welcome and the talk that we had.
Again, thanks for all your valuable advice and friendly help!
My sincere thank to my examiner at University of Gävle, Olof Bengtsson for his help and
detailed review during the preparation of this thesis.
I would like to acknowledge my friends and teachers at University of Gävle, Sweden who
were kind enough to help me during my course work and teaching me with the best of
their knowledge.
To the class of 2005 thank you for the very interesting and enjoyable two years!
I would also like to thank my dear cousin Mohammed El-Tanani and my dear friend
Ramadan Al Halabi for their encouragement and support that they gave to me throughout
my study and my research.
I owe my loving thanks to my Parents, my Brothers, my sister and their families. They
have supported me very much during my study and research abroad. Without their
encouragement and understanding it would have been impossible for me to finish this
work.
Thank you All!
V
VI
To my lovely country Palestine!
To my lovely Parents!
VII
Table of Content
INTRODUCTION ............................................................................................................................. 1
1
SI-LDMOS CHARACTERISTICS AND MODELING ....................................................... 3
1.1
SI-LDMOS RF PROPERTIES ................................................................................................. 3
1.2
INFINEON LDMOS TECHNOLOGY (GM8)............................................................................ 4
1.3
LDMOS CAD MODELING .................................................................................................... 4
1.3.1
Yang model .................................................................................................................. 5
1.3.1.1
1.3.2
1.3.2.1
2
Channel current modeling and elements extractions............................................................. 5
ELMO Model............................................................................................................... 6
Intrinsic device model............................................................................................................ 6
POWER AMPLIFIER: ESSENTIALS AND CLASSES...................................................... 7
2.1
POWER AMPLIFIER: FIGURE OF MERITS................................................................................ 7
2.2
LOAD LINE THEORY .............................................................................................................. 8
2.3
POWER AMPLIFIER CLASSES ................................................................................................. 9
2.3.1
Classical classes.......................................................................................................... 9
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.1.5
2.3.2
Switch mode power amplifiers .................................................................................. 15
2.3.2.1
2.3.2.2
2.3.2.3
3
Class A power amplifier ........................................................................................................ 9
Class B power amplifier....................................................................................................... 10
Class AB power amplifier.................................................................................................... 10
Class C power amplifier....................................................................................................... 11
Overdriven class AB power amplifier simulated example ................................................. 12
Class D power amplifier ...................................................................................................... 15
Class E power amplifier....................................................................................................... 17
Class F power amplifier ....................................................................................................... 19
CLASS J POWER AMPLIFIER........................................................................................... 21
3.1
THEORY OF OPERATION...................................................................................................... 21
3.2
CLASS J EXAMPLE .............................................................................................................. 21
3.3
CLASS J COMPARISON WITH CLASS E AND F -1 ................................................................... 29
3.3.1
Load line comparison................................................................................................ 29
3.3.2
Voltage and current waveforms ................................................................................ 30
3.3.3
Losses in the three classes ........................................................................................ 31
3.4
CLASS J PROS. AND CONS. ................................................................................................. 32
4
DESIGN STRATEGY............................................................................................................. 33
4.1
SINGLE-ENDED AND PUSH-PULL......................................................................................... 33
4.1.1
Push-pull ................................................................................................................... 33
4.1.2
Single-ended .............................................................................................................. 33
4.1.3
Advantages of single-ended push-pull topology....................................................... 33
4.2
IDEA ................................................................................................................................... 34
4.3
CIRCUIT DESIGN AND ANALYSIS ........................................................................................ 35
4.4
INPUT MATCHING CIRCUIT ................................................................................................. 36
4.5
BONDWIRE: THEORY AND DESIGN ...................................................................................... 36
5
IN/OUT- PCB DESIGN .......................................................................................................... 39
5.1
BALUN DESIGN ................................................................................................................ 39
5.1.1
BALUN Topologies ................................................................................................... 42
5.1.2
N-half wavelength balun ........................................................................................... 43
5.2
PCB IN/OUT MATCHING NETWORK .................................................................................. 46
5.3
DC-BIAS NETWORK ........................................................................................................... 46
6
SIMULATION, MEASUREMENTS AND DISCUSSIONS .............................................. 47
6.1
6.2
VIII
SIMULATION AND RESULTS ................................................................................................ 47
STABILITY CHECK .............................................................................................................. 54
6.3
MEASUREMENTS ................................................................................................................ 56
6.3.1
Package model .......................................................................................................... 60
7
COMPARISON AND FUTURE WORK ............................................................................. 63
7.1
7.2
7.3
COMPARISON WITH 0.94 GHZ............................................................................................ 63
CONCLUSION ...................................................................................................................... 65
FUTURE WORK.................................................................................................................... 66
REFERENCES ................................................................................................................................ 67
APPENDIX A.
PACKAGE CHIP............................................................................................ 71
APPENDIX B.
PCB SCHEMATICS....................................................................................... 73
APPENDIX C.
MEASUREMENT AND NEW MODEL SIMULATION .......................... 79
C. 1
C. 2
C. 3
C. 4
C. 5
BALUN MEASUREMENT AND MODEL................................................................................ 79
OUTPUT MATCHING NETWORK........................................................................................... 80
OUTPUT PCB ..................................................................................................................... 81
INPUT MATCHING NETWORK .............................................................................................. 82
INPUT PCB ......................................................................................................................... 83
IX
Introduction
The demands of high capacity, faster services and connection security require developing
new techniques for wireless communication. From analog transmission to digital, from
second generation to third generation, from GSM to EDGE and WCDMA, etc…. These
standards require new equipment to fulfill their operation. Power amplifiers (PAs) are a
vital component in any RF transmitter. High efficiency, wider bandwidth, high linearity,
high gain and high output power are needed in all the applications. However, it is hard to
meet all these qualities in the power amplifier. Hence, a trade off between them should be
made depending on the applications that intend to be used. The main trade off is usually
done between the linearity and the efficiency, because the gain and the output power
depend on the device (i.e., the transistor) transconductance and size, respectively [1].
Higher data rate in the 3rd generation mobile standard requires high output power, which
in turn needs high efficiency to reduce the losses that appear as a heat and cause
degradation of the device performance. Increasing the power efficiency is one of the
primary research areas. Various PA classes are developed recently to meet the high
efficiency requirement. The PA classes can not be used (without modification) in the
applications that use the amplitude modulation. To achieve a high efficiency, the
amplifier should be driven with large input signal which degrades the linearity required in
the amplitude modulation systems. Various technologies of efficiency enhancement
techniques are being under the spot of the research. Techniques like envelope tracking
and load modulation is required to improve the linearity of the PA.
This work studies different classes with simulation. Choosing the suitable class to achieve
the high efficiency was the base stone. Analysis and motivation of choosing the class is
included. Moreover, it concern to build a suitable topology that fit the requirements of
mobile base station and future development. Choosing the suitable IN/OUT-PCB (i.e.;
BALUN circuit, Matching and DC bias networks) external circuits is part of the work.
However, there is much work done previously with switched mode power amplifier. This
work was based on discrete components. Recently, a CMCD amplifier was manufactured
to attain 75.6% drain efficiency at 900 MHz frequency with output power 28.6 dBm (0.73
W) using discrete circuit elements [2]. A CMCD power amplifier for the base-station
applications was also shown to achieve 60% drain efficiency with high output power (13
W) [3]. An amplifier from a closely related class-E/F with 85% drain efficiency at 7 MHz
has also been reported [4]–[6]. The parasitic loss in the inductance degrades the
efficiency. These losses can be reduced with using an integrated resonator inside the
1
package and the inductance resonator could be achieved by using the bondwires which
has higher quality factor.
For my knowledge, this is the second published switch mode power amplifier (SMPA)
work that integrates the resonator inside the package. The first one is done in [7], which
use HBT technology and common resonator circuit for both push-pull dies having
operating frequency of 0.7 GHz. For 2.14 GHz frequency, it is difficult to connect two
dies with large number of bondwires, which is required by the resonator. Hence, a
separate resonator for each die was used in this work with LDMOS technology.
The report starts with a theoretical study of the Si-LDMOS with ways of modelings the
device in CAD programs. Chapter 2 discusses important issues for power amplifiers and
theoretical analysis for most of the PA classes. Chapter 3 discusses the chosen class for
the design, its results from the simulation, comparison with similar classes, and the
motivation. Chapter 4 and 5 discuss the design strategy and the circuit topology used in
this work. Chapter 6 shows the results from the simulation and the measurements.
Finally, in chapter 7; a comparison was done between the 2.14 GHz design and a 0.94
GHz design, it also includes the conclusion and suggestions for future work.
2
1 Si-LDMOS Characteristics and Modeling
Choosing the device and its technology is the essential key to get high performance for
the qualities stated previously (i.e.; linearity, bandwidth, efficiency, gain, and output
power). Among all the devices, Si-LDMOS is still the most widely used in the market.
However, the research is still on going for other technologies (i.e.; GaN HEMT, GaAs
HBT, etc…).
1.1
Si-LDMOS RF properties
Silicon Laterally double Diffused MOSFET transistor is widely used in high RF power
amplifiers below a few GHz. The main reasons are the maturated technology in terms of
fabrication, the low cost and the reliability of silicon, combined with good performance.
The cross sectional view of a Si-LDMOS is shown in Fig. 1.1. [8]. The LDMOS
transistor is a modified device of the MOSFET to enhance the high power capability. The
main modifications are:
1. Low doped and long n type drift region, which enhances the depletion region and
increases the breakdown voltage. However the on-resistance is high which
increases the losses and degrade the RF performance. Thus, there is always a
trade-off between RF output power and on-resistance.
2. Short channel length created by laterally diffused P-type implantation, which
increases the operating frequency. On the other hand, this feature increases the
linearity since the electrons always transport in the saturation velocity.
3. The sinker principle is used to connect the source to the substrate backside, which
reduces the source inductance, hence, the gain increases. Also the sinker makes
the device integration much easier.
Figure 1-1: General cross sectional view of Si-LDMOS transistor.
3
CH1:
1.2
Si-LDMOS Characteristics and Modeling
Infineon LDMOS technology (GM8)
The cross section of Infineon’s LDMOS transistor is shown in Fig. 1.2. [9]. There are
four features that have been done for this technology which enhanced the RF performance
compared to the previous generations:
•
The n-type drift region is optimized to support higher breakdown voltage.
•
The poly gate is Ti-silicided for low gate resistance, which in turn reduces the
threshold voltage.
•
A grounded thin Ti/TiN field plate reduces the channel lateral field and the
feedback capacitance Cgd.
•
A source metal runner between the gate metal runner (that periodically feeds the
gate) and drain metal decreases Cgd.
Figure 1-2: The cross section view of Infineon LDMOS GM8 transistor.
1.3
LDMOS CAD modeling
A good large signal model is helpful to design the power amplifier. Much research have
been focusing on developing Si-LDMOS CAD-models as in [10]-[14]. This work is done
in two different models based on [13] with a modified circuit, and [14].
4
CH1:
Si-LDMOS Characteristics and Modeling
1.3.1 Yang model
The Yang model [13] gave good results, and requires few numbers of parameters to
model the channel current. It doesn’t have exponent, denominator or series expansion. It
also includes the thermal effect which is very important for accurate large signal
behavior.
The circuit of the model is similar to the one shown in Fig. 1.3. In the circuit there are
three nonlinear capacitors (i.e.; Cds, Cgs, and Cgd) each of which represents the capacitance
between two of the transistor’s terminals. The capacitors are highly dependent on the
terminal voltage. However the linear elements (i.e.; Lg, Rg, Ld, Rd, Rgs, Repi, Rs and Ls) can
be extracted by the S-parameters at different bias points. The resistance Repi in the model
represents the losses associated with Cds, which mainly takes place in the epi layer of the
device.
1.3.1.1
Channel current modeling and elements extractions.
The channel current model, Id(Vgs,Vds,T), is an analytical expression, which continuously
describe the operation mode of the Si-MOSFET. The equations are listed in [13], each
parameter has a unique role to describe the channel current and they are relatively
independent of each other.
For the thermal circuit, Rth and Cth can be extracted by measuring pulsed I-V curves at
different bias conditions: Short Pulse (i.e.; duration of 1 µs) at several ambient
temperatures, and Long Pulse (i.e.; duration of 1 ms) at the room temperature. Hence, Rth
is extracted from the channel heating and Cth from the transient response.
The nonlinear capacitances (i.e.; Cds, Cgs, and Cgd) can be extracted from the measured Sparameters at various bias points, and modeled using continuous empirical functions.
Lg
G
Rg
Cgd
Cgs
Rd
Id
Rgs
Ld
D
Cds
Rep
Rs
Ls
+
d Pdi
Rth
Cth
Figure 1-3: CAD circuit model.
5
CH1:
Si-LDMOS Characteristics and Modeling
1.3.2 ELMO Model
This ELMO model [14] circuit is shown in Fig. 1.4, It consists of a BSIM3 model,
surrounded by a non-linear resistor, a voltage-dependent capacitance Cdg, a constant
capacitance Cgs, a SPICE diode containing a voltage-dependent Cds, and gate and source
resistances Rg and Rs. Power sensing elements at the input and output of the power
LDMOS feed dissipated power into a thermal circuit and the temperature rise is coupled
back to the BSIM3 model and the non-linear resistor.
To decouple the electrical and thermal characteristics, a pulsed measurement system for
current and voltage was developed. The data is collected after ~3 µs with duty-cycle of
0.01 %.
Psense
D
Psense
Cgd
Rg
G
Rth
Cgs
Rs
S
Cth
Thermal
Circuit
Figure 1-4: ELMO model circuit.
1.3.2.1
Intrinsic device model
The BSIM3 parameters were extracted from Id - Vgs and Id - Vds characteristics. The nonlinear resistor was extracted in the following way: the BSIM3 parameters were locked for
good correlation in the low current region, a resistance was extracted in an automated
MATLAB-script for the high current region by subtracting the drain-source voltage of the
measurement from the simulation at each point. A function containing exponential and
power-law dependencies fit the resulting non-linear resistor with gate-source and drainsource voltage dependencies. This was repeated for temperatures in the range T=25°C to
T=125°C and temperature dependent parameters were introduced.
The bias dependent capacitances were determined from CV measurements on full-scale
devices. However, the thermal resistance was extracted using an IR camera [14].
6
2 Power Amplifier: Essentials and classes
RF power amplifiers (PA) are used in vast variety of application such as radar, mobile
communication, etc. The PA is a device that converts DC power into RF power. This
research focuses mainly on increasing the efficiency using “a new” class described in
[15]. This chapter will discuss all power amplifier classes and some analysis done from
the simulation of the classes.
2.1
Power amplifier: Figure of merits.
RF output power (Pout) is the conveyed power from the DC input power. It is limited by
the device size.
Linearity is important, especially when the signal contains amplitude and phase
modulation (i.e., QAM modulation). When the gain and phase variation versus the output
power is negligible the power amplifier has linear amplification. The linearity can be
achieved either by a chain of linear PAs or a combination of nonlinear PAs.
Gain (G) is the ratio between the power delivered to the load (Pout) and the power
available from the source (PRFin). Transducer gain can be expressed by:
G=Pout/PRFin
(2.1)
The other useful definition is maximum available gain (MAG) which is a ratio between
the power available from the output of the transistor and the power available from the
source. The maximum value occurs when the input and the output of the transistor are
conjugate matched [16].
Efficiency is one of the important parameters in the PAs which has been studied
extensively recently. There are three different definitions for the efficiency.
1. The drain efficiency (η) is the ratio of the fundamental (i.e.; the power
component at the operating frequency) RF output power to DC input
power
η = Pout /Pdc
(2.2)
2. Power added efficiency (PAE) is the ratio of the fundamental RF net
power to the DC input power.
PAE= (Pout-PRFin)/Pdc.
PAE= (Pout (1-PRFin/Pout))/Pdc.
PAE= η(1-1/G).
(2.3)
7
CH2:
Power Amplifier: Essentials and classes
As it can be seen, when the gain is high the power added efficiency is close to
the drain efficiency
3. Overall efficiency (OAE) is the ratio of the fundamental output power
(i.e.; RF power) to the all input power
OAE=Pout/(Pdc+PRFin).
2.2
(2.4)
Load line theory
Studying the current and voltage waveforms is the key of knowing; if the transistor is
working with the full power capability or not, if it is working in the saturation, or even
predicting the output resistance that the transistor should see for giving the maximum
linear output power. All of this can be calculated from the “load line theory”. Fig. 2.1
shows the load line imposed on the I-V curves. The line is centered on the bias point of
the transistor and its slop equal to the susceptance of the load (i.e.; in the real impedance
case). This line shows the peak current and voltage. The minimum current is zero and the
minimum voltage is the knee voltage. In Fig 2.1, the optimum power results when the
load is equal to ROL (i.e.; optimum load). In this case the current swings fully between
zero and the saturation current values, and the voltage swings between the knee voltage
and the breakdown voltage. Also, two other cases are shown when the load is less than or
greater than ROL, where either the current or the voltage is limiting the output power and
does not give the maximum possible power [17].
IDS
RL=ROL
IMAX
RL<ROL
IQ
RL>ROL
0
VKnee
Vdd
2VDD-VKnee
Figure 2-1: Load line imposed on IV-curve.
8
VDS
CH2:
2.3
Power Amplifier: Essentials and classes
Power amplifier classes
Power amplifiers can be classified upon their way of operation into different classes: A,
B, AB, C, D, E, F, J etc. Classes of operation differ not only in the method of operation,
but also in the efficiency and their circuit topologies. The basic topologies are single
ended, and push pull power amplifier, see Fig. 2.2.
This section shows the main differences between each class and some simulated
VDD
-
Vo
+
examples for a few chosen types.
Output
Filter
DC -
Output
Filter
Feeder
IDS
+
+
VDS
Vo
-
(a)
0o
VDD
180o
(a)
Figure 2-2: Typical circuit topology, (a) Single ended; (b) Push-Pull.
2.3.1 Classical classes
2.3.1.1
Class A power amplifier
The gate bias in the Class A power amplifier is set to make the transistor active all the
time as a current source (i.e.; above the threshold voltage) which means the conduction
angle is 2 π . The applied signal at the input is sinusoidal and the output network has a
filter to pass the fundamental (could be matching network), and high pass filter to ground
for the harmonics. In consequence for this, the drain current and voltage waveforms are
sinusoidal.
Since the transistor is on during all the cycle, the maximum efficiency is 50% for the
ideal case. This efficiency number, in practice, is reduced significantly to about 35% for
L band (i.e.; 1-2 GHz) applications. The ideal drain current and voltage waveforms for a
class A power amplifier is shown in Fig. 2.3.
9
CH2:
Power Amplifier: Essentials and classes
g
2Vdd-Vknee
Imax
Vdd
Vknee
Iq
0
T/8
T/4
3T/8
T/2
Time
5T/8
3T/4
7T/8
T
Current [A]
Voltage [V]
Current
Voltage
0
Figure 2-3: Class A power amplifier drain voltage and current waveforms.
2.3.1.2
Class B power amplifier
In class B the gate voltage is biased at the threshold to make the conduction angle equal
to π , which increases the maximum theoretical efficiency from 50% in class A to 78.5%
in class B. The ideal drain current and voltage waveforms for a class B power amplifier
are sinusoidal because the drive input signal is sinusoidal and the output network has
filters to pass the fundamental and to short out the harmonics, see Fig 2.4.
g
2Vdd-Vknee
Imax
Vdd
Vknee
Iq
0
T/8
T/4
3T/8
T/2
Time
5T/8
3T/4
7T/8
T
Current [A]
Voltage [V]
Current
Voltage
0
Figure 2-4: Class B power amplifier drain voltage and current waveforms.
2.3.1.3
Class AB power amplifier
The class AB power amplifier is a state in between class A and class B, in which the gate
is biased slightly above the threshold voltage to make the conduction angle between
π and 2 π . Since the conduction angle is larger than in class B, and less than in class A,
10
CH2:
Power Amplifier: Essentials and classes
the efficiency varies between 50% and 78.5%. The ideal drain current and voltage
waveforms for a class AB power amplifier are shown in Fig. 2.5 (the sinusoidal shape
occurs when the load is assumed to act as an ideal short circuit i.e.; zero resistance, for
the harmonics).
g
2Vdd-Vknee
Imax
Vdd
Vknee
Current [A]
Voltage [V]
Current
Voltage
Iq
0
T/8
T/4
3T/8
T/2
Time
5T/8
3T/4
7T/8
T
0
Figure 2-5: Class AB power amplifier drain voltage and current waveforms.
g
2Vdd-Vknee
Imax
Vdd
Vknee
Iq
0
T/8
T/4
3T/8
T/2
Time
5T/8
3T/4
7T/8
T
Current [A]
Voltage [V]
Current
Voltage
0
Figure 2-6: Class C power amplifier drain voltage and current waveforms.
2.3.1.4
Class C power amplifier
In class C, the biasing voltage is less than the threshold voltage. Hence, the conduction
angle is less than that in class B (i.e.; less than π ). The efficiency may reaches up to
100%. However, there are several problems for an (1-2 GHz) Class-C implementation.
The first one is that the efficiency comes at the expense of the gain. In fact, the efficiency
could reach 100% by reducing the conduction angle to zero. Unfortunately, this cause the
output power to decrease toward zero and the drive input power to infinity. The second
11
CH2:
Power Amplifier: Essentials and classes
drawback is that the amplifier is highly nonlinear because it requires large drive input
power, so it can be used only in applications that can tolerate a high degree of
nonlinearity, or it has to be used with linearization techniques. The ideal drain current and
voltage waveforms for a class C power amplifier are shown in Fig. 2.6.
Before we go to other classes, the next part shows simulation of an overdriven class AB
power amplifier [15] with the effects of all the parasitic parameters from the device.
2.3.1.5
Overdriven class AB power amplifier simulated example
The device model used for this example has 100 mm gate width with including all the
capacitances. For this amplifier, the load network was an ideal one in which the
impedance value does not depend on the operating frequency. The operating frequency is
fo=1 GHz.
The circuit topology used in this example is shown in Fig. 2.7. (i.e.; single ended). The
load network is a function of harmonic, see Equation 2.1 and the input source is one tone,
its impedance is 1 Ω.
⎧ R + jX
ZL = ⎨
⎩0
(2.1)
, f = fo
, f = n fo
where n = 2,3...
To achieve the maximum efficiency, the load value should be adjusted to 6.4 Ω and
inductive susceptance equal to -j0.141 S to tune out the effect of the output capacitance
(i.e.; Cds), see Table 2.1 on page 13. The drain voltage is set as the default value (i.e.;
Vdd=28 V). To make the conduction angle in the range of a class AB power amplifier, we
need to have the gate voltage swinging above the threshold for more than the half period.
Hence, it biased with gate voltage 3 V and input power level is equal to 25 dBm. The load
line graph is shown in Fig 2.8.
Cgd
vggg
DC_Block
DC_Block1
P_1Tone
PORT1
Num=1
Z=1 Ohm {o}
P=polar(dbmtow(Pin),phi)
Freq=fc0
I_Probe
I_gs
DC_Feed
DC_Feed1
V_DC
Vgs
Vdc=Vg V
Cgs
Vout
Cds
Id
VAR
VAR1
w=100
I_Probe
I_Probe1
Var
Eqn
GM8_simplified
T1
m=100/1.2
repi=repi
cgs=Cgs
cds=Cds
cgd=Cgd
alpha2=a
I_Probe
I_ds
DC_Block
DC_Block2
I_Probe
I_dc
Y1P_Eqn
Y1P1
Y[1,1]=j*yout
Z1P_Eqn
Z1P1
Z[1,1]=rout
DC_Feed
DC_Feed2
Yout
V_DC
Vdd
Vdc=Vd V
Figure 2-7: Circuit topology for class AB example.
12
I_Probe
I_out
Zout
CH2:
Power Amplifier: Essentials and classes
35
30
Ids [A]
25
20
15
A
10
B
5
0
0
10
20
30
40
50
60
Vds [V]
Figure 2-8: Overdriven class AB simulated load line.
As it can be seen from this graph the load line has small loops (i.e.; region A and B) which are
probably due to two reasons. The first is that the load impedance still has some reactive value
at the fundamental frequency, and the other is the feedback capacitor in the model (i.e.; Cgd)
which allows a leakage current passing from the input side to the output side.
The load line graph shows that the peak drain voltage is around 55 V (i.e.;2Vdd-VKnee) and the
minimum voltage is about 2 V (i.e.; the knee voltage) and it is swinging around drain bias
voltage (i.e.; 28 V), the DC feeder has no losses. On the other hand, the current has peak value
around 10 A.
The resultant current and voltage waveforms are shown in Fig. 2.9. The two current peaks are
due to loop A in Fig. 2.8, and the asymmetry of the waveforms (rising and falling edges) is
due to loop B in Fig. 2.8. The current waveform has one dip caused by the linear region in the
I-V curve, this effect let us to call this class as an overdriven class AB [15].
The output load is shown in Fig 2.10 which has an impedance with almost zero imaginary part
at the fundamental frequency and zero impedance at all the higher harmonics.
The results of this simulation (i.e.; output power, gain, and efficiency) are shown in Table 2.1.
Table 2-1: Numerical Values for Class AB
RL [Ω]
6.4
Bias and Load setup
B1[S]
Vg [V]
Vdd [V]
-0.141
3
28
Pin [dBm]
25
η [%]
53.5
Results
Pout [W]
55
G [dB]
19.5
13
CH2:
Power Amplifier: Essentials and classes
MaxVds
time=640.0psec
ts(T1.vd)=54.67 V
60
MaxVds
MaxIds
time=1.240nsec
ts(T1.Id.i)=9.741 A
MaxIds
10
40
8
30
6
20
4
10
Ids [A]
Vds [V]
50
12
2
MinVds
0
0
0.0
0.2
0.4
0.6
0.8
MinVds
time=140.0psec
ts(T1.vd)=1.314 V
1.0
1.2
1.4
1.6
1.8
2.0
t [ns]
ZL [Ohm]
Figure 2-9: Voltage and Current Waveform for Class AB.
H
F
F
freq=1.000GHz
Gload[1::5]=0.231 / 168.033
impedance = 6.285 + j0.637
H
freq=3.000GHz
Gload[1::5]=0.999 / 179.983
impedance = 0.007 + j0.001
freq (1.000GHz to 5.000GHz)
Figure 2-10: Load impedances for the first five harmonics.
Comments
We could see that the efficiency is degrading from the maximum theoretical efficiency of
an ideal class AB. The major reasons are: the conduction angle is larger than π , and the
losses due to the knee region (Rds-on), overlapping waveforms due to the sinusoidal drainsource voltage and the epi layer resistance.
14
CH2:
Power Amplifier: Essentials and classes
2.3.2 Switch mode power amplifiers
Switch mode power amplifiers (SMPAs) in all have a great advantage over previous
classes in that they have 100% theoretical efficiency. They are called switch mode
because the transistor is used like a switch instead of a linear current source as in the
classes A, B, AB and C, and also because the current or the voltage waveforms have none
sinusoidal shape.
Active devices can be modeled as a switch in two different ways, see Fig 2.11. Each
model has its effect on the losses. In Fig. 2.11 (a), the losses are during the transition
from off to on states, when the capacitor is discharged. On the other hand, in Fig. 2.11
(b), the losses are during the transition from on to off states, when the inductor is
discharged. Both models need either zero voltage (across the switch) just before the
switch is closed (i.e.; for the model in Fig 2.11. (a)) and this referred to zero voltage
switching (ZVS), or zero current (through the switch) just before the switch is opened
(i.e.; for the model in Fig 2.11. (b)) in this case it is referred to zero current switching
(ZCS). Hence, one should take care of both transition states to reduce these losses as
much as possible.
L
L
T
T
C
R
C
R
(a)
(b)
Figure 2-11: Transistor model as Switch.
The next sections are a give discussion of the switch mode power amplifiers.
2.3.2.1
Class D power amplifier
The class D power amplifier (or voltage mode class D VMCD) is the only class which
requires two transistors working out of phase 180o. The circuit topology is shown in Fig.
2.12; the load network has a series resonant circuit to pass the current at the fundamental
frequency to the load and to block all other current components. Hence the voltage and
current waveforms are a square (odd component) and sinusoidal (even component)
waveforms, respectively, see Fig. 2.13.
15
CH2:
Power Amplifier: Essentials and classes
VDD
T1
L
C
IDS
+
T2
VDS
RL
Figure 2-12: Class D circuit topology.
2*Vdd-Vknee
Idmax
Current [A]
Voltage [V]
Current
Voltage
Vdd
Vknee
Idmax/2
0
T/2
T
Time
3T/2
0
2T
Figure 2-13: Class D voltage and current waveforms.
There is another class which is complementary to class D called D-1 (or current mode
class D CMCD). Its circuit topology could be as the circuit shown in Fig. 2.14. The class
D-1 load network has a parallel resonant circuit with the load to pass the fundamental
frequency and to short the odd harmonics. This topology allows the current to have
square waveform and the voltage sinusoidal waveform as shown in Fig. 2.15.
This class has an advantage over class D, in that it can tune out the transistor output
capacitance, which comes from grounding the source in both transistors, and include it as
a part of the resonant circuit. Therefore, we can still achieve high efficiency, but not
100% due to the knee region. Also, class D PA may exceed the breakdown voltage for T1
in Fig. 2.12 because its source terminal is not grounded
16
CH2:
Power Amplifier: Essentials and classes
VDD
R
L
C
0o
T1
180o
T2
Figure 2-14: Class D-1 circuit topology.
3.14*Vdd
Idmax
Current [A]
Voltage [V]
Current
Voltage
1.5*Vdd
Vknee
Idmax/2
0
T/2
T
Time
3T/2
0
2T
Figure 2-15: Class D-1 voltage and current waveforms.
Another reason of degrading the efficiency from the theoretical value is the transistor
output capacitance which is significant at high frequency, is large due to the size required
for the high output power application. The susceptance of the output capacitance is very
high for the high frequency and cannot be ignored (i.e.; Y=jB=jωCds).
Also another reason of not achieving the theoretical efficiency is that the transistors do
not work as ideal switches, which can be toggled between ON state and OFF state
instantaneously. Within the finite turn-on and turn-off time, the voltage and the current
overlap, and cause the transistor losses (switching loss). This drawback is addressed in
the time domain design and analysis in Class E amplifiers.
2.3.2.2
Class E power amplifier
The typical circuit topology of class E power amplifier is shown in Fig. 2.16. The load
network consists of series resonant circuit at the fundamental frequency and the
17
CH2:
Power Amplifier: Essentials and classes
fundamental load tuned slightly inductive. This inductive load reduces the slope of the
voltage waveform before the switch turns on. The ideal voltage and current waveforms
for class E (assuming square drive signal) are shown in Fig 2.17.
Class E has two main advantageous:
1. Soft switching which reduces the losses.
2. Simple circuit topology compared to other switching classes.
However, class E has disadvantages in that the drain voltage has high peak value due to
charging the large output capacitance, and the difficult to tune the output capacitance of
the transistor. Additionally, to achieve ZVS condition, all the current must go through
Cds//Lout when the switch turn off. The current limit is set by I= jωCdsVds. Hence, the class
E has limit tolerance for large transistor output capacitance Cds that degrades the
maximum operating frequency performance.
VDD
fo
+
Vds
RL
-
Figure 2-16: Class E Circuit Topology.
3.6*Vdd
Idmax
Current [A]
Voltage [V]
Current
Voltage
1.8*Vdd
Vknee
Idmax/2
0
T/2
T
Time
3T/2
Figure 2-17: Class E voltage and current waveforms.
18
0
2T
CH2:
2.3.2.3
Power Amplifier: Essentials and classes
Class F power amplifier
The class F power amplifier circuit is the most complex circuit among all the classes; it
needs at least three resonators (to control up to the fifth harmonics) to short out even and
to block the odd harmonics. The circuit topology is shown in Fig. 2.18. Class D is an
ideal case for class F, in which the current is a sinusoidal waveform and the voltage is a
square waveform.
VDD
f5
f3
+
fo
Vds
RL
-
Figure 2-18: Class F Circuit Topology.
As in class D, class F has a complementary circuit in which it blocks the even harmonics
and short out the odd ones. This class called F-1 and it is circuit topology is shown in Fig.
2.19. This class has similar waveform as the ones in class D-1. However, this class needs
lower drain bias voltage than any other classes for the same output power (since the
voltage waveform has higher peak than the square waveform i.e.; class F PA) and give
high efficiency with lower peak voltage than class E. Hence, the breakdown voltage will
not be exceeded in this class.
VDD
f4
f2
+
Vds
fo
RL
-
Figure 2-19: Class F-1 Circuit Topology.
19
CH2:
20
Power Amplifier: Essentials and classes
3 Class J power amplifier
In all the discussed switch mode classes there are some drawbacks for each one. Hence,
one should find a compromise to achieve all the advantageous of the classes. Class J
introduced recently in [15] combines the advantages of class E and F-1. However, this class
is introduced in some articles with different names but same operation like high frequency
class E in [18] and class E/F in [19].
3.1
Theory of operation
The class J power amplifier requires a slightly inductive load at the fundamental frequency
and only capacitive load at the second harmonic. The first requirement is similar to that one
in the class E power amplifier. However, class J try to make fast switching transitions
during the on and off state which reduces the losses and increases the efficiency, while in
class E the on transition switching has less losses than the off transition switching (for
sinusoidal drive signal).
On the other hand, class F-1 requires infinite number of resonators to achieve high
efficiency (but most of the work done by controlling up to the third harmonics), but class J
requires one resonator (to control the first harmonic).
Like any other classes, class J power amplifier can be single ended or push-pull. In
addition, it can be designed starting from any classic class of power amplifier.
3.2
Class J example
This example shows how to build class J PA starting from the example of class AB
discussed before (i.e.; fo=1 GHz, single ended topology).
A class J design can be done in three steps (summarized from [15]) stated below:
Step 1.
Voltage peaking.
The first starting step is to use the previous example of class AB and try to block
(ZL(2ωo)= ∞ ) the second harmonic. The efficiency increased from 53% to 63%
(about 10 %!!), see Table 3.1. The table shows that the power increased about 10
Watt, the gain increases and the power loss is reduced about 10 Watt. This
increment in the efficiency is because the transistor starts to act as a switch (the
voltage waveform have higher second harmonic). Fig. 3.1 shows the waveforms
for the current, voltage and instantaneous power between these cases, and Fig. 3.2
shows the voltage spectrum.
21
CH3:
Class J Power Amplifier
10
Class AB blocking 2nd H
Class AB
Ids [A]
8
6
4
2
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(a)
Voltage Waveforms
80
Class AB blocking 2nd H
Class AB
Vd [V]
60
40
20
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(b)
Instantaneous Power Losse
120
Inst_Power [W]
Vds [V]
100
Class AB blocking 2nd H
Class AB
80
60
40
20
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(c)
Figure 3-1: (a) Currents waveforms; (b) Voltage waveforms; (c) Instantaneous power
waveforms for step 1.
22
CH3:
Class J Power Amplifier
Table 3-1: Numerical results for Class J steps
Vpk [V]
Pout [w]
Gain [dB]
η [%]
Average
Dissipated
Power [w]
Class AB
55
55.6
22.45
54.3
46.78
Voltage peaking
62
65.7
23.18
63
38.68
Inductive Tuning
74
65.5
23.16
70.54
26.15
Class J
77
55.6
17.5
86
7.40
40
Class AB blocking 2nd H
Class AB
Vd [dBm]
[dBV]
20
0
-20
-40
-60
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Freq [GHz]
Figure 3-2: Voltage spectrum for step 1.
Step 2.
Tune the fundamental inductively.
The next step directly is to try to tune the fundamental load slightly more
inductive. Hence, high efficiency is achieved with same power in step 1. In Fig.
ZL [Ohm]
3.3 the first three harmonic loads are shown for this step and the previous one.
Third
Third
freq=3.000GHz
Gload[1::3]=0.999 / 179.995
impedance = 0.033 + j0.002
FunJ
Fun
SecJ
Sec
FunJ
freq=1.000GHz
ABJ2..Gload[1::3]=0.272 / 106.805
impedance = 37.588 + j21.164
Fun
freq=1.000GHz
Gload[1::3]=0.240 / 165.323
impedance = 6.195 + j0.799
SecJ
freq=2.000GHz
ABJ2..Gload[1::3]=0.894 / -114.953
impedance = 3.928 - j31.742
freq (1.000GHz to 3.000GHz)
Sec
freq=2.000GHz
Gload[1::3]=1.804 / -93.834
impedance = -5.014 - j8.008
Figure 3-3: Load impedances for the first three harmonics.
23
CH3:
Class J Power Amplifier
This step gives different shape for the drain current and reduces the dissipated
power, see Fig. 3.4. The peaks in the drain current don’t have the shape of the
peaks in class AB or the peaks gotten from the previous step; this due to the
load is inductive at the fundamental which makes the waveforms approach the
ZVS condition. The numerical results are shown in Table. 3.1 on page 23 .
10
Inductive Load
Class AB blocking 2nd H
Ids [A]
8
6
4
2
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(a)
Voltage Waveforms
80
Inductive Load
Class AB blocking 2nd H
Vd [V]
60
40
20
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(b)
Instantaneous Power Losse
Inst_Power
Vds [V] [W]
100
Inductive Load
Class AB blocking 2nd H
50
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(c)
Figure 3-4: (a) Currents waveforms; (b) Voltage waveforms; (c) Instantaneous power
waveforms for step 2.
24
CH3:
Step 3.
Class J Power Amplifier
Relative phasing – Class J
The last step is to try to adjust the relative phasing between the voltage and the
current for the second harmonic (in another way, make the second harmonic
load capacitive). In Table. 3.2, the phases for the first and the second harmonic
for step two and step three are shown ( ∠ Id- ∠ Vd). However, the relative
phasing is not purely capacitive for the second harmonic because the output
capacitor for the transistor is not linear which degrades the desired +90o phase
difference. The fundamental load impedance has a high positive phase (not
exactly -90o phase) and that is due to the real part is high compared to the
inductive part, see Fig. 3.5.
Table 3-2: Relative phases for all three steps.
Harmonics
Class AB
Relative Phase
( ∠ Id- ∠ Vd) [o]
Blocking Inductive
2nd Hr
Tuning
Class J
Fundamental
0.21
-275
-20
-30
2nd
-21
141.82
75.4
82
ZL [Ohm]
Fun
Fun
freq=1.000GHz
Gload[1::3]=0.389 / 90.806
impedance = 7.298 + j6.698
Snd
freq=2.000GHz
Gload[1::3]=0.947 / -124.450
impedance = 0.347 - j5.262
Snd
freq (1.000GHz to 3.000GHz)
Figure 3-5: The first three harmonics impedances.
25
CH3:
Class J Power Amplifier
Vd [V], Id [A]. (Fundamental)
Vd1
Id
Vd
Id1
-40
-30
-20
-10
0
10
20
30
40
(0.000 to 0.000)
Vd [V], Id [A]. (Second harmonic)
Vd1
indep(Vd1)=0
vd[1]=39.183 / 135.060
Id1
indep(Id1)=0
-Id.i[1]=3.329 / 105.080
Id2
-15
-10
-5
0
5
10
15
Vd2
(0.000 to 0.000)
Vd2
indep(Vd2)=0
vd[2]=12.331 / -84.743
Id2
indep(Id2)=0
-Id.i[2]=1.845 / -1.997
Figure 3-6: Phase graph for the drain voltage and current (a) fundamental, (b) 2nd harmonic.
In addition, two last modifications are done. The first is to reduce the gate bias voltage
this allows the current to have a low dip value (i.e., knee region) and minimum voltage
value during the ON/OFF-state, see Fig. 3.7 blue circles. The second modification is to
increase the driving power to achieve high efficiency with the maximum output power
rating, Table. 3.1 last raw on page 23. Fig. 3.8 (c), shows the instantaneous power loss.
The dashed area is the reduction in the losses achieved by class J which is about 40 W
(around 34%) loss reductions from class AB. However, the drain peak voltage increased
from 55 V in class AB to 77 V in class J, and the gain reduced about 5 dB from the gain
achieved in class AB.
26
CH3:
Class J Power Amplifier
Current Waveforms
10
Ids [A]
8
Class J
Class AB inductive+2nd H
6
4
2
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(a)
Voltage Waveforms
80
Vd [V]
60
Class J
Class AB inductive+2nd H
40
20
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(b)
Figure 3-7: (a) Current Waveforms; (b) Voltage Waveforms for step 3.
Figure 3-8: Instantaneous power waveforms for step 3.
27
CH3:
Class J Power Amplifier
Now, the class J design is complete and we can start analysis of its waveforms. The load
line graph is shown in Fig. 3.9, and it can be seen that the voltage has the minimum value
during the on-state which reduces the losses. Also, there is zero drain voltage at the dip of
the current, which means no lost power, see Fig. 3.10. However, the waveforms look like
class E and F-1!
Load Line Graph
12
10
Id [A]
8
6
4
2
0
0
10
20
30
40
50
60
70
80
Vd [V]
Figure 3-9: Load line for class J.
Current, Voltage, & Instantaneous Power Waveforms
Vmax
Imax
80
9
8
Voltage
Current
7 Inst_Power
60
6
50
5
40
4
30
Id [A]
Vd [V], Inst_Power [W]
70
3
20
2
10
1
0
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
t [ns]
Vmax
Imax
time=260.0psec time=580.0psec
ts(Id.i)=8.422 A ts(vd)=77.09 V
Figure 3-10: Voltage, current and instantaneous power waveforms for class J.
28
CH3:
3.3
Class J comparison with class E and F
Class J Power Amplifier
-1
The comparison will be taken in three different steps stated below. The circuit topologies
for class E and class F-1 is the same as the circuit shown in Fig 2.7 on page 12. The bias
setup and drive input power values are shown in Table 3.3 on page 32. The concern was
to compare these classes with class J for the same output power and same gate bias
voltage.
3.3.1 Load line comparison
The load lines of class J and F-1 are shown in Fig. 3.11. Class J has lower dip and bigger
loop at the knee region comparing to F-1. On the other hand, class J and E load lines are
shown in Fig. 3.12. Class J has smaller loop at the knee region, but not zero drain voltage
during turn on-state, on the contrary to class E (i.e.; ZVS). However, class E has higher
losses in the turn off-state (i.e.; since we are assuming sinusoidal gate drive instead of
rectangular). Hence, class J is a trade off in losses between the on-transition and the offtransition.
14
Class J
Class Finv
12
Id [A]
10
8
6
4
2
0
-2
0
10
20
30
40
50
60
70
80
Vd [V]
Figure 3-11: Class J and class F-1 load line.
14
Class J
Class E
12
Id [A]
10
8
6
4
2
0
-2
-10
0
10
20
30
40
50
60
70
80
90
Vd [V]
Figure 3-12: Class J and class E load line.
29
CH3:
Class J Power Amplifier
3.3.2 Voltage and current waveforms
The current waveforms for class J, class E and class F-1 are shown in Fig. 3.13 (a). Class
F-1 has a symmetrical current waveform which is almost square shaped (if the infinite
harmonics are controlled). Class E has longer OFF-state and higher peak current. On the
other hand, class J has two peaks and one dip (unlike class F-1 which is symmetrical). For
the voltages in each class we can find that class J is a middle case in the peak value with
respect to class E and class F-1, see Fig 3.13 (b).
12
Class J
Class E
Class Finv
10
Ids [A]
8
6
4
2
0
-2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
(a)
Vd [V]
Voltage Waveforms
90
80
70
60
50
40
30
20
10
0
Class J
Class E
Class Finv
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
t [ns]
Figure 3-13: Class J, class E and class F-1, (a) Current and (b) Voltage waveforms.
(b)
30
CH3:
Class J Power Amplifier
3.3.3 Losses in the three classes
It is worth to look at the losses in each of the three classes, see Fig. 3.14 and Table 3.3.
The blue dashed area in Fig. 3.14 is the reduction in loss in class J with respect to class E
and F-1 while the black dashed area is the increment loss. It is clear from these dashed
areas that class J has less loss than class E while almost the same loss as class F-1, see
Table 3.3.
(a)
(b)
Figure 3-14: Instantaneous power waveforms (a) between class J and class E (b) between
class J class and F-1.
31
CH3:
Class J Power Amplifier
Table 3-3: Numerical comparisons for class E, class J and class F-1.
Circuit setup
Classes*
Results
Vdd
Vgs
Pin
ZL
Vd(fo)
Vd(2fo)
Id(fo)
[V]
[V]
[dBm]
[V]
[V]
[V]
[A]
E
28
2.56
30
41.7
18.5
4.5
F-1
21
2.57
35
30.7
12.4
3.5
J
28
2.5
30
39.2
12.3
3.3
7.3
+j6.6
7.8
+j2.9
7.3
+j6.6
Id(2fo)/
Vpk
Vpk/Vdd
Pdc
η
G
Losses
[V]
[V]
[W]
[%]
[dB]
[W]
2.7
90
3.2
84
80.3
18.3
16.7
0.72
62
3
60
87.5
12.2
6.6
77
2.8
64.7
86
817.5
7.4
Id(3fo)
[A]
1.9/
1.3
*: All the classes designed for 50 W output power and more than 12 dB gain
3.4
Class J Pros. and Cons.
One can recognize some advantages of class J which motivate to choose it as a good
approach for high efficiency. Table. 3.4 summarize the main pros and cons of class J with
respect to class E and F-1.
Table 3-4: Comparison between class E, class J and class F-1.
Circuit topology
E
Easy (i.e.; need one
resonator) and could be
single ended or pushpull
Peak voltage
Very high
Losses
Highest losses (i.e.;
adjust ZVS condition)
Efficiency
Lowest
*: The comparison for class F
−1
J
Easy (i.e.; need one
resonator) and could
be single ended or
push-pull
Lower than class E
and higher than class
F-1
Small losses (i.e.;
trade off between
OFF and ON-state
transition )
High as the case in F-1
F-1
Very complex (i.e.; need
at least 5 resonator to
achieve high efficiency)
Low (i.e.; Doesn’t exceed
the break down voltage)*
Almost like class J losses
High as the case in J*
when controlling 5 harmonics
It can be concluded from Table. 3.4, class J is a trade off between class E and class F-1
and easier to implement that class F-1, which motivate the research to take class J as a
base-stone of the design strategy.
32
4 Design strategy
This chapter will describe in detail the design strategy; including the circuit model, and
the bondwire model.
It is obvious now from pervious chapters that any type of SMPA needs a resonator
circuit(s) to perform the waveform shaping. Class J PA requires one resonator to give an
inductive load for the fundamental and a capacitive load of appropriate size for the
second harmonic. Before we discuss the schematic, we should decide if either of the
single-ended or push-pull topologies should be used.
4.1
Single-ended and push-pull
4.1.1 Push-pull
A push-pull amplifier consists of an input 0o-180o power splitter driving two identical
devices in anti-phase and an 180o-0o output power combiner adding the output power of
the two devices in the amplifier load. These types of splitters/combiners, which are key
elements of the amplifier, are called BALUNS (BALanced to Unbalanced transformer).
They transform a balanced system that is symmetrical (equal in magnitude and opposite
in sign) with respect to ground to an unbalanced system with one grounded terminal. Note
that the microwave push- pull amplifier consists of two devices, each contributing half
the total power. Fig. 2.2 on page 9 shows the circuit topology.
4.1.2 Single-ended
The single-ended topology (see Fig. 2.2) uses one power amplifier. It doesn't need a
splitter at the input side, or a combiner at the output side which reduces the complexity
and loss of the circuits.
4.1.3 Advantages of single-ended push-pull topology
Table 4.1 shows the advantages and disadvantages of the single-ended and push-pull
power amplifiers.
.
33
CH4:
Design Strategy
Table 4-1: comparison between Single-ended and push-pull.
Comparisons points
Push-Pull
Single-Ended
Lower impedance ratio (for
double the impedance ratio the
Output Power and
matching impedance
output power is same as single
ended; while for four times
-
higher impedance ratio, the
output power is double of the
single ended).
Bandwidth
Higher BW due to the lower
impedance ratio.
The output current (i.e.;
Harmonic termination
balanced load current) doesn't
contain even harmonics [21].
Voltage peaking without
nd
2 harmonic resonator
Can use the output capacitance
in the resonator for class J
More complex since it requires
complexity
two transistors and
input/output BALUNs
Total Efficiency
Lower; since it uses balun for
the output.
Lower BW.
The output currents contains
all the harmonics
Need either small Cds like
GaN, or 2nd harmonic
resonator to tune Cds.
Simple circuit topology
(requires one transistor and
normal input/output
matching network)
higher
Push-pull topology gives a wider bandwidth, even harmonics filtering and could use the
output capacitance in the resonator. Hence, it is a good topology choice for class J (taking
in consideration to design low loss balun).
4.2
Idea
The goal of the project now is to build a one stage push-pull PA with maximum drain
efficiency and high gain at 2.14 GHz. The resonator is integrated inside the package using
the bondwire and capacitances. Several baluns will be studied to figure out a low loss
circuit compatible with the design. The input output PCB (printed circuit board) matching
networks will be designed for 50 Ω SMA connectors.
34
CH4:
4.3
Design Strategy
Circuit design and analysis
Designing a push-pull class J requires a parallel resonator to tune the output capacitance
Cds. The most straight forward topology is the one shown in Fig. 2.3 or Fig. 4.1. In this
topology Cds is used as a part of the resonator. The circuit can be modified by dividing the
shunt inductance, as it is shown in Fig. 4.2, for practical implementation inside the
package using bondwires. The capacitors Csh are necessary to block the DC-current
components.
T1
Cgs
Id1
Cg
Id2
Cd
Id1
Cds
Zpcb
Cgs
Ld
Cg
Ld
Cgd
Cgs
Cds
2Lsh
T2
T1
Ld
Cgd
T2
Id2
Cds
Lsh
Csh
Csh
Lsh
Ld
Cgd
Figure 4-1: Typical circuit for push-pull
Figure 4-2: Modified circuit for push-pull
topology including transistor model.
topology including transistor model.
The resonant current at the fundamental is the red path shown in Fig. 4.2. Moreover, the
differential load branch (Zpcb+jωLd) is invisible at the even harmonics due to the push pull
operation. Hence, it satisfies the second harmonic condition for class J (i.e.; capacitive
load which is Cds, assuming Ish(2fo) ≈ 0).
There are different types of resonators, each has different properties. The choice of the
resonator shown in Fig 4.2 is due to practical implementation. It can be open at the
fundamental (i.e.; Cds is not seen from the transistor). Equation 4.1 helps to find the
inductive value for Lsh. However, one may optimize this value to get the impedance level
that achieves high efficiency with maximum gain rating.
Lsh =
C sh - C ds
ω o2 C ds C sh
(4.1)
Finally, this circuit topology can be done either with discrete component or integrated
inside the package. The second choice could give further development to integrate the
in/out balun, and to use the integrated resonator on silicon substrate (i.e.; P7MI
technology). Moreover, it is easier to build this circuit integrated inside the package with
currently available tools, which still gives high efficiency in the simulator. Hence, Fig 4.2
is the motivated one for this work.
35
Zpcb
pc
b
CH4:
4.4
Design Strategy
Input matching circuit
The complete circuit of the package device with internal matching network is shown in
Fig 4.3. The input side includes two sections of low pass filter circuit to give a wider
bandwidth than a single section circuit since the impedance ratio per section is lower than
for the single section case. The design formula for matching network can be found in [15]
or [16]. Also it includes the pad capacitances for the input and output leads Cpg and Cpd,
respectively.
L2
Cpg
L1
Cgs
C1
Ld
Cgd
Id1
Cds
Lsh
Cpd
Csh
Csh
Cpg
Cgs
C1
L
Id2
Cds
Lsh
Cpd
L
Cgd
Ld
Figure 4-3: Full circuit model of the IC.
4.5
Bondwire: theory and design
Bondwires are used to connect any semiconductor device to the output world. For low
frequency the bondwire parasitics are negligible. However, at high frequency (i.e.;
microwave frequency) the bondwire parasitic cannot be neglected. A typical bondwire
model valid at high frequency is shown in Fig. 4.4. It is constructed from inductance and
series resistance with shunt capacitance on both sides. A typical inductive value is 1
nH/mm length of bondwire. However, the inductance does not reduce linearly with the
number of parallel bondwires, due to the mutual inductive coupling between the
bondwires, see Fig. 4.5. On the other hand, the capacitance increases linearly with the
number of bondwires, but usually it is neglected for small number of bond-wires at low
GHz frequency, because the surface area of the bond-wires is small.
Figure 4-4: Bond-wire, with its circuit model.
36
CH4:
Design Strategy
The bond-wire inductance can be calculated analytically or by simulation. The latter one
is used here because the bond-wire inductance in the resonator circuit is relatively small;
hence, the number of bond-wires will be large, which makes the analytical calculation
difficult. The simulation is done using Agilent ADS, Philips/Delft model [21]. This
model calculates the bond-wire inductance and mutual inductance between each set of
bond-wires. Also, it calculates the DC-resistance and AC-resistance. However, the
substrate losses are not included with this model, which reduces the quality factor
compared to what can be calculated from the model (i.e.; Q= ωL R ). The model does not
calculate the coupling capacitance between the bondwires and the coupling capacitance
between the bond-wires and the ground plane. Moreover, it does not calculate the
radiation losses, and neglect the current distribution due to the proximity effect (i.e.;
when two or more bondwires are located very close to each other) [21].
The self-inductances and mutual-inductances of the bond-wires are designed and included
in the circuit model for all bond-wire sets, see appendix B page 75 and 76.
1.4
1.2
L [nH]
1.0
0.8
0.6
0.4
0.2
0
2
4
6
8
10
12
14
No. of Bond-Wires
Figure 4-5: Inductance value vs. number of Bond-wires.
37
CH4:
38
Design Strategy
5 IN/OUT- PCB design
The IN-PCB (i.e.; BALUN, input matching and the DC-feeder) is critical for the input
impedance matching to achieve high gain, which in turn would mean the PAE will be
almost equal to the drain efficiency. The OUT-PCB is important to obtain the correct load
line giving high efficiency and the maximum power. Both parts (IN/OUT-PCB) contain
three sub networks; BALUN, matching network and DC-bias, see Fig 5.1. The transistor
package sub circuit is shown in Fig 4.3 on page 36. The topologies used for IN-PCB
network and OUT-PCB network are same. Also, the four DC-Bias networks have the
same topology.
DC-Gate
Bias
BALUN
Pin
INMatching
DC-Drain
Bias
Packaged
push-pull
OUTMatching
BALUN
Zload=50 Ω
Zo=50 Ω
DC-Gate
Bias
DC-Drain
Bias
Figure 5-1: Design Blocks.
5.1
BALUN Design
The BALUN is a three port device that splits the signal into two equal signals but with
180o difference in phase. However, it can also combine two signals which are 180o out of
phase. Before we go for the topologies discussion, it is good to discuss the impact of two
signals which are different in phase or in magnitude [22]. Fig 5.2 shows the typical pushpull amplifier with IN/OUT BALUN.
39
CH5:
IN/OUT-PCB Design
0o
IN
180o
180o
V1o
V1i
OUT
V2i
V2o
0o
Figure 5-2: Push-Pull topology with BALUN.
First let us find the output voltage when there is no phase or amplitude imbalance.
Assume
V1 = Acos(ωt ) , and
V2 =-A cos(ωt )
are inputs for the balance ports of the BALUN. Hence, the output is:
Vout = Acos(ωt ) + Acos(ωt )
Vout = 2 Acos(ωt )
(5.1)
Equation 5.1 represents the ideal output voltage from the BALUN.
1. Let us take the phase imbalance case:
Assume
V1 = Acos(ωt ) , and
V2 = Acos(ωt + ∆Φ )
are inputs for the balance ports of the BALUN. Hence, the output is:
Vout, P imbalance
Vout = Acos(ωt ) + Acos(ωt + ∆Φ )
Vout, P imbalance
Vout = A[cos(ωt ) + cos(ωt + ∆Φ )]
Vout, P imbalance
Vout = 2 Acos(
∆Φ
2ωt + ∆Φ
)cos(
)
2
2
(5.2)
Hence comparing equation 5.2 with equation 5.1, the loss1 will be:
∆Φ ⎤
⎡
Ploss
)
LP = ⎢cos(
2 ⎥⎦
⎣
1
2
(5.3)
The imbalance in phase or/and in amplitude lead to mismatch which may result in nonideal
(unequal splitting or combining) push-pull operation, and in the end degrades the performance.
40
CH5:
IN/OUT-PCB Design
2. Next, the amplitude imbalance case:
V1 = A1cos(ωt ) , and
V2 = A2 cos(ωt )
are inputs for the balance ports of the BALUN. Hence, the output is:
Vout, V imbalance
Vout = A1cos(ωt ) + A2 cos(ωt )
Vout, V imbalance
Vout = [A1 + A2 ]cos(ωt )
Vout, V imbalance
Vout = A1 [1 + A2 A1 ]cos(ωt )
(5.4)
comparing equation 5.4 with equation 5.1, the loss will be:
Ploss
LV = [A2 A1 ]
(5.5)
2
For microwave frequencies it is difficult to measure the amplitude of a signal, hence,
equation 5.3 and 5.5 could be converted to S-parameters for simplicity during the
simulation and the measurements.
From [10] S-parameters could be calculated by:
Sij =
Vi −
V j+
(5.6)
Vk+ = 0 for K ≠ j
where positive sign and negative sign represent the incident and the reflected waves.
For the phase difference
∆Φ = 180 − abs(phase( S 31 ) − phase( S 21 ))
(5.7)
where, port 1 represent the unbalanced port, and port 2 and port 3 represent the balanced
ports.
For the amplitude ratio
A2 / A1 = S 31 / S 21
(5.7)
Now we can use equation 5.3 and 5.5 with the new values of ∆Φ and A2 / A1 .
Fig 5.3 and Fig 5.4, show the power loss represented in equation 5.3 & equation 5.5,
respectively. The power loss due to the phase imbalance can be neglected for more than
5o. On the other hand, power loss due to the amplitude imbalance is critical even for small
imbalance amplitudes. Hence, the design should consider the amplitude balance as an
important issue.
41
CH5:
IN/OUT-PCB Design
p
0
-0.05
Power Loss [dB]
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
0
5
10
15
20
Phase imbalance [Degree]
25
30
Figure 5-3: Power loss due to phase imbalance.
0
-0.2
-0.4
Power Loss [dB]
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Amplitude imbalance [dB]
0.8
0.9
1
Figure 5-4: Power loss due to amplitude imbalance.
5.1.1 BALUN Topologies
There are a huge number of balun circuits, each of which has different topology and
concerns. One can classify the balun circuits into two categories, lumped element balun
as in [23], [24] and [25], and microstrip balun as in [26], [27], [28], and [29]. The lumped
element balun s are good choice for the low power while in high power, the losses (due to
low quality factor for the coil) are high, which in turn reduce the efficiency. Hence, the
lumped element is a good choice for the input side but not for the output side. Moreover,
it can achieve quite good bandwidth and can have impedance transformation.
42
CH5:
IN/OUT-PCB Design
The microstrip baluns have very small losses which don’t affect the overall efficiency of
the system, but it needs two metal layers as in [26] or larger size as in [29]. Its bandwidth
is not large as the lumped baluns. Moreover, it can have impedance transformation.
To cancel the effect of the imbalance in phase from the in-balun, the out-balun should be
same as the in-balun. The two layer microstrip baluns were excluded because the
unavailability of such kind of substrate for this design. So, the design decision directed to
N section-half wavelength balun [29]. There are some kind of balun that requires one
layer but high dielectric substrate like in [30] and [31], because it is uses the microstrip
coupling (i.e.; 3 dB coupling). These were also excluded.
5.1.2 N-half wavelength balun
Fig 5.5 shows the topology of N-half wavelength balun. It is N-sections of half
wavelength resonators connected by λ/4. As the sections number increases the bandwidth
increases. The half wavelength resonator achieves 180o phase difference while the quarter
wavelength achieves the matching between the ports (e.g.; 50 Ω unbalanced port to 100 Ω
balanced port).
Unbalanced
Input 1
n
λ/4
n-1
n-2
1
2
Balanced
50 Ω
λ/2
Figure 5-5: N-Half wavelength balun.
Output
100 Ω
3
A N=2-half wavelength balun was simulated and the section widths were optimized to
achieve good results fitting the PA design. The balun impedance transformation ratio is
1:2 (50Ω unbalanced port to 100 Ω balanced ports). The simulated S-parameters are
shown in Fig 5.6 and 5.7, both figures show good bandwidth and match. The input match
at the unbalanced port (i.e.; S11) is less than - 30 dB at the center frequency, and the input
match at the balance port (i.e.; S22 and S33) are 6 dB.
The transmission S-parameters show a good splitting/combining result for 0.4 GHz
bandwidth (i.e.; S31 is between -3 dB and -2.7 dB while S21 is between -3 dB and -3.2 dB,
both for bandwidth 2 GHz- 2.4 GHz)
43
CH5:
IN/OUT-PCB Design
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
dB(S(3,3))
dB(S(2,2))
dB(S(1,1))
0
-50
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
freq, GHz
Figure 5-6: Reflection coefficients for BALUN ports.
0
dB(S(3,1))
dB(S(2,1))
-10
-20
-30
-40
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
freq, GHz
Figure 5-7: Transmission coefficients for BALUN ports.
The power loss due to phase imbalance is shown in Fig 5.8 (Blue) while the phase
difference is in red. As it can be seen the losses is negligible over very wide range. The
loss is less than 0.1 dB between 1.7 GHz and 2.5 GHz.
On the other hand, the power loss due to amplitude imbalance is shown in Fig 5.9 (Blue)
while the amplitude ratio is in red. The loss is less than 0.1 dB between 2.1 GHz and 2.2
GHz. These losses can be handled for our bandwidth design (2.11-2.14 GHz) without
harming the efficiency too much. The schematic of the BALUN is shown in Appendix B,
page 73.
44
CH5:
IN/OUT-PCB Design
0
-50
100
-100
0
-150
-100
P_Loss [dB]
Delta_Phi [Degree]
200
-200
-200
-250
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
25
0.0
20
-0.2
15
-0.4
10
-0.6
5
P_Loss [dB]
Delta_Phi [Degree]
freq, GHz
-0.8
0
-5
-1.0
1.5
1.7
1.9
2.1
2.3
2.5
freq, GHz
40
20
30
0
20
-20
10
-40
0
-60
-10
P_Loss [dB]
Amplitude Imbalance [dB]
Figure 5-8: Phase difference imbalance and its corresponding power loss over the frequency.
-80
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
0
16
-5
12
-10
8
-15
4
-20
0
P_Loss [dB]
Amplitude Imbalance [dB]
freq, GHz
-25
1.5
1.7
1.9
2.1
2.3
2.5
freq, GHz
Figure 5-9: Amplitude difference imbalance and its corresponding power loss over the
frequency.
45
CH5:
5.2
IN/OUT-PCB Design
PCB IN/OUT matching network
The matching network for both input and output sides uses 50 Ω transmission lines with
shunt capacitances. This has been chosen in case tuning is needed (after the fabrication)
to optimize the gain and efficiency of the power amplifier. Moreover, the package lead is
modeled as a transition of transmission lines before connecting them to the matching
network. In Appendix B, the schematic of the IN/OUT matching network is presented.
5.3
DC-Bias network
DC-bias network is the same for the drain and the gate. A λ/4 transmission line (DCfeeder) with shunt capacitor (combination is an open circuit for RF-signal) is used for the
biasing network. Simply, one can tune the position of the shunt capacitor to get good
matching at the lead of the IC, see Appendix B for the DC-bias network schematic.
Now, all the blocks presented in Fig. 5.1 (The layout is shown in Appendix B, page 77)
are completed and ready to be assembled together and find the total efficiency and to
investigate where the major part of losses occurs.
46
6 Simulation, measurements and discussions
The simulations with details of the losses are discussed. Also, the measurements of the
fabricated power transistor and PCB are included with some discussions.
6.1
Simulation and results
The load line is shown in Fig 6.1, while the current voltage and instantaneous power
waveforms are shown in Fig 6.2 for Pout=34.3 W (Pin=29.7 dBm). The loss due to the
current-voltage overlapping (i.e.; switching loss) is 9 W. This loss is due to the onresistance and the resonator circuit.
4.0
3.5
3.0
I
Ad [A]
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0
10
20
30
40
50
60
70
Vd [V]
Figure 6-1: Load line graph for the designed PA.
Max Vd
Max Vd
Figure 6-2: Voltage, current and instantaneous power waveforms for the designed PA.
47
CH6:
Simulation, Measurements and discussions
The first three harmonics load impedances are shown in Fig 6.3. It is obvious from this
figure that the fundamental impedance is slightly inductive and the second harmonic load
impedance is capacitive, which satisfies class J PA. The nonlinear capacitance (i.e.; Cds)
supplies the transistor with the current for the second harmonic (Id(fo)<0 while Id(2fo)>0),
which make the second harmonic impedance negative. Table 6.1, presents some
important numerical values for this design. Table 6.2 presents the latest published SMPA
for Si-LDMOS technology above 1 GHz.
Z [Ohm]
Fund
Thrd
Snd
Fund
freq=2.140GHz
Gload2[i2,1::3]=0.283 / 165.454
impedance = 28.284 + j4.362
Snd
freq=4.280GHz
Gload2[i2,1::3]=1.403 / -147.132
impedance = -9.102 - j14.297
Thrd
freq=6.420GHz
Gload2[i2,1::3]=0.958 / -173.894
impedance = 1.074 - j2.666
freq (2.140GHz to 6.420GHz)
Figure 6-3: The first three harmonics for PA.
Table 6-1: The numerical results of the designed PA after each node.
Directly,
After the die
On the lead (after
the resonator)
Final
result
η [%]
76.4
73.4
70
Pout [W]
40.6
39
34.3
Gain [dB]
16.4
16.2
16.3
PAE [%]
75.2
72.3
69
Table 6.1, needs some investigation of where the major losses occurs. The resonator
efficiency and the OUT-PCB efficiency are 96.1% and 96.2%, respectively. Hence, the
major losses occur in the transistor mainly due to the switching loss since only a finite
number of harmonics can be controlled. Fig 6.4 shows a pie chart losses in the entire
design elements. Switching loss is the major loss, after that the resonator loss is the
second largest loss (i.e.; Lsh and Repi); this is mainly due to the shunt conductor (Lsh)
which supply the capacitance Cds with a relatively large current (i.e.; 4.5 A passing in the
48
CH6:
Simulation, Measurements and discussions
shunt inductor branch and 1.2 A passing to the load). Table 6.3 represents the values in
the chart.
Table 6-2: The recent published SMPAs for LDMOS technology*.
Author / Year**
Class
Frequency [GHz]
η [%]
Gain
Pout [W]
[dB]
A. Ådahl/2003
[32]
E
1
75
10
13
F. Wang/2004
[33]
E/F
1.1
72
60
14
K. Ji-yeon/2005
[34]
CMCD
1.8
68
60
15
F. Lẻpine/2005
[35]
F-1
1
81
15
13.7
F. Lẻpine/2005
[35]
F-1
1.8
62
15
10
H. M. Nemati/2006
[36]
CMCD
1
78
20
13
A. Al Tanany/2007
[This work]
D/J
2.14
70
34
16.4
*: The values are taken from the simulated result.
**: This Table is taken from [36] with focusing on the paper above 1 GHz.
Pout
Psw
Prepi
Plsh
Plead
Pbalun
Poutmatch
Prepi
22%
Pout
71%
Losses
29%
Plsh
9.4%
Plead
1.3%
Psw
57.9%
Pbalun
5.1%
Poutmatch
4.3%
Figure 6-4: Chart represents the loss in every block in the designed PA.
49
CH6:
Simulation, Measurements and discussions
Table 6-3: Power distributions over all elements design.
Power Parameters
Percentage
Percentage
Absoulute
(with respect to
(with respect
Power
the input DC
to the total
[W]
power)
power loss)
[%]
[%]
Pout
36
71.0
Pswitching
9.1
18.2
57.9
PRepi
3.4
6.9
22
PLsh
1.4
3
9.4
0.2
0.4
1.3
Pbalun
0.8
1.6
5.1
Pout-match
0.68
1.3
4.3
≈ 50
≈ 100
100
Output
Respnator
Loss
Dissipated
PLd
PCB Loss
Total
The plot of the dissipated power (Percentage with respect to the total power loss) over the
drive signal is shown in Fig. 6.5. From this figure we can classify PA operation into three
regions. When the drive signal is small, the transistor does not produce output current
because the gate voltage is less than the threshold voltage, hence, the major loss is the
switching loss (i.e.; current voltage overlapping waveform), Fig 6.5 (a) for this region the
PA does not work as SMPA (i.e., it performs like class C PA). On the other hand, when
the drive signal increases (i.e.; The transistor works like current source) the switching loss
decreases and the resonator loss start to increases due to the large current passing through
the shunt branch and through the Cds-Repi branch. Also, the PCB loss increases because
the current passing to the load increases. When the drive input signal becomes very large
the PA start to work in the saturation region (i.e.; passing the compression point), hence,
the dissipated power does not increase from all the elements except the losses in epi layer.
To find out why the losses in epi layer increases after the compression point, one should
see the losses for all the harmonics in this layer, see Fig 6.6.
50
CH6:
Simulation, Measurements and discussions
2x
2x
(a)
(b)
(c)
Figure 6-5: (a) switching power loss and the total output power, (b) package and resonator
elements power loss, and (c) PCB loss.
The losses (in epi layer) are small for the low input power, however, when the power
increases the current passing through epi layer increases and the losses increases also.
For higher input power the resonator start to work (i.e.; because the nonlinear capacitor
getting closer to the value used in the design), hence, the blocked harmonic (i.e.; 2nd
harmonic) current increases which increase the losses in epi layer. When the compressed
51
CH6:
Simulation, Measurements and discussions
point is reached, the second harmonic losses start to decrease because the second
harmonic’s drain current decreases see Fig. 6.7. On the other hand, the fundamental loss
increases because the drain voltage and the epi layer current increases with very slow rate
as the output power increases also with very small rate, see Fig. 6.7.
Figure 6-6: Power loss in Repi for the first three harmonics.
Figure 6-7: current and voltage curves and output power.
The efficiencies stated in Table 6.1 over the output power with sweeping the input power
are shown in Fig 6.8. The losses due to the resonator and the OUT-PCB increases with
increasing output power. From Fig 6.9 that the efficiency of the resonator changes
slightly with the output power due to the large variation in the current passing through the
shunt inductance, while the OUT-PCB are almost constant over the output power.
52
CH6:
Simulation, Measurements and discussions
Figure 6-8: The efficiency over the output power after each node and the gain over the
Eta_resonator & Eta_OUT-PCB [%]
output power.
100
98
96
94
92
90
0
5
10
15
20
25
30
35
40
Pout [W]
Figure 6-9: The efficiency of the resonator and the BALUN.
Another important issue is the bandwidth i.e.; the efficiency, power added efficiency,
output power and gain over the frequency, shown in Fig 6.10. The figure is at 29 dBm
input power. The bandwidth looks good for 2.14 GHz band in term of efficiency, power
and gain. E.g., the efficiency is higher than 69 % over the entire band (at the center
frequency about 70 %), while the output power is higher than 32.5 W for the entire band.
One important parameter is the gain flatness. From Fig 6.10 the gain flatness is about 0.4
dB.
53
CH6:
Simulation, Measurements and discussions
Figure 6-10: Efficiency, PAE, Gain and output power over the frequency.
6.2
Stability check
Before manufacturing the IC and the IN/OUT-PCB, one should check the stability of the
overall design. There are different ways to check the stability found in many textbooks
like [10]. Rollet’s condition, ∆-K check, is the test used here, where the device is
unconditionally stable if both of Equation 6.1 and Equation 6.2 are satisfied.
2
K=
2
1 − S11 − S 22 + ∆
2 S12 S 21
2
>1
∆ = S11 S 22 − S12 S 21 < 1
(6.1)
(6.2)
These conditions are plotted in Fig 6.11 from DC to 10 GHz and shows that both
conditions are satisfied (Note that K factor is in dBm to give a good representation). The
bias point was Vgs=2.65 V, and the small signal gain was G=18.8 dB.
54
CH6:
Simulation, Measurements and discussions
minK
freq=2.810GHz
dbm(K)=-0.767
1.0
250
200
0.8
150
Delta
100
0.4
Delta
K
minK
0.2
K [dBm]
0.6
50
0
-50
0.0
0
2
4
6
8
10
Freq [GHz]
minK
freq=2.810GHz
dbm(K)=-0.767
1.0
15
10
0.8
5
Delta
minK
0
0.4
K [dBm]
0.6
-5
0.2
-10
-15
0.0
0
2
4
6
8
10
Freq [GHz]
Figure 6-11: (a) Stability factors for the design and (b) zoom in for K factor.
55
CH6:
6.3
Simulation, Measurements and discussions
Measurements
The first measurement done was far away from the simulated result. Hence, each part of
the PCB (i.e.; input and output matching, balun and whole input and output PCB) was
measured using GS probing and was compared to the simulated result. Fig 6.12 and Fig
6.13 show that the measurement for the whole output PCB fits the simulated results. Fig
6.14 shows the block diagram of the measurement setup.
Figure 6-12: The real part of the differential impedance of the whole output PCB.
56
CH6:
Simulation, Measurements and discussions
Figure 6-13: The imaginary part of the differential impedance of the whole output PCB.
DC-Gate
Bias
DC-Drain
Bias
Port 1
BALUN
Pin
Packaged
INZd=Z11+Z22-Z12-Z21
Matching
push-pull
Zo=50 Ω
OUTMatching
BALUN
Zload=50 Ω
Port 2
DC-Gate
Bias
DC-Drain
Bias
Figure 6-14: The measurement setup of the output PCB.
57
CH6:
Simulation, Measurements and discussions
Fig 6.15 and Fig 6.16 show the differential impedance for simulated model and the
measurement result of the input PCB. The measurement showed good agreement with the
model. The measurement setup for the input PCB is shown in Fig 6.17.
Figure 6-15: The real part of the differential impedance of the whole input PCB.
58
CH6:
Simulation, Measurements and discussions
Figure 6-16: The imaginary part of the differential impedance of the whole input PCB.
DC-Gate
Bias
DC-Drain
Bias
Port 1
BALUN
Pin
INMatching
Zo=50 Ω
Packaged
push-pull
Zd=Z11
+Z22-Z12-Z21
OUTBALUN
Matching
Port 2
DC-Gate
Bias
DC-Drain
Bias
Figure 6-17: The measurement setup of the output PCB.
59
Zload=50 Ω
CH6:
Simulation, Measurements and discussions
6.3.1 Package model
The packaged circuit was measured by GS probing machine for different bias points.
ADS model was created to fit the measured data. The output package model that fits the
measurement has higher losses than the expected from the simulation and lower value for
Lsh. The output leads of the package force the Lsh bondwires set to be mounted on the
middle part of the Csh, hence, a resistance was added to the Csh model. This resistance
increases the losses in this branch which having the largest current. The new model and
the measurement are shown in Fig 6.18.
(a)
(b)
(c)
Figure 6-18: The measured impedance for one lead at the output side of the package, (a) real
part, (b) imaginary part, and (c) the phase.
60
CH6:
Simulation, Measurements and discussions
Another measurement was done for the input side of the package and new ADS model
was created to fit the measurement data. The ordered capacitance die at the input of the
package was unavailable at the time of the fabrication, a new capacitance die having close
value to the required one but longer length was replaced. Hence, a new model for this die
was modeled. The measurement and the new model of the package are shown in Fig 6.19
(a)
(b)
(c)
Figure 6-19: The measured impedance for one lead at the input side of the package, (a) real
part, (b) imaginary part, and (c) the phase.
61
CH6:
Simulation, Measurements and discussions
The package model was done without changing any parameter from the die model.
However, the losses in the resonator part are from Repi and Lsh but when the package was
modeled, the extra losses were included in the Lsh branch. Hence with more advanced
measurement technique one can verify that whether the die model is accurate. As it was
stated before, the die model is accurate enough for the first evaluation of the device.
Moreover the die model was used previously in many designs and showed good
agreement with the measured result.
62
7 Comparison and Future Work
This work was extended to compare it with lower frequency and the same topology
following the design and the concepts stated before but since there was no intent to
fabricate a device for lower frequency, there was no need to design the IN/OUT-PCB
circuit.
7.1
Comparison with 0.94 GHz
The same idea was designed at 0.94 GHz, where the results were very promising and one
can fabricate it. The load line and the waveforms are shown in Fig 7.1 and Fig 7.2,
respectively. The loss due to the switching loss is 4.56 W. This loss is 1/2 of the loss at
2.14 GHz; the reason is because the ratio of charging-discharging time (i.e.; time
constant) of Cds compared to the 0.94 GHz period is less than the same ratio to the 2.14
GHz period. Hence, the overlapping time is less.
4
Id [A]
3
2
1
0
-1
0
10
20
30
40
50
60
70
80
Vd [V]
Figure 7-1: Load line graph for 0.94 GHz design.
Figure 7-2: Voltage, current and instantaneous power waveforms for 0.92 GHz design.
63
CH7:
Comparison, Conclusion and future work
The efficiency, output power and gain versus the frequency are shown in Fig 7.3. This
figure represents a good bandwidth for this design for 0.94 GHz band, where the
efficiency is higher than 80% at the center frequency, power is larger than 30 W (between
0.88-1.02 GHz) and the gain flatness is about 0.3 dB for the same bandwidth
Figure 7-3: Efficiency, PAE, Output power and gain over the frequency.
The efficiency at the transistor die and at the lead versus the output power (sweeping the
input power) is shown in Fig 7.4, where the efficiency of the resonator is about 94 %
which is less than the resonator efficiency at 2.14 GHz. However, this efficiency can be
increased if an integrated BALUN is designed and optimized to achieve high output
efficiency. Also, this figure shows the gain versus the output power. Table 7.1 represents
numerical results at 0.94 GHz design.
64
CH7:
Comparison, Conclusion and future work
90
23
80
22
60
21
50
40
Gain [dB]
Eta [%]
70
20
30
20
19
0
5
10
15
20
25
30
35
40
Pout [W]
Figure 7-4: The efficiency after each node and the gain over the output power.
Table 7-1: Numerical result for 0.94 GHz after each node in the design.
7.2
Directly,
After the die
On the lead (after
the resonator)
η [%]
88.50
83.01
Pout [W]
34.32
32.19
Gain [dB]
15.66
15.38
PAE [%]
86.10
80.61
Conclusion
Designing for high power, efficiency, and good flatness require a lot of knowledge in
devices, CAD-modeling, and PA concepts. This work was able to show by simulation that
Si-LDMOS can achieve more than 70 % drain efficiency at 2 GHz. However, due to the
parasitic in Si-LDMOS, there was a lot of loss at the die output. The class J could be a
promising candidate to achieve the highest efficiency in PA base station.
However, the measured result degrades from the simulated one. This mainly due to the
uneven distribution of the bondwires mounted on the capacitance dies. Also, probably the
coupling factor is larger than the simulated result which degrades the gain performance.
Another design was done at lower frequency and it showed very high efficiency when
compared to any published design for the same technology and the same frequency. This
65
CH7:
Comparison, Conclusion and future work
shows that the push-pull topology, class J PA, and LDMOS technology are very
promising for high efficiency PA applications at 1 GHz.
7.3
Future work
The following points discuss the suitable future work that could be done afterwards.
•
Advanced measurment technieque
An IR camera could be used to see the power loss distribution in the package. This
will verify the new ADS model for the package (specially the loss). Another
measurement could be done to find the mutual coupling between all the bondwires.
•
Redesign the Package
The measurement could be done with new design of the package with careful choice
for the capacitance dies dimension. Also, one could try to distribute the bondwires
set evenly on the mounted die to reduce the associated loss.
•
BALUN Integration
One could work more and develop the IN/OUT BALUN inside the transistor
package. There are different process technologies for high Q passives; one of them
is Infineon's P7MI.
•
Modulator circuit and architecture.
Measure the device with different modulator circuits and study which architecture
could be suitable and what can be done to improve this design for different kind of
modulation scheme.
•
Si-LDMOS development.
The efficiency degradation was mainly due to the parasitics of Si-LDMOS. Hence,
to reduce these losses one could do more development on the Si-LDMOS process to
reduce these parasitic effects.
•
Other Device technology.
The evaluation of wide band gap technology and some published paper like [1] and
[14] that used these technologies as SMPAs, motivate the research to study this
topology on these devices, mainly because of the low parasitics, and high
breakdown voltage of these devices.
•
Memory effect and linearization
One should study the memory effect from this topology and this class to investigate
the algorithm techniques needed for the linearization, which is not less important
than the efficiency for the base station. Hence, the work may be extended to figure
out the linearization needed and which application fit this work.
66
References
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A. Long, J. Yao, and S. I. Long, “A 13 W current mode class D high efficiency
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[4]
S. D. Kee, I. Aoki, and D. Rutledge, “7-MHz, 1.1-kW demonstration of the new
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[5]
S. D. Kee, I. Aoki, A. Hajimiri, and D. Rutledge, “The class-E/F family of ZVS
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[6]
F. Bohn, S. D. Kee, and A. Hajimiri, “Demonstration of a harmonictuned class
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[7]
T-P Hung, A. G. Metzger, P. J. Zampardi, M. Iwamoto and P. M. Asbeck,
“High Efficiency Current-Mode Class-D Amplifier with Integrated Resonator”,
IEEE-MTT-S Digest, 2004.
[8]
A Syed, “Large Signal Physical Simulations of Si LD-MOS transistor for RF
application”, Dept of Physics, Chemistry and Biology, Linköping University,
2004.
[9]
Ma, G.; Qiang Chen; Tornblad, O.; Tao Wei; Ahrens, C.; Gerlach, R. “High
frequency power LDMOS technologies for base station applications status,
potential, and benchmarking” IEEE IEDM Technical Digest, 2005.
[10] M. Miller, T. Dinh, and E. Shumate, “A new empirical large signal model for
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[11] Angelov, N. Rorsman, J. Stenarson, M. Garcia, and H. Zirath, “An empirical
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Frequency Electronics, Oct & Nov 2004.
[13] Y. Yang,Y. Y. Woo, J. Yi, and B. Kim, “A New Empirical Large-Signal Model
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Microwave Theory and Tech, vol. 49, NO. 9, Sept 2001.
[14] O. Tornblad, C. Blair, “An electrothermal BSIM3 model for large-signal
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[15] S.C. Cripps, “RF Power Amplifiers for Wireless Communications”, Second
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[16] D. Pozar, “Microwave Engineering”, Third Edition, Danver MA, USA Wily,
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[17] R. Gilmore, L. Besser, “Practical RF Circuit Design for Modern Wireless
Systems Vol. 2: Active Circuits and Systems”, Artech House, USA, 2006.
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B. Nauwelaers, “High Frequency Class E Design Methodologies”, IEEE
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[20] U. Gustavsson, “Design of an Inverse Class D Amplifier Using GaN-HEMT
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[21] Agilent ADS manual 2006.
[22] G. Bouisse, “Design for balun integration in RF LDMOS” adopted on Sept 21,
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Issue , 7-12 Jun 1998 Page(s):777 – 780
[27] King-Chun Tsai Gray, P.R “1.9GHz 1W CMOS class E power amplifier for
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[30] W. M. Fathelbab, M. B. Steer, ”Distributed biasing of differential RF circuits”
IEEE Transactions on Microwave Theory and Techniques, vol. 52, Issue 5, May
2004 Page(s): 1565 – 1572.
[31] K. S. Ang, Y. C. Leong, C. H. Lee, “Impedance-transforming, coupled-line
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International Microwave Symposium Digest, 2003, vol. 2, Issue , 8-13 June
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[32] Adahl, H. Zirath, "An 1 GHz class E LDMOS power amplifier," 33rd European
Microwave Conference, Vol. 1, Page(s):285 - 288, Oct. 2003.
[33] F. Wang, D. B. Rutledge, "A 60 W L-band Class-E/FOdd2 LDMOS Power
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[34] K. Ji-Yeon, H. Dong-Hoon, K. Jong-Heon, S. P. Stapleton, "A 50 W LDMOS
current mode 1800 MHz class-D power amplifier," International Microwave
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[35] F. Lepine, A. Adahl, H. Zirath, "L-band LDMOS power amplifiers based on an
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References
70
Appendix A.
Package Chip
(b)
(a)
Figure A-1: Bonding diagram; (a) Side view, (b) Top view.
71
Appendix A:
Package Chip
Figure A-2: Photo of the fabricated Push-pull LDMOS transistor.
72
Appendix B.
PCB Schematics
MTEE_ADS
Tee1
Subst="MSub1"
W1=1.685540 mm
W2=w3 mm
W3=w2 mm
Port
P1
Num=1
MLIN
TL5
Subst="MSub1"
W=1.685540 mm
L=2.5 mm {t}
MSOBND_MDS
Bend4
Subst="MSub1"
W=w2 mm
MLIN
TL1
Subst="MSub1"
W=w3 mm
L=L1 mm
MTEE_ADS
MLIN
Tee2
Subst="MSub1" TL6
Subst="MSub1"
W1=w3 mm
W=1.685540 mm
W2=1.685540 mm
L=2.5 mm
W3=w3 mm
MLIN
TL3
Subst="MSub1"
W=w2 mm
L=L2 mm
MLIN
TL2
Subst="MSub1"
W=w1 mm
L=L1 mm
Port
P2
Num=2
MLIN
TL4
Subst="MSub1"
W=w3 mm
L=L2 mm
MTEE_ADS
Tee3
Subst="MSub1"
W1=1.68554 mm
W2=w1 mm
W3=w3 mm
MLIN
TL7
Subst="MSub1"
W=1.685540 mm
L=2.5 mm
Port
P3
Num=3
Figure B-1: Schematic of the IN/OUT BALUN.
Momentum model of
a coupled taper TL
Port
P3
Num=3
Port
P1
Num=1
Port
MACLIN
P2
CLin6
Num=2 Subst="MSub1"
W1=1.7 mm
W2=1.7 mm
S=2.1 mm
L=3.5 mm
MTEE_ADS
Tee7
Subst="MSub1"
W1=1.7 mm
W2=1.7 mm
W3=wb mm
MTEE_ADS
Tee8
Subst="MSub1"
W1=1.7 mm
W2=1.7 mm
W3=wb mm
Port
P4
Num=4
MTEE_ADS
Tee1
Subst="MSub1"
W1=w mm
W2=w mm
W3=w0603 mm
MLIN
TL3
Subst="MSub1"
W=w0603 mm
L=0.1 mm
SMTcap_0603
C12
S4P
MCLIN
SNP1
CLin4
r=0.1 Ohm
File="/home/altanany/adswork3/smpa_thesis_prj/data/coupled_taper_mom_a.ds"
Subst="MSub1"
l=0.15 nH
W=w mm
c=c1 pF
SMTcap_0603
S=s mm
C16
L=l1 mm
r=0.1 Ohm
l=0.15 nH
c=c1 pF
MLIN
TL4
Subst="MSub1"
W=w0603 mm
L=0.1 mm
4
1
DC-Blocking
capacitor
MSTEP
Step1
Subst="MSub1"
W1=w mm
W2=w0603 mm
MLIN
TL5
Subst="MSub1"
W=w0603 mm
L=0.1 mm
SMTcap_0603
C14
r=0.1 Ohm
l=0.15 nH
c=c2 pF
MCORN
Corn3
Subst="MSub1"
W=w mm
Port
P5
Num=5
MLIN
TL1
Subst="MSub1"
W=w mm
L=l2 mm
MLIN
TL7
Subst="MSub1"
W=w0603 mm
L=0.1 mm
MCORN
MSTEP
Corn1
Step3
Subst="MSub1"
Subst="MSub1"
W=w mm
W1=w mm
W2=w0603 mm
2
3
Ref
MCLIN
MSTEP
CLin5
Step2
Subst="MSub1"
Subst="MSub1"
W=w mm W1=w mm
S=s mm
W2=w0603 mm
L=(10-l1) mm
MLIN
TL6
Subst="MSub1"
W=w0603 mm
L=0.1 mm
SMTcap_0603
MLIN
C15
TL8
r=0.1 Ohm Subst="MSub1"
l=0.15 nH W=w0603 mm
c=c2 pF
L=0.1 mm
MSTEP
Step4
Subst="MSub1"
W1=w mm
W2=w0603 mm
MCORN
Corn2
Subst="MSub1"
W=w mm
MLIN
TL2
Subst="MSub1"
W=w mm
L=l2 mm
MCORNPort
Corn4 P6
Subst="MSub1"
Num=6
W=w mm
MTEE_ADS
Tee2
Subst="MSub1"
W1=w mm
W2=w mm
W3=w0603 mm
Figure B-2: Schematic of the IN/OUT matching network.
MLIN
TL24
Subst="MSub1"
W=w0603 mm
L=0.1 mm
SMTcap_0603
C13
r=0.1 Ohm
l=0.15 nH
c=c pF
MLIN
TL27
Subst="MSub1"
W=w0603 mm
L=0.1 mm
Port
P1
Num=1
MLIN
TL25
Subst="MSub1"
W=wb mm
L=L mm
MTEE_ADS
Tee9
Subst="MSub1"
W1=wb mm
W2=wb mm
MLIN
W3=w0603
mm
TL21
Subst="MSub1"
W=wb mm
L=L mm
Port
P2
Num=2
Figure B-3: Schematic of the DC-network.
73
Appendix B:
PCB Schematics
INMatching
Die
OUTMatching
(Resonator)
PCB-OUTNetworks
(Model)
PCB-INNetworks
(Schematic)
INLead
OUT-Lead
Model
PCB-OUTNetworks
(Schematic)
Bondwire
Matrixe
PCB-INNetworks
(Model)
Figure B-4: Full design Model.
74
Appendix B:
PCB Schematics
Figure B-5: Schematic model of the Bond-wires.
75
Appendix B:
PCB Schematics
IN-Bond-Wires
Set Model
OUT-Bond-Wires
Set Model
(a)
(b)
Figure B-6: Bond-wire model from the layout; (a) Top view, (b) Side view.
76
Appendix B:
100 Ω
40 Ω
PCB Schematics
100 Ω
50 Ω
Figure B-7: Full design layout.
77
Appendix B:
78
PCB Schematics
Appendix C.
Measurement and new model simulation
This appendix show the measurement of each part of the PCB and it is model simulation.
C. 1 BALUN measurement and model
The balun was measured by GS probing from very low frequency to 7 GHz with one port
terminated with 47 Ohm. The ADS model was modified by adding the parasitics of the
probe. The measurements gave a good fit with the designed PCB. Hence there was no
problem with the Balun.
Figure C-1: Balun measurement for one port.
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Measurement and new model simulation
C. 2 Output matching network
A new measurement was done for the output match; the simulated model was also fitting
the measurement data. Hence, the output matching network is acceptable for the design
Figure C-2: Reflection measurements and simulation for the output match netwrok.
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Appendix C:
Measurement and new model simulation
Figure C-3: Transmission measurements and simulation for the output match netwrok.
C. 3 Output PCB
Figure C-4: the differential impedance for the whole output PCB.
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Measurement and new model simulation
C. 4 Input matching network
Same as the Out match, a new measurement was done for the output match; the simulated
model was also fitting the measurement data. Hence, the output matching network is
acceptable for the design
Figure C-5: Reflection measurements and simulation for the output match netwrok.
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Measurement and new model simulation
Figure C-6: Transmission measurements and simulation for the output match netwrok.
C. 5 Input PCB
Figure C-7: the differential impedance for the whole output PCB.
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Appendix C:
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Measurement and new model simulation