A Fully-Integrated 40-Phase Flying-Capacitance-Dithered Switched-Capacitor
Voltage Regulator with 6mV Output Ripple
Suyoung Bang1, Jae-sun Seo2, Inhee Lee1, Seokhyeon Jeong1, Nathaniel Pinckney1, David Blaauw1, Dennis Sylvester1, and Leland Chang3
1
University of Michigan, Ann Arbor, MI 2Arizona State University, Tempe, AZ
3
IBM T. J. Watson Research Center, Yorktown Heights, NY
Abstract
A switched-capacitor voltage regulator (SCVR) that dithers flying
capacitance (CFLY) to reduce output ripple is presented. The
proposed technique is implemented in a 40-phase SCVR with 4b
CFLY modulation in 65nm CMOS. At 2.3V input, on-chip ripple
magnitude of 6~16mV at 1V output is measured for 11~142mA load.
Peak efficiency is 70.8% at a power density of 0.187W/mm2.
Introduction
Integrated voltage regulation using on-chip DC-DC step-down
converters can provide fast load response as well as reduced package
current, which reduces IR and LdI/dt drops. Switched-capacitor
voltage regulators (SCVRs) have gained popularity for on-chip
regulation [1-5] as they are compatible with CMOS processes and do
not require magnetic materials for inductors.
To stabilize the output voltage against fluctuating loads, prior
SCVR designs employed closed-loop regulation techniques
including single-boundary multi-phase control [1], multi-phase pulse
frequency modulation (PFM) [2-3], or PFM combined with discretelevel capacitance modulation [4]. Even with multi-phase interleaving,
SCVRs can exhibit >50mV output ripple [2], which incurs power
overhead due to increased voltage margins. Partial charging using
clock duty cycle [5] or switch conductance modulation [6] can
reduce output ripple, but may be limited by challenges in precise
timing control, variability tolerance, or intermediate voltage
generation. Recently, an open-loop SC converter reported a small
ripple of 3.8mV [7], but it requires external frequency modulation.
Proposed Technique
We propose dithered capacitance modulation (DCM) as a new
scheme for output ripple minimization. Figs. 1 and 2 show
conceptual timing diagrams of DCM and traditional PFM. The key
ideas of DCM are to (1) modulate fine-grain flying capacitance
(CFLY) according to load current (IL) rather than modulating phase or
frequency, and (2) temporally distribute charge transfer as much as
possible. In PFM, clock pulses are generated on demand with a fixed
frequency clock and the full CFLY is switched each time a clock pulse
is generated. For instance, 1/3 of the maximum load current requires
PFM to generate a clock pulse every third cycle (Fig. 1 at T1 and T4
across 6 clock cycles). However, this full CFLY switching followed
by no CFLY switching yields high ripple. In contrast, DCM generates
a clock pulse every cycle, but the transferred charge in a cycle is
modulated by changing CFLY on a cycle-by-cycle basis. To
accomplish this, each SC converter phase is split into several parallel
structures with binary-sized CFLY. We use 4b modulation (CM[3:0])
to provide discrete CFLY values. In the above example with 1/3 of the
maximum load, DCM sets CM[3:0] = 5 at time T0, corresponding to
5/16 of maximum charge transfer in that cycle (Fig. 1). Since 5/16 <
1/3, the output voltage drops slightly and falls below the threshold
voltage, triggering DCM to increase CM[3:0] to 6 (or 6/16 of
maximum transfer) at T1, increasing the output voltage. Since the
output now exceeds the threshold, DCM switches back to CM[3:0] =
5 for T2 and T3, creating a repeating pattern every three cycles with
an average transfer of 1/3 × 6/16 + 2/3 × 5/16 = 1/3 of the maximum.
A 2-phase SC converter with 4b DCM is built as shown in Fig. 3.
The proposed DCM technique is implemented in a 40-phase
SCVR with 4b CFLY modulation. CFLY uses MIM and MOS
capacitors with a total value of 3.7nF. CFLY is divided into 40 phases,
each consisting of binary-weighted SC converters (CLSB = 5.8pF).
No explicit output capacitance is used. The number of phases and the
modulation resolution present a trade-off between ripple and area
overhead due to capacitor spacing requirements. The chosen
configuration minimizes ripple while limiting area overhead to 10%.
The 40-phase DCM SCVR has four SC banks (Fig. 4). Each SC
bank comprises five SC converters with 2-phase 4b DCM. A
760MHz master clock is divided to 190MHz and then split into
twenty phases by a DLL with 263ps between phases. Each 190MHz
clock drives a 2-phase SC converter, where two non-overlapping
95MHz clocks are locally generated. Three comparators (C0~C2)
operate at the 760MHz master clock, generating a comparison output
every ten SC phases. References Vth,p and Vth,m are used to adjust
CM upon IL changes, and Vtarget is used to regulate Vout in steady
state. The steady-state example in Fig. 4 shows CM dithering
between CM[3:0] = 3.6, when CMP = 1 (cycles 1-2), and CM[3:0] =
3.4, when CMP = 0 (cycles 3-5). This yields an average CM value
of 3.48. Finally, a shunt push-pull regulator is used to mitigate
undershoot/overshoot against transient IL change.
Figs. 5-7 show the DCM controller flow chart and a stabilization
example given an IL transient. Five modulation signals CM0~CM4
are generated as a function of the base modulation level CM and the
dithering value Nd (Fig. 6). Upon a large step change in IL, if Vout <
Vth,m, (Fig. 7) counter CNTM is incremented and added to CM (CM
= CM + CNTM). This increases CFLY geometrically for each
subsequent cycle as long as Vout < Vth,m. After increasing CM, if Vout
> Vth,p the controller decrements the stored dithering level Nd,reg by
one in each cycle until Nd,reg reaches one, at which point CM is
decreased by one and Nd,reg is reset to five. In steady-state, when Vout
lies between Vth,p and Vth,m, only Nd is adjusted.
Measurement Results
DCM is evaluated in a 65nm CMOS testchip that also includes a
40-phase PFM SCVR. Since package parasitics act to attenuate
ripple, off-chip ripple measurement is difficult and tends to underestimate ripple magnitude. Hence, an on-chip ripple measurement
circuit [8] is incorporated, consisting of an asynchronously clocked
comparator and two counters that record the fraction of cycles with
Vout < VRMC (Fig. 8). Ripple is defined by the VRMC voltage range
with probability = 1% to 99%, while VRMC with 50% probability is
defined as the average Vout. Also, an on-chip digital-load
performance monitor [9] is implemented to measure the impact of
ripple on digital circuit delay (Fig. 9). Power and area overhead of
DLL, controller, and comparators are 3.3mW and 1.3%, respectively.
Parameters Vin, Vtarget, Vth,m, and Vth,p are set to 2.3V, 1V, 0.985V,
and 1.015V, respectively. Using the on-chip ripple measuring circuit
DCM achieves steady-state 6mV ripple at IL = 11mA, compared to
145mV for PFM at the same IL. A periodic load change between
11mA and 48mA (period ~2s) results in 65mV undershoot and
105mV overshoot in DCM (Fig. 10). The smaller undershoot is a
result of the more aggressive controller response to Vout < Vth,m.
Fig. 11 shows measured DCM and PFM ripple versus power
density (IL = 11-142mA). DCM ripple ranges from 6−16mV and
scales with load current as expected according to the open-loop
ripple expression (IL/(FSC×40×CFLY)). In addition, DCM Vout is
tightly regulated to Vtarget=1V (Fig. 12). The load performance
monitor was used to measure the impact of ripple on digital circuit
frequency: the PFM-driven circuit shows 16% slower performance
than DCM at large IL (Fig. 12). DCM achieves peak efficiency of
70.8% at a power density of 0.187W/mm2 (Fig. 13). Fig. 14 shows
the die photo and Fig. 15 compares with prior work.
References
[1] T. V. Breussegem, JSSC, July 2011. [2] R. Jain, VLSIC, Jun. 2013.
[3] T. M. Andersen, ISSCC, Feb. 2014. [4] Y. K. Ramadass, JSSC, Dec. 2010.
[5] S. S. Kudva, JSSC, Aug. 2013. [6] R. Jain, CICC, Sep. 2014.
[7] G. V. Pique, ISSCC, Feb. 2012. [8] K. Yang, ISSCC, Feb. 2014.
[9] E. Alon, JSSC, Aug. 2008.
- PFM(Pulse Frequency Modulation);Baseline
Average CF Switching = 5.33⨯CLSB
16CLSB
Time
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
Vout
Vtarget
CLK T0
VIN
VOUT CFLY = 16CLSB
CM4[0]: Input to TFF
190MHz
Charge
Transfer
Load
CLK190MHz
CMPP
C1
C2
CM4 DO[4]
Vin
Vtarget
Vout
DO[19]
Vout
Vth,p
Vth,m
Vout
Nd = Nd,reg
Nd = Nd,reg
4
3
4
3
4
4
3
4
3
4
3
4
3
4
3
3
4
3
4
3
3
4
3
4
3
Start
Reset
DONE
D Q
Probability (%)
100
Vovershoot = 1.105V
DCM
in transient
condition
DCM in steady state
@IL=11mA
4
3
4
3
4
Local CLKs
(A, Ab, B, Bb)
Nd = Nd,reg - 1
2
CM-1
CM
CM-1
CM
CM-1
Nd
4
CM
CM
CM-1
CM
CM
3
CM
CM-1
CM
CM-1
CM
5
CM
CM
CM
CM
CM
CLK
VCO
0
0
0
0
3
1
0
N1
D Q
D Q
RESET
1.00
VMIN (V)
of SCVR Output
Lower bound ripple
(Open-loop ripple)
= IL/(FSC⨯NPH⨯CFLY)
75
DCM
16mV
6mV
0
0
0
0
3
1
0
1
0
1
1
4
1
1
1
0
1
2
6
1
1
1
0
1
3
9
1
1
1
0
1
4
D
1
1
1
0
1
5
F
5
5
0
1
0
0
F
4
3
0
1
0
0
F
3
2
0
1
0
0
F
2
1
0
1
0
0
F
1
0
0
1
0
0
E
5
4
0
0
0
0
E
5
4
1
0
0
0
E
5
5
Time
1
0
0
0
E
5
5
0
0
0
0
E
5
4
0
0
0
0
E
5
4
CMP
CMPP
CMPM
CNTM
CM
Nd,reg
Nd
10mV
Fig. 11. Measured output
ripple vs. power density.
0.98
SCVR Core
65
Comp.s,
Controller, DLL
60
55
Shunt PushPull Regulator
50
45
0.00
0.05
0.10
0.15
Power density (W/mm2)
0.20
850m
Fig. 13. Measured DCM efficiency. Fig. 14. Die photo.
Metric
PFM
0.94
0.92
0.92V
0.90
0.00 0.05 0.10 0.15 0.20
Power density (W/mm2)
DCM
480
70
DCM
0.992V
0.96
520
880m
75
VDD is connected
to VOUT of SCVR
PFM
175mV
50
Vth,p
Vtarget
Vth,m
Controller and comparators
CLK period (CLK760MHz)
N0
VCTRL
0
0
0.90 0.95 1.00 1.05 1.10 1.15 1.20
0.00 0.05 0.10 0.15 0.20
VRMC (V)
Power density (W/mm2)
Fig. 10. Ripple measurement:
DCM and PFM (top), and DCM
in transient condition @
IL=11mA ↔ 48mA (bot)
1
CM-1
CM-1
CM
CM-1
CM-1
0
CM-1
CM-1
CM-1
CM-1
CM-1
CM0
CM1
CM2
CM3
CM4
ERROR
Controller
VTEST
D Q
125 130mV
25
Nd = Nd,reg - 1
Fig. 7. DCM controller stabilization example upon load change.
D Q
Frequency (MHz)
Of Performance Monitor
0.95 1.00 1.05 1.10 1.15 1.20
VRMC (V)
Nd,reg = 5, CM = CM - 1
Fig. 5. Flow chart for controller operation.
BANK-1 BANK-2 BANK-3 BANK-4 BANK-1 BANK-2
100
No
Nd,reg = Nd,reg - 1
Vout Large Step Increase in IL
150
Ripple Magnitude (mV)
Probability (%)
PFM
Yes
No
CM = CM + CNTM
CMP
130mV
DCM
Steady-state
@ IL=11mA
CNTM = 0
Nd = Nd,reg - 1
Nd,reg > 1?
Fig. 6. Dithered capacitance modulation outputs (CM0~CM4)
of controllers as function of CM and Nd.
CM0
CM1
CM2
CM3
CM4
175
Nd = Nd,reg
No
830m
100
Yes
CNTM = 0
CNTM = 0
Nd,reg = 5, CM = 15
Time
Fig. 8. Ripple measuring circuit (Ref. [8]).
20 = 935mV
Bb
A
Bb
A
Non-overlapping
CLK gen.
No
CM + CNTM > 15?
DO[0]
DO[1]
DO[2]
DO[3]
DO[4]
(2) When DONE = 1, calculate probability = CNT/(2 -1)
(3) Find Vprob99 and Vprob1, and calculate Vripple = Vprob99 – Vprob1
40 Vundershoot
Vin
Vout > Vth,p?
Yes
CNTM = CNTM + 1
5.26nsec (=1/190MHz)
263psec (=5.26nsec/20)
15
60
T8 T9
Vripple (DCM)
*CM (Cap. Modulation Level) = 0~15
Nd: Output Dithering Level = 0~5
Nd,reg: Dithering Level in Registers = 1~5
CNTM: # of CLK Counts while Vout < Vth,m
Vout < Vth,m?
DCM
2-phase
SC
Fig. 9. On-chip digital-load performance
monitor (Ref. [9])
(1) At each VRMC, reset CNT and CNTREF = 0 and start
80
95MHz
Every Rising CLK edge
Vout < Vtarget?
Yes
No
Local CLK B: 95MHz
5.26nsec (=1/190MHz)
CLK760MHz
CLK Generator
(Asynch. to SC CLK)
Reset
15b Counter
CNT
Reset
15b Reference
CNTREF
Counter
20
T7
CM[3:0], 1
Fig. 4. Top-level diagram of closed-loop 4b DCM SCVR with 40-phases: The 40phase DCM SCVR is composed of four SC-banks (top). Local clock generation
example (right). Timing diagram for DCM operation in steady state (bottom right).
40
T6
Ab CF
B
Ab Vout
B
TFF
T
Efficiency (%)
C0
CMPM
60 6mV
T5
CF = CLSB
x [8,4,2,1,1]
Local CLK A: 95MHz
DLL
CMP
80
T4
Vin
CF
Yes
Vout
Shunt
Push-Pull
Regulator
DCM
2-phase
SC
CM3 DO[3]
DCM
2-phase
SC
CM2 DO[2]
DCM
2-phase
SC
CM1 DO[1]
DO[0]
CM0
DO[15:19]
DO[10:14]
DO[5:9]
DO[0:4]
SC BANK-4
SC BANK-3
SC BANK-2
SC BANK-1
DCM
2-phase
SC
CLK190MHz
Controller Outputs:
CM0[3:0],
CLK Divider
CM1[3:0],
(÷ 4)
CM2[3:0],
CM3[3:0],
CM4[3:0]
CLK760
MHz
Vout
T3
Fig. 3. Converter implementation for 2-phase SC for 4b DCM.
Fig. 1. Conceptual timing diagram of flying capacitance switching
(When single-phase SC is assumed).
VRMC
T2
Time
8⨯ 4⨯ 2⨯ 1⨯ 1⨯C
Dithered Flying Cap.
Modulation (DCM)
Controller
T1
Fig. 2. Conceptual output voltage waveforms for DCM & PFM.
- DCM (Dithered Flying Cap. Modulation); Proposed Scheme
6CLSB
Average CF Switching = 5.33⨯CLSB
5CLSB
Time
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
C = CLSB
DO[0:19]
(190MHz)
Vripple (PFM)
PFM
DCM
PFM
Capacitor Type
Conversion
Ratios (M)
Closed-loop
Modulation
Comp. Freq.
SC Freq. (FSC)
Number of
Phases (NPH)
CFLY / COUT (nF)
16% drop
440
0.00 0.05 0.10 0.15 0.20
Power density (W/mm2)
Fig. 12. Measured results:
VMIN of output voltage (top),
and frequency of on-chip
performance monitor (bot).
[2]
22nm
Tri-gate
MIM
2:1, 3:2,
5:4, 1:1
Technology
[3]
[4]
This Work
32nm SOI
45nm Bulk
65nm Bulk
Deep Trench
MOS
MIM + MOS
2:1, 3:2
3:2, 2:1
2:1
Freq. (PFM),
Capacitance
30MHz
≤ 30MHz
Capacitance
Dithering
760MHz
95MHz
Freq.
Freq.
2GHz
≤ 250MHz
4GHz
≤ 125MHz
8
16
2
40
N/R / 0.1
16 / 0
0.534 / 0.7
3.7 / 0
Vin / Vout
1.23V /
0.45 ~ 1V
1.8V /
0.7 ~ 1.1V
1.8V /
0.8~1V
2.3V / 1V
Ripple
Measurement
Off-chip
Off-chip
Off-chip
On-chip
Vripple,pp
60mV
@≤88mA
30mV
@365mA
50mV
@≤10mA
6~16mV
@11~142mA
<25mV
94mV
@15→30mA
@30→365mA
155mV
@2→10mA
65mV
@11→48mA
0.064
2.71
0.050
0.187
68%
86.4%
66%
70.8%
Vdroop
1
2
Power Density
(ρ, W/mm2)
Efficiency @ ρ
Fig. 15. Comparison table (1N/R = Not reported,
2
Power density = reported @ M = 2:1).