Topology Selection by the Numbers
Is the topology you selected for your current design the best topology available, or is there another
topology that might be more suitable? This is a question that every engineer faces with every new design.
It is an engineer’s job to understand the trade offs between different design approaches and how and why
one approach is better than another approach for a particular application with its unique set of requirements
and operating conditions. Typically we find that there are several different approaches we can take to a
design challenge, each with advantages and disadvantages in comparison to the other options. This article
looks at some tools that can help the engineer make better design choices.
In 1988 a landmark paper (Carsten, B., “Converter Component Load Factors: A Performance Limitation
of Various Topologies”, PCIM, 1988, Munich) appeared that provided a simple method for direct
numerical comparison of power converter topologies. The Carsten paper provided a description of the
concept of component load factor, some examples of its use, and some results and general conclusions.
The component load factors for each component type are summed to form a total component load factor for
each component type for a specific circuit topology. The total component load factors for one topology
can be compared to the total component load factors for other circuit topologies for comparison purposes.
Circuits with lower total component load factors can be expected to offer better efficiency than other
topologies with higher total component load factors under the specific set of operating conditions in which
the component load factors are calculated. In some cases one topology may have lower component load
factor for one component type, but higher component load factor for another component type, so the best
topology for a specific application may not be obvious. Also, circuit topology A may be superior to circuit
topology B for one set of operating conditions, based on component load factor, but circuit topology B may
be superior to circuit topology A for a different set of operating conditions. Although the methods
available may not provide a definitive answer in every case, it can be said that component load factor and
the new numerical method introduced in this article help the engineer to shorten the list of topological
contenders for a specific set of operating conditions.
This article proposes a new numerical method, which is conceptually similar to, but in the specific details
different than, the original concept of component load factor. In order to distinguish the new method from
component load factor we will call the new method component stress factor (CSF). The goal of the new
method is to provide an apples to apples comparison between topologies which provides numerical scores
for each component type for each topology for a specific set of operating conditions. The differences
between component stress factor and component load factor lie in how the individual and total component
factors are calculated and in the results achieved.
In the new method we will assume that all of the candidate topologies have available exactly the same
amount of silicon, magnetic winding area, and capacitor volume. We will calculate three different
component stress factors. For semiconductors we will calculate a semiconductor component stress factor
(SCSF). For magnetically inductive windings we calculate a winding component stress factor (WCSF) and
for capacitors we calculate a capacitor component stress factor (CCSF). After calculating a component
stress factor for each component we sum component factors of the same type. We get the three sums
Total SCSF =
∑ SCSF ,
i
semiconductors
Total WCSF =
∑WCSF , and
windings
Total CCSF =
i
∑ CCSF .
capacitors
i
In general we will have an operating condition that specifies a range of line voltages. The CSFs may be
different at the high line condition than at the low line condition. In some cases the worst case condition
Copyright © Technical Witts, Inc., 2006. All rights reserved.
1
occurs at the minimum line voltage, but in other cases the worst case condition occurs at the maximum line
voltage. In a few rare cases the worst case condition will occur at a line voltage in the range between
maximum line voltage and minimum line voltage, but not at either the minimum line voltage or the
maximum line voltage. Good design practice requires designing for the worst case conditions, since
reliability is almost always a primary goal. So it makes sense to calculate a worst case total CSF for each
component type and to compare optimal worst case sums for different topologies. We will calculate total
CSFs for each line voltage extreme as well as total worst case CSFs for each component type, and we will
form the sums
Total Worst SCSF =
∑ SCSF
WORST ,i
semiconductors
Total Worst WCSF =
∑WCSF
windings
Total Worst CCSF =
WORST ,i
, and
∑ CCSF
WORST ,i
capacitors
,
,
where SCSFWORST ,i is the worst case SCSF for transistor i , WCSFWORST ,i is the worst case WCSF for
winding i , and CCSFWORST ,i is the worst case CCSF for capacitor i .
Next we will describe how we form the individual component CSFs. In the case of silicon we can compare
circuit A with two transistors to circuits B and C with 8 transistors each, by insisting that circuit B and
circuit C must use transistors with one fourth the die area, so that the total amount of silicon used in all
cases is exactly the same. Circuit A could be a synchronous rectifier flyback converter, circuit B could be
a full bridge forward converter with a full bridge synchronous rectifier, and circuit C could be the same as
circuit A, but with four transistors in parallel. We will even the playing field by giving each component a
weight and factoring the component’s weight into the component stress factor for each individual
component. How can we factor a component’s individual weight into the component’s component stress
factor in a way that makes sense and has some validity? For the example of circuits A, B, and C we would
want the weighting factor to give a four times advantage to the circuit A transistors over the other two
circuits and we will want the total SCSF for circuit A to be equal to the total SCSF for circuit C. Suppose
we give each transistor an individual weight of 1 in all three designs. We will want the weighting factor to
be larger by a factor of four for the transistors in circuits B and C. We can do this by forming a weighting
factor which is the sum of the weights of all the transistors in the circuit divided by the individual
component’s weight.
∑W
j
Weighting Factor for component i =
where Wi is the individual weight assigned to component i , and
∑W
j
Wi
j
j
,
is the sum of the individual
weights for all components of the same type in the circuit. For circuits A, B, and C we assigned Wi = 1
for each transistor. For circuit A
∑W
j
j
= 2, and for circuits B and C
∑W
j
j
= 8, so that the weighting
factor for each transistor in circuit A is 2 and the weighting factor for each transistor in circuits B and C is
8. This weighting factor technique yields a four times higher weighting factor for each individual
transistor in circuits B and C than for circuit A, as needed. We will use the weighting factor, as defined
above in the component stress factor for every component, regardless of type. For the case where there is
only one appearance of a particular component type, i.e., there is only one winding in a simple buck
converter, then the numerator and denominator in the weighting factor is the same number and the
weighting factor will have a value of 1. The total CSF for a topology will depend on how weights are
Copyright © Technical Witts, Inc., 2006. All rights reserved.
2
assigned to individual components. By adjusting the weights to achieve the lowest total CSFs we gain
insight into how to assign silicon, winding area, and capacitor resources to achieve a more optimal design.
In making comparisons between designs we must first optimize the designs by finding the combination of
weights that yields the lowest total worst case CSFs, in order to make a valid comparison.
Another quantity that determines an individual component’s stress factor is the component’s maximum
voltage stress. How should a component’s voltage stress effect its CSF? For a transistor, stress is related
to power dissipated in the transistor. For the analysis in this article series we will assume that all of the
semiconductors are mosfets. Conduction losses in a mosfet can be calculated from the average squared
current in the mosfet multiplied by the on resistance of the mosfet, so we will form the CSF for a transistor
by using the maximum average squared current, or the rms current squared. The on resistance for a mosfet
of a given die size is proportional to the square of the voltage rating of the mosfet. This is because the
channel length is proportional to voltage breakdown and, for a given die size, a longer channel length
results in a smaller channel cross sectional area. Resistance, R , can be found from R = ρ
L
, where ρ is
A
the resistivity of enhanced silicon, L is the channel length, and A is the channel cross sectional area. For
a transistor, we include the square of the maximum voltage in the CSF for the individual transistor, because
voltage rating increases channel length and decreases channel cross sectional area, so that for an individual
transistor we will define the component stress factor to be
∑W
SCSFi =
j
V MAX ,i 2 I RMS ,i 2
,
P2
j
Wi
where SCSFi is the individual transistor’s component stress factor, V MAX ,i is the maximum peak voltage
applied to the transistor, I RMS ,i is the maximum rms current in the transistor, and P is the total power
processed by the circuit, assuming the converter is 100% efficient. The inclusion of P in the definition of
CSF normalizes the CSF by removing any dependence on the power processed and makes CSF a
dimensionless quantity.
In the calculations of rms current in this article we will assume that the circuit’s inductors are large and that
there is no variation in the current during the operating states of the circuit. We can calculate the rms
current from
I RMS =
∑D
i
i
Ii 2
where Di is the duty cycle of the i operating state, and I i is the transistor current during the i operating
state. One operating state may be the state in which the converter’s main switch is on, while a second
operating state may be the state in which the main switch is off and the main rectifier is on.
For magnetic components we will assume that each circuit has available exactly the same amount of
window area for windings. We will not consider the fact that some designs require multiple cores. We
will treat each winding as a separate component and assign a weight to each winding and then calculate a
CSF for each winding. First we define a CSF for windings
∑W
WCSFi =
j
Wi
j
V MAX ,i 2 I RMS ,i 2
P2
Copyright © Technical Witts, Inc., 2006. All rights reserved.
3
Conduction losses in a winding are joule heating, or I2R type, losses, so we can readily see why we need to
2
2
include I RMS ,i in the definition. I RMS ,i is calculated in the same way as indicated above for transistors.
In order to accommodate applied voltage in a magnetically inductive element we need turns of wire in
proportion to the voltage. More turns of wire mean less window area available for each turn and a longer
wire. The winding resistance will be proportional to the number of turns and inversely proportional to the
area available for each turn, therefore, the winding resistance will increase with the square of the number
of turns which will be proportional to the voltage squared. We calculate a worst case V MAX ,i , by the
formula,
V MAX ,i = ∑ Di |Vi |
i
under worst case conditions for the winding, i.e., the condition that yields the largest value for V MAX ,i ,
where Di is the duty cycle of the i operating state of the converter under the worst case condition and
|Vi | is the absolute value of the winding voltage in the i operating state. For most converter types V MAX ,i
occurs at the maximum line voltage, but for boost chokes V MAX ,i occurs at a duty cycle of 0.5. For boost
chokes that operate in a range where the duty cycle is always greater than 0.5, V MAX ,i occurs at the
maximum line voltage. For boost chokes that operate in a range where the duty cycle is always less than
0.5, V MAX ,i occurs at the minimum line voltage.
For capacitors we calculate CSF in much the same way. We assign a weight to each capacitor in the
circuit. We determine the peak voltage stress for the capacitor and we calculate the rms current in the
capacitor. We reason that the stress in the capacitor is primarily due to joule heating, so we want the CSF
to represent a joule heating loss, or I2R loss, where R represents an equivalent series resistance (esr) in the
capacitor, which means that the CSF for capacitors will depend on the square of the rms current in the
capacitor. Esr is, generally, a function of the volume of a capacitor. The volume of a capacitor is
proportional to its energy storage capacity,
1
C V 2 , so that the component stress for the capacitor also
2
depends on the squared peak voltage of the capacitor. For capacitors we define the CSF to be
∑W
CCSFi =
j
Wi
j
VPEAK ,i 2 I RMS ,i 2
P2
Some circuit approaches combine topologies. Our leading candidates may be a forward converter or a
buck converter pre-regulator combined with a dc transformer. We will want to compare the CSFs for the
forward converter to the CSFs for the combination of buck sub-converter plus dc transformer subconverter. How do we create a valid comparison in the case where one of the candidate topologies is
actually a combination of two topologies? Would it be correct to just add the total component load factors
for the buck plus dc transformer and compare that to the forward converter? We decided at the onset that
we would insist that each candidate topology would have to rely on exactly the same amount of silicon,
window area, and capacitor volume, so we established weighting factors to enforce that rule. We can
enforce the equal resource rule by giving each sub-converter a weight for each component type and
forming new CSF sums for each candidate topology where we add up the CSF sums but also give each
sub-converter a weight for each component type. For the buck plus dc transformer combination we can say
that the buck converter, or sub-converter 1, has a set of weights, and that the dc transformer, or subconverter 2, has a set of weights and we can form new CSF sums which combines the CSF sums from the
two sub-converters and factors in the sub-converter weights in the new sums. For the total semiconductor
CSF (SCSF) for a combination of sub-converters we define
Copyright © Technical Witts, Inc., 2006. All rights reserved.
4
Total SCSF =
∑
subconverters
∑W
j
semiconductors
Wi
( Total SCSFi ) ,
where Wi is the semiconductor sub-converter weight for sub-converter i ,
∑W
j
semiconductors
is the sum of the
semiconductor sub-converter weights, and Total SCSFi is the total SCSF for sub-converter i . If we are
going to compare a buck plus a dc transformer combination to a forward converter we could give the buck
sub-converter a semiconductor weight of 1, the dc transformer sub-converter a semiconductor weight of 1,
and the total SCSF for the combination would be two times the total SCSF for the buck plus two times the
total SCSF for the dc transformer. We calculate winding and capacitor CSFs for the sub-converter
combinations in the same way, but the weights for windings and capacitors may be different than the
semiconductor weights. We may find that the lowest total CSFs correspond to unequal weights for the
sub-converters and we may find that the sub-converter semiconductor weights are different than the subconverter winding or capacitor weights. Knowing the weights for sub-converters that yields the lowest
CSFs gives insight into how to assign silicon, winding area, and capacitor resources. For example, if we
combine sub-converter A with high semiconductor CSF and low winding CSF with sub-converter B with
low semiconductor CSF and high winding CSF it might make sense to give a higher semiconductor subconverter weight to sub-converter A and a lower winding sub-converter weight to sub-converter A
compared to sub-converter B so that resources will be assigned where they are most needed.
Now that we have CSF defined for transistors, windings, and capacitors let’s apply our new method to
some circuit examples and see what kind of results can be achieved.
Figure 1. Buck converter with synchronous rectification
As a first example consider a buck converter with synchronous rectification, as illustrated in figure 1. The
input voltage is 200 volts, the output voltage is 100 volts and the load is 100 watts. In this converter the
duty cycle is 0.5. Let’s give each mosfet a weight of 1 for now, which suggests that we intend to make
each mosfet the same die size. For MMAIN the maximum voltage stress V MAX , MAIN is 200 volts. We can
calculate the rms current to be
I RMS , MAIN = DMAIN I MAIN 2 = 0.5 ( 1 amp ) 2 = 2 / 2 amp
and the power processed is 100 watts. We can plug the values we know into the formula for SCSF to find
the SCSF for MMAIN.
∑W
SCSFMMAIN =
j
j
WMMAIN
V MAX , MMAIN 2 I RMS , MMAIN 2 ( 1 + 1 ) ( 200 volts ) 2 ( 2 / 2 amp ) 2
=
=4
P2
1
( 100 watts ) 2
For MSYNC the maximum voltage stress is 200 volts, the rms current in MSYNC is the same as in MMAIN, and
the power is 100 watts. We calculate the SCSF for MSYNC to be
Copyright © Technical Witts, Inc., 2006. All rights reserved.
5
∑W
SCSFMSYNC =
j
j
WMSYNC
V MAX , MSYNC 2 I RMS , MSYNC 2 ( 1 + 1 ) ( 200 volts ) 2 ( 2 / 2 amp ) 2
=
= 4.
P2
1
( 100 watts ) 2
Now we can calculate a total SCSF for the figure 1 circuit
Total SCSF =
∑ SCSF = SCSF
semiconductors
i
MMAIN
+ SCSFMSYNC = 4 + 4 = 8 .
We can calculate a winding CSF for the buck choke and set the weight for the buck choke to 1. The
current in the buck choke is a constant 1 amp and the voltage magnitude is always 100 volts, so
WCSFCHOKE =
1 ( 100 volts ) 2 ( 1 amp ) 2
=1.
1
( 100 watts ) 2
Since there is only one winding the total WCSF is also 1.
We have two capacitors in figure 1. We will assign a weight of 1 to each of the capacitors and calculate
CCSFs. The peak voltage of the input capacitor is 200 volts. The average current into the capacitor is 0.5
amp. During the on time of the main switch there is a net current of 0.5 amp out of the input capacitor and
during the off time of the main switch there is a net current of 0.5 amp into the input capacitor, so that the
magnitude of the capacitor current is always 0.5 amp. For the output capacitor the input current to the
capacitor is always equal to the output current from the capacitor so that the net current in the output
capacitor is 0.
CCSFCIN =
CCSFCOUT =
( 1 + 1 ) ( 200 volts ) 2 ( 0.5 amp ) 2
= 2,
1
( 100 watts ) 2
( 1 + 1 ) ( 100 volts ) 2 ( 0 amp ) 2
= 0 , and
1
( 100 watts ) 2
Total CCSF = CCSFCIN + CCSFCOUT = 2 + 0 = 2 .
Figure 2. Isolated flyback converter with synchronous rectification
As a second example, consider an isolated flyback converter with synchronous rectification operating at a
line voltage of 200 volts, a load voltage of 100 volts, and a load power of 100 watts, as illustrated in figure
2. The turns ratio of the transformer is 2:1 and the duty cycle is 50%. We will give a weight of 1 to both
the main switch and the synchronous rectifier. We will give a weight of 1 to each winding, and we will
give a weight of 1 to each capacitor. For the main primary side switch the component stress factor is
Copyright © Technical Witts, Inc., 2006. All rights reserved.
6
SCSFMAIN =
( 1 + 1 ) ( 400 volts ) 2 ( 2 / 2 amps ) 2
= 16 .
1
( 100 watts ) 2
For the secondary side synchronous rectifier switch the component stress factor is
SCSFSYNC =
( 1 + 1 ) ( 200 volts ) 2 ( 2 amps ) 2
= 16 .
1
( 100 watts ) 2
For the isolated flyback the total semiconductor component stress factor is
Total SCSF = SCSFMAIN + SCSFSYNC = 16 + 16 = 32
For the primary winding the component stress factor is
WCSFPRIMARY
( 1 + 1 ) ( 200 volts ) 2 ( 2 / 2 amps ) 2
=
= 4.
1
( 100 watts ) 2
For the secondary winding the component stress factor is
WCSFSECONDARY =
( 1 + 1 ) ( 100 volts ) 2 ( 2 amps ) 2
= 4.
1
( 100 watts ) 2
For the isolated flyback the total winding component stress factor is
Total WCSF = WCSFPRIMARY + WCSFSECONDARY = 4 + 4 = 8 .
For CIN the component stress factor is
CCSFCIN
( 1 + 1 ) ( 200 volts ) 2 ( 0.5 amp ) 2
=
= 2.
1
( 100 watts ) 2
For COUT the component stress factor is
CCSFCOUT =
( 1 + 1 ) ( 100 volts ) 2 ( 1 amp ) 2
= 2.
1
( 100 watts ) 2
For the isolated flyback converter the total capacitor component stress factor is
Total CCSF = CCSFCIN + CCSFCOUT = 2 + 2 = 4 .
Consider for a moment the total SCSFs we calculated for the buck and the flyback. We found that the total
SCSF for the buck was 8 and the total SCSF for the flyback was 32, assuming equal weights for the two
transistors in both cases. These results for the buck and the isolated flyback used for the same design
problem beg the question. What is it that is worse by a factor of 4 about the isolated flyback converter? If
we were to assume that the two transistors in the flyback had the same die size as the two transistors in the
buck we might compare the conduction power losses in the mosfets of the two circuits. Let’s do that. We
will assume that the channel resistance goes up as the square of the voltage for a given die size. This
assumption holds up well at higher voltages, but breaks down at low voltages due to the contribution of
Copyright © Technical Witts, Inc., 2006. All rights reserved.
7
lead resistance. For the flyback converter we need a primary side mosfet with a channel that is twice as
long to handle the voltage (400 volts) compared to the buck converter with its 200 volt mosfet. Since we
stipulated that to make a valid comparison the total die size should be the same for both circuits, the cross
section for the channel of the 400 volt mosfet must be half the cross section of the 200 volt mosfet used in
the buck converter. The net result is that the primary side mosfet in the flyback would have a channel
resistance four times the channel resistance of the mosfet in the buck converter. If the channel resistance
for the main switch in the buck converter is R, then the channel resistance for a main switch with the same
die size in the flyback is 4R. We can calculate conduction losses. For the buck converter the conduction
losses are PBUCK = ( 1 amp )2 R. For the flyback converter we have one mosfet with a channel resistance of
4 R operating with a rms current of 0.707 amp, and one mosfet with a channel resistance of R operating
with a rms current of 1.414 amps. The total mosfet conduction losses for the flyback are PFLYBACK = (
0.707 amp )2 ( 4 R) + ( 1.414 amp )2 R = 4 ( 1 amp )2 R = 4 PBUCK. This result would seem to suggest that
the semiconductor component stress factor for the isolated flyback should be 4 times worse than the
semiconductor component stress factor for the buck converter, since the total component stress due to
conduction losses are 4 times worse for the flyback converter with the same amount of silicon. We defined
component stress factor so that it would indicate the relative power losses in the components of the same
type, so that we could have a measurement tool that would predict which topology will be more efficient
than another topology and by how much. So far the calculated results seem to be consistent with the
reality.
Figure 3. Full bridge forward converter with synchronous rectification.
As a third example consider the isolated full bridge forward converter of figure 3. The isolated full bridge
forward converter has a line voltage of 200 volts, a load voltage of 100 volts, and a load power of 100
watts. The full bridge forward converter has a full bridge primary switch arrangement and a full bridge
secondary synchronous rectifier arrangement. The transformer turns ratio is 2:1 and each switch operates
at 50% duty cycle. We assign a weight of 1 to each mosfet so that the sum of transistor weights is 8. The
maximum voltage of the primary switches is 200 volts and the rms current in each primary switch is
2
1
( 1 / 2 amp ) 2 =
amp .
2
4
I rms =
For the secondary switches the maximum voltage is 100 volts and the rms current in each secondary switch
is
I rms =
1
2
( 1 amp ) 2 =
amp .
2
2
For each primary switch the component stress factor is
SCSFMi =
8 ( 200 volts ) 2 ( 2 / 4 amp ) 2
=4
1
( 100 watts ) 2
and for each secondary switch the component stress factor is
Copyright © Technical Witts, Inc., 2006. All rights reserved.
8
SCSFMi
8 ( 100 volts ) 2 ( 2 / 2 amp ) 2
=
= 4.
1
( 100 watts ) 2
The total semiconductor component stress factor for the full bridge forward converter is
Total SCSF =
∑ SCSF
semiconductors
Mi
= 8 ⋅ 4 = 32 .
The total semiconductor CSF for the full bridge forward converter is identical to the total semiconductor
CSF for the flyback converter operating under the same conditions of line and load. Compared to the buck
converter both the flyback and the full bridge forward converter have 4 times the total semiconductor CSF.
The figure 3 circuit has 3 windings. We will assign each winding a weight of 1, so that the sum of the
winding weights is 3. The current in the primary winding is 1/2 amp. The current in the other two
windings is 1 amp. The voltage of the primary transformer winding is 200 volts, the voltage of the
secondary transformer winding is 100 volts, and the voltage of the choke winding is 0 volts. For the
transformer primary winding CSF we get
3 ( 200 volts ) 2 ( 0.5 amp ) 2
=
= 3.
( 100 watts ) 2
1
WCSFPRIMARY
and for the secondary winding we get
WCSFSECONDARY
3 ( 100 volts ) 2 ( 1 amp ) 2
=
= 3.
1
( 100 watts ) 2
For the output choke winding we get
WCSFCHOKE =
3 ( 0 volt ) 2 ( 1 amp ) 2
= 0.
1
( 100 watts ) 2
We calculate the total winding CSF to be
Total WCSF = WCSFPRIMARY + WCSFSECONDARY + WCSFCHOKE = 3 + 3 + 0 = 6 .
Despite the fact that the full bridge forward converter has 3 windings the total winding CSF for the full
bridge forward converter is lower than the total winding CSF for the flyback. We can achieve even lower
total WCSF by choosing different winding component weights. We achieve the optimal result of 4 by
assigning a weight of 1 to each transformer winding and a weight of 0 to the choke winding.
The figure 3 circuit has two capacitors. We will assign a weight of 1 to each capacitor so that the sum of
capacitor weights is 2. The peak voltage for the input capacitor is 200 volts and for the output capacitor
the peak voltage is 100 volts and the rms current in each capacitor is 0 amp. We calculate the capacitor
CSFs to be
CCSFCIN =
2 ( 200 volts ) 2 ( 0 amp ) 2
= 0 and
1
( 100 watts ) 2
Copyright © Technical Witts, Inc., 2006. All rights reserved.
9
I )SY
C
N
sSY
,(rm
=−
I1
D
C
N
CCSFCOUT
2 ( 100 volts ) 2 ( 0 amp ) 2
=
= 0.
1
( 100 watts ) 2
We calculate the total capacitor CSF to be
Total CCSF = CCSFCIN + CCSFCOUT = 0 + 0 = 0 .
Compared to the flyback converter the full bridge forward converter has much lower total capacitor CSF.
By comparison to the flyback converter the full bridge forward converter has the same total SCSF, but
lower total WCSF, and lower total CCSF. That would suggest that for an application with a very limited
line voltage range a full bridge forward converter would have an efficiency advantage over a flyback and
that the efficiency advantage would appear in the form of higher efficiency magnetics and capacitors.
Alternatively, for a given efficiency in the subject application we would expect that the flyback converter
would require larger magnetics and capacitors than the full bridge forward converter.
Figure 4. Buck converter with synchronous rectification.
We will now consider the effects of variable line voltage. Figure 4 illustrates a buck converter with
variable line voltage. We first consider the semiconductor CSF. We will assign a weight of 1 to each
transistor. For both transistors the voltage stress is 800 volts. At high line the duty cycle is 12.5% and at
low line the duty cycle is 50%. We will assume that the inductor is large and the inductor current is a
constant 1 amp. We need to calculate the rms currents in the switches at high line and low line. For the
main switch the rms current is found from
I rms , MAIN =
D I MAIN 2
so that at 800 volts
Total CCSF = CCSFCIN +CCSFCOUT = 0+0 = 0
and at 200 volts
C C S F
C O U T
=
2
1
( 1 0 0 v o lts ) 2 ( 0 a m p )
( 1 0 0 w a tts ) 2
2
= 0
.
For the synchronous rectifier we use the formula
so that at 800 volts
Copyright © Technical Witts, Inc., 2006. All rights reserved.
10
,5.=watts
rm
−
=
MAIN
8SCSF
1Y
vs==
F
otalSC
T
IN
A
20()M
=+
=
a206418)(Y
Sw
p7+
5/.m
volts00
F
C
N
1600
lts
and at 200 volts
.
The CSF for the main switch at 800 volts is
.
For the synchronous rectifier the CSF at 800 volts is
.
The total SCSF at 800 volts is
.
The CSF for the main switch at 200 volts is
.
For the synchronous rectifier the CSF at 200 volts is
.
The total SCSF at 200 volts is
.
The total SCSFs are the same for the buck converter at high line and at low line. For the buck converter
the total SCSF does not vary with line voltage, but the component stresses of the two transistors vary over
the line range, so that, as the line voltage changes, the stresses shift from one transistor to the other
transistor. In the figure 1 buck converter the total SCSF was 8 and the ratio of maximum line voltage to
minimum line voltage was 1. In the figure 4 buck converter the ratio of maximum line voltage to minimum
line voltage is 4 and the total SCSF is 128, which is 16 times 8, or 4 squared times 8. Can we say, in
general , that the total SCSF is proportional to the square of the ratio of maximum to minimum line
voltage? It seems to be true for the buck converter and it will prove to be true for other converters too with
a few caveats.
For comparison purposes we must calculate a total worst case SCSF which takes into account the fact that
we have to design for worst case conditions. The worst case CSF for the main switch in the buck converter
of figure 4 is
Copyright © Technical Witts, Inc., 2006. All rights reserved.
11
(|∑
Y=
==
T
R
O
N
,=+
V
+
X
A
aM
w
SF
C
817W
si).IvoltD
205rm
−
=
vSM
I+
A
F
T
R
O
W
C
N
p871236olts,4Y
m
05(.)a
.
For the synchronous rectifier the worst case CSF is
.
The total worst case SCSF for the buck converter of figure 4 is
.
The reader will notice that over the line range the synchronous rectifier has CSF that is greater than or
equal to the CSF of the main switch. This suggests that it would make sense to use a larger synchronous
rectifier and a smaller main switch for this application. If we adjust the relative weights of the two
semiconductors we can achieve a lower total worst case SCSF. We achieve a minimum total worst case
SCSF when the synchronous rectifier has a weight of 57% and the main switch has a weight of 43%. The
total worst case SCSF with optimal weights is 172.7. When we compare the buck converter to the other
topology contenders we will use the 172.7 number for the buck converter and compare that number to the
optimized worst case numbers for the other contenders. We calculated SCSFs above assuming that the two
transistors had equal weights, but we have found that unequal weighting of the transistors will improve the
worst case condition. We have not illustrated the calculation of SCSFs for figure 4 with the unequal
weighting, but we show the results of the SCSF calculations below in table 1. The results shown in table 1
are not precisely consistent with the hypothesis that the total SCSFs are proportional to the square of the
ratio of maximum line voltage to minimum line voltage, but as an approximate rule of thumb the
hypothesis holds up, and it would hold up precisely had we not altered the component weights for
optimization.
In the buck converter there is only one winding so the weight assignment for the winding is arbitrary and
inconsequential. Let’s give the choke winding a weight of 1. The worst case winding voltage occurs at
maximum line voltage for the buck converter. The maximum average choke voltage is
The choke current is a constant 1 amp. We can calculate the winding CSF to be
.
Since there is only one winding and the winding current does not change with line voltage 3.0625 is the
total winding CSF and also the total worst case winding CSF.
We have two capacitors in the buck converter of figure 4. Let’s assign an initial weight of 1 to each
capacitor. For the input capacitor the peak capacitor voltage stress is 800 volts. When the line voltage is
800 volts the rms current for the input capacitor is
At the minimum line voltage the rms current for the input capacitor is
.
Copyright © Technical Witts, Inc., 2006. All rights reserved.
12
volts8w
()SF
IN
201C
==
1032()ats4
For the output capacitor the peak voltage is 100 volts and the current is 0 amp.
For the input capacitor the CSF at 800 volts is
.
At a line voltage of 200 volts the CSF for the input capacitor is
.
For the output capacitor, since the output capacitor current is 0, we can say that the CSF for the output
capacitor is 0. The total CCSF for the buck converter of figure 4 will just be equal to the CCSF for the
input capacitor. The total worst case CCSF for the buck converter is the CCSF for the input capacitor at
200 volts, or 32. Since the CSF for the output capacitor is 0 this suggests that we can eliminate it or
replace it with a very small capacitor, very much smaller than the input capacitor. The lowest total worst
case CCSF that we can achieve corresponds to the case where the output capacitor is assigned a weight of
0 and eliminated. In that case the optimal total worst case CCSF is 16 for the figure 4 buck converter.
Now let’s try to calculate CSFs for a different topology operating under the same conditions of line and
load. What would be the alternate circuit topologies to solve the same non-isolated problem that might
yield lower total worst case CSFs? A tapped inductor buck converter comes to mind as a possibility. We
will evaluate the tapped inductor buck converter, as illustrated in figure 5.
Figure 5. Tapped inductor buck converter with synchronous rectification.
In the tapped inductor buck converter we have a coupled inductor. The turns ratio of the inductor affects
the switch voltages and currents and the CSFs of all of the components. Since we have already illustrated
how to calculate all of the quantities we need for CSF, instead of illustrating all of the calculations again
we will summarize the results for both the buck converter of figure 4 and the tapped inductor buck
converter of figure 5 in table 1.
The tapped inductor buck converter with a turns ratio of 0 reduces to the simple buck converter of figure 4.
As the turns ratio increases the semiconductor CSF and the capacitor CSF decreases while the winding
CSF increases. One of the major shortcomings of the simple buck converter for wide line ranges is that the
semiconductor stress becomes very large because, at the low end of the line range, a relatively high voltage
switch with relatively high on resistance must operate at the relatively large currents required at relatively
low voltage. By tapping the inductor we need a slightly higher voltage switch operating at much lower
current for the main switch, but the synchronous rectifier becomes a much lower voltage switch that can
more readily handle the higher currents. The minimum semiconductor CSF occurs at a turns ratio of about
8/3. At this turns ratio the capacitor CSF is also about half that of the simple buck, but the winding CSF is
almost 4 times larger, so we have traded off semiconductor CSF and capacitor CSF for winding CSF.
Notice also that when the turns ratio is 2 or higher the highest total CSFs for the tapped inductor buck
Copyright © Technical Witts, Inc., 2006. All rights reserved.
13
converter corresponds to the minimum line voltage and all the CSFs decrease at higher line voltages. All
things considered the tapped inductor buck converter with a turns ratio of 2 seems like a more suitable
topology for the application than the simple buck converter. The calculation of CSFs in this case yields
some useful numbers to indicate which topology might be better, but not a definitive answer. In the case of
CCSFs the capacitor requirement may be driven by other considerations, such as filtering, hold up, or
transient requirements. Also, the two topologies illustrated are candidates for multi-phasing so that, if the
capacitor stress factor is a major liability for one topology, but the other CSFs are superior, then the CCSFs
can be reduced by the square of the number of sub-converters in a parallel multi-phase converter system.
The simple buck converter would benefit most from multi-phasing since it has the highest total CCSFs.
For the particular problem under consideration in those cases where efficiency is a primary goal, the tapped
inductor buck converter illustrated in figure 5 or one of the other tapped inductor buck topologies available
are likely to be preferred, since in many, if not most, situations the semiconductor losses account for a
significantly greater share of the losses than either the winding or capacitor losses. Where tapped inductor
converters are clearly superior are in applications with limited line voltage range and where the step up or
step down ratio is either very large or very small. For very small step up or step down ratios with limited
line voltage range there are tapped inductor converters that provide CSFs less than 1!
Table 1
Figure #
Turns Ratio
Weight Main Switch
Weight Sync Switch
Weight L2
Weight L1
Weight Input Capacitor
Weight Output Capacitor
Total SCSF( 800 volts )
Total SCSF( 200 volts )
Total Worst Case SCSF
Total WCSF( 800 volts )
Total WCSF( 200 volts )
Total Worst Case WCSF
Total CCSF( 800 volts )
Total CCSF( 200 volts )
Total Worst Case CCSF
4&5
0
43
57
0
1
1
0
117
131
173
3.06
3.06
3.06
7
16
16
5
1
1.23
1
0.596
1
8
1
54.8
88.9
99.5
4.53
4.36
6.5
4.43
10.1
10.1
5
2
1.66
1
1.08
1
4
1
40.7
83
85.7
5.46
7.07
9.7
3.65
8.33
8.33
5
2.66
1.91
1
1.36
1
3
1
36.7
83.9
83.9
5.9
8.78
11.7
3.4
7.76
7.76
5
4
2.24
1
1.89
1
2
1
32.3
90.5
90.5
6.56
12
15.3
3.15
7.2
7.2
What other topologies might be worth considering for the subject application of figures 4 and 5? A boost
converter pre-regulator with a non-isolated dc transformer has lower total SCSF and lower total CCSF than
the buck, but with higher total WCSF and it does not compare favorably with the tapped inductor buck for
this particular set of line and load conditions.
Figure 6. Full bridge forward converter with wide line voltage range.
Copyright © Technical Witts, Inc., 2006. All rights reserved.
14
Total
dcX
+
=
W
SCSF
Boost
2o9 r s t
.9
04
32
124
+
=
1
Figure 6 illustrates a full bridge forward converter similar to figure 3, but it operates over a wide line
voltage range. The application is the same as the application for figures 4 and 5, except that the line and
load are isolated in figure 6. The isolation requirement adds to the design problem, and, generally, adds to
the component stress factors. The results for the full bridge forward converter are illustrated below in table
2. Figure 3 illustrated a full bridge forward converter with a ratio of maximum line voltage to minimum
line voltage of 1 and it had a total SCSF of 32. If our hypothesis that the total SCSF increases with the
square of the line voltage ratio holds up we should have a total SCSF for figure 6 of 512 which is 16, or 4
squared, times 32. At the minimum line voltage the total SCSF is 512, but at maximum line voltage the
total SCSF is only 224.
Figure 7. Combination of boost pre-regulator sub-converter with full bridge dc transformer sub-converter
Figure 7 illustrates a boost pre-regulator plus dc transformer combination that seeks to solve the same
problem as the figure 6 circuit. In the figure 7 approach a boost converter provides a regulated 800 volts to
the input of a full bridge dc transformer, which provides 100 volts to the load. This two stage approach
might seem like an unlikely candidate topology for the problem, because all of the power is processed
twice, once by the boost sub-converter then again by the dc transformer, but the numbers suggest
otherwise. Table 2 summarizes the results of the CSF calculations for figures 6 and 7. Notice that the total
SCSF for the boost converter varies significantly over the line voltage range. The total SCSF for the boost
converter is more than 10 times smaller at the maximum line voltage than at the minimum line voltage,
unlike the simple buck converter whose total SCSF varies not at all over the line range, or only very little if
the transistor weights are altered for worst case optimization. If the boost converter of figure 7 had equal
transistor weights then its total SCSF at high line would be 2 and its total SCSF at low line would be 32,
which is 16 times, or 4 squared times, larger than the high line SCSF. In general the highest total SCSF
corresponds to the minimum line voltage, regardless of the topology.
We will illustrate the calculation of the total SCSF for the combination of boost sub-converter with dc
transformer sub-converter according to the equations and method described earlier. We will use the subconverter weights indicated in table 2. From table 2 the boost sub-converter semiconductor weight is 1 and
the dc transformer sub-converter weight is 1.04. The total worst case semiconductor CSF for the boost
converter is 29.9 and the total worst case semiconductor CSF for the dc transformer is 32. The total worst
case semiconductor CSF for the combination is
.
Copyright © Technical Witts, Inc., 2006. All rights reserved.
15
Table 2
Figure #
Transformer Turns Ratio
Weight Main Boost Switch
Weight Sync Boost Switch
Weight Primary Switch
Weight Secondary Switch
Weight Sub-converter Boost Semiconductor
Weight Sub-converter dc Xfmr Semiconductor
Weight Boost Choke
Weight Forward Choke
Weight Primary Winding
Weight Secondary Winding
Weight Sub-converter Boost Winding
Weight Sub-converter dc Xfmr Winding
Weight Input Capacitor Forward
Weight Output Capacitor Forward
Weight Input Capacitor Boost
Weight Output Capacitor Boost
Weight Input Capacitor dc Xfmr
Weight Output Capacitor dc Xfmr
Weight Sub-converter Boost Capacitor
Weight Sub-converter dc Xfmr Capacitor
Total SCSF( 800 volts) Forward
Total SCSF( 800 volts ) Boost
Total SCSF( 800 volts ) dc Xfmr
Total SCSF( 800 volts ) Boost + dc Xfmr
Total SCSF( 200 volts ) Forward
Total SCSF( 200 volts ) Boost
Total SCSF( 200 volts ) dc Xfmr
Total SCSF( 200 volts ) Boost + dc Xfmr
Total Worst Case SCSF Forward
Total Worst Case SCSF Boost
Total Worst Case SCSF dc Xfmr
Total Worst Case SCSF Boost + dc Xfmr
Total WCSF( 800 volts) Forward
Total WCSF( 800 volts ) Boost
Total WCSF( 800 volts ) dc Xfmr
Total WCSF( 800 volts ) Boost + dc Xfmr
Total WCSF( 200 volts ) Forward
Total WCSF( 200 volts ) Boost
Total WCSF( 200 volts ) dc Xfmr
Total WCSF( 200 volts ) Boost + dc Xfmr
Total Worst Case WCSF Forward
Total Worst Case WCSF Boost
Total Worst Case WCSF dc Xfmr
Copyright © Technical Witts, Inc., 2006. All rights reserved.
6
2:1
1
1
1.5
1
1
7
8:1
1
1.73
1
1
1
1.04
1
1
1
1
1
1
0
0
1
1
1
1
0
224
2.73
32
68.3
512
29.9
32
124
512
29.9
32
124
7
0.25
4
8.5
12.25
4
4
16
12.25
4
4
16
Total Worst Case WCSF Boost + dc Xfmr
Total CCSF( 800 volts) Forward
Total CCSF( 800 volts ) Boost
Total CCSF( 800 volts ) dc Xfmr
Total CCSF( 800 volts ) Boost + dc Xfmr
Total CCSF( 200 volts ) Forward
Total CCSF( 200 volts ) Boost
Total CCSF( 200 volts ) dc Xfmr
Total CCSF( 200 volts ) Boost + dc Xfmr
Total Worst Case CCSF Forward
Total Worst Case CCSF Boost
Total Worst Case CCSF dc Xfmr
Total Worst Case CCSF Boost + dc Xfmr
16
3
0
0
0
0
3
0
3
3
3
0
3
We can see from table 2 that the boost plus dc transformer has much lower SCSFs than the forward
converter for the wide line range condition. The CCSFs for the two are the same and the WCSFs are just
slightly better for the forward converter. For this wide line range application and for isolated wide line
range applications in general, the boost plus dc transformer is the topology of choice for high efficiency.
For limited line ranges the forward converter has lower CSFs. When the line voltage maximum is about
1.5 times the line voltage minimum the total SCSFs for the forward converter are about the same as the
total SCSFs for the boost plus dc transformer combination.
Are there other topologies that we should consider for isolated wide line range applications? For the
power level specified the most likely topologies that one would likely find in common use are single ended
flybacks and forward converters. Single ended flybacks and active reset forward converters may have
lower total SCSFs than the full bridge forward converter of figure 6, but they will have larger total WCSF
and larger total CCSF. The preference of the single ended flybacks and forward converters at lower power
levels is a result of the lower circuit complexity which will likely translate into lower cost, although there is
a price to be paid for the simplicity and cost savings in higher CSFs.
What conclusions can we draw from CSF calculations?
1. For many topologies there is a relationship between total SCSF and line voltage range that depends on
the square of the ratio of line maximum voltage to line minimum voltage. This would suggest that any
topology will be more efficient if it can be operated over a limited line voltage range. There are many
converters that are designed to operate over a line voltage range of 85 volts ac to 265 volts ac. One
approach to this problem is to use a rectifier that functions as a voltage doubler rectifier at the low end of
the line voltage range and as a full bridge rectifier at the high end of the line voltage range. The change
from doubler rectifier to full bridge rectifier would occur near mid range and can be implemented
automatically with a triac and line voltage sensing circuit or manually with a switch or jumper. With a
switchable rectifier the effective line range seen by the power conversion circuits is much reduced in
comparison to a full range full bridge rectifier circuit. The power conversion circuits can be expected to be
significantly more efficient with the switchable rectifier.
2. For non-isolated power conversion tapped inductor bucks, boosts, flybacks, and SEPICs do better than
the simple ( untapped ) bucks, boosts, flybacks, and SEPICs for applications with very small step up or
step down ratios and for applications with very large step up or step down ratios. These results are not
proven in this paper, but can be proven by the reader by applying the methods taught in this paper.
Another approach that has been proposed for wide line range non-isolated applicationsis are the quadrature
converters. The advantage of the quadrature converters is that they require only a single modulator to
operate over a wide line range, but they have high CSFs. With a dual modulator approach much lower
CSFs are achieved.
Copyright © Technical Witts, Inc., 2006. All rights reserved.
17
3. For some wide line range applications the combination of a boost sub-converter plus a dc transformer
sub-converter may provide results that are as good or better than what can be achieved by a single
converter topology.
4. Most isolated topologies are most efficient when operated in a range near 50% duty cycle. For full
bridge forward topologies efficiency is greatest when the duty cycle is 50% at the minimum line voltage.
For single ended flybacks and active reset forward converters greatest efficiency (lowest total SCSF) will
occur when they operate over a duty cycle range centered around a duty cycle of 50%. It should be
recognized that some converters, such as full bridge forward converters and some two switch flybacks and
forward converters, cannot operate above 50% duty cycle.
5. Boost converters will have efficiency greater than or equal to buck converters in any application where
either type of converter can be practically used. Buck converters have a total SCSF that varies little over
the line range. Boost converters have total SCSF that is about equal to the buck converter at minimum line
voltage but boost converters have much lower SCSF at maximum line voltage.
6. For non-isolated topologies ratios of line voltage to load voltage near 1 provide low CSFs, near zero in
some cases, while ratios much different than 1 provide relatively high CSFs. For isolated topologies the
relationship between line voltage and load voltage is inconsequential. Isolated topologies will always have
CSFs that are equal to or larger than what can be achieved with a non-isolated topology.
7. The assumptions made in the analysis for SCSF assumes a relationship between transistor voltage rating
and transistor on resistance that holds up well at medium and high voltages, but does not hold up well at
low voltage. The reader should re-examine any conclusions drawn from the analysis for applications with
operating voltages less than about 50 volts. In many situations there are alternate circuit topologies that are
roughly equivalent but operate at higher voltage and lower current. These should be preferred at lower
voltages.
8. The analyses based on CSF calculations provides the user with a set of three numbers that can be
compared to sets of three numbers for alternate candidate topologies. The analysis also yields a set of
compoents weights that specify how resources should be assigned to achieve optimal results. In some
cases one topology will have a set of CSFs wherein all three CSFs are equal to or lower than the other
candidates, but, more often, one topology will be superior for one component type and inferior for another
component type, so that the choice of the best candidate may not be obvious. In many cases the set of three
numbers achieved will depend on the parameters of the design such as the turns ratio of a transformer or
coupled inductor and varying the parameters enables the designer to improve CSF for one component type
at the expense of another component type. This paper has not provided a method to achieve a single
number for a topology for comparison purposes, although it is easy to imagine how the numbers might be
combined. The three CSF numbers could simply be summed. There are many other ways that a single
number can be achieved. The question remains as to how the three numbers can best be combined into a
single number. This subject will remain a topic for a future paper or article.
9. The methods taught in this article are methods that can be readily performed by a computer. The
creation of a computer program to calculate CSFs and to optimize designs intelligently based on CSF and
other considerations will be a valuable tool to the power supply design engineer.
Copyright © Technical Witts, Inc., 2006. All rights reserved.
18
Copyright © Technical Witts, Inc., 2006. All rights reserved.
19