Power MOS FET Attention of Handling Semiconductor Devices 1. R07ZZ0004EJ0200 (Previous: RJJ27G0013-0100Z) Rev.2.00 Aug 18, 2014 Selection of Semiconductor Devices Semiconductor reliability is remarkably affected by using conditions such as electronic circuits, mounting, environments, etc. In order to keep high reliability of our semiconductor devices for customer’s use important hints on selecting the maximum rating, derating, and device package are explained in this chapter. 1.1 Maximum Ratings The maximum ratings of a semiconductor device are usually defined by the “absolute maximum ratings” and can not be exceeded in any circumstances, even momentarily. For example, it is defined by the JIS C 7030 as follows: Note: “Absolute Maximum Ratings”: Absolute maximum ratings are limiting values of operating and environmental conditions being applied to any transistor, and are officially specified for each type of transistor. These limiting values have not to be exceeded under any worst conditions. These values are determined by transistor manufactures and assure enough ability of transistors as far as their absolute maximum ratings are not exceeded (Reference: JIS C 7030). If a device operates in excess of the absolute maximum ratings, even momentarily, the device may immediately be degraded or broken. Even if it goes on operating, its lifetime should be considerably reduced. Therefore, in designing an electronic circuit using semiconductor devices, it is necessary to consider that the maximum ratings of devices shouldn’t be exceeded under any changes of external conditions. Furthermore, it should be noted that most of ratings are closely related to each other and ratings are not always allowed at the same time. For example, even if a current and a voltage applied to a transistor are individually within their maximum ratings, the collector dissipation should also be kept within the maximum rating at the same time, because power consumption is the product of current and voltage. In addition to maximum D.C. ratings, it is necessary to consider ratings of ASO, loading locus, peak voltage, and peak current when devices are used in pulse condition. 1.2 Consideration about Derating It is a very important matter for high reliable design to decide the degree of derating from the maximum ratings. Derating of RENESAS semiconductor devices are already mentioned. Here it is noted that the derating items during system design, depending on the semiconductor device are electrical stress (voltage, current, power, load) environmental stress (temperature, humidity) and mechanical stress (vibration, shock). Table 1 shows some examples of derating standards to be used for reliability designs. Items for junction temperature are forecast to allow usage over ten years in intermittent operation for about three hours a day. Furthermore, the values in parentheses (“()”) are forecast to be conditions for high-reliability, allowing all-night around-the-clock operation over ten years. It is desirable to consider the derating standards during system designing for its reliability. Examples of improper deratings are shown in tables 2 and 3. R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 1 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 1 An example of a derating standard*1 Derating factors*2 Temperature Junction temperature Device ambient temperature Others Humidity Voltage Current Power Pulse*3 Notes: 1. 2. 3. Transistor Remarks 110°C or less (especially for high (Tj = 60°C or less) reliability application) — (especially for high (Ta = 0 to 45°C) reliability application) Consumption power, ambient temperature, heat radiation conditions Tj = PD × θja + Ta Relative humidity RH = 45 to 75% Others Printed circuit boards are coated in case of condensation by rapid change of temperature Tolerance voltage Max rating × 0.8 or less Overload voltage Make the proper preventive way for overvoltage, including breakdowns by static electricity Mean current IC × 0.5 or less Peak current iC (peak) × 0.8 or less Mean power Max rating × 0.5 or less ASO Not to exceed the maximum ratings specified in each catalog Surge iC (peak) or less Exclude special applications. Fill the requirements as many of these derating items as possible at the same time. For the transient state peak voltage, current, power and junction temperature including surges are normally limited by the maximum ratings and the averages of the above values are used for reliability derating. Since the ASO varies with the operating circuit, contact our engineering division when designing. Table 2 The hFE Down when Maximum Rating is Exceeded (Example 1) Description Transistor A high reverse voltage was applied between emitter and base of a transistor in the monostable multi-vibrator circuit while it is switching. Since the applied voltage exceeded the maximum rating, the low current hFE was down as shown in the graph. Degradation of hFE is shown by using VCC parameter in the circuit diagram. 36k 1k 0.05μ VCC 36k 0.05μ 1k hFE Drop rate (%) Item Device Details VCC = 6V 0 –40 12V –80 18V 500 1,000(hr) Countermeasures (1) Inhibition of break-down (Reduce VCC voltage). (2) Use another transistor with a higher emitter to base voltage tolerance. (3) Take a circuit margin for hFE. Classification Maximum rating R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 2 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 3 Short Circuit by ON/OFF Cycles (Example 2) Item Device Details Description Silicon power transistor (TO-3P) The silicon power transistor used in a power supply unit was operated for approximately 20 hours and 150 ON/OFF cycles per day. After one to two years’ operation, short circuit occurred between the collector and emitter. The ON/OFF cycles (PC) were too frequent, and accordingly, the junction temperature difference (Tj) rose 90°C and the number of ON/OFF cycles was 50,000 per year. The trouble cause was determined as ASO destruction due to the soldering fatigue between the chip and the heat sink. Countermeasures To derate ON/OFF cycles, lower the junction temperature difference to 50°C or less and improve radiation fins. If possible, design a system to reduce the number of ON/OFF cycles. Classification Derating 1.3 Selection of Package Type Package types are generally classified to two, one is the hermetic sealed type using metal or glass and the other is the plastic molded type. Selection of package types should be done with considering the purpose of system, environment, reliability, cost etc. The reliability of plastic molded-type semiconductor devices has been greatly improved. Recently, their applications have also been expanded to automobiles, measuring and control systems, and computer terminal equipment operated under relatively severe conditions. Actually, field application data has revealed that their trouble factors under favorable indoor environmental conditions are equivalent to those of the hermetically sealed type. 2. Precautions for Physical Handling There are considerable precautions when semiconductor devices are attached to circuits. In order not to impair the reliability of the semiconductor devices during installation, care should be taken in forming and cutting leads, mounting on to circuit boards, soldering, surplus flux removal, attaching to the heat sink, arrangement of component parts, circuit board coating, etc. 2.1 Forming and Cutting Leads When forming and cutting the lead wires of semiconductor devices, be careful of the following points: (1) When bending the lead wires, hold the lead wires securely between the package and the point to be bent with a pair of pliers. Then, bend them, holding the open end of the leads with your fingers, so that no bending stress is applied to the package, as illustrated in figure 1. Do not bend the leads by holding the package. The same consideration should be paid when many devices are simultaneously bent using lead forming machines (See figure 2). × Wrong Right Figure 1 Bending the Lead Wires R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 3 of 19 Power MOS FET Attention of Handling Semiconductor Devices W1 W2 W3 Lead forming mechanism t W1 Clamp mechanism Spaced (t) must be the necessary distance between the package and the clamp (W1) even if the leads are pulled toward W3. Figure 2 Bending the Lead Wires Using a Mould (2) When bending the lead wires at right angles, make the bend at least 3 mm away from the package end as illustrated in figure 3 (A). Do not bend them more than 90°. When they must be bent less than 90°, allow a space of more than 1.5 mm (See figure 3 (B)). (3) Do not repeatedly bend the leads. (4) Do not bend them sideways as shown in figure 3 (C). (5) Do not pull the leads with excessive force, to prevent the device from being broken. The prescribed tensile strength depends on their cross-sectional areas as already mentioned in RENESAS Reliability Hand book. (6) Take care not to use any improper jig or pliers for bending, since the surfaces in contact with the plated surfaces of the lead wires may be damaged. It is advisable to use a tool with a contact area of 0.5 mm radius. Table 4 shows an example of a lead forming failure. A B 3.0min 1.5min Right Right C D × Wrong × Wrong Figure 3 Places and Angles for Lead Wire Bending R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 4 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 4 An Example of Lead Forming Failure Item Device Details Description Power transistor (TO-220AB) Since the lead wires of the transistor were not securely held by the clamping tool, while the lead X Lead wire was being bent wires were loosened resulting in open circuit. Excessive stress was applied in the Transistor Clamping tool “X” direction and the internal bonding wire was Bent broken. Countermeasures Hold the lead wire firmly at a point between the place to be bent and the end of the transistor while being bent as illustrated. Also refer to paragraph 2.1. Classification Physical handling (lead forming and cutting) 2.2 Mounting on the Circuit Board Do not apply excessive stress to the lead wires of semiconductor devices when attaching them to the circuit board. Refer to figure 4. (1) Make installation holes on the circuit board at intervals corresponding to the distance between lead wires, so that no excessive stress is produced when mounting. (2) Do not force the lead wires through the holes during insertion. This will create excessive stress on the device. (3) Leave proper space between the device and the circuit board surface. Insertion of a spacer between them is recommended. (4) Do not apply any additional stress to the device already attached to the board. For example, if a device is connected to a heat sink after the leads of the device have been soldered to the board, stresses produced by small differences in lead wire length and component distance will be concentrated on the leads. As the result, problems like detached leads, broken packages, or broken bonding wires may occur. In order to prevent these accurately position the device first and solder the leads later. (5) Refer to paragraph 2.1 when automatic forming and soldering machines are used. × Wrong Right Semiconductor device Printed circuit board Same installation hole and lead spacing Right Semiconductor device Same installation hole and lead spacing Installation holes are positioned improperly × Wrong Printed circuit board Device is smoothly inserted into the board by a gentle push. A lead wire is pulled from the bottom with pliers Figure 4 Mounting Method to Printed Circuit Boards R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 5 of 19 Power MOS FET 2.3 Attention of Handling Semiconductor Devices Soldering It is not good in general to leave semiconductor devices at high temperatures for a long term. Regardless of the soldering method, whether it may be a soldering iron or the flowing solder method, soldering must be done in the shorter time and at the lowest temperature possible. Your soldering work must meet test conditions of soldering heat, tolerability, namely, 260°C for 10 seconds and 350°C for 3 seconds at a point 1 to 1.5 mm away from the end of the device. An example of junction temperature increasing curves during soldering obtained from a plastic package small power transistor is shown in figure 5. These data were measured after dipping the transistors into the soldering baths at 260°C and 350°C, respectively, for the prescribed periods. If transistors are soldered at temperatures or periods of time exceeding the ratings, their temperature rises and may be degraded or in the worst case broken. Use of a strong alkali or acid flux may corrode the lead wires, deteriorating device characteristics. The recommended soldering iron is the type that is operated with a secondary voltage supplied by a transformer and grounded to prevent current leads. (See figure 6). Try to solder the lead wires at the farthest point from the device surface. 260°C soldering bath Pick up 200 Exposed to air Junction temperature (°C) Junction temperature (°C) 200 Transistor 100 1.5mm Solder 0 260°C 20 40 60 80 100 140 180 Time (sec.) 240 Exposed to air 100 Transistor 1.5mm Solder 0 300 350°C soldering bath Pick up 10 20 30 350°C 10 20 40 50 30 60 Time (sec.) Figure 5 Junction Temperature Curves During Soldering AC 100 V C 24 V Soldering tip 1 MΩ A soldering iron which has no leak current at tip, and does not induce electric potentials and grounded is recommended. Figure 6 Recommended Soldering Iron 2.4 Removing Residual Flux To ensure the reliability and lifetime of electronic systems, residual flux must be removed from circuit boards. Detergent or ultrasonic cleaning is usually applied. If cholorous detergent is used for the plastic molded devices, package corrosion may occur. Since cleaning over extended periods or at high temperatures will cause swollen chip coating due to solvent permeation, pay special attention to these precautions prior to determining the type of detergent and cleaning condition. (Isopropylalkohol is recommended as a detergent with respect to dissolution and toxicity.) Do not use any trichloroethylene solvent. For ultrasonic washing, the following conditions are advisable: R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 6 of 19 Power MOS FET • • • • Attention of Handling Semiconductor Devices Frequency: 28 to 29 kHz (to avoid device resonation) Ultrasonic output: 15W/l (once) Do not allow the devices to contact the generator source directly. Washing time: Less than 30 seconds Table 5 shows an example of a detergent problem. Table 5 Example of Detergent Problem (Example 4) Item Device Details Description Power transistor (TO-220AB) Plastic molded power transistors were rinsed in an organic solvent for extended periods. The solvent entered through a gap in the header and the plastic reacted with the internal chip coat, and the swollen chip coat resulted in wire breakage. Countermeasures Modification of cleaning method (Cleaning period was reduced to not more than 30 sec.) Classification Handling (rinsing) 2.5 Mounting to the Heat Sink The heat sink is normally used to radiate heat from the power device preventing a rise of the junction temperature. Semiconductor devices must be mounted carefully to the heat sink so that heat is efficiently radiated and the semiconductor reliability is not impaired. (1) Use a suitable silicon grease In order to improve heat radiation efficiency by increasing the heat conductivity from the transistor to the heat sink, a thin layer of silicon grease is evenly applied to the contact surfaces before they are coupled together. There are some types of silicon grease which penetrate the transistor and swell internal chip coat. To prevent chip coat swelling, a special oil featuring outstanding oil separation and excellent permeation to the mold resin is employed. Use G746 (Shinetsu Chemical Industry Co., Ltd.) or its equivalent. Use of other grease may not be guaranteed. Note that the resin will crack during screw tightening when employing a high-viscosity silicone grease. An excessive amount of grease may cause excessive stress, except for metal-enclosed semiconductor devices. Table 6 shows trouble which occurred due to improper silicone grease. (2) Tighten the package with the proper torque If the tightening torque is too loose, thermal resistance will be increased. On the contrary, if it is too tight, the device will be distorted and its pellet and lead wires may be broken. To avoid such troubles, apply proper torque to tighten the package according to the torque range listed in table 7. For your reference, figure 7 and figure 8 show the relation between thermal resistance and insulator thickness, or tightening torque, respectively. Table 6 Chip Coating Resin Swollen by Silicone Grease (Example 5) Item Device Details Description Power transistor (TO-220AB) To obtain better heat radiation through reduction of thermal resistance between the device and the heat sink, silicone grease is applied to their mating surfaces. The oil contained in the silicone grease was aborded in the chip coat resin, thus swolling and breaking the package. This type of trouble occurs with dimethyl system silicone oil. Shinetsu G 746 silicone grease is recommendable to prevent swelling. Swelling is promoted by power applied to the device during operation. Countermeasures When silicone grease is used for devices whose chips are coated with resin, the undermentioned silicone grease is recommended to prevent swelling: G 746 manufactured by Shinetsu Chemical Ind. Co., Ltd.. Classification Handling (improper grease) R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 7 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 7 Optimum Tightening Torque for Typical Packages External forms TO-220 TO-220FM, TO-220CFM TO-3P, TO-3PL TO-3PFM TO-3PL Thermal resistance of insulator (including contact thermal resistance) θc+θj (°C/W) Optimum torque (N•m) 0.4 to 0.6 0.4 to 0.6 0.6 to 0.8 0.4 to 0.6 0.6 to 0.8 4.0 (0.6N•m) lar My 3.0 Without silicone grease 2.0 r Myla Mica 1.0 0 a Mic 0.05 Silicone grease applied 0.10 0.15 0.20 Thickness of insulator d (mm) Figure 7 Relation between Thermal Resistance and Insulator Thickness Contact thermal resistance θc (°C/W) 1.0 0.8 Without silicone grease 0.6 0.4 Silicone grease applied 0.2 0 0.2 0.4 0.6 0.8 Tightening torque (N•m) 1.0 Figure 8 Relation between Contact Thermal Resistance and Tightening Torque R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 8 of 19 Power MOS FET Attention of Handling Semiconductor Devices An example of a package broken during installation is shown in table 8. (3) Heat sink flatness If heat sinks don’t properly match with the semi-conductor device, they may fail to radiate heat, or deterioration of characteristics and the crack of regin results in abnormal stress. When mounting the device on a heat sink, observe the following precautions: (i) Do not allow the heat sink to bend upwards, downwards, or twist to such an extent leaving more than 0.05 mm from the screw holes of the header. (ii) Check to ensure that aluminum, copper, or iron plate edges are smooth without burrs and that all screw holes have been chamfered. (iii) The surface of the heat sink in contact with devices must be polished flat. (iv) Make sure that metallic chips or foreign matter is not left between the heat sink and the header. (4) Inhibition of direct soldering to the radiation fin of the device. If the radiation fin of the transistor is directly soldered, junction temperature will rise far above the rating and the device may be broken or its lifetime is remarkably reduced. Table 8 Package Broken by Installation (Example 6) Item Device Details Description Power transistor (TO-220AB) When the transistors were mounted, a torque larger than 10 kg.cm was accidentally applied by a pneumatic screwdriver. Also, since excessively large installation holes were provided on the heat sink, the mating surfaces of the header and plastic were separated. Some pneumatic screwdrivers increase their torques. Should a torque exceed 8 kg.cm, should the mounting holes on the heat sink be larger than the screw head, or should the surface around the mounting holes be uneven, the header may be distorted and the header become separated from the plastic. Countermeasures Do not apply excessive torque. Recommended torque for the TO-220 type is between 4 and 6 kg.cm. Flatness of the heat sink surface shall not exceed 50 µm. Never drill mounting holes larger than the screw head. Also, be sure to use the provided washers (YZ033S) Classification Handling (Mounting) (5) Don’t stress the package mechanically If a screw driver or fastening jig hits the plastic package while tightening the heat sink, not only the package may be cracked but the mechanical stress may be transmitted to the inside of the device and wire fatigue may result in breakage or disconnection. (6) Don’t mount devices to a heat sink after soldering them If a device is mounted on a heat sink whose lead wires have already been soldered to the circuit board, excessive stress will be concentrated on the lead wires due differences in lead wire length and distance between the heat sink and the device on the board. This may cause the loosened lead wires, package damage, or disconnection of a bonding wire. Therefore, solder the lead wires of the device after mounting it on a heat sink. (7) Do not cut or change the shape of the radiation fin and package of the device. Do not cut or modify the radiation fin and package of the device under any circumstances, in order to prevent any increase in thermal resistance or abnormal stress. R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 9 of 19 Power MOS FET Attention of Handling Semiconductor Devices (8) Use the recommended parts (spacer, washer, lug terminal, screw, nut, etc.) for the power device installation (see figure 9). TO-220AB type TO-3P type Screw (3φ) Screw (3φ) Metal washer Metal washer Metal spacer (YZ033 S) Insulator (SK16B) Insulator (SK022A) Heat sink Heat sink Insulation washer Metal washer Metal washer Spring washer Nut (3φ) Spring washer Nut (3φ) Figure 9 Examples of Power Transistor Installations (9) Use only suitable screws Machine screws and tapping screws are used to mount the heat sink on the transistor. Observe the following precautions: (i) Use binding-head screws, truss-head screws (JIS-*B1101, Slotted-head Machine Screws), or their equivalent. * Japanese Industrial Standards (ii) Do not use flat head screws which cause abnormal stress in the device (see figure 10). (iii) Apply the proper torque to tighten the tapping screws listed in table 8. (iv) When a tapping screw is used, use only a screw with a diameter small than the installation hole of the device, so that the device is not tapped while tapping the heat sink. (10) Diameters of heat sink screw holes (i) If diameter is too large: Do not make or chamfer a diameter of screw hole on the heat sink larger than that of the head of the screw to be passed. Especially, take care when mounting a device using a copper flange (TO-220AB, TO-3P etc.) on a heat sink, because the copper flange and plastic package are easily deformed by the tightening torque. (ii) If diameter is too small: When a tapping screw is inserted, excessive torque may be applied to heat sinks or a desired contact thermal resistance may not be obtained. (11) Other precautions and recommendations for heat sink installation (i) When two or more devices are attached to same heat sink, the thermal resistance of each device is increased (see figure 11). (ii) Heat sink must have a suitable shape and dimensions for efficient radiation. Use a forced air-colling device etc., if necessary (figure 12 and figure 13). Binding-head Screw Truss-head Screw (Use round-head screws, panhead screws, truss-head screws, binding-head screws, or flat fillister-head screws.) Figure 10 Types of Recommended Screws R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 10 of 19 Power MOS FET Attention of Handling Semiconductor Devices Junction temperature ΔTj (°C) 120 100 es 80 vic 2 de 60 e vic 1 de 40 20 0 5 10 15 20 25 30 Collector dissipation (W) Notes: (1) Heat sink, aluminium plate (mm) 300 × 200 × 1.5 (2) Method of installation: (a) Position: As illustrated (unit: mm) 200 300 70min (b) Tightening torque: 9 kg•cm. (c) Silicone oil was applied to the contact surface and mylar was not used. (d) Natural ventilation, horizontal position Heat sink thermal resistance (°C/W) Figure 11 Thermal Resistance with 2 Devices on a Heat Sink 20 Natural ventilation, Horizontal position 10 Aluminium plate (1.5mm thick) 5 Copper plate (3mm thick) 2 1 20 50 100 200 500 1,000 Heat sink area S (cm2) Figure 12 Relation between the Heat Sink are and Thermal Resistance Table 9 Characteristic Failure Caused by Temperature Increase (Example 7) Item Device Details Description Transistor A transistor mounted just above a heat generating component changed its biased point caused by the temperature increase. The instrument resulted in a failure. Countermeasures Relocate the transistor to a well ventilated position. Classification Handling (component parts positioning) R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 11 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 10 Noise Failure in Poor Environments (Example 8) Description Small signal transistor Dust on the external surface of a transistor mounted in the differential pre-amplifier unit of an audio frequency amplifier caused deterioration of the insulation between the terminals. As the result of this, the transistor generated noise. It was positioned in the dusty place of system. Countermeasures (1) Relocate the transistor to a cleaner place. (2) Coat the printed circuit board with resin. Classification Handling (Component parts positioning) Thermal resistance θj-a(°C/W) per device between junction and air Item Device Details 8 6 4 2 Transistors 2 0 1 Transistor 2 4 6 8 10 Air velocity (m/s) Notes: 1. Insulator was not used and silicone oil was applied to the contact surface. 2. Ventilation: As illustrated Air current direction Figure 13 Thermal Resistance with Forced Air-cooling 2.6 Positioning of Component Parts Reliability and characteristics of semiconductor devices are remarkably affected by operating environments. Therefore, it is not only important to exam operating temperatures and the heat radiation methods, but also the positioning of each semiconductor devices in the system, to obtain high reliability. Improper positioning of a semiconductors are as follows: (1) By heat generators such as large resistors, the heat sink or semiconductor device itself may be heated. A device in such a location may have its reliability reduced because of abnormal heat (see table 9). (2) High voltage circuit and corners on the bottom of instrument may sometime be dusty. Insulation of devices will be deteriorated by dust. This can be prevented by coating the semiconductor device and printed circuit board with water-proof resin (see table 10). Coating applied to the printed circuit board is an extremely effective means of improving system reliability. For example, such coating prevents misoperation caused by short circuit between the printed circuit board wiring and the semiconductor terminals due to deposited conductive materials, noise caused by deposited dirt and moisture absorption, trouble caused by overcurrent, and metallic migration (Ag migration) due to condensed moisture or other adverse environmental conditions. For systems operated under adverse environmental conditions such as high humidity, condensed moisture, and a dusty atmosphere, the printed circuit boards shall be coated to ensure long-term, trouble-free service. (3) In high voltage or high frequency equipment, surge voltage may be induced to semiconductors depending on the method of wires bundling and path of connecting wires. Take care not to expose the semiconductors to such conditions. Refer to paragraph 3.2. R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 12 of 19 Power MOS FET Attention of Handling Semiconductor Devices (4) When installing the test terminals in the printed circuit board, carefully select its position in order to be free from any abnormal voltage source, during maintenance and service. 3. Mounting Precautions To make reliable circuits, it is necessary to consider the applications of derating and safety allowances for possible fluctuations of characteristics during operation, in addition to the satisfaction of initial device ratings incorporated. The problems to be taken up, for making reliable circuits, are methods of wiring, external surge, reactive load, noise margin, area of safety operation (ASO), reverse bias, fly-back pulse, static charge, pulse stress, and others. 3.1 General Precautions The important things to assure the reliability of system are: Use them within the maximum ratings specified in the brochure, and pay special attention to the operating environments detailed below. (1) Try to lower ambient temperatures in semiconductors. (2) Operate the semiconductors within the prescribed ratings for power voltage, input voltage, and power consumption. Also, apply deratings. (3) Take care not to allow any induction voltage or overvoltage, accompanied by noise, to the input, output, or power source terminals. Also, care must be used not to let strong electromagnetic waves affect semiconductors. (4) Try to prevent electrostatic charges. (5) Since high-speed devices are made using fine patterns add a protective circuit on the input, or modify the circuit so that it is not impressed by static-electrical pulses. (6) Take care not to impress unbalanced voltage of ON/OFF power. If a power voltage is applied to the input or power terminals whose grounding terminal is floating, excessive stress will be put on the device. 3.2 Noise and Surge Countermeasures The problems of surge voltage, static charge, and noise are common to all semiconductor devices and the necessary countermeasures should be taken to eliminate the causes of these problems. In general, electronic equipment is designed considering about a 10% voltage fluctuation from commercial electric power-sources. However, if any equipment which produces surge voltage is operated in the near area, it may cause failures and malfunctions in other electronic equipment through line voltage. The similar type of noise in the form of pulse is also produced in the power supply lines by thunderbolt. To reduce the influence of line surges, it is useful to connect a filter to the A.C. input line as shown in figure 14. If there is a possibility that the component parts or semiconductors in the circuit will directly be exposed to a surge or static charge, a shielding system must be provided. When installing a shielding circuit, make sure that the ground impedance is low enough. If there is a possibility that a static charge or surge pulse will be applied to the devices in the form of noise, a protective circuit shown in figure 15 may be connected, in special cases. In this circuit, a suitable value of Ri × Ci Time Constant must be determined to absorb surge noise without affecting circuit operation. L1 C AC100V L2 Primary (P) Secondary (S) Figure 14 An Example of a Surge Absorption Circuit R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 13 of 19 Power MOS FET Attention of Handling Semiconductor Devices Object circuit (Semiconductor device) External surge External noise R1 Separate circuit R2 R3 C1 External surge External noise C3 C2 Ri Ci is determined depending an operating conditions. Figure 15 An Example of a Protection Circuit for Surge Table 11 Breakdown Caused by Surge Voltage (Example 9) Item Device Details Description Transistor During electronic equipment assembly, a transistor emitter was shorted to its base. It was found that a discharge in the high-voltage circuit induced a surge voltage, breaking the transistor. Countermeasures (1) To absorb the surge voltage, install a resistor in series or a C.R. (2) Insulate the high-voltage circuit. (3) Add a bypass circuit for high-voltage. Classification Mounting (Protection from surge) Table 12 Transistor Breakdown in a Strong Magnetic Field (Example 10) Item Device Details Description Transistor The transistor emitter in the control circuit was shorted to the collector due to noise induced in the signal line. Due to the fact that the equipment was operated in a strong magnetic field and the signal line was extended too far, noise was induced. In addition, the noise protection system was not sufficient. Countermeasures (1) Connect a capacitor between base and emitter. (2) Shield the signal line which passes through the strong magnetic field. Classification Mounting (noise) 3.3 Relation between Characteristic Parameters and Reliability Characteristic parameters and their required ranges for each semiconductor device are fixed according to function and application. The importances of these parameters are sometimes different in designing systems. Cares must be needed for important parameters, for instance taking a margin of initial characteristic or considering a derating. With regard to take a margin, it is important to choose a device with considering the operating limit of system or to apply the statistical designing method, or to design with considering the value of failure judgement already mentioned in chapter 2. Parameter changing is little in use. Therefore in general it is allowable to design using initial characteristic values. R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 14 of 19 Power MOS FET Attention of Handling Semiconductor Devices Cares mentioned above should be taken when parameters are very important for system margin. The following points are essential for parameter assessment: (1) Is the parameter important? Does it cause the system failure? (2) Consider the initial value margin of the parameter. (3) Does it vary with time or not? If yes, does it fluctuate in an allowable direction? (4) Is the fluctuation allowable or not in relation to other devices being used? (5) Is their redundancy in the design? (6) Is it possible to employ a statistical designing method for the parameters? 4. Reliability test methods and failure determination criteria for semiconductor devices The reliability test methods currently employed in the industry to check the reliability of semiconductor devices vary depending on the purposes of the tests. Moreover, when performing a reliability test, what need to be determined first should be the definitions of defects and failures (failure determination criteria). Outlined below are the reliability test methods and the failure determination criteria for discrete components. 4.1 Reliability test methods (1) When performing a reliability test, an appropriate test method should be chosen, proper test conditions should be selected and reliable determination criteria should be set out fitting to applications of the product or to the purposes of the test. For example, if a test is meant to find out the limits or if a test is meant to determine if a product conforms to the specifications would require different test plans, respectively. What to use as the failure detection mode should also be important and the environmental factors relevant to the structures, production processes and using conditions of respective devices, means "stress", should normally be used as the failure detection mode. Meanwhile, such stress can be singular or multiplex depending on the circumstances. When applying multiplex stress, it is necessary to consider the actual using environments. Upon the above prerequisites, objectives of implementing the reliability tests should be to make accurate presuppositions and to contribute to enhancement of the reliabilities of the object devices. For this purpose, it becomes necessary to accumulate the accomplishments of various reliability tests and to feed back the failure analysis results. (2) While, as the reliability tests, tests under the actual using conditions should be ideal but, in majority of the cases, it becomes extremely difficult to acquire accurate and sufficient data within the limited time and costs. Consequently, it is necessary to simulate them as far as feasible. In such cases, although stress conditions not as far as causing breakage will usually be selected as the stress strength, depending on the circumstances, stress conditions causing breakage may sometimes be applied intentionally to cause failures in an earlier stage for the failure analysis purposes. Meanwhile, from the viewpoint of reproducibility of the reliability tests, standardized test methods should also become necessary. The EIAJ Standard, JIS Standard, IEC Standard, MIL Standard, etc. prescribe these test methods. They are exemplified in Table 13 below, listing their typical reliability test standards. Table 14 exemplifies the results of reliability tests conducted for a discrete component and Table 15 exemplifies the failure determination criteria for reliability tests for discrete components for your reference, respectively. R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 15 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 13 Typical reliability test standards JEITA (Japan Electronics and Information Technology industries Association) Standards JEITA ED-4701: Environmental and durability test methods for semiconductor devices JIS (Japan Industrial Standard) Standards JIS C7021:Environmental test methods and durability test methods for individual semiconductor devices JIS C7022:Environmental test methods and durability test methods for integrated circuits of semiconductors IEC (International Electrotechnical Commission) Standards Publication 68: Environmental test methods Publication 749: Mechanical test methods and environmental test methods for semiconductor devices MIL (U.S. Military Standard) Standards MIL-STD-202F: Test methods for electronic parts and electric parts MIL-STD-750C: Test methods for individual semiconductor devices MIL-STD-883D: Micro-Electronics test methods R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 16 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 14 Exemplified test results of 2SK1170 Categorization Mechanical tests Test items Natural drop test Vibration fatigue test Constant acceleration test Impact drop test Terminal pulling test Terminal bending test Environmental tests Life tests Temperature cycling test Withstand soldering heat test Solderability test Temperature cycling life test Pressure Cooker Test Continuous high temperature test Continuous low temperature test High temperature reverse bias test Operating life test High-temperature, high-humidity test High-temperature, high-humidity reverse bias test Intermittent operation test R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Test conditions h = 75cm Onto a maple board. For 3 times. f = 60Hz, 196m/S2, for 32h in the X, Y and Z-directions. 196000m/S2,1 min / in the X, Y and Z-directions. 14700m/S2, 0.5ms. For 3 times / in the X, Y and Z-directions Load: 25N, Tensile stress for 30 sec. Load: 10N, Bending by 90° to a single direction for 2 times. Ta = –55°C to +150°C, for 10 cycles. Numbers of defectives/Numbers of samples 0 / 1152 0 / 22 0 / 22 0 / 22 0 / 22 0 / 22 0 / 1152 T = 260°C, dipping the lead for 10 sec. 0 / 22 T = 230° ± 5°C, for 5 sec. to see if solder covers 95% or more of the surfaces. Ta = –55°C to +150°C, for 200 cycles. Ta = 121°C, for 96h. Ta = 150°C, for 1,000h. 0 / 22 0 / 22 0 / 22 Ta = –55°C, for 1,000h. 0 / 22 Ta = 150°C, VDSS = 500 V, for 1,000h. 0 / 22 Ta = 25°C, Tch = 150°C, for 1,000h. Ta = 85°C, RH = 85%, for 1,000h. 0 / 22 0 / 22 Ta = 85°C, RH = 85%, VDSS = 500 V, for 1,000h. 0 / 22 ΔTc = 90°C, for 10,000 cycles. 0 / 22 0 / 22 Page 17 of 19 Power MOS FET Attention of Handling Semiconductor Devices Table 15 Exemplary failure determination criteria for reliability tests for a discrete component Test items Electrical Breakdown voltage characteristics Leak current | yts |, hFE rate of change VDS(on) VCE(sat), VBE(sat) Vth Open circuit and shorting Appearance and others Failure determination criteria (Note) Lower limit Upper limit L ×0.8 — — U×2 –30 +30 — U × 1.2 Units V μA % V L × 0.8 U × 1.2 V — The open circuit, semi-open-circuit, shorting and semi-shorting include high-temperature and low-temperature failures. Airtightness leak test Major leakage / Minor leakage — Appearance According to the limit samples According to the limit samples Rusting and discoloration Solderability According to the limit samples Marking According to the limit samples Notes: U: Upper limit of the initial specification L: Lower limit of the initial specification R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Remarks Applicable to airtightsealed devices — — — — Page 18 of 19 Power MOS FET Attention of Handling Semiconductor Devices Website and Support Renesas Electronics Website http://www.renesas.com/ Inquiries http://www.renesas.com/contact/ All trademarks and registered trademarks are the property of their respective owners. R07ZZ0004EJ0200 Rev.2.00 Aug 18, 2014 Page 19 of 19 Revision History Rev. 1.00 2.00 Date Aug. 18, 2004 Aug. 18, 2014 Description Page Summary ̵ First edition issued P.1 1.2: Text addition P.2 Table 1: Amended of Relative humidity A-1 Notice 1. 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