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Multiplier–Free Lagrange Interpolators for Oversampled D/A Converters
F. Francesconi (1), G. Lazzari (2), V. Liberali (1), F. Maloberti (1), and G. Torelli (1)
(1) Dipartimento di Elettronica, Università di Pavia
Via Abbiategrasso, 209
27100 Pavia, Italy
(2) Genova Ricerche
Via dell'Acciaio, 139
16152 Genova, Italy
Abstract – This paper presents a novel approach to
implement the interpolation function by means of
Lagrange interpolators. The proposed architecture does
not require high-frequency multipliers. With respect to
conventional sinc filters of a comparable order, the
response of Lagrange interpolators is better both in the
passband and in the stopband, while the proposed implementation requires only a small increase in circuit
complexity.
I. I NTRODUCTION
VLSI systems are made up of analog and digital sections.
Since they are put on the same chip, robust analog solutions
must be used. For the A/D and D/A conversion functions,
the oversampled noise-shaping technique is one of the most
commonly used [1]. The complexity of the analog part is
heavily reduced at the expense of an increase in the complexity of the digital signal processing (DSP) part.
The digital section includes a multirate filter (a decimator
for an ADC and an interpolator for a DAC, respectively).
When a high resolution is required, as in audio applications,
the size of the digital part becomes remarkable. Suitable
circuit techniques have to be adopted for commercially viable
solutions. In particular, the number of digital multipliers
must be reduced, since they are the most area consuming
blocks.
This paper proposes a VLSI architecture suitable to implement the interpolation function with Lagrange interpolators.
The frequency response of a Lagrange interpolator is better
than the one of a sinc filter having the same order. However,
Lagrange interpolators are rarely used in high-frequency
systems because their direct implementation is computationally expensive. The presented architecture implements
the interpolation function with reduced circuit complexity,
avoiding high-frequency multipliers. Moerover, in specific
This work was carried out under the financial support of the
Italian National Research Council (C.N.R.) in the frame of the Telecommunications Project.
cases such as the third order interpolator, no general multiplier at all is needed.
II - C ONVENTIONAL SOLUTIONS
The conventional approach to interpolation and decimation
in D/A and A/D sigma-delta converters involves a cascade of
finite impulse response (FIR) digital filters. Generic FIR
filters are used at a lower rate, while at higher frequency sinc
filters are usually preferred due to their very simple implementation.
The coefficients of a sinc filter can be generated iteratively,
thus avoiding the need for storing them in a ROM. Alternatively, as proposed in [2], the sinc function can be obtained
by means of a cascade architecture including integrators and
differentiators, which do not require the use of multipliers, as
shown in Fig. 1. This feature is very significant when very
high operation frequency is required.
However, the simplicity of sinc filter structures limits their
frequency performance. In the upper edge of the passband,
an attenuation is introduced which depends on the order of
the filter. An equalization stage is required to compensate
the passband ripple, thus imposing a trade-off between the
order of the sinc filter and the complexity of the FIR filter.
More accurate solutions require complex circuitry and
therefore are rarely considered for high frequency operation.
III - LAGRANGE INTERPOLATION
The Lagrange interpolating function is the n-th order
polynomial passing through n + 1 input samples. We will
denote the period of the input sequence with T, and the
period of the output sequence with T'. The input sequence
will be indicated with x[mT], and L = T/T' is the interpolation
factor.
The sequence at the output of an n-th order Lagrange interpolator can be expressed by:
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Digital differentiators
+
+
+
In
–
z–1
–
z–1
–
z–1
Digital integrators
+
+
+
+
Interpolation
+
z–1
Low frequency section
Out
+
z–1
z–1
High frequency section
Fig. 1. Block diagram of a sinc3 filter.
y[mT + kT'] = c n [mT] · kn + cn–1[mT] · kn–1 +
+ … + c1[mT] · k + c0[mT] (1)
p0 [k] = 1
p1 [k] = k
for k = 0, 1, 2, …, L – 1. The coefficients {ci [mT]} must be
evaluated from the input sequence at each clock period T, by
imposing the following conditions:
y[rT] = x[rT]
for m –
n–1
n+1
≤r≤ m+
.
2
2
Let us introduce a new basis {pi [k]} for the generation of
Lagrange polynomials:
y
x[(m+1)T]
x[mT]
x[(m–1)T]
(m–(n–1)/2)T
(m–1)T
mT
(m+1)T
1 3 1 2 1
k + k + k
6
2
3
É
For i > 0, the generic term pi [k] can be expressed with binomial coefficients:
 0
pi[k] =  i + k – 1

i
(
for k = 0
)
(3)
for k > 0
Fig. 3 shows an easy way to generate the basis {pi[k]}, by
cascading n digital integrators. Each integrator is reset at
k = 0.
Using the basis {pi [k]}, we can write the interpolated
signal as follows:
y[mT + kT'] = An [mT] · pn [k] + An–1[mT] · pn–1[k] +
+ … + A1 [mT] · p1 [k] + A0 [mT] (4)
IV - FILTER I MPLEMENTATION
x[(m–(n–1)/2)T]
p3 [k] =
(2)
Fig. 2 illustrates these concepts.
In order to obtain a symmetrical impulse response (and
thus a linear phase), an odd-degree polynomial must be considered, taking the interpolated values in the central interval
[3].
A direct implementation of (1) would require the evaluation of the coefficients {ci [mT]} at each clock period T, and
tha calculation the scalar product of the coefficient vector by
the basis {1, k, k2 , k3, …, kn} at each clock period T'.
The computational effort required by this implementation
makes it unsuitable for high-frequency operation, since parallel structures would be necessary for multipliers. An architecture with reduced complexity will be presented in the next
section.
1 2 1
k + k
2
2
p2 [k] =
where the new coefficients A0 [mT], …, A n [mT] must again
be calculated at each clock period T using (2) (Fig. 4).
Fig. 5 shows a block diagram for the direct implementation
of (4). The architecture in Fig. 5 is still difficult to implement because it needs multipliers. However, it is possible to
modify this scheme by applying the rules of block transposition, thus obtaining the new configuration illustrated in
Fig. 6. In this architecture, high-frequency multiplications
x[(m+(n+1)/2)T]
(m+(n+1)/2)T
t
1
1
1 – z –1
p1 [k]
1
1 – z –1
p2 [k]
1
pn [k]
1 – z –1
mT+T' mT+2T'
Fig. 2. Time domain representation of Lagrange interpolation.
Fig. 3. Scheme of the circuit for the generation of the basis {pi[k]}.
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1
1–
Clock T
x[(m–(n–1)/2)T]
A 0 [mT]
x[mT]
A0 [mT]
p 1[k]
1
z–1
pn [k]
A2 [mT]
An [mT]
A 1 [mT]
COMBINATIONAL
LOGIC
Σ
An [mT]
x[(m+(n+1)/2)T]
y[mT+kT']
Fig. 5. Scheme for the implementation of a Lagrange interpolator.
Fig. 4. Generic scheme for the calculation of coefficients.
are removed at the expense of a larger number of integrators.
Multiplications are required only in the evaluation of coefficients Ai [mT], which is performed at a low rate. The circuit
complexity of the high-frequency section is heavily reduced.
V - DISCUSSION
A large number of D/A converters presented in the literature use a second-order noise shaper [4], [5], and therefore the
last interpolation stage is realised using a sinc3 filter. We
Low frequency section
1/T
A0 [mT]
1
1 – z–1
z–1
1–
A1 [mT]
p 2[k]
1
A 1[mT]
z–1
A n[mT]
A2[mT]
z–1
1 – z –1 Reset 1
Σ
z –1
1 – z –1 Reset 1
1 – z –1 Reset 1
z–1
1 – z –1 Reset 2
Σ
High frequency section
1/T'
z –1
1–z
–1
Reset n
Σ
y[mT+kT']
Fig. 6. Multiplier-free architecture for the implementation of a Lagrange interpolator.
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1.1
10 2
3rd order Lagrange
1.05
1
10 -1
sinc3
10 -4
3rd order Lagrange
1
0.95
sinc3
0.9
10 -7
0.85
0
2Π
Normalized frequency
0
Π/4
Π/2
Normalized frequency
Fig. 7. Comparison of the frequency responses of the sinc 3
interpolator and the third-order Lagrange interpolator.
Fig. 8. Comparison of the baseband frequency responses of the
sinc3 interpolator and the third-order Lagrange interpolator.
will compare it with a third-order Lagrange interpolator.
We have demonstrated [6] that for the third-order Lagrange
interpolator the coefficients Ai [mT] can be calculated using
only power-of-two multiplications, thus obtaining an implementation which requires no general multiplier even in the
low-frequency section.
In order to evaluate the architecture complexity, consider
that the same building blocks are required to implement a
digital integrator or a digital differentiator with a parallel
configuration, namely one parallel register and one parallel
adder. A sinc3 filter (Fig. 1) requires three integrators and
three differentiators, for a total complexity of six registers
and six adders. The third-order Lagrange interpolator shown
in Fig. 6 requires six integrators and three adders, with a total
count of six registers and nine adders. The control logic required for the two structures is similar. The additional logic
needed by the Lagrange interpolator to calculate coefficients
Ai is not a critical one, as it does not require any multiplier
and operates at low frequency. Therefore, we can conclude
that the complexity of a third-order Lagrange interpolator is
slightly larger than the one of a sinc 3 filter.
In Fig. 7, the frequency responses of the third-order
Lagrange and sinc3 interpolators are compared. Their baseband responses are shown in Fig. 8 with an enlarged scale.
The Lagrange interpolator displays a slightly better attenuation in the stopband, and a much flatter response in the passband. Therefore, in several applications the use of a Lagrange interpolator permits equalizing stages to be avoided in the
interpolation chain.
ge interpolation, suitable for VLSI integration. The proposed
topology needs no high-frequency multiplication, thereby
leading to reduced circuit complexity. In the specific case of
a third-order interpolator, the scheme can be implemented
completely avoiding the use of general multipliers.
The Lagrange interpolator has been proven to have better
performance than the sinc3 interpolation filter both in the
baseband and in the stopband. The proposed architecture for
Lagrange interpolation can be used in applications that are
conventionally covered by sinc n interpolators, such as
oversampled D/A converters, thus improving system
performance at the cost of a small increase in circuit
complexity.
VI - C ONCLUSION
In this paper we have presented a new scheme for Lagran-
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[6] F. Francesconi, G. Lazzari, V. Liberali, F. Maloberti, and
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