Design of an Integrated Switched-Capacitor Filter
Jens Pejtersen
March 3, 2008
Abstract
The design of a fully differential integrated Switched Capacitor (SC) third order Butterworth low pass filter is described. The filter is designed to have a corner frequency
of 1 MHz and unity passband gain. The filter is realized as a cascade of a first order
filter and a second order filter. The filter is implemented using a 0.35 µm CMOS
process in Cadence Virtuoso. The discrete time z-domain transfer functions is first
designed to satisfy the performance requirements. These are used to calculate the capacitor ratios required to realize the desired filtering functionality. All the necessary
components required to realize a SC filter are designed and combined in the implementation of the filter. Finally the performance of the designed filter is simulated
using the Spectre RF simulator.
i
ii
Resumé
Designet af et fuldt differentiabelt integreret Switched Capacitor (SC) trejde orden
Butterworth low pass filter bliver beskrevet. Filteret er designet til at have knækfrevens ved 1 MHz og enhedsforstærkning. Filteret realiseres som en kaskade af et
første ordens filter og et andet ordens filter. Filteret implementeres i en 0.35 µm
CMOS process i Cadence Virtuoso. Filteret bliver først designet som z-domæne
overføringsfunktioner, der opfylder kravspecifikationen. Disse overføringsfunktioner
bruges til at beregne de kapacitor-forhold, der kræves for at kunne realisere den
ønskede filterfunktion. Alle de nødvendige komponenter, der skal bruges til at realisere et SC filter, bliver designet individuelt. Disse kombineres herefter i implementationen filteret. Det endelige filters funktionalitet simuleres ved brug af Spectre
RF.
iii
iv
Preface
This thesis has been submitted in order to meet the requirements to obtain the degree
of Bachelor of Science in Engineering (BScE) at the Technical University of Denmark, DTU. This project has been carried out in the Centre for Physical Electronics
at the Deparment of Electrical Engineering (DTU Electrical Engineering). The work
in this thesis has been carried out under supervision of Erik Bruun in the period from
October 2007 to February 2008.
Kongens Lyngby, February 29th 2008
Jens Pejtersen, s042180
v
vi
CONTENTS
Contents
1 Introduction
1.1
1
Performance Specification . . . . . . . . . . . . . . . . . . . . . . .
2 Designing the Switched Capacitor Filter
2.1
2.2
2.3
3.2
3
Switched Capacitor Filters . . . . . . . . . . . . . . . . . . . . . . .
3
2.1.1
First Order Switched Capacitor Filter . . . . . . . . . . . . .
4
2.1.2
Second Order Switched Capacitor Low-Q BiQuad . . . . . .
5
Analytical Filter Design . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.2.1
Determing the Filter Transfer Functions . . . . . . . . . . . .
7
Determining the Capacitor Ratios . . . . . . . . . . . . . . . . . . .
8
2.3.1
First Order Filter Section . . . . . . . . . . . . . . . . . . . .
9
2.3.2
Second Order Filter Section . . . . . . . . . . . . . . . . . .
9
2.3.3
Matching the Capacitors . . . . . . . . . . . . . . . . . . . .
9
3 Designing the Filter Building Blocks
3.1
1
13
The CMOS Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1
Process Parameters . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2
Cadence Models . . . . . . . . . . . . . . . . . . . . . . . . 14
The Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.1
Design of the Single Output Operational Amplifier . . . . . . 15
vii
CONTENTS
3.2.1.1
3.2.2
3.3
Simulation . . . . . . . . . . . . . . . . . . . . . . 18
The Fully Differential Operational Amplifier . . . . . . . . . 20
3.2.2.1
Common Mode Feedback Circuit (CMFB) . . . . . 21
3.2.2.2
Simulation . . . . . . . . . . . . . . . . . . . . . . 23
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1
The NMOS Switch . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.2
The Transmission Gate . . . . . . . . . . . . . . . . . . . . . 27
3.4
Creating the Non-Overlapping Clock Signals . . . . . . . . . . . . . 29
3.5
Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Implementation of the Filter
33
4.1
First Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2
Second Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3
Third Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Conclusion
41
A Operational Amplifier Cadence Schematics
43
B Filter Cadence Schematics
45
List of Figures
48
List of Tables
50
Bibliography
51
viii
Chapter 1
Introduction
Switched Capacitor (SC) circuits have been widely used in the design of integrated
circuits. They have become popular in integrated filters because they can be used
to design filters with very high precision compared to normal RC-filters, that often
requires a tuning circuit to ensure proper operation.
The frequency response of SC filters is ideally a function of capacitor ratios, where
as the frequency response of RC-filters is highly dependable on the operating temperature and the fabrication process. Capacitor ratios can be made very precise and
almost independable of fabrication errors.
This report describes the design of a fully differential integrated SC third order low
pass Butterworth filter. The third order filter is realized as a cascade of a first order filter and a second order biquad filter. The filter is designed to have the corner requency
fc at 1 MHz and unity passband gain.
The filter is implemented in a 0.35 µm CMOS process with supply voltages of
±1.25 V. The supply voltages and the sampling clock signal are assumed to be
supplied by external circuitry. The filter is implemented and simulated at schematic
level using Cadence Virtuoso and the Spectre RF simulator.
1.1 Performance Specification
The SC filter is designed using the following requirements:
• Third order Butterworth low pass filter.
1
CHAPTER 1. INTRODUCTION
• Unity passband gain.
• Corner frequency at 1 MHz.
• ±1.25 V.
• Fully differential input and output.
2
Chapter 2
Designing the Switched Capacitor
Filter
This chapter describes the process of designing a third order low pass Butterworth
Switched-Capacitor (SC) filter. The filter is designed to meet the requirements stated
in the performance specification. The third order filter is realized as a cascade of a
first order and a second order SC filter section.
The filter is first designed as a continuous time (CT) transfer function, which is then
transformed to a discrete time (DT) transfer function using the bilinear z-transform.
This is performed purely analytical. The DT transfer function is then used to calculate the capacitor ratios needed to realize the first order and second order SC filter
sections.
2.1 Switched Capacitor Filters
SC circuits operates by charging and discharging capacitors with a predefined switching scheme consisting of two or more non-overlapping clock signals. The netto
charge transferred during the switching period averaged over time can be seen as
a current. This makes it possible to emulate resistors.
The charging and discharging of a capacitor ideally acts as a simple sample and hold
circuit. This sampling property makes it possible to describe the functionality of SC
circuits using DT z-domain transfer functions.
SC filters are designed to perform continuous time filtering using SC circuit concepts.
3
CHAPTER 2. DESIGNING THE SWITCHED CAPACITOR FILTER
The input signals are quantized and filtered using analog integrators similiar to RC
filters. The quantization of the input results in a quantized output signal drom which
athe continuous time signal can be recreated by an interpolation filter.
Because a SC filter acts as an analog sampling filter it is necessary that the input
signal satisfies Nyquist’s sampling criterion:
fs ≥ 2fc
(2.1)
, where fs is the switching/sampling frequency of the SC filter and fc is the maximum
frequency to be processed by the filter. This means that the input signal needs to be
bandlimited to fc to avoid aliasing.
2.1.1 First Order Switched Capacitor Filter
Figure 2.1: First order switched capacitor filter section
The first order filter section is realized as described in [3, p. 409-413]. A schematic
of the circuit is shown in 2.1. The z-domain transfer function is given by [3, Eq.
(10.33)]:
C1 +C2
z − CCA1
CA
H1st (z) = − (2.2)
1 + CCA3 z − 1
CA is the integrating capacitor in the first order filter. All the other capacitors in the
circuit are referenced to CA by the capacitor ratios: K1 = C1/CA , K2 = C2/CA
4
2.1. SWITCHED CAPACITOR FILTERS
Figure 2.2: Second order switched capacitor low-Q biquad filter section
and K3 = C3/CA . Inserting the capacitor ratios into equation (2.2) expresses
H1st (z) as a function of the capacitor ratios.
H1st (z) = −
(K1 + K2) z − K1
(1 + K3) z − 1
(2.3)
2.1.2 Second Order Switched Capacitor Low-Q BiQuad
The second order filter section is implemented using the low-Q SC biquad described
in [3, p. 415-420]. The schematic of the second order section is shown i figure 2.2.
The capacitor ratios are calculated by comparing the coefficients of the second order
filter transfer function with (2.4).
H2nd (z) −
a2 z 2 + a1 z + a0
b2 z 2 + b1 z + 1
(2.4)
5
CHAPTER 2. DESIGNING THE SWITCHED CAPACITOR FILTER
The coefficients are then used to calculated the capacitor ratios using (2.5)-(2.9)
p
(2.5)
K4 = K5 = b2 + b1 + 1
K1 = (a0 + a1 + a2 )/K5
(2.6)
K2 = a2 − a0
(2.7)
K3 = a0
(2.8)
K6 = b2 − 1
(2.9)
2.2 Analytical Filter Design
The normalized CT transfer function of a third order Butterworth low pass filter is
given by:
1
(s + 1) (s2 + s + 1)
H0 (s) =
(2.10)
H0 (s) can be realized as a cascade of a first order transfer function H0,1 (s) and a
second order transfer function H0,2 (s).
H0 (s) = H0,1 (s) H0,2 (s)
, where
1
s+1
1
2
s +s+1
H0,1 (s) =
H0,2 (s) =
(2.11)
(2.12)
The normalized transfer function H0 (s) has a unity passband gain and a corner frequency at 1 rad/s. The corner frequency of the normalized transfer functions is scaled
to a specific corner frequency ωc by exchanging s with s/ωc . Frequency scaling of
H0,1 (s) and H0,2 (s) yields:
H1 (s) =
H2 (s) =
s
ωc
ωc
1
=
+1
s + ωc
1
s
ωc
2
+
(2.13)
=
s
ωc
+1
ωc2
s2 + ωc s + ωc2
(2.14)
The CT transfer function is transformed from the s-domain to the z-domain using the
bilinear z-transform. This is done by replacing s in the CT transfer function with its
bilinear z-domain equivalent:
s =
6
2 z−1
T z+1
(2.15)
2.2. ANALYTICAL FILTER DESIGN
Due to the frequency aliasing of the bilinear z-transform, the corner frequency ωc is
transformed into the corresponding bilinear equivalent Ωc . This is done using:
ωc T
2
tan
Ωc =
(2.16)
T
2
, where T is the number of samples per radian. The α parameter is introduced to
simplify the development of the DT transferfunctions.
ωc T
α = tan
(2.17)
2
Inserting (2.17) into (2.16) yields
Ωc =
2
α
T
(2.18)
The bilinear transform is now used to transform H0,1 (s) and H0,2 (s) into z-domain
transfer functions. The ωc is replaced by Ωc and s is replaced by (2.15) in the CT
transfer functions.
Ωc
H1 (z) =
s + Ωc s= 2 z−1
T z+1
=
H2 (z) =
=
=
2
Tα
2 z−1
2
T z+1 + T α
=
Ωc 2
s2 + Ωc s + Ωc 2
α(z + 1)
(α + 1)z + α − 1
s= T2
(2.19)
z−1
z+1
2
2
Tα
2
2 z−1
2 2 z−1
α z+1 +
+
T z+1
T
2
2
α
T
α2 z 2 + 2z + 1
(1 + α + α2 ) z 2 + (−2 + 2α2 ) z + (1 − α + α2 )
(2.20)
2.2.1 Determing the Filter Transfer Functions
The filter needs to have a corner frequency at fc = 1 MHz and unity gain in the
passband in order to meet the requirements stated in the performance specification.
Because a SC filter is a analog sampled filter it has to have a sampling frequency fs
that satisfies Nyquist’s sampling criterion fs ≥ 2fc . Using the Nyquist frequency as
sampling frequency would require an ideal low pass filter at the output to recreate the
analog signal from the samples. As this is not realizable the sampling frequency is
chosen to be 5 times higher than the Nyquist frequency.
fs = 5 · 2fc = 10 · 1 MHz = 10 MHz
7
CHAPTER 2. DESIGNING THE SWITCHED CAPACITOR FILTER
The period of the sampling frequency is equal to T .
T =
1
1
= 100 ns
=
fs
10 MHz
(2.21)
The α coefficient is calculated using (2.17) by inserting T from (2.21) and the corner
frequency in radians ωc = 2πfc = 20π Mrad/s.
ωc T
2π Mrad/s · 100 ns
α = tan
= tan
2
2
= tan (0.1π)
' 0.3249
(2.22)
Inserting (2.22) into (2.19) and (2.20) yields the numerical expressions of the DT
transfer functions H1 (z) and H2 (z) that satisfies the performance requirements.
0.3249z + 0.3249
1.325z − 0.6751
0.1056z 2 + 0.2111z + 0.1056
1.431z 2 − 1.789z + 0.7807
H1 (z) =
H2 (z) =
(2.23)
(2.24)
The transfer functions has been plotted in figure 2.3.
10
Magnitude (dB)
0
−10
−20
−30
First
−40
Second
Third
−50
90
45
Phase (deg)
0
−45
−90
−135
−180
−225
−270
−315
4
10
5
6
10
10
7
10
Frequency (Hz)
Figure 2.3: Bode plot of the seperate and cascaded transfer functions.
2.3 Determining the Capacitor Ratios
The capacitor ratios of the first order and the second order filter sections can now be
determined from the numerical transfer functions.
8
2.3. DETERMINING THE CAPACITOR RATIOS
2.3.1 First Order Filter Section
The capacitor ratios are determined by comparing the numerical first order transfer
function (2.23) and (2.3). Normalizing H1 (z) with respect to the zero order coefficient of the denominator yields:
H1 (z) =
0.4813z + 0.4813
1.963z − 1
(2.25)
Comparing (2.25) with (2.3) gives the capacitor ratios:
K1 = 0.4813
(2.26)
K2 = −0.4813 − 0.4813 = −0.9626
(2.27)
K3 = 1.963 − 1 = 0.9626
(2.28)
2.3.2 Second Order Filter Section
H2 (z) is normalized with respect to the zero order coefficient of the denominator.
H2 (z) =
0.1352z 2 + 0.2705z + 0.1352
1.832z 2 − 2.291z + 1
(2.29)
The capacitor ratios of the second order biquad can be calculated by inserting the
coefficients of (2.24) into (2.4). These are then inserted into (2.5)-(2.9) to yield the
capacitor ratios of the second order filter. The ratios are listed in table 2.1.
K1
K2
K3
K4
K5
K6
0.7355
0
0.1352
0.7355
0.7355
0.8324
Table 2.1: Capacitor ratios of the second order biquad section.
2.3.3 Matching the Capacitors
The frequency response of a SC filter is ideally determined by capacitor ratios. It is
therefore essential to every SC filter design that the capacitor ratios are immune to
imperfections caused by the fabrication process, such as overetching and variation of
9
CHAPTER 2. DESIGNING THE SWITCHED CAPACITOR FILTER
the oxide thickness [3, p. 108]. Errors due to overetching can be minimized using
multiple unit capacitor in parallel to realize the capacitor ratios. This ensures that the
error due to overetching is the same for all capacitors and that all the ratios ideally
stays the same.
The capacitor ratios of the first order filter and the second order filter are modified
to make them an integer multiple of a unit capacitor. The relative size of the unit
capacitor is chosen to be 0.125. The modified capacitor ratios are listed in the tables
2.2 and 2.3 for the first order filter and the second order filter respectively.
K1
K2
K3
0.5
-1
1
Table 2.2: Modified capacitor ratios of the first order section.
The transfer functions are updated based on the on the modified capacitor ratios.
H1m (z) =
H2m (z) =
0.5z + 0.5
2z − 1
0.1250z 2 + 0.3125z + 0.1250
1.875z 2 − 2.313z + 1
Figure 2.4 shows a comparison between the original transfer functions and the modified transfer functions. It is seen that the corner frequency of the third order filter
has not changed significantly. The modified first order filter has almost the same frequency response as the unmodified first order filter. The modification of the second
order filter has caused the frequency response to flatten to approximately -38.4 dB at
5 MHz, but has not changed the 0 dB crossing at 1 MHz significantly.
K1
K2
K3
K4
K5
K6
0.750
0
0.125
0.750
0.750
0.875
Table 2.3: Modified capacitor ratios of the second order biquad section.
10
2.3. DETERMINING THE CAPACITOR RATIOS
10
0
−10
−20
Magnitude (dB)
−30
−40
−50
−60
First
First Modified
−70
Second
Second Modified
−80
Third
Third Modified
−90
−100
6
10
Frequency (Hz)
Figure 2.4: Frequency responses of the modified transfer functions compared to the
originals.
11
CHAPTER 2. DESIGNING THE SWITCHED CAPACITOR FILTER
12
Chapter 3
Designing the Filter Building
Blocks
A SC circuit consists of several components or building blocks. The most obvious
is capacitors switches and operational amplifiers. In addition to those it is necessary
to implement a clock generating circuit that ensures that the switches are driven by
non-overlapping clock signals. It is also necessary to implement a Sample and Hold
(S/H) circuit to ensure that the output of the circuits are valid. This is done because
the output of the first and second order filters used are only valid at the end of the φ1 .
All of the components mentioned here are designed during this chapter.
3.1 The CMOS Process
The process used in the design of the filter is a 0.35 µm CMOS process from Austria
Micro Systems [2]. The process parameters listed below are used as a guideline in
the dimensioning of the transistors throughout this document.
3.1.1 Process Parameters
The threshold voltage Vthn of the NMOS transistors and Vthp of the PMOS transistors are approximated by:
Vthn = 0.6 V
(3.1)
Vthp = −0.75 V
(3.2)
13
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
The gain factor k0n of the NMOS transistors and k0p of the PMOS transistors are approximated by:
k0n = 150 µA/V2
(3.3)
2
(3.4)
k0p
= −48 µA/V
3.1.2 Cadence Models
The transistors are simulated using the PRIMLIB/NMOS4 and PRIMLIB/PMOS4
models. The resistors are simulated using the analoglib/res model. The capacitors
are simulated using the analoglib/cap model.
3.2 The Operational Amplifier
The operational amplifier is designed as a fully differential self biased folded cascode
[1, Fig. 7.3-5]. The folded cascode is a single stage operational amplifier using the
load capacitance CL as compensation capacitor. The fully differential topology has
been chosen to minimize the effects clock-feedthrough and DC offsets and other nonideal secondary effects.
The requirements of the operational amplifier to be used in the implementation of the
SC filter is inspired by [3, p. 394-395]. The operational amplifier is designed to meet
the following requirements:
• The gain bandwidth product GB should be at least 5 times higher than the
switching frequency.
GB ≥ 5fs = 50 MHz
(3.5)
• The DC-gain should be higher than 40 dB.
A0 ≥ 40 dB
(3.6)
• The phase margin PM should be about 70 degrees.
PM ∼ 70 degrees
(3.7)
These requirements should be met when both outputs are loaded with a capacitance
CL of 10 pF, and the supply rails are limited to ±1.25 V, as stated in the performance
14
3.2. THE OPERATIONAL AMPLIFIER
specification.
Vdd = 1.25 V
Vss = −1.25 V
The operational amplifier is first designed to satisfy the requirements with a single
output. The dimensions of the transistors used in the single output operational amplifier are then used as a template for the development of the fully differential operational amplifier. This shoul result in a fully differential operational amplifier with a
gain and a frequency response similar to the single output version. A Common Mode
FeedBack circuit (CMFB) is designed to ensure that the differential outputs are tied
to a stabilized common mode voltage.
3.2.1 Design of the Single Output Operational Amplifier
The schematic of the operational amplifier with a single output is shown in figure 3.1.
All transistors except the input differential pair M1 and M2 and the biasing transistors
M3 and M12 are dimensioned to have an overdrive voltage Veff of approximately
0.25 V.
Veff = 0.25 V
(3.8)
The drain current ID3 of M3 determines the bias currents of the NMOS differential
pair consisting of M1 and M2. ID3 is determined by choosing a desired slew rate.
The slew rate SR of the folded cascode is approximately determined by [1, p. 307]:
I D3
⇔
CL
= SR CL
SR =
I D3
(3.9)
A slew rate of 40 V/µs is chosen in order to minimize the slewing behaviour of the
output. ID3 is calculated by inserting SR = 40 V/µs and CL = 10 pF into (3.9).
ID3 = 40 V/µs · 10 pF = 400 µA
(3.10)
The gain bandwidth GB of the folded cascode is approximately given by [1, p. 307]:
GB =
gm1
CL
(3.11)
, where gm1 is the transconductance of the input differential pair transistors M1 and
M2.
15
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
Figure 3.1: The self biased folded cascode single output operational amplifier.
M1 and M2 has to be sized to be able to meet the GB requirement. The transconductance of a NMOS transistor operating in the saturation region is given by
q
gm1 = k0n (W/L)1 ID1
(3.12)
, where (W/L)1 is the dimensions and ID1 is the drain current of M1.
An expression for (W/L)1 is derived by combining (3.11) with (3.12).
GB =
(W/L)1 =
p
k0n (W/L)1 ID1
⇔
CL
GB2 CL 2
k0n ID1
(3.13)
The drain currents ID1 and ID2 are equal to ID3 /2.
I D1 = ID2 =
I D3
= 200 µA
2
(3.14)
(W/L)1 is calculated by inserting ID1 and CL and GB into (3.13).
(100π Mrad/s)2 · (10 pF)2
150 µA/V2 · 200 µA
= 328.9868 ∼ 330
(W/L)1 =
16
(3.15)
(3.16)
3.2. THE OPERATIONAL AMPLIFIER
The output current of the PMOS current mirror consisting of M4 and M5 is set to be
equal to ID3 . The drain current ID4 of M4 and M5 is therefore −ID3 .
ID4 = −ID3 = −400 µA
(3.17)
(W/L)4 and (W/L)5 of M4 and M5 is calculated from (3.17) and (3.8).
(W/L)4 = (W/L)5 =
2ID4
k0p Veff 2
2 · (−400 µA)
−48 µA/V2 · 0.25 V
= 266.6667 ∼ 270
=
The drain current of the cascoding PMOS transistors M6 and M7 is equal to ID4 +ID1 .
ID6 = −400 µA + 200 µA = −200 µA
(3.18)
(W/L)6 and (W/L)7 of M6 and M7 are calculated from (3.18) and (3.8).
(W/L)4 = (W/L)5 =
2ID6
0
kp Veff 2
2 · (−200 µA)
−48 µA/V2 · 0.25 V
= 133.3333 ∼ 134
=
The NMOS transistors M8 to M11 are forming a cascode current mirror. All four
transistors have the same dimensions. The drain current ID8 is equal to −ID6 .
ID8 = 200 µA
(3.19)
(W/L)8 is calculated from (3.19) and (3.8)
(W/L)8 =
2ID8
0
kn Veff 2
2 · 200 µA
150 µA/V2 · 0.25 V
= 42.6667 ∼ 43
=
The biasing NMOS transistors M3 and M12 have their gates connected to the bias
voltage VBIAS . M3 and M12 determines the bias currents of the operational amplifier
as a function of VBIAS . M12 will in the fully differential design be used to control
the common mode voltage of the outputs. The CMFB circuit is going to be designed
to have a control voltage equal to 0 V when the common mode voltage is 0 V. M3
and M12 are therefore sized using a bias voltage of VBIAS = 0 V. The gate voltage
17
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
VG3 = VBIAS . The sources of M3 and M12 are tied to the negative supply Vss =
−1.25 V.
VG3 = VBIAS = 0 V
VS3 = Vss = −1.25 V
The overdrive voltage Veff3 of M3 and M12 with a gate voltage VG3 equal to VBIAS
is
Veff3 = VG3 − VS3 − Vthn = 0 V + 1.25 V − 0.6 V = 0.65 V
(3.20)
The dimensions of M3 and M12 are calculated using (3.20) and ID3 = 400 µA
(W/L)3 =
2ID3
0
kn Veff3 2
2 · 400 µA
150 µA/V2 · (0.65 V)2
= 14.8148 ∼ 15
=
The resistors R1 and R2 are set to 1250 Ω.
3.2.1.1
Simulation
All the transistors have been sized to have a length of 1 µm.
The DC simulation has been used to reduce the output offset voltage as much as possible with as little modification as possible. During the optimization the dimensions
of M6, M7 and M8 has been changed to 128 µm and R1 has been changed to 2500 Ω.
The modified dimensions of the single output operational amplifier are listed in table
3.1.
The DC operating points of the circuit can be found on the plot of the schematic in
figure A.1 in Appendix A.
Both the AC and the transient simulations was performed using the modified transistor dimensions from table 3.1 and a capacitive load at the output of 10 pF.
The frequency response of the operational amplifier is shown in figure 3.2. The measurements of the design requirements are listed below:
• DC-gain
A0 = 78.41 dB
18
3.2. THE OPERATIONAL AMPLIFIER
Transistor
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
Resistor
R1
R2
Width
330 µm
330 µm
15 µm
270 µm
270 µm
128 µm
128 µm
43 µm
43 µm
43 µm
43 µm
15 µm
128 µm
270 µm
Length
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
Resistance
1250 Ω
2500 Ω
Table 3.1: Modified transistor dimensions of the single output operational amplifier.
• Gain bandwidth product
GB = 54.15 MHz
• Phase margin
PM = 68.78degrees
The slew rate SR was measured using a transient simulation where the operational
amplifier was connected as a buffer, with the differential input connected to a squarewave voltage source. The slew rate of the positve and the negative slope are denoted
SR+ and SR− respectively.
SR+ = 40.5 V/µs
(3.21)
SR− = 37.1 V/µs
(3.22)
All of the design requirements have been met and exceeded except for the phase
margin. But the phase margin is acceptably close to 70 degrees.
19
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
Gain
Phase
50.0
100
75.0
0
50.0
−50.0
0
−100
Phase (deg)
Gain (dB)
25.0
−25.0
−150
−50.0
−200
−75.0
−100
10 0
10 1
10 2
10 3
10 4
10 5
freq (Hz)
10 6
10 7
10 8
10 9
−250
10 10
Figure 3.2: Bode plot of the single output operational amplifier.
3.2.2 The Fully Differential Operational Amplifier
The fully differential operational amplifier is a modified version of the single output
folded cascode that was designed in the previous section. The schematic of the fully
differential operational amplifier is shown in figure 3.3. The common mode voltage
of the differential outputs is stabilized using a internal Common Mode FeedBack
(CMFB) circuit. The transistor dimensions from the single output design are kept.
The differential operational amplifier has three additional transistors compared to the
single output version. M15 are used to determine the current flowing through the
cascode current mirror consisting of M16 and M17. This current mirror is used to
bias the two NMOS current sinks at the outputs. M16 and M17 are both sized to have
the same dimensions as the transistors of the cascode current sinks, e.g. M8.
(W/L)16 = (W/L)17 = (W/L)8 = 43
(3.23)
The dimensions of M15 is initially set to half of M4 because the drain current ID16 of
M16 and M17 approximately 200 µA.
(W/L)15 =
(W/L)4
= 135
2
(3.24)
M3 and M12 are contrary to the single output design not biased at the same gate
voltage. M3 is still biased using VBIAS but M12 is now used to control the common
20
3.2. THE OPERATIONAL AMPLIFIER
mode voltage level at the differential output. The gate of M12 is connected to the
output voltage Vctrl of the CMFB circuit.
Figure 3.3: The self biased folded cascode with differential outputs.
3.2.2.1
Common Mode Feedback Circuit (CMFB)
The common mode feedback is implemented using the CMFB circuit shown in figure
3.4 [3, Fig. 6.19]. This circuit is connected to the positive and negative output of the
operational amplifier. The output signal of the CMFB circuit Vctrl is connected to
the gate of M12. The CMFB circuit creates negative feedback from the outputs to the
gate of M12. This ensures that the output common mode voltage is stabilized around
a specific operating point. Which is ideally 0 V.
The CMFB is designed to consume little power and utilize relatively small transistor,
in order to minimize the capacitive loading of the operational amplifier outputs. The
feedback signal Vctrl should be equal to 0 V when the common mode voltage at the
outputs is 0 V.
Vctrl = 0 V
(3.25)
The current sinks M7 and M8 are sized to meet the requirement of Vctrl = 0. The
gate voltage VG7 of M7 is equal to Vctrl and the source is tied to the negative supply
21
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
Figure 3.4: The CMFB circuit.
Vss .
VG7
= Vctrl = 0 V
VS7
= Vss = −1.25 V
The dimensions (W/L)7 of M7 and M8 are set to 2 to reduce the size of the CMFB
circuit.
(W/L)7 = 2
(3.26)
The drain current flowing through M7 is calculated.
1 0
kn (W/L)7 (VG7 − VS7 − Vthn )2
2
1
=
150 µA/V2 · 2 · (VG7 − VS7 − 0.6 V)2
2
= 63.375 µA
I D7 =
(3.27)
The PMOS current source consisting of M5 and M6 is now sized using the result
from (3.27).
ID5 = −ID7 = −63.375 µA
(W/L)5 =
2ID5
k0p Veff 2
2 · (−63.375 µA)
−48 µA/V2 · (0.25 V)2
= 42.2500 ∼ 42
=
22
(3.28)
3.2. THE OPERATIONAL AMPLIFIER
The drain current ID1 flowing through each of the PMOS transistors of the differential
gain stage is half of ID5 .
I D1 =
I D5
= −31.687 µA
2
(3.29)
The dimensions of M1 are now calculated.
2 I D1
(W/L)1 =
0
kp Veff 2
2 · (−31.687 µA)
−48 µA/V2 · (0.25 V)2
= 21.1250 ∼ 22
=
3.2.2.2
(3.30)
Simulation
The simulation was conducted on a circuit consisting of the fully differential operational amplifier with the CMFB circuit. All the transistors has been implemented
using a transistor length of 1 µm.
The transitor dimensions and resistor values have been optimized using the DC simulation in order to minimize the common mode voltage at the outputs. The modified transistor dimensions and component values of the operational amplifier and the
CMFB circuit are listed in table 3.3 and 3.2 respectivelly.
Transistor
M1
M2
M3
M4
M5
M6
M7
M8
M9
Width
20 µm
20 µm
20 µm
20 µm
40 µm
40 µm
2 µm
2 µm
40 µm
Length
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
Table 3.2: Modified transistor dimensions of the CMFB.
The DC operating points of the operational amplifier and the CMFB circuit can be
found on the schematics shown in figure A.2 and A.3 in Appendix A.
The frequency response of the fully differential operational amplifier was measured
with both outputs loaded by 10 pF. The frequency response is plotted in figure 3.5.
23
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
Transistor
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
Resistor
R1
R2
Width
330 µm
330 µm
15 µm
270 µm
270 µm
122 µm
122 µm
43 µm
43 µm
43 µm
43 µm
14 µm
122 µm
270 µm
128 µm
43 µm
43 µm
Length
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
1 µm
Resistance
1250 Ω
1250 Ω
Table 3.3: Modified transistor dimensions of the fully differential operational amplifier.
The measurements of the design requirements are listed below:
• DC-gain
A0 = 72.67dB
• Gain bandwidth product
GB = 54.4 MHz
• Phase margin
PM = 77.04 degrees
The DC-gain has decreased at the cost of a increased gain bandwidth and the phase
margin has increased above the 70 degrees. The fully differential operational amplifier satisfies all the design requirements.
24
3.3. SWITCHES
Gain
Phase
75.0
50.0
50.0
0
25.0
Gain (dB)
0
−100
−25.0
Phase (deg)
−50.0
−150
−50.0
−200
−75.0
−100
10 0
10 1
10 2
10 3
10 4
10 5
freq (Hz)
10 6
10 7
10 8
10 9
−250
10 10
Figure 3.5: Bode plot of differential operational amplifier with CMFB.
3.3 Switches
Switches are an essential part of SC circuits because they control the charge flow in
the circuit. An ideal switch has no ON resistance and thus conducts a signal from the
input to the output without loss. MOSFET switches are non-ideal elements and they
provides a resistive load between the capacitors in a SC circuit. This limits the rate
of which the charge can be transferred between the capacitors. This has to be taken
into account when sizing the switches.
Some switches in SC circuit must be able to pass a fully differential voltage signal. This can be done using a transmission gate which is a parallel combination of a
NMOS and a PMOS transistor. This ensures that the switch will always be conducting even though either the PMOS or the NMOS transistor is in the cut-off region.
Other switches in SC circuits are connected to ground or virtual ground. These
switches does not have to be able to pass a full signal swing, and can therefore be
implemented using a single NMOS transistor.
All switches connected to ground or virtual ground in the first order and second order filter sections are implemented using NMOS switches. All other switches are
implemented using transmission gates.
A MOSFET transistor is operating in the triode region when it is used as a switch.
25
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
The drain source resistance RDS of a MOSFET operating in the triode region can be
found using (3.31).
RDS =
k0n
1
(W/L)N Veff
This is only valid when the drain source voltage of the transistor is equal to or close
to zero, which is the case when the transistor is used as a switch. The switches
are implemented using the minimum transistor length Lmin = 0.35 µm in order to
minimize RDS . Inserting Lmin into (3.31) gives an expression for the width of the
transistor.
(W/L)1 =
W1 =
1
k0n
RDS1 Veff1
Lmin
k0n RDS1 Veff1
⇔
(3.31)
The time constant of a switch can be approximated by:
τ = Ron CL
(3.32)
, where Ron is the effective resistance and CL is the total capacitive load of the the
switch.
Each switch needs to be able to pass the signal from input to output in less than T/2.
It is assumed that a first order circuit has reached its settling point after a period
tsettle = 5 τ .
tsettle = 5Ron CL
(3.33)
Using (3.33) yields an equation that can be used to determine the largest allowable
value of the Ron to ensure that the charge transfer has settled during the ON period.
T
2
Ron
≥ 5 Ron CL ⇔
=
T
10 CL
(3.34)
Inserting CL = 10 pF and T = 100 ns into (3.34) gives the maximum allowed ON
resistance in order to satisfy the requirements.
Ronmax =
26
100 ns
= 1000 Ω
10 · 10 pF
(3.35)
3.3. SWITCHES
Figure 3.6: NMOS switch.
3.3.1 The NMOS Switch
The ON resistance of a NMOS switch is the drain source resistance RDSN . The
gate voltage of the NMOS transistor is VG1 = Vdd and the overdrive voltage is
Veff1 = 0.65 V assuming that the signal voltage Vsig at the input of the switch is
close to zero. The width W1 of the NMOS switch required to meet the settling time
requirement are calculated using (3.31).
Lmin
k0n Ronmax Veff
0.35 µm
=
150 µA/V2 · 1000 Ω · 0.65 V
= 3.5897 µm ∼ 4 µm
W1 =
(3.36)
The calculated width is the minimum size allowed to satisfy the settling time requirement. The NMOS switches are implemented with a transistor width of 20 µm.
3.3.2 The Transmission Gate
The ON resistance Ron of the transmission gate, shown in figure 3.7, is the parallel
combination of the drain source resistances RDS1 of the NMOS transistor and RDS2
of the PMOS transistor.
Ron = RDS1 k RDS2
(3.37)
The worst case resistances of the transmission gate is now determined. A transmission gate can operate in three possible states when it is ON. In the first state both the
NMOS and the PMOS transistors are conducting. Ron is the parallel combination of
the drain source resistances RDS1 and RDS2 . Ron has the smallest value during this
state.
The transmission gate is operating in the second state when only the NMOS transitor
is conducting. Ron is in this state equal to the RDS1 . RDS1 has the largest resistance
at the voltage where the PMOS transistor enters the cut-off region. This voltage can
27
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
Figure 3.7: Transmission gate switch.
be found by setting the overdrive voltage of the PMOS equal to 0 V.
Veff2 = 0 V
(3.38)
The effective voltage of the NMOS transitor can be found by deriving the source
voltage VS2 of the PMOS from (3.38), which is equal to the signal voltage Vsig at the
input of the transmission gate.
Veff2
VS2
= VS2 − VG2 + Vthp ⇔
= Veff2 + VG2 − Vthp
= 0 V − 1.25 V + 0.75 V
= −0.5 V
(3.39)
The minimum width of the NMOS are calculated using (3.31).
W1 =
Lmin
k0n
Ronmax VS2
0.35 µm
=
150 µA/V2 · 1000 Ω · (−0.5 V)
= 2.0290 µm ∼ 3 µm
(3.40)
The transmission gate is operating in the third state when only the PMOS transistor
is conducting, thus Ron is equal to the drain source resistance RDS1 of the PMOS
transistor. The largest resistance of the PMOS transistor is calculated using the same
method as for the NMOS transistor above.
Veff1 = 0 V
28
(3.41)
3.4. CREATING THE NON-OVERLAPPING CLOCK SIGNALS
Transistor
M1
M2
M3
M4
Width
10 µm
20 µm
0.35 µm
0.35 µm
Length
0.35 µm
0.35 µm
0.35 µm
0.35 µm
Table 3.4: Modified transistor dimensions of transmission gate switch.
Veff1
VS1
= VG1 − VS1 − Vthn ⇔
= VG1 − Veff1 − Vthn
= 1.25 V − 0 V − 0.6 V
= 0.65 V
(3.42)
The minimum width of the PMOS are calculated using (3.31).
W2 =
Lmin
k0p
Ronmax VS1
0.35 µm
=
−48 µA/V2 · 1000 Ω · 0.65 V
= 6.3406 µm ∼ 7 µm
(3.43)
As for the NMOS switch the widths are the minimum required to fulfill the requirements. The transmission gates are implemented with W1 = 10 µm and W2 =
20 µm. The final dimensions of the transmission gate transistors are listed in table
3.4.
3.4 Creating the Non-Overlapping Clock Signals
The circuit used to generate the non-overlapping clock signals is based on the circuit
presented in [3, p. 398]. The circuit is shown in figure 3.8.
The digital gates are normally implemented using the minimum transistor dimension
for both width and length, as they are usually not used to drive relatively large capacitive loads. The clock generating circuit is loaded with the combined capacitance the
of all the NMOS transistors used as switches. The PMOS transistors are not directly
loading the clock generating circuit, as their gate capacitances are loading the local
inverter. The NOR-gate transistors are dimensioned to realize a low output resistance,
and thereby reducing the settling time of the clock signals φ1 and φ2 . This is done by
29
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
Figure 3.8: The non-overlapping clock generator.
setting the width to 4 µm and the length is set to the minimum size of 0.35 µm.
WNOR = 4 µm
LNOR = 0.35 µm
The inverter used to invert the reference clock signal clk is implemented using a
NMOS and a PMOS transistor with the minimum dimensions allowed for the process.
WINV = 0.35 µm
LINV = 0.35 µm
Each delay block is implemented using 8 inverters in cascade. The inverters are
dimensioned to realize a relatively large time constants in order to increase the propagation delay. This is done to make a suitable delay between φ1 and φ2 . The width is
set to 2 µm and the length is set to 3 µm in order to increase the output resistance of
the inverters.
WDLY = 2 µm
LDLY = 3 µm
Figure 3.9 shows the non-overlapping clock signals φ1 and φ2 together with the reference clock signal clk, during a transient simulation of the third order filter. The
delay between φ1 and φ2 is measured to be approximately 14.1 ns.
30
3.5. SAMPLE AND HOLD CIRCUIT
1.5 Reference Clock
Voltage (V)
1.0
.5
0
−.5
−1.0
−1.5
1.5 phi1
Voltage (V)
1.0
.5
0
−.5
−1.0
−1.5
1.5 phi2
Voltage (V)
1.0
.5
0
−.5
−1.0
−1.5
0
100
200
time (ns)
300
400
500
Figure 3.9: Transient plot of the non-overlapping clocks.
3.5 Sample and Hold Circuit
The output of the SC filter is only valid at the end of φ1 . It is therefore necessary
to sample the filter output at φ1 . This is done by implementing a simple open loop
sample and hold circuit shown in figure 3.10. The single output operational amplifier
designed earlier is used to implement the buffers. The switches are implemented as
transmission gates because they have to transfer the full signal swing. The holding
capacitors Cs are set to 1 pF.
Figure 3.10: The sample and hold circuit used to sample the filter output at φ1 .
31
CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS
32
Chapter 4
Implementation of the Filter
At this point the capacitor ratios of the of the first and second order filter sections
have been determined. All the components needed to implement the SC filter have
been designed. The filters are now implemented in Cadence Virtuoso and simulated
using the Spectre RF simulator.
The first order and the second order SC filter are simulated seperately to determine
their individual frequency response and transient performance. Finally the two filter
sections are combined to form the third order SC filter.
The transient simulations are performed with a 1 MHz sine wave with an amplitude
of 500 mV applied to the differential input terminals of the filters.
The AC simulations are performed using the periodic small signal (PAC) analysis,
which are performed after a periodic steady state (PSS) analysis. The PSS analysis
determines the steady states of the circuit nodes when the switches duty cycles is
taken into account. The frequency responses of the filters are measured at the differential output of the sample and hold circuit to ensure that the measurements are
valid.
4.1 First Order Filter
The integrating capacitor CA is set to be 10 pF and the other capacitor are referenced
to CA using the ratios listed in table 2.2. The schematic of the first order filter used
in the simulation is shown in figure B.1 in Appendix B. The simulation is performed
using the test bench shown in figure B.2 in Appendix B.
33
CHAPTER 4. IMPLEMENTATION OF THE FILTER
Amplitude
0
Phase
25.0
−2.5
0
−5.0
−7.5
−50.0
−10.0
Phase (deg)
Amplitude (dB)
−25.0
−75.0
−12.5
−100
−15.0
−17.5
10 −1
10 0
10 1
10 2
10 3
freq (Hz)
10 4
10 5
10 6
−125
10 7
Figure 4.1: Frequency response of the first order filter.
The frequency response of the first order filter is shown in figure 4.1.
The passband gain is measured to be:
Apass = −573.2 mdB
(4.1)
It is a little lower than unity which is to expected because of the resitance of the
non ideal switches. The corner frequency fc is measured at −3 dB relative to the
passband gain (−3.5732 dB).
fc = 1.8822 MHz
(4.2)
This is almost two times higher than the 1 MHz design requirement.
The transfer function of the first order section could be changed to take the -573.2
mdB passband gain into account, by designing it to have a gain at of atleast 573.2
mdB. Adjusting the corner frequency requires that the capacitor ratios are lowered
to reduce the frequency of the transfer function pole. The filter output is valid up
to 5 MHz because of sampling criterion, where the gain is approximately -8.5 dB,
which is a little higher than is expected from a first order filter assuming a -20 dB per
decade asymptote.
The transient simulation of the filter is shown i figure 4.2. The output of the sample
and hold is at approximately 400 mV, which is expected based on the results of the
34
4.2. SECOND ORDER FILTER
750 Input Signal
Voltage (mV)
500
250
0
−250
−500
−750
600 Filter Output
Voltage (mV)
400
200
0
−200
−400
−600
600 S/H Output
Voltage (mV)
400
200
0
−200
−400
−600
0
1
2
time (us)
3
4
Figure 4.2: Transient response of the first order filter.
frequency response. The output signal is as expected an inverted quantized sine wave
but it is not perfect. The charging and discharging of the capacitors during the sampling period is easily seen from the waveform. This effect could be minimized by
lowering the capacitance of the integrating capacitor CA . Because the three other capacitors are related to CA by fixed ratios, this would ideally reduce the time constants
in circuit without affecting the filtering performance.
4.2 Second Order Filter
The integrating capacitors CB and CC is set to 10 pF, all other capacitors in the
second order filter are sized using the the capacitor ratios listed in table 2.3. The
schematic of the circuit is shown figure B.3 and the test bench is shown in figure B.4
in Appendix B.
The frequency response of the first order filter is shown in figure 4.3.
The passband gain is measured to be:
Apass = −592.7 mdB
(4.3)
As for the first order section the passband gain is a little lower than unity. The frequency response of the second order filter has to cross 0 dB at 1 MHz in order to
35
CHAPTER 4. IMPLEMENTATION OF THE FILTER
Phase
100
0
0
−100
Amplitude (dB)
−10
−20
−200
−30
−300
−40
−400
−50
10 −1
10 0
10 1
10 2
10 3
freq (Hz)
10 4
10 5
10 6
Phase (deg)
Amplitude
10
−500
10 7
Figure 4.3: Frequency response of the second order filter.
meet the requirements. The 0 dB crossing frequency f0 dB is measured relatively to
the passband gain (−592.7 mdB):
f0 dB = 758 kHz
(4.4)
f0 dB is lower than the required value. This can be compensated by increasing the
dominant pole frequency of the second order transfer function. The less than unity
gain can be compensated by modifying the gain of the transfer function, as described
for the first order sectio n above.
The transient response is plotted in figure 4.4. The output signal measured at the
sample and hold circuit is a quantized sine wave inverted with respect to the input
signal. The output signal doesn’t suffer from large time constants as the first order
section did.
36
4.3. THIRD ORDER FILTER
750 Input Signal
Voltage (mV)
500
250
0
−250
−500
Voltage (mV)
−750
1000 Filter Output
750.0
500.0
250.0
0
−250.0
−500.0
−750.0
−1000
750 SH Output
Voltage (mV)
500
250
0
−250
−500
−750
0
1
2
time (us)
3
4
Figure 4.4: Transient response of the second order filter.
4.3 Third Order Filter
The third order filter is implemented by cascading the first order and the second order
filter sections that were simulated above. The test bench used to perform the simulation is shown in figure B.5 in Appendix B. The input signal is feed into the first
order filter which is then connected to the second order filter. The output of the second order filter is connected to a differential sample and hold circuit. The frequency
response of the filter is measured at the output of the sample and hold circuit, and is
shown in figure 4.5.
The passband gain of the third order filter is measured to be
Apass = −2.348 dB
(4.5)
The passband gain is lower than unity and is approximately 1.17 dB lower than expected by cascading the first order filter (-573.2 mdB) and the second order filter
(-592.7 mdB).
The corner frequency fc is measured at −3 dB relative to the passband gain (−5.348 dB).
fc = 1.003 MHz
(4.6)
The corner frequency are measured to be very close to the design requirement. A
37
CHAPTER 4. IMPLEMENTATION OF THE FILTER
Amplitude
Phase
0
100
0
−10
−100
Amplitude (dB)
−300
−30
Phase (deg)
−200
−20
−400
−500
−40
−600
−50
10 −1
10 0
10 1
10 2
10 3
freq (Hz)
10 4
10 5
10 6
−700
10 7
Figure 4.5: Frequency response of the third order filter.
difference of approximately 8 kHz is very acceptable but the filter doesn’t satisfy the
unity gain passband requirement.
The transient response of the filter is plotted in figure 4.6. The output of the sample
and hold circuit is as expected a quantized sine wave. But the amplitude is about half
of the input sine wave. The transient output of the first order section in third order
filter is very similar to the transients results of the first order section when it was
measured separately. The signal has the same amplitude level and characteristics.
The output of the second order filter has a waveform similar to that simulated earlier
but has a significantly lower amplitude. A possible explanation could be that the
second order section was not tested with additional capacitance equivalent to the
output capacitance of the first order section. This additional capacitance has then
affected the gain of the second order section, yielding a lower gain than theoretically
expected from the cascade combination.
38
4.3. THIRD ORDER FILTER
Input Signal
Voltage (mV)
750
500
250
0
−250
−500
−750
600
400
200
0
−200
−400
−600
750
500
250
0
−250
−500
−750
400
Voltage (mV)
First Order Output
Voltage (mV)
Voltage (mV)
Second Order Output
S/H Third Order Output
0
−400
0
1
2
time (us)
3
4
Figure 4.6: Transient response of the third order filter.
39
CHAPTER 4. IMPLEMENTATION OF THE FILTER
40
Chapter 5
Conclusion
The integrated third order Butterworth SC filter was first designed mathematically as
a transfer function. The transfer function was then used to synthesize the third order
filter using a cascade of a first order and second order section. All the necessary
components required to implement the filter in a CMOS process was then designed.
Finally the filter was successfully implemented and tested in Cadence Virtuoso using
the Specttre simulator.
The frequency response of the filter was only partly satisfying the design requirements. The corner frequency of filter response was very close to the desired value.
The passband gain requirement was not met and was at an unacceptable level.
Even though the performance of the filter did not satisfy the design requirements, the
implementation of the filter and all of the necessary components yielded a functioning
filter that confirmed the theory of SC filters.
The most time consuming part of the project was the design of the necessary components needed to implement the SC filter. Once the designs of the components were
done they were simply wired together to realize the SC filter.
Optimization of the third order filter to satisfy the design requirements should be
possible by iterating through the processes of optimizing the transfer functions, calculating the modified capacitor ratios, performing capacitance matching, simulating
the filter using the new capacitance values.
41
CHAPTER 5. CONCLUSION
42
Appendix A
Operational Amplifier Cadence
Schematics
Figure A.1: Single output operational amplifier Cadence schematic.
43
APPENDIX A. OPERATIONAL AMPLIFIER CADENCE SCHEMATICS
Figure A.2: Differential output operational amplifier Cadence schematic.
Figure A.3: CMFB Cadence schematic
44
Appendix B
Filter Cadence Schematics
Figure B.1: First order filter Cadence schematic.
45
APPENDIX B. FILTER CADENCE SCHEMATICS
Figure B.2: First order filter simulation test bench.
Figure B.3: Second order filter Cadence schematic.
46
Figure B.4: Second order filter simulation test bench.
Figure B.5: Third order filter simulation test bench.
47
APPENDIX B. FILTER CADENCE SCHEMATICS
48
LIST OF FIGURES
List of Figures
2.1
First order switched capacitor filter section . . . . . . . . . . . . . . .
4
2.2
Second order switched capacitor low-Q biquad filter section . . . . .
5
2.3
Bode plot of the seperate and cascaded transfer functions. . . . . . . .
8
2.4
Frequency responses of the modified transfer functions compared to the originals. 11
3.1
The self biased folded cascode single output operational amplifier. . . 16
3.2
Bode plot of the single output operational amplifier. . . . . . . . . . . 20
3.3
The self biased folded cascode with differential outputs. . . . . . . . . 21
3.4
The CMFB circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5
Bode plot of differential operational amplifier with CMFB. . . . . . . 25
3.6
NMOS switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7
Transmission gate switch. . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8
The non-overlapping clock generator. . . . . . . . . . . . . . . . . . 30
3.9
Transient plot of the non-overlapping clocks. . . . . . . . . . . . . . 31
3.10 The sample and hold circuit used to sample the filter output at φ1 . . . 31
4.1
Frequency response of the first order filter. . . . . . . . . . . . . . . . 34
4.2
Transient response of the first order filter. . . . . . . . . . . . . . . . 35
4.3
Frequency response of the second order filter. . . . . . . . . . . . . . 36
4.4
Transient response of the second order filter. . . . . . . . . . . . . . . 37
49
LIST OF FIGURES
4.5
Frequency response of the third order filter. . . . . . . . . . . . . . . 38
4.6
Transient response of the third order filter. . . . . . . . . . . . . . . . 39
A.1 Single output operational amplifier Cadence schematic. . . . . . . . . 43
A.2 Differential output operational amplifier Cadence schematic. . . . . . 44
A.3 CMFB Cadence schematic . . . . . . . . . . . . . . . . . . . . . . . 44
B.1 First order filter Cadence schematic. . . . . . . . . . . . . . . . . . . 45
B.2 First order filter simulation test bench. . . . . . . . . . . . . . . . . . 46
B.3 Second order filter Cadence schematic. . . . . . . . . . . . . . . . . . 46
B.4 Second order filter simulation test bench. . . . . . . . . . . . . . . . . 47
B.5 Third order filter simulation test bench.
50
. . . . . . . . . . . . . . . . 47
LIST OF TABLES
List of Tables
2.1
Capacitor ratios of the second order biquad section. . . . . . . . . . .
9
2.2
Modified capacitor ratios of the first order section. . . . . . . . . . . . 10
2.3
Modified capacitor ratios of the second order biquad section. . . . . . 10
3.1
Modified transistor dimensions of the single output operational amplifier. 19
3.2
Modified transistor dimensions of the CMFB. . . . . . . . . . . . . . 23
3.3
Modified transistor dimensions of the fully differential operational amplifier. 24
3.4
Modified transistor dimensions of transmission gate switch. . . . . . . 29
51
LIST OF TABLES
52
BIBLIOGRAPHY
Bibliography
[1] Phillip E. Allen and Douglas R. Holberg. CMOS Analog Circuit Design. Oxford
University Press, second edition, 2002.
[2] Austria Micro Systems. 0.35 µm CMOS C35 Process Parameters, 2007. Revision 5 - Eng-182.
[3] David Johns and Ken Martin. Analog Integrated Circuit Design. Wiley, first
edition, 1996.
[4] B. P. Lathi. Signal Processing and Linear Systems, USA. Oxford University
Press, 2000.
[5] Adel S. Seedra and Kenneth C. Smith. Microelectronic Circuits. Oxford University Press, USA, fifth edition, 2003.
53