A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
ASNT3010
1Gbps LVDS/CMOS Converter
•
2-channel LVDS-to-CMOS converter (Receiver).
•
2-channel CMOS-to-LVDS converter (Transmitter).
•
Triple-action programmable LVDS/CML/ECL inputs.
•
Optional DS (Data/Strobe) encoding/decoding for compatibility with Space Wire Standard.
•
Flexible selection of channels enabling and operational modes.
•
High-impedance states of disabled CMOS outputs.
•
Single +3.3V power supply.
•
Industrial temperature range.
•
Power consumption: 115mW with all 4 channels enabled.
27 26 25 24 23 22 21 20 19
28
18
29
17
30
16
31
15
32
14
33
13
34
12
35
11
36
10
1
Rev.: D02, Sept2006.
2
3
4
5
6
7
8
9
ASNT3010
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
A D S A N T E C
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
DESCRIPTION
d1p
d1n
Mux
2:1
UIB
oncml
onecl
d2p
d2n
UIB
q1p
q1n
LVDS
q2p
q2n
LVDS
Mux
2:1
Mux
2:1
Mux
2:1
CML to
CMOS
qm1
RCB
crlr1
crlr2
CML to
CMOS
qm2
CMOS
to CML
dm1
TCB
crlt1
crlt2
CMOS
to CML
dm2
ASNT3010 is a bi-directional 4-channel digital interface converter. It includes two independent
“Receiver” channels with programmable LVDS/CML/ECL differential inputs (“d1p/n”, “d2p/n”)
and CMOS outputs (“qm1’, “qm2”), as well as two reverse “Transmitter” channels with CMOS
inputs (”dm1”, “dm2”) and LVDS differential outputs (“q1p/n”, “q2p/n”).
All channels can be independently enabled or disabled by control signals (“crlr1”, “crlr2”,
“crlt1”, “crlt2”). When disabled, the CMOS output drivers are set to a high impedance (high-Z)
state. Both receiver and transmitter channel pairs can be combined into a Space Wire
receiver/transmitter with optional data/strobe (DS) encoding or decoding. The assignment of data
and strobe or data and clock signals to the individual channels is user-selectable.
The converter operates at data rates up to 1Gbps with a nominal power consumption of 115mW
from a single +3.3V power supply in a fully activated mode. The device is characterized for
operation from −25°C to 125°C of junction temperature.
The converter has improved TID tolerance due to the HBT-based implementation.
Universal IB
The proprietary Universal Input Buffer (UIB) is designed to accept differential signals with
amplitudes higher than 60mV, DC common mode voltage variation between the negative and
Rev.: D02, Sept2006.
ASNT3010
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
positive supply voltages, and AC common mode noise with a frequency up to 5MHz and voltage
levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of more
than 60mV and threshold voltages between the negative and positive supply rails. The buffer
outputs standard internal CML signals with amplitude of 220mV.
The buffer features a reconfigurable input block with internal LVDS, CML, or ECL termination
that is controlled by two external CMOS signals “oncml” and “onecl” in accordance with the
following table.
“oncml”
“onecl”
Termination
value
value
Type
Resistance Voltage
VCC
VEE (default) Single-ended (SE)
50Ohm VCC
VEE (default)
VCC
Single-ended (SE)
50Ohm VECL
VEE (default) VEE (default)
Differential
100Ohm
The ECL termination mode requires an external termination voltage of VECL=VCC-2V applied to
the pins labeled “vecl”. The buffer is set to work with incoming LVDS data by default.
CML-to-CMOS Converter
The CML-to-CMOS converter represents the output buffer of the Receiver. It includes a signal
converter based on the current mirror architecture and an output CMOS driver. The block
designed in a BiCMOS configuration operates at a data rate up to 1Gbps.
CMOS-to-CML Converter
The input CMOS-to-CML converter represents the input buffer of the Transmitter. It is designed
as a standard CML buffer with additional resistive dividers required for the handling of rail-torail CMOS signals.
LVDS Output Buffer
The proprietary LVDS output buffer utilizes NPN HBTs that are available in standard BiCMOS
technologies. It accepts the internal CML signals and converts them into output LVDS signals.
The buffert utilizes a special architecture that ensures operation at data rates up to 1Gbps with a
low power consumption level of 19mW. The buffer satisfies all the requirements of the IEEE Std.
1596.3-1996 and ANSI/TIA/EIA-644-1995.
Internal Data Processing Circuitry
The internal parts of all 4 channels include an XOR and multiplexer 2:1 CML cells. When
activated, the XOR performs the DS encoding or decoding required by the Space Wire protocol,
while the multiplexer operates as a selector between the channel’s input signal or XORprocessed signals. The corresponding control signals are generated by the receiver or transmitter
control blocks (RCB or TCB) from 3-state external activation control signals.
Each channel can function as an independent converter, as well as a data or clock/strobe
converter in accordance with the following table.
Rev.: D02, Sept2006.
ASNT3010
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
“crlt1”/”crlr1” “crlt2”/”crlr2” Channel 1 (T or R) Channel 2 (T or R)
off
off
VEE
VEE
N/C (Default)
off
on
VEE
off
on
VEE
VCC
N/C (Default)
on
off
VEE
N/C (Default) N/C (Default)
on
on
N/C (Default)
Data
Strobe/Clock
VCC
on
off
VCC
VEE
N/C (Default)
Strobe/Clock
Data
VCC
on
on
VCC
VCC
TERMINAL FUNCTIONS
Name
vcc
vee
veed
vecl
rfbL
rfb2_2
rfb2_1
rfb1_1
rfp
crlt2
crlt1
crlr1
oncml
onecl
crlr2
vcm
dm2
dm1
qm2
qm1
d1p
d1n
d2p
d2n
q1p
q1n
q2p
q2n
TERMINAL
Number
2,7,14,20
1,5,9,15,23,27
19
26
3
4
21
22
6
10
13
18
24
25
32
8
11
12
16
17
28
29
30
31
33
34
35
36
Rev.: D02, Sept2006.
DESCRIPTION
Type
PS
PS
PS
PS
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
DC voltage
Input
Input
Output
Output
Input
Input
Input
Input
Output
Output
Output
Output
Positive power supply
Negative power supply (analog ground)
Digital ground
ECL input termination voltage
Internal reference voltages. Used only in test
operational modes. For normal operation must be left
not connected.
Transmitter channel 2 activation control signal
Transmitter channel 1 activation control signal
Receiver channel 1 activation control signal
Activation of the input CML termination mode
Activation of the input ECL termination mode
Receiver channel 2 activation control signal
CMOS input threshold voltage, default: (VCC+VEE)/2
Transmitter channel 2 SE CMOS input
Transmitter channel 1 SE CMOS input
Receiver channel 2 SE CMOS output
Receiver channel 1 SE CMOS output
Receiver channel 1 LVDS direct input
Receiver channel 1 LVDS inverted input
Receiver channel 2 LVDS direct input
Receiver channel 2 LVDS inverted input
Transmitter channel 1 LVDS direct output
Transmitter channel 1 LVDS inverted output
Transmitter channel 2 LVDS direct output
transmitter channel 2 LVDS inverted output
ASNT3010
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNIT
COMMENTS
General Parameters
VCC
VEE
VEED
VECL
Power consumption
3.14
Junction temperature
-25
3.3
0.0
0.0
VCC-2.0
7.0
20.0
115.0
50
3.47
125
V
V
V
V
mW
mW
mW
°C
±5%
LVDS grownd
CMOS ground
1 Receiver channel, DC
1 Transmitter channel
Total
LVDS Inputs
Data Rate
DC common mode voltage
AC common mode voltage
Sensitivity
0.0
VEE
VEE
1.0
VCC
2.4
Frequency
Logic “1” level
Logic “0” level
0.0
VCC-0.4
60
Gbps
V
V
mV
DC voltage
AC signal <5MHz
CMOS Inputs
1.0
0.4
Gbps
V
V
LVDS Outputs
Voltage Swing
CM voltage
Impedance
Total current
Output current
Rise/Fall Times
320
1.2
77
45
5.2
17
4.5
73
1.25
122
115
5.7
27
7.0
95
mV
V
Ohm
Ohm
mA
mA
mA
pS
Each SE output
DC test
AC test (0-1Gbps)
From “vcc”
Shorted to VEE
Shorted together
20%-80%
CMOS Outputs
Logic “1” level
Logic “0” level
Rise/Fall Times
Duty Cycle
VCC-0.2
45%
0.2
TBD
50%
V
V
20%-to-80%
55%
CMOS Control Inputs
Logic “1” level
Logic “0” level
Rev.: D02, Sept2006.
VCC-0.4
0.4
V
V
ASNT3010