The “Ultimate” CMOS Device:
A 2003 Perspective
(Implications for Front-End
Characterization and Metrology)
Howard R. Huff and Peter M. Zeitzoff
International SEMATECH
Austin, TX 78741
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
Agenda
• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
2
Simplified Cross-Section of MOSFET
Transistor Structure
Gate electrode,
poly
Spacer
High-k Gate
Dielectric Stack
Source
Upper interfacial
region
Lg
Bulk high-k
film
Si Substrate
(or SOI with Si
thickness ≈1/3 Lg)
Drain
Lower interfacial
region
Modified from P.M. Zeitzoff, R.W. Murto and H.R. Huff, Solid State Technology, July 2002
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
3
Integrated Circuit Historical Scaling Trends
• 4K DRAM (1974)
• SiO2 thickness ≈ 75-100 nm
• Channel physical length (Lg) ≈ 7500 nm
• Junction depth ≈ several µm
• Power supply = 5 V
• High-performance MPU (2003) - ITRS:
100 nm technology generation
• SiO2 equivalent oxide thickness (EOT) ≈ 1.1 - 1.6 nm
• Channel physical length (Lg) ≈ 45 nm
• Extension junction depth ≈ 25 nm
• Power supply = 1 V
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
4
Pervasiveness of Microelectronics Revolution
• Learning curve (Haggerty)
– Market elasticity (1960’s …)
• Moore & device scaling (Dennard –1968 -1T/1C DRAM cell)
– Moore’s Law
• Number of transistors per chip doubles every year (1965)
– Technology: Feature reduction
– Design: Reduction in number of transistors per memory cell
from 6 (SRAM) to 1.5 (DRAM)
• Number of transistors per chip doubles every two years (1975)
– Technology: Feature reduction
– Design: No more reduction in transistors per memory cell
possible. Benefits derived only from improvements in layout
• Industrial concern in mid ’90s as regards fab economic
constraints might reduce return on capital investment
• Int’l Technology Roadmap for Semiconductors (ITRS)
– Focus to ensure Moore’s law by realizing the roadmap
– Expansion of economy (GWP) - market elasticity (2000’s) accommodates IC CAGR
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
5
Introduction
• Moore’s law and scaling – lower cost per function
– Lower power dissipation per function
– Increased speed (intrinsic transistor gate delay)
– Increased transistor and function density
• MOSFET scaling: processes/structures/tools
– Meet both increased Ion and low Ioff (Ileak) metrics
– Reduce Igate for ≤ 1.5 nm gate dielectric
– Fabrication / control for abrupt, shallow, low sheet
resistance S/D extensions
– Control short channel effects (SCE) ….
• Potential solutions & approaches:
– Material and processes (front end): high-k gate
dielectric, metal gate electrodes, elevated source / drain
– Structural configurations: non-classical CMOS devices
Mar 25, 2003
• Fully depleted, multi-gate SOI structures
• Challenge of uniformity control in scaling body thickness and
width in fully depleted SOI with decreasing Lg
2003 International Conference on Characterization and Metrology for ULSI Technology
6
2001 ITRS Projections of EOT for HighPerformance Logic and Low Standby-Power
EOT vs. Calendar Year
3.00
2.50
EOT (nm)
2.00
EOT, High-Perf.
EOT, LSTP
1.50
1.00
0.50
1 molecular layer of oxide
0.00
2001
2003
2005
2007
2009
2011
2013
2015
Calendar Year
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
7
2001 vs. 1999 ITRS Projections of Physical Gate
Length (Lg): High Performance Logic
100
90
80
Lg (nm)
70
60
Lg, ’99
50
ITRS
40
30
20
10
0
2000
Mar 25, 2003
Lg, ’01
ITRS
2002
2004
2006
2008
2010
2012
2014
2016
Year
2003 International Conference on Characterization and Metrology for ULSI Technology
8
ITRS Projections of Vdd and Vt Scaling
1.2
Vdd-Low Power
V dd , V t (V)
1.0
0.8
Vdd-High Perf.
0.6
0.4
0.2
0.0
2001
Vt-Low Power
Vt-High Perf.
2003
2005
2007
2009
2011
2013
2015
Year
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
9
2001 ITRS Projected Scaling of 1/τ and Isd,leak for
High Performance & Low Standby Power
(under revision)
10000
1.E+01
Isd,leak, High Perf.
1.E+00
1/ (GHz)
1.E-01
1.E-02
1000
1/τ, Low
Power
Isd,leak, Low Power Driver
100
2001
1.E-03
1.E-04
I sd,leak (µA/µm)
1/τ , High Perf.
Driver
1.E-05
1.E-06
2003
2005
2007
2009
2011
2013
2015
Year
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
10
Idsat Trends
• Idsat trending slightly above 1 mA/µm for nMOS
and approaching > 0.5 mA/µm for pMOS
• Concurrently, intrinsic transistor gate delay has
trended below sub 1 psec for nMOS and slightly
below 1 psec for pMOS as Lg ≤ about 20 nm
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
11
Relative Chip Power Dissipation for High
Performance MPU (Based on 2001 ITRS)
Relative Chip Power Dissipation
Normalized to 2001
1.E+04
Assumptions:
Chip Static Power
Dissipation
•Only one type of
(high Ion, high
Ileak) transistor
and no power
reduction
techniques
1.E+03
•Simple scaling
1.E+02
•Unrealistic
scenario, only
meant to clearly
illustrate static
power dissipation
issues
Chip Dynamic Power
Dissipation
1.E+01
1.E+00
2001
2003
2005
2007
2009
2011
2013
2015
Year
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
Allowable
Total Chip
Power
Dissipation
12
Agenda
• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
13
Difficult Transistor Scaling Issues
• Previously discussed scaling results involve high-level,
idealized MOSFET physics
– Assumption: highly scaled MOSFETs with required characteristics
can be successfully fabricated
• Lateral / vertical MOSFET dimensions (EOT, xj’s, spacer
width, etc.) scaling down rapidly with Lg
• Increasing difficulty in meeting transistor requirements
with scaling
– High gate leakage
• Direct tunneling increases rapidly as Tox is reduced
– Poly depletion in gate electrode⇒ increased effective TEOT,
reduced Ion
– Quantum effect on near-surface charge additionally increases TEOT
– High Rseries,s/d ⇒ reduces Ion in scaling source / drain extension and
deep source / drain junctions
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
14
Advanced CMOS Scaling Options
Device Type
High-k
Metal Gate
MG
DM
Strained Si
SiGe Process R S/D
SOI
Permutations
Scaled Bulk CMOS
X
X
X
X
X
X
Partially Depleted
X
X
X
X
X
X
Req'd
47
Fully Depleted
X
X
X
X
X
Req'd
31
Multi-Gate FET
FinFET - 2 gates
X
X
X
X
Req'd
15
X
X
X
X
Req'd
15
MuG-FET >2 gates
47
Courtesy of Rinn Cleavelin and Rick Wise, Texas Instruments, Inc.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
15
High-k Gate Dielectric Candidates (and Issues)
• Modest k (<10)
• Al2O3
• Negative charge, complicated defect structure
• Medium k (10-25)
• Group IV Oxides - ZrO2, HfO
• Low crystallization temperature, unless “doped”
• Group III Oxides - Y2O3, La2O3,…
• Charge, epitaxial configurations
• Silicates - (Zr, Hf, La, Y, ..) • SiO4
• Lower k if too diluted with SiO2
• Aluminates - (Zr, Hf, La, Y, ..) • Al2O3
• Charge issue, complicated defect structure
• High k (≥ 25)
• Ta2O5 , TiO2
• Low-barrier height
C. M. Osburn & H. R. Huff, Spring ECS Meeting, 2002, abst. #366
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
16
High-K Issues
• Process integration
– Thermal stability of high-k material
• Retain high-k performance with planar CMOS flow (S/D anneal
temperature, ambient, oxygen partial pressure, etc.,)
– “Replacement gate” flow useful to quickly assess materials
– Thermal, chemical compatibility with polysilicon
• Boron penetration
• Metal electrode may be required
– Interface with both Si substrate and gate electrode
• Deposition / post process anneals modify interfacial SiO2 layer,
TEOT
• Interface properties: Dit, Nt, Qf, µ = µ(interfacial SiO2)
• Leakage, reliability
• Short channel effects (SCE)⇒ fringing field effects
• New material: major challenge
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
17
Process - Structure - Property Relation
• Crystalline / polycrystalline
– Phase structure
• Epitaxial alignment to substrate
– Stoichiometry
– Bond coordination
– Morphology
– Interfacial microroughness
• Retention of amorphicity by doping
• Mixed oxide phase separation
• Spatial inhomogeneity / periodicity in energy gap(s)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
18
MOCVD HfO2 CV Curve (EOT = 0.95 nm)
140
Corrected Freq Data
CVC Model
100
Area = 5.0E-5 cm2
Frequency = 100 and 250
kHz
Gate Electrode : PVD TiN
80
HfO2 @ 485C
Interface: N2O at 750C
Capacitance [pF]
120
60
CVC Model
40
EOT = 0.95
nm
Gate Leakage
4.3 A/cm2 @ 1V
10 A/cm2 @ Vfb+1
20
Vfb = -0.239 V
Nsurf = 2.11E15
0
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
Voltage [V]
Avinash Agarwal et al., (Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics,
2001 MRS Workshop Series (2001) (reprinted with permission of the MRS Society)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
19
MOCVD HfO2 TEM (EOT = 0.95 nm)
(HfO2 on HF-last, N2O-750°C Pre-Deposition Anneal)
PVD TiN 450 Å
HfO2 21 Å
Interfacial layer 12 Å
Silicon substrate
• Effective k for above dielectric stack ≈ 13.5
• k for interfacial layer may be significantly greater than SiO2 indicating
reaction or intermixing of HfO2 film with interfacial SiO2
• “High” surface roughness at HfO2 / TiN interface may contribute to high Jg
Avinash Agarwal et al., Alternatives to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics,
2001 MRS Workshop Series (2001) (reprinted with permission of the MRS Society)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
20
2001 ITRS Projections Versus Simulations of Direct Tunneling
Gate Leakage Current Density for Low Standby Power Logic
(under revision)
1.E+02
3
Simulated Jgate2.5
,
oxynitride
1.E+00
1.E-01
2
1.E-02
Specified 1.5
Jgate, ITRS
1.E-03
1.E-04
1
1.E-05
1.E-06
1.E-07
Tox
Beyond this point, oxynitride
too leaky; high k needed
T ox (nm)
J gate (A/cm 2)
1.E+01
0.5
0
2001 2003 2005 2007 2009 2011 2013 2015
Year
Implementation of high-k driven by low standby power logic in 2005
Simulations by C. Osburn, NCSU and ITRS
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
21
Polysilicon Limitations
• Polysilicon depletion
– Increases effective “electrical” EOT ⇒ reduces
Eox and hence inversion charge
– As EOT is scaled ⇒ poly doping must increase
• Ge:Si facilitates increased B incorporation
• Boron penetration (PMOSFET) in thin oxides
– Oxynitrides & reduction of (DT)0.5 effective now
• Compatibility with high-k
• Gate resistance of thin gates (with silicide)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
22
Metal Gate Electrodes
• Metal gate electrodes potential solution
when poly “runs out of steam”
– Implement <≈ 65 nm technology node (2007)
– No depletion, very low resistance gate, no
boron penetration, compatibility with high-k
• Issues
– Different work functions for PMOS and NMOS
⇒ 2 different metals required
• Process complexity, process integration
• Utilize one metal: tune work function via N implant
(i.e., Mo)
– Plasma etching / damage of metal electrodes
– Compatibility with spacer and sidewall profile
– New materials: major challenge
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
23
ALD HfO2 / Poly-Si vs. HfO2 /TaN/Al
3 nm HfO2/poly- Si transistor ( Yudong Kim)
SC-1 SC-2 / HO / Poly-Si
Top Interface
2.5E-06
EOT = 15.3 A
Capacitance [F/cm^2]
2.0E-06
Vfb = -0.471 V
RMS = 1.7 %
1.5E-06
1.0E-06
Poly-Si Electrode ; +2V->-2V
Poly-Si Electrode ; -2V->+2V
Poly-Si Electrode ; CVC model
TaN/Al Electrode ; +2V->-2V
TaN/Al Electrode ; -2V->+2V
TaN/Al Electrode ; CVC model
Bottom
Interface
EOT = 18.62 A
Vfb = -0.751 V
RMS = 9.7 %
poly Con.=1e20 /cm3
5.0E-07
Frequency = 100 kHz
0.0E+00
-2
-1.5
-1
-0.5
0
0.5
1
Voltage [V]
• EOT increase by poly-Si gate process comes from both top and
bottom interfaces, former suppressed by metal electrode
• CV stretch-out becomes worse in HfO2 / poly stacks, suggesting
degraded interface quality after thermal cycle process
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
24
Source / Drain Extension Issues
• Increasingly abrupt, shallow, heavily
doped profiles required for
successively scaled technologies
– Needed for optimal devices, especially to
control SCE
– Difficult ρs,ext-xj,ext tradeoffs, especially for
PMOS (B) ⇒ difficult to control RS/D,series
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
25
Source / Drain Extension Potential Solutions
• Near-term
– Ultra-low energy implants (< 1 KeV, B)
– Rapid Thermal Processing (RTP) and spike
anneal: reduces (DT)0.5 and thermally
enhanced diffusion
• Role of residual Sii during “slow” cool-down
– Increase dose as much as possible ⇒ reduced
Rseries,s/d
• Beyond 90 nm technology generation
– Doped, selective epi
– Co-implant
– Laser thermal annealing, …
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
26
Potential Front-end Solutions for Power
Dissipation Problems, High-Performance Logic
• Increasingly common approach to concurrently
meet chip power, performance and density
requirements to place multiple transistor types on
chip ⇒ multi-Vt, TEOT, Lg, Xj…
– Utilize high-performance, high-leakage transistors only
in critical paths - lower leakage transistors elsewhere
– Improves flexibility for system-on-chip (SOC)
• Electrical or dynamically adjustable Vt devices
(future possibility)
• Circuit and architectural techniques: pass gates,
power down circuit blocks, etc.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
27
Agenda
• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
28
Device Metrics
• Power
• Pdynamic = fclock Cload Vdd2 and Pstatic = NtrW Ileak Vdd
• Intrinsic transistor gate delay (speed)
• τ = Cload Vdd / IDSAT
• Idsat (maximum saturated drain current)
• Idsat = (W/2Lg) (3.9KoA) (TEOT,INV)-1 µeff (VG-VT)2 (long-channel, ideal)
– W and Lg device width and physical gate length
– TEOT,INV = equivalent oxide thickness in inversion
• TEOT = (khigh k / kSiO2) Tphys
– µeff = mobility, generally determined in long-channel device (gm)
– VG-VT = gate overdrive, where VG is voltage applied to gate
(VG ⇒ Vdd) and VT is threshold voltage
• Transconductance
– gm = (W/Lg) (3.9KoA) (TEOT,INV)-1 µeff Vdd (long-channel, ideal)
– Sub-threshold swing ⇒ Inverse slope of ln ID versus VG
• Drain-induced-barrier-lowering (DIBL)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
29
Limits of Scaling Planar, Bulk MOSFETs
• 65 nm technology generation (Lg = 25 nm, 2007) ⇒ beyond
– Increased difficulty meeting device metrics with classical planar,
bulk CMOS (even with material and process solutions: high k,
metal electrodes, elevated source/drain ….)
•
•
•
•
•
•
•
Control of SCE
Impact of quantum effects
Dopant stochastic variations (number and spatial location in channel)
Need for enhanced mobility, Id,sat
Impact of high substrate doping
Control of series source / drain resistance (Rseries,s/d)
Other contributors
• Alternative structures (non-classical CMOS) may be
required
– Band engineered transistors ⇒ improved transport/mobility
– Ultra thin body SOI
– Multi- gate SOI - Including FinFET and Vertical FETs
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
30
Electrostatic Scaling - Channel Leakage (Ioff)
Gate
Leakage
Gate
Source
Drain
Channel
Leakage
Substrate
Thermionic
Emission
E CB
E VB
Source
QM
Tunneling
Sum = Ioff
BTB
Tunneling
Lgate
Channel Leakage
Drain
Jim Hutchby
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
31
High Resolution TEM Showing 30 nm
Channel Length
Polysilicon Gate
polysilcon gate
13 layers
of Si atoms
consumed
to create
3.5nm SiO2
3.5nm SiO2
inversion charge
two decades
Source in 10 nm
electron
mean free path
Drain
4 nm
30 nm Channel Length
78 columns of Si atoms
donor atom
acceptor atom
Courtesy of Yoshi Nishi / Dick Chapman
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
Representative Theoretical and Universal
Mobility Curve
µeff (cm2/v-sec)
Universal
curve
µpk,univ
Degraded high-k
curve
µpk
µhi,univ
µhi
ET
Mar 25, 2003
Epk
Eeff (MV/cm)
Ehi
2003 International Conference on Characterization and Metrology for ULSI Technology
33
Mobility Considerations
• Theoretical
– Low electric field
• Unscreened (by inversion layer free carriers) ionized dopant
scattering centers in silicon
– High electric field
• Surface acoustic phonons
• Surface microroughness
– H x L (where H is height of surface undulation and
L is undulation correlation length)
• Remote scattering by high-k phonons (modulated by
interfacial SiO2)
• Experimental adders (not presently theoretically modeled)
–
–
–
–
Interfacial and high k bulk traps
Crystalline inclusions in amorphous high k gate dielectric
N, Al and other elemental (interface) scatterers
Remote scattering due to gate electrode
• Universal curve ignores scattering from ionized dopants
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
34
Band Engineered MOSFETs: Surfacechannel Strained-Si MOSFET Structures
Gate
Source
n+ poly
high mobility
channels
Drain
SiO2
Gate
Source
n+ poly
Drain
SiO2
Strained Si
n+
n
+
p
Strained Si1-xGex p+
p- Relaxed Si1-xGex
y=x
n- Relaxed Si1-xGex
y=x
p Strained Si
n+
p- Si1-yGey Graded Layer
p+ Si Substrate
y=0.05
n- Si1-yGey Graded Layer
n+ Si Substrate
y=0.05
+ Increased effective mobility, increased Ion
- Difficult integration issues, manufacturability
- Compatibility with ultra-thin body SOI
- Cost
Judy Hoyt, MIT
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
35
Effective Electron Mobility, µeff (cm2/ V sec)
Electron Mobility Enhancement in Strained Si
MOSFETs (Rim,et al., IEDM 1998)
800
Welser et. al., IEDM '94
Strained Si on
relaxed Si0.8Ge0.2
this work
600
400
200
Unstrained Si control
Universal Mobility
(S. Takagi et. al., TED '94)
Room T
0
0.00
0.25
0.50
0.75
1.00
1.25
Vertical Effective Field, Eeff (MV/cm)
• Electron mobility enhancement of ~ 1.8X persists up to high Eeff (~ 1MV/cm)
• Strained-Si allows “moving off” universal mobility curve
Judy Hoyt, MIT
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
36
Strained Si:Ge
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
37
Strained Si Device Structures
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
38
Electron Transport in εMOS™
Biaxial
Tension
Unstrained
[001]
[001]
perpendicular
∆2 valleys
in-plane
∆4 valleys
[010]
[010]
[100]
Tensile strain splits
conduction band
degeneracy
[100]
• Reduced intervalley scattering
• Light in-plane effective mass
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
39
Hole Transport in εMOS™
Biaxial
Tension
Unstrained
E
in-plane
out-of-plane
in-plane
out-of-plane
k
Heavy Hole
Light Hole
Split-Off
Tensile strain splits
valence band
degeneracy
• Reduced intervalley scattering
• Light in-plane effective mass
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
40
εMOS™ Electronic Structure
EV
EF EC
Strained Si channel
Uniform SiGe
layer
Graded SiGe
Si substrate
Type II Band Offset B Vt Shift
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
41
Defect Control: SiGe Virtual Substrates
Threading
dislocation
aSiGe
Misfit dislocation
array at each
interface
aSi
Each layer relaxed
to intermediate
lattice constant
• Constant low strain rate
• minimize dislocation nucleation
• Relaxation via existing defects
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
• low threading dislocation density
2003 International Conference on Characterization and Metrology for ULSI Technology
42
Systems Substrate Technology
• Underlying misfit dislocation array affects local
epitaxial growth rates
• “Crosshatch” surface roughness can be
problematic for device manufacturability
– Photolithography
– Optical metrology
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
43
Substrate Technology
RMS Roughness before CMP : 50-100 Å
After CMP : <2 Å
Proprietary planarization & regrowth process is a
key differentiator of AmberWave substrate technology
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
44
Strained Silicon: XTEM
Strained Si
Relaxed SiGe
Relaxed SiGe
Graded SiGe
Si Substrate
• 20% SiGe virtual substrate
• 175 Å strained Si
Well-controlled introduction of misfit dislocations results
in a high quality relaxed SiGe substrate for strained Si
Courtesy of Matt Currie
AmberWave Systems Corp.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
45
Drain Current versus Source-Drain Voltage
15-20%
self-heating
degradation
K.A. Jenkins and K. Rim, Measurement of the Effect of Self-Heating in Strained-Silicon MOSFETs,
Electron Dev. Lett., 23, 360-362 (2002) (© 2002, IEEE)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
46
Strained-Si PMOSFET on SiGe-on-Insulator
Tensile Strain
S
p+
G
Gate
SiO2
Strained Si
Relaxed
Si1-xGex
D
p+
Buried SiO2
SiGe Buffer
Si Substrate
T. Mizuno et al., IEDM, 934-936 (© 1999, IEEE)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
47
Strained-Si PMOSFET on SiGe-on-Insulator
n+-Poly Gate
(200 nm)
SiO2 (9 nm)
Strained-Si (20 nm)
Si0.9Ge0.1 (340 nm)
Buried-Oxide (100 nm)
T. Mizuno et al., IEDM, 934-936 (© 1999, IEEE)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
48
Limits of Scaling Planar, Bulk MOSFETs
• 65 nm technology generation (Lg = 25 nm, 2007) ⇒ beyond
– Increased difficulty meeting device metrics with classical planar,
bulk CMOS (even with material and process solutions: high k,
metal electrodes, elevated source/drain ….)
•
•
•
•
•
•
•
Need for enhanced mobility, Id,sa t
Control of SCE
Impact of quantum effects
Dopant stochastic variations (number and spatial location in channel)
Impact of high substrate doping
Control of series source / drain resistance (Rseries,s/d)
Others
• Alternative device structures (non-classical CMOS) may be
required
– Band engineered transistors ⇒ improved transport/mobility
– Ultra thin body SOI
– Multi- gate SOI - Including FinFET and Vertical FETs
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
49
Transistor Structures
Planar Bulk
Partially Depleted
SOI
Fully Depleted
SOI
G
D
G
D
S
D
G
S
S
BOX
Buried Oxide (BOX)
Depletion Region
Substrate
Substrate
+ Wafer cost / availability
- SCE scaling difficult
+ Lower junction cap
+ F.B. performance
- High doping effects and
statistical variation
- Parasitic junction
capacitance
boost
- F.B. history effect
- SCE scaling difficult
- Wafer cost/availability
Substrate
+ Lower junction cap
- SCE scaling difficult
- High Rseries,s/d⇒raised
S/D
- Sensitivity to Si
thickness (very thin)
- Wafer cost/availability
References:
1. P. Zeitzoff, J. Hutchby and H. Huff, Internat. Jour. High Speed Electronics & Systems
2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Short-channel
Short-channel MOSFET:
MOSFET:
DIBL
DIBL
or: Drain-Induced Barrier Lowering
Gate
Source
Drain
E-field
lines
Silicon wafer (back gate)
J-P Colinge, U.California., Davis
Mar 25, 2003
Electric field lines
from the drain
encroach on the
Electric field lines from drain
channel
encroach
on region.
channel Any
region.
increase of drain
Any increase of drain voltage
voltage decreases the
decreases threshold voltage
voltage
(the
(thethreshold
“NPN” potential
barrier
“NPN”
potential
between
source
and drain is
barrier between source
lowered)
and drain is lowered).
2003 International Conference on Characterization and Metrology for ULSI Technology
51
Electrostatic Scaling - Channel Leakage (Ioff)
Gate
Leakage
Gate
Source
Drain
Channel
Leakage
Substrate
Thermionic
Emission
E CB
E VB
Source
QM
Tunneling
Sum = Ioff
BTB
Tunneling
Lgate
Channel Leakage
Drain
Jim Hutchby
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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E-Field lines
G
G
S
D
P+
P+
S
D
P+
P-Si
P-Si
Ground-plane SOI MOSFETs
J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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E-Field lines
G
S
G
D
S
D
G
Regular SOI MOSFETDouble-gate MOSFE
J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Schematic Cross Section of Planar Bulk, UTB
SOI and DG SOI MOSFET
Inversion
Layer
Depletion
Region
Bulk MOSFET
+
+
++
-
-
-
+
++ +
-
Tsi
Tsi
S
- -
+
++
D
Ultra-Thin
Body SOI
+
+
-
+
+
-
Double-Gate SOI
MOSFET
BOX
BOX
Si Substrate
Mar 25, 2003
Ultra-thin
silicon film
Ultra-thin
silicon film
Si Substrate
2003 International Conference on Characterization and Metrology for ULSI Technology
55
Ultra-Thin Body, Fully Depleted Single and DoubleGate Transistors: Pros and Deltas
Single Gate:
+ Lower junction capacitance
G
S
Tbody
+ Reduced channel doping for
metal gate electrode, fully depleted
- SCE scaling difficult
- Sensitivity to Si thickness
- Wafer cost/availability
D
Buried Oxide
(BOX)
+ Enhanced scalability
SUB
Double Gate SOI:
Top
S
Ultra-thin
Si body
D
Bottom
Tbody
SUB
Buried
Oxide
+ Near ideal subthreshold slope, S
+ Reduced channel doping for metal
gate electrode, fully depleted
+ Lower junction capacitance
+ ~2x drive current
- ~2x gate capacitance
- Complex process
- Wafer cost/availability
- Most advanced, optimal device
structure, difficult to fabricate
P. M. Zeitzoff, J. Hutchby and H.R. Huff
M. Bohr, ECS Meeting PV 2001-2, Spring, ‘01
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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“Multiple Gates”
G
G
D
S
1
G
D
S
D
S
2
3
Buried Oxide
G
1: Single gate
2: Double gate
3: Triple gate
4: Quadruple gate (GAA)
5: Π gate
G
D
S
4
D
S
5
Buried Oxide
J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Simulation of Multiple-Gate SOI MOSFETs
4 IDo
3iIDo
π IDo
2 IDoo
o
o
IDo
Π Gate
1 Gate
2 Gates
3 Gates
4 Gates
J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
58
Double-Gate Transistor Structures
top gate
Double Gate
S
SOI
100 nm
G
IBM ‘97
D
source
bottom gate
Schematic
Cross-Section
S
FinFET
G
Gate
SiO2
D
Simplified view of
FinFET
(one type
(one
typeof
of
double-gate
double -gate
MOSFET)
MOSFET)
Key advantage: relatively
conventional processing,
largely compatible with
current techniques
drain
SiO2
Source
SiO2
Drain
BOX
T-J. King and C. Hu, UC/Berkeley
and Mark Bohr, ECS Meeting PV
2001-2, Spring, 2001
Top View
Fin
Drain
Source
Poly Gate
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Tri-gate Relaxes TSi Requirement of Single-gate
Courtesy of Robert Chau et al., ISSDM, 2002
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Tri-gate Relaxes WSi Requirement of Double-gate
Courtesy of Robert Chau et al., ISSDM, 2002
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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PI-Gate / OMEGA Gate Structure
β1
SOI
island
α
Buried oxide
SOI
island
Gate
material
Π
Buried oxide
Buried oxide
Silicon substrate
Silicon substrate
Silicon substrate
β2
SOI
island
Gate
material
Ω
Buried oxide
Buried oxide
Silicon substrate
Silicon substrate
J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
62
TSMC's Ω-gate (IEDM'02)
Fu-Liang Yang et al., IEDM, 255-258 (2002)
(© 2002, IEEE)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Quantum Wire MOSFET
(UCL SOI Conf., 1995)
J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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J-P Colinge, U.California., Davis
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
65
The Ideal MOS Transistor
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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One Can Utilize Multiple Fins to Enhance
Transistor Total Drive Current
Fin
Drain
Source
Poly Gate
T-J. King and C. Hu, UC/Berkeley and
Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Other 3-D Transistor Structures
HfO2
Vertical FET
(one type of
double-gate
MOSFET)
S
G
D
source
PSG
gate
c-Si
body
Agere ‘02
gate
PSG
drain
100 nm
REF: Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
Silicon on
Nothing
(SON):
localized
buried oxide
(BOX)
STM ’01
S. Monfray et al., IEDM, 645-648 (2001) (© 2002, IEEE)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Other 3-D Transistor Structures (con’t)
Agere ’02
c-Si
body
nitride
underlayer
50 nm
poly-Si gate
HfO2
nitride
45 Å
7Å
nitride
HfO 2
gate
Jack Hergenrother et. al., 50 nm Vertical Replacement-Gate (VRG) nMOSFETs with ALD HfO2 Gate Dielectrics,
Semiconductor Silicon/2002, ECS PV 2002-2, 929-942 (2002)
Reproduced by permission of The Electrochemical Society, Inc.
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Agenda
• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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2001 ITRS Key MOSFET Scaling Results
• High-performance logic
– Average 17%/yr improvement in 1/τ attained
– Isd,leak very high, particularly for 2007 and beyond
• Chip static power dissipation scaling an issue
• Assumption: Igate ≤ Isd,leak ⇒ unacceptably large Igate
under revision
• Low standby power logic
– Very low Isd,leak target met
• Igate ≤ Isd,leak ⇒ Igate low, but difficult to achieve
– 1/τ scales considerably slower (14%) than highperformance MPU
• ITRS MOSFET targets are chosen to aggressively
drive technology scaling
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Summary
• MOSFET device scaling “raw material” for meeting projected overall
chip power, performance, and density requirements
– Goals/requirements/tradeoffs jointly established between
designers and technologists
– Considerable design innovation and focus required, even with
aggressive technology scaling
• Scaling goals vary for different applications
– High-performance logic driven by transistor speed requirements
• Result: high speed, but high leakage, static power dissipation issues
– Low standby power logic driven by transistor leakage requirements
• Result: lower speed than high-performance logic
• Material and process potential solutions include high-k gate dielectric,
metal gate electrodes, elevated source / drain, spike annealing, and
eventually, novel S/D annealing and doping
– High-k needed first for low standby power (mobile) chips in ~ 2005
• Structural configurations: non-classical CMOS
• Material, process and structural solutions pursued in parallel and may
be combined in “ultimate,” end-of-roadmap device
– Lg ≤ 10 nm MOSFETs anticipated end of ITRS in 2016 (if not earlier)
• Lg~10 – 20 nm experimental devices reported in literature and
simulations indicate 5 nm or less feasible
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Summary
• Gate stack is a multi-element arrayed structure wherein
high-k and metal electrodes must be successfully
integrated into planar, scaled CMOS processes
– Extremely stringent material, electrical and integration challenges
• Impact of surface clean and wafer pre-conditioning
prior to high-k deposition as well as post-deposition
anneal (temperature, time and partial pressure of oxygen
in ambient) significantly impacts EOT and leakage
• Control of electrical charges incorporated at interfaces
and bulk high-k during high-k deposition /anneals critical
• Mobility complicated compilation of various contributors
• Interactive effects within Gate Stack process modules and
IC fabrication process requires utmost attention to
achieve requisite IC performance characteristics
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Non-Classical CMOS Summary
• Planar bulk CMOS < Lg ≈ 25 nm scaling difficult
– Enhanced mobility required
• Strained Si on relaxed or strained Si:Ge may be potential solution
• Key issues:
– Effectiveness of planar bulk CMOS scaling regime
• Working devices with Lg ≈ 10-20 nm recently noted
– Effective non-planar solutions must rectify very difficult
process issues for multi-gate, FD ultra-thin SOI
– Control short-channel effects by gate shielding
– Lg ≈ 5 nm may be possible with FD ultra-thin body SOI without
excessive band-to-band tunneling
• Ultimate MOSFET (Lg < 10 nm) may be lightly doped
channel, ultra-thin body SOI (multiple fins) with high-k gate
dielectric, multi-gate metal electrodes (mid-gap work
function), elevated source / drain, strained Si, etc. ⇒
“ultimate” CMOS device
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Evolving Trends of Alternative Novel Device
Structures Beyond CMOS
• Requirements
–
–
–
–
Capability to be integrated with Si-CMOS
Room-temperature operation
Capability for SOC, including gigabytes of memory storage
Portable capability, with opportunity for large-scale market
• Examples (non-ranked)
–
–
–
–
–
–
–
–
–
–
–
–
Opto-electronic system (with multi-layered epitaxial structures)
Spintronics
Self-assembled nanostructures (including molecular structures)
Nanowire arrays
Microclusters/quantum dots in “SiO2” (in higher-dimensional matrix)
Carbon nanotubes
Cellular automata
Fullerenes
Single-electron structures
Optical computers
DNA computers
Quantum computers
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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CMOL CONCEPT
molecular single-electron latching switch
gold nanowires
thiol group
as an alligator clip
S
OPE bridge
as a tunnel junction
single-electron
trap
SiO2 insulation
CMOS-to-MOL
plug
CMOS wiring
diimide acceptor as
an island
O
O
N
O
O
N
O
O
O
N
O
O
N
O
O
CMOS
plug
O
N
SOI MOSFET
Si substrate
S
O
O
N
O
gate
single-electron
transistor
O
S
longer bridge as an insulator/capacitor
S
Possible density: 3×1012 functions per cm2
K. Likharev and A. Mayr, 2002
(see http://rsfq1.physics.sunysb.edu/~likharev/nano/GigaNano010603.pdf)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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MOSFETS Below 10 nm: Quantum Theory
Konstantin K. Likharev – NanoMES 2003* – Tempe, AZ
• “Room-temperature devices with gate length (Lg) as short
as 5 nm still have high transconductance and relatively
small DIBL effects and thus may be suitable for nearly all
digital applications. Moreover, transistors with Lg as small
as 2.5 nm may still feature voltage gain above unity and
hence may be the basis for digital electronics
• However, all characteristics of such devices are extremely
sensitive to very small variations of their geometrical
parameters (Lg, TSi and TEOT) as well as single charged
impurities inside (or in the immediate vicinity of the
channel)
• As a result of this sensitivity, fabrication of sub-10 nm
devices with acceptable yield will require extremely tight
specifications, far exceeding recent ITRS projections for
the year 2016”
* To be published in Physica E (2003)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Jim Hutchby
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
78
Microelectronics Revolution
• Gordon Moore (a)
– “But then you see the numbers or hear your
company’s name on the evening news … and
you are once again reminded that this is no
longer just an industry, but an economic and
cultural phenomenon, a crucial force at the
heart of the modern world.”
• Gordon Moore (b)
– “No exponential is forever: but “forever” can
be delayed!”
(a) Beyond Imagination:Commemorating 25 Years, SIA (2002) [Introduction by Gordon Moore]
(b) ISSCC 2003 / Session 1/ Plenary 1.1 (2003)
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Gordon Moore
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Agenda
• Introduction
– MOSFET scaling drivers
• Front-end approaches and solutions
• Non-classical CMOS structures
• Summary / Trends
• Acknowledgements
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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Acknowledgements
– Mark Bohr
– Konstantin Likharev
– Douglas Buchanan
– Gerry Lucovsky
– Dick Chapman
– Veena Misra
– Robert Chau
– T. Mizuno
– Jim Chung
– S. Monfray
– Rinn Cleavelin
– Patricia Mooney
– J-P Colinge
– Yoshi Nishi
– Matt Currie
– Carl Osburn
– Paolo Gargini
– Gregory Parsons
– Evgeni Gusev
– Darrell Schlom
– Jack Hergenrother
– Thomas Skotnicki
– Judy Hoyt
– Bob Wallace
– Chenming Hu
– Glen Wilk
– Jim Hutchby
– Rick Wise
– T- J. King
– Fu-Liang Yang
Assistance of IC Fab line and FEP team at International SEMATECH and our
colleagues at the FEP- RC, IMEC, ASM and AMAT
Mar 25, 2003
2003 International Conference on Characterization and Metrology for ULSI Technology
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