December 2001
OKI Technical Review 188
Vol. 68
Special Edition on the Environment
Design of Low Power-Consumption LSI’s
Toshiaki KURITA*, Mitsuo TAKEMOTO*
Abstract
As one of our approaches to environmental protection, at Oki Network Systems Group (hereinafter, NW Group), we have
been working on reducing the power consumption of communications equipment. In this paper we describe in particular
our work to reduce the power consumption of LSI’s which make up a large part of the power consumed by such equipment.
Over the years, CMOS LSI’s have held the position of being exemplary low power-consumption devices. However,
demands on equipment incorporating CMOS LSI’s for higher speed and greater levels of integration have caused CMOS
LSI power consumption to increase four-fold in just three years.1
In this situation, beginning in 1998 NW Group has implemented a program to manage reduction of LSI power
consumption whenever such devices are designed. Specifically, we are having LSI designers develop design methods to
lower power consumption and we encourage the application of those design methods in each step of the LSI design process.
As a result, we have succeeded in reducing power consumption per logic kilo-gate at the rate of 20 ~ 30% per year. (See
Figure 1.)
In this paper we provide a brief summary of these design methods for reducing power consumption and describe work
planned for the future.
Concerning Power Consumption in CMOS
LSI’s
The formula for calculating power consumption in CMOS
LSI’s is shown in “Equation 1.”
P=1/2.CV 2fN+QVfN+I1 V (Equation 1)
Here, P is power consumption, C is load capacity, f is
frequency, V is source voltage, N is signal switching coefficient, Q is charge due to through-type current, and I 1 is
leakage current.
Figure 2 shows the concept of CMOS power consumption by showing the basic circuit (cell) and the components
of power consumption represented by each of the elements
in Equation 1.
The elements of Equation 1 are understood as follows:
① is the power consumption caused by signal line switching
Vdd
PMOS
2
1
3
NMOS
Figure 2: Concept of power consumption in a basic
CMOS circuit cell
0.009
0.008
0.0077
0.007
0.0060
W/KG
0.006
0.005
0.0040
0.004
0.0032
0.003
0.002
0.001
0
1997
23%
34%
31%
reduction
reduction
reduction
1998
1999
2000
Figure 1: Trend in reduction in power consumption
per kilo-gate
*
Network Systems Company, Net Convergence Dept., Network LSI Business Promotion Unit.
and is represented by the first element on the right side
of Equation 1. This element accounts for 70% or more of
the electrical power consumption of the whole LSI.
② is the power consumption due to through-type current
within the cell and is represented by the second element
on the right side of Equation 1. It accounts for 10 ~ 30%
of the electrical power consumption of the whole LSI.
③ is the power consumption due to leakage current and is
represented by the third element on the right side of
Equation 1. It accounts for about 1% of the electrical
power consumption of the whole LSI.
④ In order to reduce electrical power consumption in
CMOS devices, it is necessary to reduce ¨ and which
have the largest contribution, and the following are
some effective measures which can be taken.
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Special Edition on the Environment
LSI design
Power management
STEP1
Study methods /
specifications
• Block-out LSI
• Power consumption estimation
• Specification design
• Selection of low voltage devices
• Selection of low power consumption
hardware macro-cells
Study achievability of
design as an LSI
• Decide on design methods for low
power consumption
STEP2
Function design
STEP3
Circuit design
STEP4
Layout design
• Create function specification sheet /
test specification sheet
• Optimization of block configuration
• Function description
• Power consumption estimation (gate level)
• Logic synthesis
• Function verification
• Selection of clock driver
• Optimization of floor plan
• Layout
• Timing design
• Test design
• Optimization of driver cells
• Control of wiring lengths
• Clock management
To the manufacturing
process
Figure 3: Approach to reduction of power consumption in CMOS LSI’s
(1) Lower source voltage (or signal amplitude) V. (voltage lowering)
(2) Lower circuit load capacity C. (capacity lowering)
(3) Lower frequency f (or the switching coefficient of
circuit, N) (toggle lowering)
Specific methods of lowering power
consumption
Below we explain the specific work being done in NW
Group to lower power consumption of CMOS LSI’s.
Figure 3 shows the design flow for LSI’s. Here, we have
divided the design process into the following four steps:
Step 1: From the specifications required of the LSI,
study the achievability of the LSI and determine design
rules and manufacturing methods.
Step 2: Function design; determine the functions and
configuration of the LSI.
Step 3: Circuit design; create the circuit data.
Step 4: Layout design; expand circuit data onto the chip.
In Step 1, of the various possible measures for reducing
power consumption, the most effective measure is voltage
lowering, as described under (1) above.
As shown in Equation 1, voltage V is a parameter which
relates to each element, ①, ②, and ③ in Figure 2, so voltage
30
lowering measures are the most effective means for reducing power consumption.
Figure 4 shows the year-to-year trend in the breakdown
of CMOS LSI’s developed by NW Group, by supply voltage. It shows the increase in the low voltage LSI segment.
In Step 2, of the main measures explained above, the
primary one we employ is circuit configuration design
which implements toggle lowering (3).
Below, we describe one example of a toggle lowering
method.
① Lower speed of internal operation through clock frequency division.
② Add a feature which stops the clock depending on the
operating mode.
③ Add a feature which stops the clock operation of nonselected functions .
① is the most effective method of reducing clock power.
Within the circuit, clock signals are the ones which
switch at the highest rate, and depending on the design, in
some cases they may account for approx. 60% of the power
consumed by the whole circuit. However, because, by
lowering the internal operating speed, the number of data
bits which can be transferred per unit of time also falls,
parallel processing of data becomes necessary and the scale
of the circuit becomes larger than in the case of high speed
December 2001
OKI Technical Review 188
Vol. 68
Function A
1997
0
1
1998
5V devices
3.3V devices
2.5V devices
1999
Function B
0
2000
0%
20%
40%
60%
80%
100%
0
1
Figure 4: Breakdown of LSI’s by supply voltage
operation. For that reason, when that method is applied,
the power consumed by the incremental circuitry must be
calculated and the actual benefit confirmed.
② is a method whereby supply of the clock signal is
stopped for circuit blocks which are not operating, thus
holding back unnecessary power requirements. It is effective in cases such as when several pieces of equipment share
the use of a multi-function LSI. One disadvantage is that
circuits are inserted combinatorial with the clock and time
delay variations (clock skew) may occur between the separated clocks. As a countermeasure, we perform layout design, which is usually a later process step, in advance, thus
facilitating timing convergence.
③ is a method that is similar to ②, but it is an effective
means in cases where the scale of gates in the circuit which
is to be stopped is small. (See Figure 5.)
Specifically, the operation of functional blocks not selected by a later stage selector is stopped by a control circuit
in an early stage of the block (fixing input data, forcing the
resetting of flip-flops, etc.)
Next we will explain the voltage consumption reducing
measures taken in Step 3.
The primary measures taken in this stage are aimed at (2)
capacity lowering and (3) toggle lowering, which are two of
the countermeasures described above.
Here is one example.
④ Insert a flip-flop in the large capacity network in which
it is easy for pulse noise (hazards), caused by minute
delay differences, to propagate.
⑤ Through logic synthesis, create circuits with a shallow
number of logic steps.
⑥ Optimize driver cells.
④ is a measure for toggle lowering and its main use is
for the output(s) of circuits configured with many branch
ends. Power consumption due to hazards is said to reach
15 ~ 20% of the circuit total, so this measure has a large
impact.
⑤ also is a method, like ④, for preventing the occurrence of hazards. In general, hazards tend to occur in
circuits with a deep number of logic steps. Consequently, hazards can be controlled by “flattening the
circuit” at the time of logic synthesis and thus creating
a circuit with a shallow number of logic steps.
Function A
0
1
Function B
0
Fixed
Figure 5: Stopping the clocks of unused blocks
⑥ is a measure for reducing through-type current
in a cell. Through-type current in cells of CMOS
circuits is generated when signal transition occurs.
Consequently, if the rise time (from low to high) (t lh )
and the fall time (t hl ) become large, the through-type
current becomes large. The driver cells are used for
adjusting the waveform of the signals in the circuit.
By inserting them in signal networks where the abovementioned t lh and thl are large, t lh and t hl will be
improved and through-type current can be reduced.
Because it is not possible for his work to be done
manually by the designer, it is done with a commercial power synthesis tool or a layout tool.
Lastly we will explain the power reduction measures
which are taken in the layout design stage. The following is
one example:
⑦ In chip layout, increase density of function blocks having high signal transition rates.
⑧ Reduce number of wiring nets between multi-function
blocks whose location area has been specified. (See
Figure 6.)
⑨ Make a floor plan that minimizes block-wiring area.
Thus, in layout design, lowering load capacity by shortening wiring lengths between cells becomes a means of
lowering power consumption.
Cell A
Cell A
Block C
Block B
(a) A wiring net that extends
across blocks
(b) A wiring net confined
within a block
Figure 6: Reducing wiring between blocks
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Special Edition on the Environment
⑦ is a measure to shorten the distance between cells and
thus prevent occurrence of long wiring traces, by laying out
cells in high density on the LSI chip.
Like ⑦, ⑧ is a measure for shortening wiring lengths.
In general, there is a tendency for the wiring lengths of
inter-block wiring (wiring between blocks whose layout
area is specified) to become long. In (a) of Figure 6,
because cell A was positioned in block C, inter-block
wiring, between block B and block C, results. In contrast, in (b) cell A was positioned in block B, so interblock wiring was eliminated. At Oki Electric, we optimize chip “floor plans” using floor plan tools and a
“layout difficulty checker” (LDC), which we developed
internally. These enable shorter turnaround time (TAT)
and provide a means of reducing power consumption by
shortening wiring traces.
⑨ is noteworthy because of its effect in reducing clock
power consumption by optimizing the drive cells for clock
networks. Figure 7 shows two examples in which clocks of
the same type are wired in chip areas D and E. In example
(a), the layout relationship for D and E is an L shape. In this
kind of a layout the distances between the elements in D
and E are long, so it is easy for clock delay variations
between D and E to become large. As a result, using a layout
tool, an appropriate number of driver cells for adjusting the
delays must be inserted into the clock wiring to minimize
the clock delay variations between D and E. In contrast, in
example (b), the shape of the layout areas for D and E is
made into a rectangle. In such a layout, the distances
between the elements in D and E is shorter and the amount
of delay variation which occurs is less than in the case of (a).
As a result, the number of driver cells needed for adjusting
the delays between clock wiring becomes less than the case
of (a) and the power consumption for such cells can be
correspondingly reduced.
In this way, through a floor plan that takes account of
block wiring areas, it becomes possible to lower the amount
of power consumed by clocks. At Oki Electric, when making floor plans, we estimate clock power consumption and
optimize block layout.
Concerning Future Directions in Reducing
Power Consumption
D
B
C
A
C
E
F
(a) An inefficient block layout
B
A
D
F
E
(b) An efficient block layout
Figure 7: Optimization of clock wiring
lowering of supply voltage while maintaining high speed
operation. We think that introducing such devices will be
a very effective means for reducing power consumption in
CMOS LSI’s which are expected to require even higher
speeds and denser integration in the future.
At Oki Electric, we are developing proprietary macro’s
which incorporate SOI technology and we plan to use them
in future designs. (They are becoming part of our Intellectual Property (IP).)
To achieve automation of gated clocks, we use commercially available power synthesis tools. By inserting a dedicated control cell into the clock, we can make clock operation stop when data is not switching, thus reducing clock
power consumption.
The thinking behind this is the same as for item ② above,
but a special feature is that, by automating the insertion of
clock control cells, using dedicated cells for control, and
linking to the layout tool, we can stop the occurrence of
timing problems.
In this paper, we have described the work of Oki Electric’s
NW Group aimed at reducing LSI power consumption and
have explained how this will develop in the future.
With the proliferation of portable devices and growing
concern about environmental protection, requirements for
lower power consumption in all communication equipment are becoming stronger every day.
Looking toward the future, at Oki Electric it is our policy
to continue our efforts to reduce LSI power consumption
and thus respond to the above-mentioned requirements.
References
Here are two measures for reducing CMOS LSI power
consumption which we plan to introduce in the future.
• adoption of Silicon on Insulator (SOI)
• automation of gated clocks.
SOI, as has already been announced in publications,
etc., refers to CMOS devices which use special silicon
wafers in which a dielectric layer such as SiO 2, etc. and thin
film silicon are formed on the CMOS surface. 2 SOI enables
32
1.
2.
Tadahiro Kuroda: Designing for Low Power Consumption, in the Journal of the Japan Electronic
Information Communication Institute, Vol. 81, No.
11, p. 1144, November, 1998.
Fukuda, et. al., Technologies for SOI-CMOS Devices, Oki Technical Review, Number 185, Vol. 68,
No. 1, p. 100, January, 2001.