CMOS standard‐cell performance
propagation delay models
Lecture 5
2013
Standard‐cell performance
•
•
•
•
•
•
•
Logic function
Silicon area
Input capacitance
Driving capability
Power dissipation
Propagation delay
Transition time
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AND2 cell
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AND2 cell
KLOAD is a resistance[ns/pf=k]
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Inverter
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Inverter
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Inverter cell architecture
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Inverter step‐response model
VDD
VDD
CGP
VIN
VOUT
IDSAT,P
CDP
VOUT
VIN
CGN
IDSAT,N
CDN
VSS
VDD
VOUT
tpd
VIN
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VDD/2
VSS=0
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Inverter ramp‐response model
VDD
VDD
CGP
VIN
VOUT
RP
CDP
VOUT
VIN
CGN
RN
CDN
VSS
VDD
VOUT
tpd
VIN
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VDD/2
VSS=0
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Inverter two‐port model
VDD
+
+
RP
VIN
VOUT
VIN
CG
VDD
RN
CD
VOUT
‐
‐
CG=CGP+CGN
CD=CDP+CDN
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Properties of 60 nm MOSFETs
IDS
IDS
N‐channel device
P‐channel device
IDSAT,max =
IDSAT,max =
600 uA/um
300 uA/um
RN´=2 km
RP´=4 km
VDS
VDD=1.2 V
VDD=1.2 V
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VDS
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Inverter twoport model
Widen p‐channel device to compensate for RP=2RN for equal device width: i.e. make p‐channel twice as wide as n‐channel
Now input gate cap: CG=3WLCox=3.6 fF/um, Output parasitic cap: CD=pCG, best value for p yet to be discussed.
+
VIN
+
Reff
CG
CD
VDD
‐
VOUT
‐
CG=CGP+CGN
CD=CDP+CDN
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Inverter twoport model
Widen p‐channel device to compensate for RP=2RN for equal device width: i.e. make p‐channel twice as wide as n‐channel
Now input gate cap: CG=3WLCox=3.6 fF/um, Output parasitic cap: CD=pCG, best value for p yet to be discussed.
+
VIN
Reff
CG
CD
VDD
‐
Gate capacitance ‐
important parameter
for device functionality
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+
VOUT
‐
CG=CGP+CGN
CD=CDP+CDN
Integrated Circuit Design
Drain capacitance ‐
parasitic parameter not good for device performance
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Inverter delay model
Delay model: tpd=0.7RC=R´C
R´=1.4 km n‐channel width
C=Cintrinsic +CLOAD
If p‐channel is twice the width of n‐channel: Cintrinsic ≈3*0.6=1.8 fF/m
Intrinsic delay=R´Cintrinsic =2.5 ps
Turns out to be an underestimation of intrinsic delay ~5‐10 ps
FO4 delay: R´(CD+4CG)=R´CG(p+f)=5R´CG
R´=1,4 km
CG=3*1.2=3.6 fF/m
R´CG=5 picoseconds
FO4 delay= 25 ps
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FO4 delay
25 ps
VIN
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FO4‐
delay
VOUT
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FO4 delay
25 ps
VIN
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FO4‐
delay
VOUT
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Performance scaling Assuming VDD‐VT scales like VDD between technologies we get the following scaling laws:
R´~L/(WCoxVDD)
CG~WLCox
and hence, R´CG=L2/VDD
For 0.35 um CMOS we had R´CG=25 ps @ 3.3 V
What should we get now at 65 nm and VDD=1.2 V?
R’CG=L2/VDD=25*(65/350)2/(1.2/3.3)=2.4 ps
Hm, not fully scalable . . .probably due to velocity saturation September 18, 2012
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Classical performance scaling September 18, 2012
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Performance scaling Assuming velocity saturation
we get the following scaling law:
R´CG~L
For 0.35 um CMOS we had R´CG=25 ps @ 3.3 V
What should we get now at 65 nm and VDD=1.2 V?
R’CG~L →25*(65/350)=4.64 ps≈5 ps
Quite close . . . September 18, 2012
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Classical performance scaling September 18, 2012
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Validation vs. cell library data
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Validation vs. cell library data
My resistance of 1.4 km (red)
ST kLOAD value in cell lbrary (blue)
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How about sizing the inverter?
sizing
delay
VIN
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VOUT
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Small or large?
VDD
W=4 um VDD
R, CG
W=1 um in
R/4, 4CG
in
out
R, CG
W=1 um
out
R/4, 4CG
VSS
W=4 um VSS
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Inverter scaling
390 nm
780 nm
X9
X4
560 nm
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280 nm
X2
280 nm
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200 nm
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Inverter scaling
WP=µWN
WP=WN
WP=WN
X9
WN
WN
WN
General case:
WP = WN
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Electrical symmetry:
RP = RN when WP = µWN
Integrated Circuit Design
Geometric symmetry:
RP = µRN when WP = WN
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Inverter scaling
WP=µWN
WP=WN
WP=WN
X9
WN
WN
WN
General case:
WP = WN
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Electrical symmetry:
CP = µCN when WP = µWN
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Geometric symmetry:
CP = CN when WP = WN
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Choosing the channel width aspect ratio for minimum delay
Sizing laws:
Width dependence
R=R´/W
C=W*C´
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Inverter pair delay
tdr=RPCL
V
in
RP
RN
CL
Vout
CL
tdf=RNCL
Pair delay: tpair= RPCL+ RNCL =(RP+RN)*CL where CL=CN+CP
MP1
Vin
MN1
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CP
CN
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MP2
Vout
MN2
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Inverter pair delay
RP
Vout
V
in
CL
WP=WN
CL
RN
Pair delay: tpair =(RP+RN)*C L = (/*RN+RN)*(CN+CN)= RNCN(/+1)*(+1) MP1
Vin
MN1
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CP
CN
Integrated Circuit Design
MP2
Vout
MN2
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Inverter pair delay
Two examples
Geometric symmetry: =1 WP=WN
Electric symmetry: =µ
WP =µWN
R´P =µR´N
CL=2C´N
R´P =R´N
R´N
td= (1+)RN*2CN
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2C´N
CL=(1+µ)C´N
R´N
(1+µ)C´N
td= 2RN*(1+)CN
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Inverter pair delay
General delay formula
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 
td   RN  RP  CN  CP   RN CN 1   1   
 
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Inverter pair delay
General delay formula
 
td   RN  RP  CN  CP   RN CN 1   1   
 
We want to find the  value yielding the minimum propagation delay. Taking the derivative w r t  we find
td

 1 2  0


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Inverter pair delay
General delay formula
 
td   RN  RP  CN  CP   RN CN 1   1   
 
We want to find the  value yielding the minimum propagation delay. Taking the derivative w r t  we find
td

 1 2  0


Minimum delay when

Normalized
inverter pair delay
6
µ=2
3%
5,8
 µ
1
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
µ
µ
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Inverter pair delay
General delay formula
Cwire 
  
td   RN  RP  CN  CP  Cwire   RN CN 1   1   

CN 
  
We want to find the  value yielding the minimum propagation delay. Taking the derivative w r t  we find
td
  Cw 
 1  2 1 
0

  CN 
Minimum delay when

Normalized
inverter pair delay
6
µ=2
3%
5,8
 Cw 
  µ / 1 

C
N 

1
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Integrated Circuit Design
 C 
µ / 1  w 
 CN 
 C 
µ 1  w 
 CN 

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Conclusion?
The ST standard‐cell library is designed with =√2=1.4
+ Minimum pair delay
+ Minimum average delay
+ Area efficient
‐ Different rise and fall delays (more parameters)‐
‐ Different rise and fall transition times
For hand calculations of speed we need to simplify:
We choose =2 for simplicity
+ equal rise and fall delays
We will validate against simulations during labs!
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How about delay in an AND gate?
a
zout
&
b
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What’s inside the AND‐gate?
a
zout
&
b
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Transistor level
zout
a
b
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Do you see all the caps?
zout
Cgate
a
Cpar
b
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Do you see all the switch resistors?
zout
a
b
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Why important?
Cpar
&
Cinput
Cpar
Two‐port model: inverter input cap, inverterdriving capability, inverter parasitic drain cap
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Cinput
Cinput
Two‐port model: NAND input cap, NAND driving capability, NAND parasitic drain cap
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Unit width MOSFET resistances
W=1
2R
W=1
2R
zout
W=1
R
W=1
2R
W=1
R
a
W=1
R
b
All critical paths in the NAND gate have the same resistance 2R, twice the resistance of the inverter.
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Sizing MOSFETs for equal path resistances
W=2
2R/2=R
W=2
R
zout
W=1
R
W=2
2R/2=R
W=2
R/2
a
W=2
R/2
b
If we want the same resistance in the NAND‐gate as in the inverter NAND MOSFETs must have double width.
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NAND‐gate input capacitances scale
W=2
2C
W=2
2C
2C
zout
C
W=2
2C
W=2
2C
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Integrated Circuit Design
a
b
45
NAND‐gate input capacitances scale
CGinv=3C
CGNAND=4C
W=2
2C
W=2
2C
2C
zout
C
W=2
2C
W=2
2C
a
b
CGNAND/CGinv=4/3! September 18, 2012
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NAND‐gate input capacitances
CGinv=3C
CGNAND=4C
W=2
2C
W=2
2C
2C
zout
C
W=2
2C
W=2
2C
a
b
For equal NAND & inverter resistive paths, the NAND‐gate input cap is 4/3 times that of the inverter
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Compare RC products
RINV
RNAND
CGINV
RINV
a
RNAND
CGNAND
b
CGNAND
RNANDCGNAND=4RC; RinvCGinv=3RC! The NAND RC product is larger!
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Define logical effort
RINV
RNAND
CGINV
RINV
a
RNAND
CGNAND
b
CGNAND
Logical effort: g=RNANDCGNAND/RinvCGinv=4/3!
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Define logical effort
RINV
RNAND
CGINV
RINV
a
RNAND
CGNAND
b
CGNAND
For equal NAND & inverter resistive paths, RNAND=Rinv
the NAND‐gate input cap is 4/3 times that of the inverter
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Parasitic output caps
W=2
2C
3C
W=2
2C
Only output parasitic caps
are considered
Internal node caps neglected
W=2
2C
a
b
CNANDpar=3*2C=6C; p=CNANDpar/CGinv=2. The parasitic effort!
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NAND gate capacitor model
a
&
3C
3C
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4C
b
6C
Integrated Circuit Design
4C
52
AND gate delay model
3C
&
3Ct
6C
4C
4Ct
Relative delay: d=pNAND+1(inv)+pinv+gNAND=2+1+1+4/3=5.3
Absolute delay: tpd=RC*d=5*5.3= 26.5 ps
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Exercise 1: The NOR2 gate
≥1
Determine MOSFET widths, logical effort and parasitic effort!
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Exercise 2: The AO12 gate
≥1
&
Determine MOSFET widths, logical effort and parasitic effort!
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In summary
In this lecture, we have
• shown how to determine MOSFET effective resistance • developed an equivalent inverter RC circuit for propagaton delay calculations
• looked at scaling of the inverter RC constant between technology nodes
• looked at sizing of the pMOS device vs. NMOS for minimum propagation delay
• calculated the delay of home assignment zero‐detect array
• normalized logic gate propagation delay vs. inverter RC product
• introduced and defined the concept of logical effort
• used de Morgan´s theorem to eliminate inverters
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