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Estimation of Propagation Delay considering
Short-Circuit Current for Static CMOS Gates
Akio Hirata, Hidetoshi Onodera and Keikichi Tamaru
Abstract | We present formula of propagation delay for
static CMOS logic gates considering short-circuit current
and current owing through gate capacitance and using the
n-th power law MOSFET model which considers velocity
saturation eects. The short circuit current is represented
by a piece-wise linear function, which enables detailed analysis of the transient behavior of a CMOS inverter. We found
that the error of our formulas for a CMOS inverter is less
than 8% from circuit simulation in most cases of our experiments. We also applied these formulas to logic gates made
up of series-parallel connected MOSFETs by replacing the
series-connected MOSFETs with an equivalent MOSFET.
The inuence of short-circuit power on delay, which is explicitly modeled in our formula, is numerically demonstrated
such that the inuence becomes large with slow input transition and small output load capacitance.
Keywords | short-circuit current, propagation delay.
I. Introduction
Power dissipation and circuit speed are the most important performance parameters in VLSI design. Among various fabrication technologies and logic design styles, static
CMOS logic structure is widely used for ASIC design due
to its negligible DC power dissipation as well as its robust function. Accurate estimation of power dissipation
and speed of a static CMOS gate is therefore essential for
the design and analysis of high performance VLSI circuits.
However, calculation of critical path delay or power dissipation in large VLSI systems using a circuit simulator
such as SPICE is prohibitively time consuming. Analytical models of power dissipation and propagation delay for
static CMOS gates are very useful in the design of large
VLSI systems. For accurate estimation of the propagation
delay and power dissipation, consideration on current-ows
in a gate during input signal transition is very important.
The current-ows include a current through the capacitive load, a current through a turning-on MOSFET(ID ), a
current through gate capacitances (IG ), as well as a shortcircuit current (IS ) which ows through a turning-o MOSFET(See Fig. 1). The short-circuit current IS is aected by
many factors such as the transition time of the input signal,
the amount of the capacitive load, the sizes of MOSFETs
that make up the logic gate, etc.[1], which makes the analysis of CMOS logic gates non-trivial. Several methods have
been proposed for the analysis using dierent approximations. In reference [2], [3], simple closed-formed formula
of a propagation delay of a CMOS inverter circuit was derived. However the eect of short-circuit current was neglected. Jeppson[4] and Embabi[5] derived delay formula
Authors are with the Department of Communications and Computer Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-8501,
Japan
considering short circuit-currents and gate-to-drain overlap
capacitance. Reference [4], however, relies on a square-law
long-channel model, hence its applicability to logic gates
with recent short-channel MOSFETs is limited. In [5] a
current through gate capacitances is not considered, which
introduces non-negligible eects in delay modeling.
In [6], we derived a short-circuit power dissipation formula by representing short-circuit current by a piece-wise
linear function(Fig. 2). The error of the formula for a
CMOS inverter is within 15% in many cases of our experiments. In this paper we present a formula for propagation delay considering a short-circuit current using the n-th
power law MOSFET model proposed by Sakurai and Newton[3]. We show that the formula gives reasonable estimation compared with SPICE simulated delays. We discuss
the accuracy of the delay formula for complex gates(e.g.
NAND3) and the inuence of short-circuit current on propagation delay.
II. Delay estimation
We estimate propagation delay taking the eects of
short-circuit current and a current owing through gate-todrain capacitance into account for a CMOS inverter circuit
shown in Fig. 1. Now we consider the case of rising input,
which has a ramp shaped waveform of transition time tT
from ground to supply voltage VDD . The equivalent gateto-drain capacitance CGD is connected from the input node
to the output node. A capacitive load CL is connected to
the output node.
We dene the parameter tIN V which represents the time
when the output voltage becomes logical threshold voltage
VINV . The time tINV appears either one of the following
three regions(Fig. 3).
(A) While the input rising.
(B) While the turning-on transistor operating in the saturation region.
(C) While the turning-on transistor operating in the linear region.
The dierential equation which governs the behavior of
the inverter in region (A) is expressed as follows[6]
CL
0
dVO
dt
V
En
Bn (1 + n VO )( DD t 0 VT Hn )nn
0W
L
t
=
En
C
+VDD GD + IS ;
tT
T
(1)
where n; ; B; VT H are parameters of the n-th power law
model[3] and CL CL + CGD . WE and LE are eective
channel width and eective channel length, respectively.
Subscripts n and p denote nMOS and pMOS, respectively.
0
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The output voltage VO in region (A) is obtained by inte- current IS is expressed by the piece-wise linear function in
grating both sides of Eq. (1), and expressed as follows;
Fig. (2), the integration of the third term is straightforward.
The resulting equation, which is a non-linear funcZt V
WEn Bn
DD
tion
of
tINV(A) , can be solved numerically within a few
nn
VO = VDD 0
(
t 0 VT Hn ) dt
(1 + n VDD )
LEn CL
Newton-Rephson iterations. Please note that a numerical
n tT tT
Z
analysis is only necessary for region (A), whereas closed
V
WEn Bn t
n (VDD 0 VO )( DD t 0 VT Hn )nn dt
+
form
formulas are obtained in regions (B) and (C).
LEn CL n tT
tT
If
t
INV exists in region (B) (VDOn < VINV < VT T ), the
ZtI
CGD t
S
time
t
INV(B ) is expressed as
+
dt;
(2)
+VDD
CL tT
0 CL
V
+ 1=n
CL
log INV
;
(8)
tIN V(B) = tT 0
where n = VT Hn =VDD . The third term in right-hand side
n IDOn
VT T + 1=n
of Eq. (2) contains VO . However, if the parameter n is
very small, the term can be safely neglected and the output If tINV exists in region (C) (VDOn > VINV ), the time
tIN V(C ) is expressed as
voltage in region (A) is given by
0
0
0
0
0
(1 + n VDD ) t
t I
VO = VDD 0 T DOn
CL nn + 1 (1 0 n )nn
tT
Z
t
C
t
IS
+VDD GD +
dt:
CL tT
C
0 L
0
0
0
0 n
nn +1
0
(3)
C V
V
1
tINV(C ) = tDO + L DOn
log DOn
IDOn
2
VIN V
2VDOn 0 VINV
1
log
+
2(1 + 2n VDOn )
VDOn
(9)
where tDO tINV(B) (VDOn ), VDOn = Kn (VDD 0 VT Hn )mn .
K and m are parameters of the n-th power law model.
The propagation delay is expressed as
0 VT Hn If the parameter
where IDOn =
n is large and in addition VO becomes far below VDD at
the end of region (A), the third term in the right-hand side
V
of Eq. (2) cannot be neglected. In this case we approximate
(10)
tpHL = tINV 0 tT INV
VDD
the function (VDD 0 VO ) in the third term by the second
and the third terms in the right-hand side of Eq. (2) which The delay of falling input can be obtained by exchanging
are dominant terms in (VDD 0 VO ). The output voltage is nMOS parameters with pMOS ones.
represented by;
WEn
LEn Bn (VDD
)nn .
III. Discussion and conclusion
1
VO =
f01 + (1 + n VDD ) exp(0n F )g
We examine the accuracy of the propagation delay evaln
uated
by Eq. (10). Figures 4 and 5 show the delay valZ
t
CGD t
IS
ues
(Fig.
4:output falling delay, Fig. 5:output rising delay)
+VDD
+
dt;
(4)
CL tT
0 CL
calculated by Eq. (10), those calculated by the formulas
t
nn+1
proposed by Sakurai and Newton[3] and those simulated
1
t I
0
(5) by SPICE. The process technology assumed is 0.8m. The
F = T DOn
n
n
n
CL nn + 1 (1 0 n )
tT
supply voltage is 5[V]. The model parameters of the n-th
Detailed explanation of the derivation is shown in Ap- power law model are listed in Table I. We can see that
pendix A.
the error of our formula is smaller than that of Sakurai
We dene the parameter VT T which represents the out- and Newton's formula, especially when the velocity satuput voltage when the input voltage reaches VDD . The pa- ration parameter of driving MOSFET is large(Fig. 5).
rameter VT T is expressed from Eq.(4) as follows.
The error of Eq. (10) is within 8% in our experiments.
We also applied this formula to logic gates made up of
1
series-parallel connected MOSFETs by replacing the seriesVT T =
f0
1 + (1 + n VDD ) exp(0n FT T )g
n
connected MOSFETs with an equivalent MOSFET [7]. TaC
P
+VDD GD + Sf all
(6) ble II shows the propagation delay of NAND2, NAND3,
CL
CL VDD
and NOR2 gates in various input patterns, output load capacitances, and input transition times. In general, errors
1
tT IDOn
nn +1
(1 0 n )
(7) are larger than those of an inverter. Also, errors tend to
FT T =
CL nn + 1 (1 0 n )nn
become larger when the input transition is applied to a
The second term of the right side in Eq. (6) repre- MOSFET which is farther from the output. One of possents the eect of the current owing through CGD and sible reasons is that the actual IDS 0 VGS characteristics
the third term represents the eects of the short-circuit of the series connected MOSFETs are not well modeled
current(PSfall is dissipated energy caused by the short- by their equivalent MOSFET. Another possibility is the
circuit current. See Appendix B).
existence of internal capacitances in the series connected
If tINV exists in region (A) (VT T < VIN V ), the time MOSFETs, which is not modeled in the equivalent MOStINV(A) is obtained by solving the Eq. (3) or Eq. (4) in FETs. Improvement of the modeling is one of our future
terms of t replacing the VO by VINV . Since the short-circuit work.
0
0
0
0
0
0
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Now, we show the inuence of the short-circuit current
IS in the evaluation of propagation delay(50% to 50% delay). These eects are explicitly formulated in our delay
evaluation as shown in Eq. (6). Figure 6 shows the contribution of IS in the total delay time. As the input transition
time becomes larger and the output capacitance becomes
smaller, the contribution of the short-circuit current increases. When the output capacitance is 0.05 [pF] and the
input transition time is 2.0 [ns], 87 % of the total delay
is contributed by the short-circuit current. Therefore in
CMOS structure, reducing the short-circuit current is important to design high speed VLSIs.
References
[1] H. J. M. Veendrick, \Short-circuit dissipation of static CMOS
circuit and its impact on the design of buer circuits," IEEE
Jour. of Solid-State Circuits, vol. SC-19, no.4, pp. 468{473, Aug.
1984.
[2] N. Hedenstierna and K.O. Jeppson, \CMOS Circuit Speed and
Buer Optimization," IEEE Trans. on Computer-Aided Design,
Vol. CAD-6, No. 2, pp. 270-281, Mar. 1987.
[3] T. Sakurai, and A. R. Newton, \A simple MOSFET model for
circuit analysis," IEEE Trans. Electron Devices, vol. 38, no.4, pp.
887{893, Apr. 1991.
[4] K. O. Jeppson, \Modeling the Inuence of the Transistor Gain
Ratio and the Input-to-Output Coupling Capacitance on the
CMOS Inverter Delay," IEEE Jour. of Solid-State Circuits, vol.
29, no.6, pp. 646{654, Jun. 1994.
[5] S.H.K. Embabi, \Delay Models for CMOS, BiCMOS, and BiNMOS Circuits and Their Applications for Timing Simulations,"
IEEE Trans. Computer-Aided Design , pp. 1132{1142, Sep. 1994.
[6] A. Hirata, H. Onodera, K. Tamaru, \Estimation of Short-Circuit
Power Dissipation for Static CMOS Gates," IEICE Trans. on
Fundamentals of Electronics, Communications and Computer Sciences, Vol. E79-A, No. 3, pp. 304{311, Mar. 1996.
[7] T. Sakurai, \Delay analysis of series-connected MOSFET circuits," IEEE Jour. Solid-State Circuits, vol. SC-26, no.2, pp. 122{
131, Feb. 1991.
Appendix
VO considering We cannot solve Eq. (2) in a strictly analytical way due
to the existence of VO in the third term of right hand side.
We thus approximate VO in the third term by the parameter VO represented as follows;
I. The derivation of
0
Z
t
V
W B
( DD t 0 VT Hn )nn dt
VO = VDD 0 En n (1 + n VDD )
LEn CL
n tT tT
Z
t
W B
V
+ En n
n (VDD 0 VO )( DD t 0 VT Hn )nn dt: (11)
LEn CL n tT
tT
0
0
0
0
Dierentiating the above equation by t and solving the differential equation, we can derive VO ;
1
f01 + (1 + n VDD ) exp(0n F )g : (12)
VO =
n
Substituting the VO in the third term of the right-hand side
of Eq.(2) by Eq. (12), we can obtain Eq. (4).
0
0
II. The formulae of short-circuit power
dissipation
The short-circuit power dissipation with falling output
is given as
PSfall
=
tT
fI
(V 0 VT Hn 0 VT Hp ) + ISmin VINV g
2 Smax DD
3
102AB 0pD
2A
: if D > 0
c
: otherwise
D = 1 0 4A(B + c)
ct2
A = 0 2 T 02 (I 0 n )2
4b CL
2CL0
I ISmin tT
CGD
0b
VDD 0 VD 0 0 VINV 0
B = 0
tR
CL
2CL0
tR = tT (I 0 n )
tT n
CGD
ISmin = 0a 0 VT Hn = 1 + a 0
CL
2CL
1
f01 + (1 + n VDD )
VD =
n
(I 0 n )nn +1
2 exp 0 nCt0T(nIDOn
nn
L n + 1)(1 0 n )
1 + n VDD
nn +1
' VDD 0 CtT0 nIDOn
nn (I 0 n )
L n + 1 (1 0 n )
:if n VDD 1
Wp
(1 + p b)(VDD 0 VINV 0 VT Hp )np
c = Bp
Lp
b = Kp (VDD 0 VINV 0 VT Hp )mp
2Bp Wp
a =
(V 0 VT Hn 0 VT Hp )np 0mp
Kp Lp DD
VINV
I =
VDD
I 1=n n + I 1=n (1 0 n )
VINV = VDD 1=nDOn 1=n DOp
IDOn + IDOp (1 0 n )=(1 0 p )
V
n + np
V
n n
; p T Hp ; n T Hn
2
VDD
VDD
ISmax
=
The short-circuit power dissipation with falling input can
be obtained by exchanging NMOS parameters with PMOS
ones.
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4
V DD
Output Voltage
VDD
IS
IG
VTT
VO
CGD
V IN
VIN
t pHL
VINV
CL
ID
GND
VOUT
VDOn
VTHn
Fig. 1. inverter circuit
0 VTHn t
T
tT
tINV tDO
Time
VDD
Region
(A)
V
(B)
(C)
Fig. 3. Output waveform
VDD
VDD
- VTHp
Input waveform
VINV
Cell delay[ns]
0.8
VTHn
Time
0
tT
0.7
tT =2.0ns
tT =1.0ns
SPICE
Eq.(10)
Sakurai’s
tT =0.5ns
0.6
I
0.5
ISmax
PS
0.4
0.3
Short-Circuit
Current Wave form
tTHn
0
ISmin
VINV t
VDD T
tTHp
tT
0.2
0.1
20
Time
Fig. 2. PWL function of short-circuit current in the case of input
rising
40
60
80
100 120 140 160 180 200
Output load capacitance[fF]
Fig. 4. Output falling delay of a CMOS inverter, gate length = 0.8
m
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5
TABLE I
MOSFET model parameters used in calculations
Gate length
Gate width
m
n
0.8m
0.8m
5m
10m
0.318
0.251
1.03
1.15
nMOS
pMOS
VT H
[V]
0.962
1.19
[V01 ]
1.38e-2
5.47e-2
K
B
1.45
2.15
4.50e-5
1.93e-5
TABLE II
Propagation delay of CMOS gates with rising input, gate length=0.8
Logic
gate
NAND2
NOR2
NAND3
Wp
[m]
10
Wn
[m]
5
10
10
5
10
an active
input
close
to
output
tT
[ns]
1.0
further
from
output
1.0
close
to
output
1.0
further
from
output
1.0
close
to
output
1.0
2.0
2.0
2.0
2.0
2.0
CL
[fF]
20
100
20
100
20
100
20
100
20
100
20
100
20
100
20
100
20
100
20
100
Eq. (10)
[ns]
0.106
0.259
0.071
0.255
0.089
0.227
0.002
0.175
0.261
0.449
0.325
0.534
0.358
0.521
0.457
0.643
0.190
0.359
0.194
0.396
SPICE
[ns]
0.106
0.261
0.059
0.262
0.097
0.231
0.025
0.203
0.269
0.450
0.347
0.564
0.382
0.542
0.501
0.689
0.187
0.349
0.186
0.395
m
Error
[%]
0
-0.7
20.3
-2.7
-8.2
-1.7
-92.0
-13.8
-3.0
-0.2
-6.3
-5.3
-6.3
-3.9
-8.8
-6.7
1.6
2.9
5.4
0.3
Propagation Delay[ns]
0.7
Cell delay[ns]
0.9
0.8
0.6
tT =2.0ns
tT =1.0ns
SPICE
1.0ns
Eq.(10)
Sakurai’s
0.5
Influence of
Short-Circuit
Current
0.5ns
tT =0.5ns
0.7
0.6
2.0ns
0.4
0.5
1.0ns
0.5ns
0.3
0.4
0.3
0.2
0.2
0.1
20
2.0ns
Parameters:
Input transition time
40
60
80
100 120 140 160 180 200
Output load capacitance[fF]
Fig. 5. Output rising delay of a CMOS inverter, gate length = 0.8
m
2.0ns
1.0ns
0.5ns
0.1
0.05[pF]
0.1[pF]
0.2[pF]
Output Capacitance
Fig. 6. Inuence of Short-Circuit current on propagation delay of a
CMOS inverter, gate length = 0.8 m