Certified Timing Verification and the Thmsition Delay of a Logic Circuit
Srinivas Devadas
Department of EECS
MIT,Cambridge
Shard Malik
Department of EE
Kurt Keutzer
Spq~p,
Ipc.
ountmll Vlew
Princeton University
Abstract
Moet research in timing verificstion haa implicitly a"ed
a single vecty floating mode computation d delay which
is an appmnmcrtion of the multi-vector truuition delay.
In this paper we examine the tramition del4 of a circuit
and demonstrate that the t d t i o n delay ofa circuit can
differ from the float' M a y of a circuit. We then ranride
a procedure for k v y c a l c u W i the t r d t i s n &lay of
a circuit. The most practical benefit of thio procedure is
the fact that it not only reeultr in a delay calculation but
outputs a vector aequence that m a y be timing dmulated to
certifr static t h i n g verification.
1 Introduction
Albert Wang
SmoPys, @c.
Mountam View
prim
input and u,,+l is a primary output. Each ei is a
net. %th each verkx U (edge e) we ammciate a delay d(u)
(d(Q1.
e lsn#h of a path P = {eo, UO, el, ...,e,,,u,,,e,,+l} is
d d i d U D(P) =
qui)
d(ei).
aenmtirstian eaaditions, e delay o a clrcwt ae even strictly
by the +gth ofthe longest path is called the topological
or Wcrphrul MayAn even4 k a transition 0 + 1 or 1 + 0 at a gate.
Consider a aquence of events, {ro, rl, ..., r,,) occurring
at g a b {a,91, ..., g,,} along a path, such that ri occurs
ae a raruU of event ri-1. The event ro t emid to propagate
dong the path.
A camd u e at a gate input is the value that
&e d u e at the output of the gate independent
detmnmu
'
of the dhm inputs. For exam le 0 ir a controlling value for
an m
A non-eont&
value at a ate input is
the d u e which ir not a c o n t r o 2 value for t i e gate. For
example, 1 t a non-controlling ue tor an UD gate. We
if one of its inputs
say a gate g has a contmbd &e
has a controlling value; otherwise, we say g has a non-
+p't
WO-
The longeat- ath delay of a circuit is simply the sum of the
graphical
cumulative &lays of a circuit along the 1tpath. This memure of delay ia still u d in mart static timing verifiers but hae the deficiency &at it does not take
into account fabe path. To remedy thir daficiency the
floating delay of a circuit may be a n a l y d . The tlostipg
delay of a circuit is the delay under a singlevector static
analyaie condition that considers the Boalun behavior of contrdlsd value.
the circuit but malr#l conservative amumptians about the
Let T =&eo,
...,U, e,,, u,,+l) be a path. The inputs
state of the circuit bcfomp: the single vector ir applied.. A Of V i other
y-1 Ue reiemd to (UI the 8ide-inpUtEto
number of techniques have been propored for compuhng r. If thera wrirtr an input vector U such that all the side
circuit, but atstep was inpub docy r rettle to non-controlling valua, on U then I
a kchni ue that provided correctneus is statically aemithble.
6pet%.p. was demonstrated. h- The critical path ia the longed d t i z a b l e path in the
were made m [2, 51 where techniques circuit und- the stated delay model. If a path is not senthat more precisely identified the critical ath were pre- sitieable under the stated delay model then it is a Ealre
sented. The transition delay of a circuit is &e delay under path.
a multi-vector dynamic-ma).ais condition that makes no
assumptions about the state of the circuit before the vec- 3 Circuit History: H o w Much ia Enough?
tor sequence is applied. A circuit is presented in thir p b We am intmsted in determining the dday of a circuit for a
per whoee true floating delay is greater than its tramition given delay d,
but the real motivation is to determine
delay; thus, the floating anal+ condition itrelf has some what k the frequency at which a circuit can be clocked.
deficiencies.
There u e a number of pwible daAnitione of transition
A full consideration of tranaition delay
uirea wcaxni- delay and d definition has impliitions on the iseue of
nation of fundamental m m tions about 8
a
y modeling clockii ikqwmcy. A full comideration of these probleme
(e.g. bounded or fixed) and the r e l a t i o d p between the is beymd the mope ofthis paper, but in thie section we incomputed dela of a circuit and the mini"clock period. troduce our notion of tramition delay and show under what
Due to space &nitatioms, in thie paper we limit o d v e s conditiona it results in a valid clock clodring frequency.
to a discmion of the differences between aOrt€ngand tranCl" the operation of a synchronow digital circuit
sition delay in Section 4.2, a technique for com uting the being clocked at period 7. At every clock period, the outtransition delay in Section 5, and rcsulb on time tech- p u b are ktehed and a new eet of inputa presented to the
niques in Seetion 6. A more comprehensive cowideration circuit. Let w examine the operation of a circuit over the
of transition delay is given in [a].
period of application of a sequence of input vectors. Let
uo be the veetor applied at the preeent clock cycle, U-1 be
2 Definition8 and Notation
the vector a p p l d at the previous clock cycle and 80 on. In
In this section we introduce terminology that will allow us the floathgmode of operation, the nodes are not assumed
to discuss timing iseues as well far temporal behavior.
to be ided cupuitors and hence their a t e is unknown till
A path in a combinational circuit is an alternat'
it is set by the current vector. Thw, the timin behavior
quence of verticee and edges, {uo, eo, ..., u,,, en, o,,+~},w m for va t i n v d e n t of all previoua vectors. In tfe transiedge ei, 0 5 i 5 n, oonnecb the output of Mtex vi to an tion mode operation, the circuit nodes are aesumed to be
input of vertex ui+l. For 1 5 i 5 n, V i is a gate; uo is a ideal capacitors and retain their d u e set by the previous
m.
T-
0738-100XD253.00 @ 1992IBBB
549
P8per343
vectors till the current vector forces the voltage to change.
Thus the timing response for uo is also a function of U-1 and
possibly other previously applied vectors. In analyzing the
timing response of the circuit, we would like to deal with
as little history as possible while making no compromises
on the accuracy. In thie direction we first propose the following model of measuring the delay in the transition mode
and subsequently justify it.
Let us assume that when vector uo is applied, all circuit
nodes have stabilized to their values under U-1. In this
case the effect is the same as if U-1 is iven an arbitrary
amount of time to settle. This mode ofoperation will be
referred to as the single stepping transition mode and for the
remainder of this paper and whenever we refer to transition
delay it will be relative to this mode of operation. The input
transition from U-1 to uo will result in some transitions at
the circuit nodes. Let 6 be the time taken for the last
transition at any of the output nodes for all possible vector
chan es U-1 to UO. Thus, for all r > 6 no transition will
ever %eobserved at any of the outputs in the single stepping
mode.
Let us now use this value of r to clock the synchronous
circuit. At time 0, when uo is applied it is possible that the
circuit nodes may not have stabilized to their values under
U-1. (Note that the fact that the outputs have stabilized
does not imply that all the circuit nodes have stabilized.)
A simple sufficiency condition for a transition delay r to be
a valid clock period is for the state of the circuit to be the
same whether 1) 00 is applied only an interval of r after U-1
or 2) uo is applied at an arbitary interval after U-1. This is
expressed in the following theorem.
Theorem 3.1 Let C be
a combinational sub-circuit of a
synchronous digital circuit. Let r be the transition delay of
the circuit den’ued using the single stepping mode of operation. Let w be the length of the longest graphical path an C .
If r > w / 2 then r is a valid clocking period for C .
Proof:Let U-1 be the vector applied at time -r and let uo
be the vector applied at time 0. Let e-1 be an event in the
circuit that occurs after time 0 and is caused by 11-1, i.e.
an event that is caused by the U-1 but is still propagating
at time 0 after uo is applied. Event e-1 has traversed a
distance corresponding to delay r from the primary inputs
and has at most a distance correspondin to w--7 to traverse
to reach the primary outputs. Let eo (%ean event caused
by uo that propagates along a path r of delay at least r .
Singlestepping transition analysis has analyzed the delay
assumin that all events at side inputs of a 4ate g along T
have setfied when eo arrives at g. This analysis will be valid
if each e-1 has settled to its final value under U-1 when eo
reaches that gate. This is equivalent to the condition that
e-1 not present itself at the input of a gate g along U after
eo. This will be true as long as w - r < r or equivalently
T
>w/2.
When this condition is true, then for events propagating
along all paths of length at least 7 , each gate will have settled to its value under U-1 by the time the event gets to that
gate, which is the same as it would be in the single s t e p
ping mode. The restriction r > w/2 is not very stringent.
Based on practical experience this property holds for most
circuits. This is significant since it enables us to consider
only the two vectors involved in the change at the inputs in
the analysis of the timing response of this transition.
4 Component Delay Models
All simulation techniques as well as timing analyzers make
some assumptions about the possible variations in the delay
Paper 34.3
of various circuit components. To avoid further confusion
with other uses of the term “delay model” we call these
component delay models. We now examine some of the
models used and then specify the domain of this paper in
terms of these.
The most common component delay model for a circuit
component is one in which the delay is assumed to be a fixed
number d. This is referred to as the fixed delay model.
In this model a delay of 2 units on a ate indicates that
the gate switches instantaneously to a kogical 0 or 1 value
but that the communication of this event to the output of
the gate is delayed by 2 units. In reality this number is
typically an upper bound on the expected delay, so in fact
the actual delay ma be any number bounded above by d .
This potential speedrup is incorporated in the monotone
speedup model [lo which assumes that the delay for each
component lies in t e range [O,dJ.
The bounded delay model is more realistic about how
much each gate can in fact be sped up. It specifies the delay
aa a range,Jd’, d”], given by the lower and upper bounds on
the actual elays. There is some ambiguity in the literature
as to what the bounded delay model means. It has been
interpreted as either the switching delay or as the propagation delay. With the former interpretation, a gate delay
of [2,4] would imply that the gate would take somewhere
between 2 and 4 units to make the transition between the
two logical values. Ternary al ebras 111 have been used to
accommodatethe unknown v ue o f t e gate output (which
is neither a 0 or a 1) in the interval of uncertainty. If the
bounded dela relates to the propagation delay then this
implies that t i e gate switches instantly, but it is uncertain
as to the time in the [2,4] interval at which it will switch.
Note that unlike the previous case, the gate output is always a 0 or a l and ternary algebras are not needed. In this
paper, we use the propagation delay interpretation since we
feel it is more realistic with respect to current technologies.
To simplify the presentation of this paper we consider
only the fixed delay model and we restrict the delays in circuits to ates. This is still general enough to accommodate
other defay quantities such as wire delays and pin-to-pin d e
lays by introducing buffers with appropriate delays in the
circuit. While more sophisticated delay parameters such
as slope delays and separate rise and fall delays are not
directly accommodated into the “delay lumped at a gate”
paradigm, it can be shown with little effort that the results
in thia paper hold for even those models. Bounded delays
are treated extensively in [SI.
E
3
4.1
6
Instantaneous Glitches
Suppose that in a circuit simulation a rising event and a
falling event arrive at at precisely the same time at an AHD
gate with delay “2”. In static timing verification, which
aims at a robust though possibly pessimistic model of delay, it is commonly assumed that an “instantaneousglitch”
event immediately occurs which is then communicated at
the output of the AID gate after a delay of 2. In this paper our general assumption will be that such instantaneous
glitches will not be able to overcome the inertial delay of a
gate. This is more realistic given existing technologies.
4.2
Differences in the Floating Delay and the
Transition Delay
It is easy to show that the floating and transition delay
modes can give different results. In Figure 1 we show a twolevel circuit, resultin4 from a prime and irredundant cover,
for which the transition delay (under fixed gate delays) is
different from the floating delay. The number inside a gate
550
T
Figure 2: Floating and transition delays differ - even with
monotone speedup
a
b
C
d
C
d
Figure 1: Floating and "sition
Delays Differ
corresponds to the delay of the gate.
Figure 1 shown one of the waya that the transition delay
of a eircuit, M
g no monotOnic d u p e and no inetantaneoue feescan
, differ froIp th+ ttoafinb-ddqy of?
circuit. The ding delay of thre scut for a
trmtion at the output is 4. In this exampk, on each transition
on 01 for 0 + 1 at least one of the 0th.r gatee maeS a
0 + 1 transition sooner. For example, let UIJ look at the
~ ~ t & ~ ~ ~
< &; ~h a~ l t$ & ~ a ~
a 1 during the time int,&l\3,4] and a a A t h e by the
time the gate 01 malres a 0 1 trhtim (at time 4)s 'he
output on gate is already a 1.
However, since the work of [lo] it has been coneidefed to
be neeeesary that speed-ups in the circuit Should not
in increasing the delay of the circuit. In Figure 1, if the
input buffedinverters to g a h 92 and Bs Weed UP then the
0 glitches Of 82 and gs On < l1M, OOOo > settle
to 0 before g1 makes its 0 -+ 1 transition. As a result the
transition delay of the circuit becomes q u a l to the floating
delay.
Because of examples like this it has been con.iectured that
for any combinationalCircuit there exists a monotone8 eedup such that the transition delay quale the f l d h g e@;
however! b Figye 2 we give a circuit in Which the trsnsition
delay, m t h Or mthout x-"tOne speedup, * 1- than the
floating delay.
The floating dela of the circuit in Figure 2 is 5, and the
associated floatingh%yvector is o =< 1 >. We could give
a full and^'^ oft transition delay for this .+cuit, but for
Our p u r p m here It ~ u f f i a ato Qve an intuitive
merit
why the transition delay is strictly less than the oathg
delay even with monotone speedup.
In single stepping mode, we apply an input vector when
all circuit nodes are s t a b i l i d to their Rnal values, in this
case signal d and e to logic 1. Consider the c88e where
7%
-.)
-+
+
x
f
next input vector generatea a rising transition at the input: It immediately forces signd d, which in turn forces e,
to remain at logic 1. If the next input vector generates a
falling trsnsition, it immediately caueea a rising tranrition
at oignd e which forces e to remain at 1 also. Therefore,
no t r d t i o n can be oboerved at the output in the &#e
stepping mode of operation. The above argument r e m ~
valrd under arbitr
monotone speedup of the circuit as
will be d e m o m t r a x i n the dkumion in Section 4.3.
Thus, transition delay analuair, using the single stepping
mode returns a delay of 0. However, "heorem 3.1 only
guarantas the validity of a clock period greater than w / 2 =
3. For example with a dock period of 4, leas than the
floating delay of 5, the output of the circuit stays a stable
1.
It is interesting to note that the path {a,d,e} of length 5 in
Figure 2 is statically sensithable. While it has been known
for some time that static sensitization can be too optimistic
a condition to determine the delay of a circuit this example
d a o & r h that it can
be too pesrimietic.
1 and 2 motivate a furCircuits such as those in Fi
ther enquiry into the r e l a t i o s b e t w e e n transition delay
and floating delay.
4.3
%urce8 Of Ditference Between Floating
and Transition Delay
Ing the~ floating
~ ~ delay
b ~mode
~ the delay of a path u is com-
that
At a gate 9, along
puted
On a &de
IS controlled by 00 it is implicitly awumed that if WO m
sulb in a a Static non-controlling value at a side input e
along r , then there always exiSte a vector aequence ending in that will result in that non-controlling value on e
when 811 event propagab dong r due to w. In other worda
the
quene
the nowcontrolline value to be
available when an event owum along I,even if a Speed-up
is required to deliver that non-controlling value. It will be
useful to understand pre, why this wumption is not
almF
and why a fioLtion of this assumptioncm
result in the transition delay of a circuit being leas than the
floating delay.
It will be interesting to understand precisely why the
transition delay of a circuit can differ from the floating delay. For an event traveling down a path to be affeefed by
the delay of a gate the event must propagate through the
gate. The floatmg delay mode makes comervativeaeeump
tiom &out the initial state of a circuit when a vector is
applied. Let
m u m e that a pa& I is det,en&ed
to be
responsible for the delay of the circuit in the floating delay
mode. Let uo be the vector that sensitises I to d t in
t b delay in the fl&g
d&y mode. Let g be a ate dong
T whoee output is a eontmlled value on WO andfet e be a
sideinput of r at g that has a statically non-controlling
value on 00. In floating delay analysis it is implicitly assumed that there exists a vector 0-1 that will reeult in a
55 1
Paper343
...
i
4
!................................... !
I
Figure 3: A multilevel combinational circuit
e22 e2
non-controlling value on e when an event propagates along
?r due to vo; however, it may be the case that for any vector
U- 1, e may be slow to transition to a non-controlling value
and thus the event along T is blocked at g.
Figure 2 demonstrates this point.
The vector
vo = a = < 1 > statically sensitizes the path {a,d,e}
and thus results in a delay of 5 in the floating delay
mode. Consider the activity at gate d on the input pair
U-1 = ?
=i< 0 > and VQ = a = < 1 >. Gate b settles to a 0 on uo but only after the rising event associated
with input a has reached the input of gate d . Thus the
event on the path {a, d, e} gets stopped at d . If the delay of
gate b is reduced to 0, through a monotone speed-up, then
an instantaneous glitch (see Section 4.1) occurs at the inputs to d, but such instantaneous glitches are assumed not
to change the output of a gate. We have a more complex
example for which it is not possib e to transmit even instantaneous glitches.) Thus, the floating delay assumptions are
too conservative for this circuit.
I
Symbolic Simulation Under Fixed Gate DehYS
5.1 Introduction
5
Having motivated transition delay let us now consider its
computation. In order to compute the delay of a circuit
under the transition mode, a strategy of symbolically simulating all possible input vector pairs, that can be applied to
the circuit inputs, can be adopted. The possible resulting
waveforms at each gate are encoded by a set of Boolean
functions, one for each discrete time point. Each Boolean
function is defined over the Boolean variables correspondin to the circuit inputs for the first and second vectors. We
wifl consider the details of symbolic simulation for fixed gate
delays in the following sections. For a symbolic simulation
method for bounded gate delays, the reader is referred to
[41.
In the fixed delay case, a single set of Boolean functions
at each gate in the circuit suffices to capture all the information regarding the transitions occurring at the gate. We
will begin with an illustrative example.
5.2 An Example
Consider the multilevel combinational circuit shown in Figure 3.
It has four primary inputs and one output and consists of
four CMOS gates. (The gate surrounded by the dotted line
is a complex gate having serieeparallel connections only)
The circuit has a total of four nodes: e l , ea, e3, and e4, in
addition to the four primary input nodes. Figure 4 shows
the signal transitions at the primary input nodes as well as
the possible transitions at the internal nodes of the network.
The time points are in normalized units. The first three
inputs, i l , i2, and i3, switch simultaneously between time
periods 0 and 1. The fourth input, i4, is a late arriving
e3
e4
I
I
'
I 0' 1 '
1
I
l
l
1
'
I
1
I
2' 3 ' 4 ' 5 ' 6 ' 7 ' 8' 9'10'
,
.Normalized
Time
Figure 4: Signal waveforms for the primary inputs and the
outputs of the logic gates
signal that switches between the time points 5 and 6. In
this example, the delays of both Gate 1 and Gate 3 are one
time unit. Gate 2 has a delay of two units while Gate 4
has a delay of four units. i4 arrives five time units after the
other three inputs.
Also shown in Figure 4 are the waveforms, ei's, representing the signals at the outputs of p h lo ic gates. Each of
the possible transitions, ei,j, represents eiher a low-t-high
lIth
or high-to-low signal transition between kith and
time points. The number of all possible transitions at a
gate output may equal the sum of all possible transitions
at the gate inputs. These transitions are delayed by the
gate's propagation delay. If a gate is driven by the primary
input signals, then the transitions at the gate output will
be determined by the transitions of the primary input signals. Due to the combinational nature of the network, the
number of all possible transitions at the output node of a
given gate for all time points is
+
ieinputr of gate
for all b] distinct time points. Referrin to the example,
e l has only one possible transition, e l 1,setween the time
points 1 and 2 because the total number of transitions at
the input of Gate 1 at different time points is one. The
earliest signal event will arrive at the gate output one time
unit after i l switches because the delay of Gate 1 is one time
unit. Similarly, e4 has a total of four possible transitions
between the time points 5 and 10 because the number of
transitions at the inputs of Gate 4 at distinct time points
is four. The earliest transition, originated from node e3,
arrives at the gate output between the time points 5 and 6,
since Gate 4 has a delay of four time units.
5.3
Unit-Delay Model
In this section, we describe how symbolic simulation can
be used to compute signal transitions in a circuit under the
unit-delay model. The unit-delay restriction will be relaxed
in Section 5.5.
552
Paper 34.3
T
r&g
Figure 5: An Inverter-And Circuit
Under the unit-delay model, the circuit activity c a d
by applan input vector pair can be aeen as occurring at
discrete ints in time implied by the unit-delay model, and
all sipgare stable between the time points. The central
idea ILL our formulation is to dacribe the stable values of a
signal in a articular time intend rymbdicslly as a Boolean
function ofinput variables over two input vectors (i.e., each
implicant of fi corresponds to an input vector pair which
generates a 1 at signal f in time interval i). Determining
whether a particular ’ al ch
from interval i to i
1 now reduces to c h z g fo=@cal
equivalence of the
functions in the two inkrvals. As a by-product, the input
assignment that cauaea the two functions to differ gives us
the in ut vector pair that
crates a transition at time
point Eetween ini an$?+ 1.
As a notational convention, we w e subscripts to denote
a variable is arrociated with. A special
the time
subscript
is used to denote input variables associated
with the first vector l . The time at which the second vector
is applied is a common reference point 0. So, for an input
variable a, all aj with i < 0 map to a, and all ai with i >= 0
map to 0 0 . Furthermore, for every function f(g, h,
we
for a choeen i.
construct a new function fi(gi-1, hj-1,
For example, consider the network in Figure 5. For this
network in the first time interval,
+
-
-
go
e)
e)
=a-
fo = 8-16-1 = 6,26-1= C O In the next time interval,
91 = G
fi
= 9060 = K O 0 = O , 6 0
It should be pointed out that our formulation is more
powcrhl than a procedure that jwt determines transitions
of a
at a puticular time point. For exam le, finding
an input vector prir that
eratea transition o! f at both
an implicant of eles (e.g.,
time 1 .ad 2 amounts to
T-Ebo). A b , the inputs need not be clocLed at the
same tima. For example, d the eecond value of a is clocked
at timet, dla rith i < t maptoa, and d l a i with i >= t
map tow. Thir can be done on a per input bssis.
As an &&cy
concem, it is not necesesry to generate
function fi for rEl time points. The following lemma gives a
simpb bound cm &e time points needed for a -al
in the
circuit.
Lemmr 5.1 Lei A and 6 be the longest and shorted gnaphi d d e l q t0 (t sipnd f. The ret f o , f(,.fp+l, :..fA-l,fA $3
srficied to determine all possible transtitons an the ctrcrd.
The above lemma follows directly from the unit delay
model. Signal f cannot change until the chan e in the nearest input propsgatea through, and will atop cfanging when
the input furthest away finally arrives. All references to fi
maptofa i f i > A a n d t o f o i f i < 6 .
6.4 Symbolic Event Suppression
To compute the transition delay of a circuit, it may not
during symbolic simulation to store, or even
the Roolean functiom corresponding to each
gate and each time point. Typically, one ia i n t e d in
arpsnnring the question: “Is the delay of the circuit 2 6?”
In this case, we only require the ft’s where 6t 2 6 - 1 and
f is the circuit output. We XOB fs-1 with each such ft and
check the XOa’ed function for satieiiability to me if there is
indeed a transition at time 6.
Techniques simidar to the event suppression techniques
described in [SIfor the efficient simulationof a vector pair on
a circuit can be wed in the symbolic simulation procedure
as well. For example, given a gate g in the circuit, let wg
be the length of the longest path fiom the gate output to
the circuit output. We only need to compute the gr’s such
that t
2 6 - 1.
+
6.6
Finally for the last interval,
General Delay Model
A gate with a large fanin may have several times the delay
of an inverter. If one usea n o r m a l i d time units, one can
always introduce unit-delay buffers at the output of gates
in a circuit, which have a delay greater than unity, in order
For this example there are three poesible transitions:
to model differing delays among logic gates.
5.6 Checking Satidability
0 g changes state from time interval 0 to 1,
We
maintain the various Boolean functions as multilevel
0 f changes state from time interval 0 to 1,
logic networks during the course of symbolic simulation.
The sim of thew networks is not much larger than the
0 f changes state from time interval 1 to 2.
circuit itself. Altematively, we could have wed reduced,
The symbolic formulaefor t h e transitions are reepectively: ordered Binary Decision Diagram (ROBDD 1 representatiom for thaw fanctions, and propagated
through
el = go G3 g1 = K a o 4-G
the circuit.
Once we have the f r - 1 @ f 6 function for the circuit output, we can determine if the tnnction is s a t s a b l e by cone2 = fo @ f1 = K 6 - 6 0 C b - 6 0
e3 = f1G3 f2 = Z ~ o b o a-q6o
Each implicant in e3 gives an input vector pair which generates a transition of signal f at time 2 (between time interval 1 and 2). For exam le, implicant Tu060 corresponds
multilevel networks, and the uac of Larrabee’s Mtisfiability
to vector pair ~ l ( a , b =
) 6 , X ) and %(a,b) = (1,l).
checking algorithmsucceedsin computing the transition de‘Keep in mind that we asmme the sin& stepping mode of operation
lay of the circuit (cf. Section 6).
f2
= glbl = Gh
d8hDs
+
+ +
~~~
553
Pqmx 34.3
EX
cbp.12.2
cbp.16.4
inputs
25
33
I
outputs
literals
331
413
17
13
longest
40.00
44.00
---2
11
381
371
I
9 I
812 I 122
20 I 37
Table 3: Transition Delay Computation on Benchmark Examples for Bounded Gate Delays
EX
val
1. d.
f. d.
#check
CPU
results are shown in Table 3.
The CPU times in Tables 2 and 3 are on a SUN-4 workstation and correspond to the time re uired for floating
delay computation using the method of771 plus transition
delay computation. The time required for transition delay
calculation is typically a small fraction of the time required
for floating delay computation.
We are currently experimenting with random-logic circuits to see if logic optimization affects the transition delay
of a circuit.
7 Certified Timing Verification
In Section 4.2 we demonstrated that there can be a difference in the floating delay and transition delay of a circuit.
In Section 5 we ave a procedure that actually computed
the transition defay of a circuit assuming fixed delays and
no monotonic speed-up. This procedure produces a vector pair that sensitizes the critical path in the transition
delay mode. Finally, in Section 6 we presented results on
applying the transition delay computation procedure to a
number of benchmark examples. As Table 2 indicates, on
benchmark circuits the transition delay typically does not
differ from the floating delay, but we claim that it is still
useful to compute the transition delay because of the utility of the resulting vector set for certifying the delay of the
circuit. In this section we briefly outline a procedure for
certifying the results of static timing verification.
The transition delay procedure works on the question “Is
there a path with transition delay greater than 6?” the first
step is to identify the upper bound on the delay of the circuit. As the transition delay of a circuit is bounded above
by the true floating delay [2] the natural value for 6 is the
t. d.
secs
Table 2: Transition Delay Computation on Benchmark Examples for Fixed Gate Delays
6 Experimental Results
In this section, we present preliminary experimental results
in determining the transition delay of a circuit. Transition delay computation results in the procurement of vector
pairs that each propagate a transition along a longest true
path to the output. The set of vector pairs can be used
to perform timing analysis under more sophisticated delay
models, (e.g. using SPICE).
The techniques described in the previous sections have
been implemented in the program TrueD-T. The statistics
of the chosen benchmark circuits are shown in Table 1.
Results on applying the fixed delay simulation calculus to
compute the transition delay of a circuit are given in Table
2. We were able to exactly compute the transition delay
under the fixed unit gate delay model for all the benchmark
circuits, using the symbolic simulation algorithm described
in Section 5. In the table, Val corresponds to the logical
value the path was sensitized to, 1. d. is the longest path
delay, f. d. is the floating mode delay, and t. d. is the
transition delay.
The fixed delay model may not be realistic for use in
certified timing verification since there will always be some
statistical variation in the predicted gate delays. We next
experimented with the bounded gate delay model, where all
gates have upper bounds equal to unity, and lower bounds
equaling zero.* We have been able to obtain vector pairs
that validate the floating delay for all the ISCAS-85 benchmark circuits under the bounded gate delay model. The
’The monotone speed-up condition
Paper 34.3
return a single vector sequence which sensitizes an event
along some path, perhaps only one, of length at least 6.
Whichever approach is applied let us call the resulting vector sequence V.
The circuit model, perhaps with speed-ups required by
the transition delay computation procedure, is then given
to the timing simulator of choice. The vector sequence V is
then applied. In general the results of the timing simulation
should not give delay values that are worse than the results
of the transition delay calculation. If this happens it means
that the delays used in the transition delay calculation were
not pessimistic enough; these should be modified and the
delay calculation re-run.
554
the i"upeThe most complex case is when the timin simulation of modes give the same value. Finally, while we
a delay 7 that is 1- than 6. Ifthere is SUB- diate practical applications of thie work in certfied t h g
cient confidence in the coverage of the vector set then an verification and delay fault testing, we hope that resolution
aggressive designer may opt to clock the circuit at 7 . An- of the k u e s discuseed in this section will ultimately elimiother approach is to further investigate the r e of pomible nate the need of timing simulation for synchronous digital
clocking speeds uein statietical methodr [q.% bope here circuits altogether.
is that the etatistic3 analysis procedarea will ' a quantitative notion of what percentage of psrb are E y to run ILeferences
at each speed in the ran e between y and 6.
[l] R.Bryant. Graph-Based Algorithmsfor Boolean FuncUsing a combinationo transition delay computation and
tion Manipulation. In IEEE lhnsactions on Computtiming simulation in this way givea a greater predictability
em, d u n e G35, pages 677-691,August 1986.
to the post-manufacture delay of the circuit.
[2] E-C. Chen and D. Du. Path Sensitization in Critical
8 Conclusions
Path Problem. In Proceedings of Int7 Confennce on
In this paper we demonstrated for the first time that the
ComPater-Aided D a h I + L " h r 1991.
transition delay of a circuit can differ from the floating d e
lay even in the presence of arbitrary monotonicspeed-ups in [31 s w Chen& H-C Chen, David Du, and A* Lim. The
to motink the &,intion of
role of long and short paths in circuit performance o p
the circuit. Thie
timisation. In The Proceedings of the Design Artomaa
w h i b~ t l y computse the tr-tion
delay of
Confennee, lgg2.
a circuit. A fuller development of this procedure required
the development of a number of difterent simulation tal- [4]S. Devadas, E-F.Jyu, K. Keutzer, and S. Malik. Staculi, each suited to ~ l " ~ t b nregardincl
s
~ d ddelay
=
t i s t i d timing W d y h of combinationallogic circuits.
modeling such as bounded delay or monotonic @-ups.
In Preadings, Tau 98: 1991 ACM Workshop on TimSpace limitations have reduced thir paper to an
ing I s ~ in
a fhe Specification and Synfhesis of Digital
of a symbolic simulation procedure for computing t e tranSystems, 1992.
sition delay assuming fixed gabdelays and no speed-ups.
The output Of the t r h t i o m d e l W compu~tion rocedure [5]S. Devadas, K. Keutser, and S. Malik. Delay Comis a vector muence which excites an eve& dang tge
putation in CombinationalCircuits: Theory and Algosensitixable path of the circuit under conrideration.
rithms. In Proceedings of the International Confennce
While this theoretical framemork for the an.lySis of tranon Compufer-Aided Design, November 1991.
sition delay is in itself useful for understandins the relationship between static and dynamic delay andysm, we envision [SI S. Devadas, K. Keutser, S. Malik, and A. Wang. Certified Timing Verification and the " s i t i o n Delay of
the most practical application of these results in certified
timing verification. In such a scenario the upper bound on
a Combinational Logic Circuit. In MIT Technical Recircuit delay is first derived by means of a floating delay calport, Massachusetts Institute of Technology, October
culation. The transition delay of the circuit in then derived
1991.
using the transition dela calculator, and a vector sequence
for Wmitiging the c & , i c J p t b of& circuit, produced 88 [7]S. Devadas, K. Keutzer, S. Malik, and A. Wan . Coma by- rod& of t h i delay d c d h o n . T b w r aeguence
putation of Floating Mode Delay in b&8ircuits:
-dator quipped with
Practice and Implementation. In MIT Technical Recan tEen be applied
a t'
more =curate t i - g m d d x
a p d m mto
port, Massachusetts Institute of Technology, October
1991.
give the high accuracy of timing sirpulation wit\ the computational efficiency and the Compneensive path coverage
[8]S. Devadas, K. Keutzer, S. Malik, and A. Wang.
of static timing verification.
Efficient Timing Simulation for Delay Computation.
8.1 Work in Progress
In P m . of Bmwa/MIT Confennce on Advanced ReA great deal of work remains to be done in order to underseamh in VLSI and Parallel Sysfems, March 1992.
stand completely the relationahip between transition and
[91 T. Lmabee. Test pattern Generation
floating delay. Even the definition of tr-itbn
delay
Satisfiability. In IEEE Zhnsactions on 8omprt erquires further examination. The common single-stepping
Aided Design, volume 11, pages 4-15, January 1992.
definition of transition delay to ether with a simple sufficiency condition for a valid do$ frcclUenCY w q P F n t e d [lo] p. c. McGmr and R. K. Brayton. Integrating p n c in Section 3,but a full eonsideration of the relationship be+
and tempomidomains in logic design. K uwer
tween transition delay and clocking inquency remaim to be
~ d ~ Pub&&ers,
m i ~1991.
done. Encour ng pro
towa.rd reeolving thia question
withre ardto oating elaywillbepreaentedat thisconfer- [U]C-J. Seeer and R. E. Bryant. Modelling of Circuit
ence [$ correct computation of transition dday seems to
Delay8 111 Symbolic Simulation. In IFIp Internubecome enmeshed in m
technology specific hues, such
tional Workshop on Applied Formal Methods for Coras the instantaneous
es di"d in Section 4.1, and
net VLSI Design, pages 625-639,November 1989.
uue further reeolution. F'urthermore,
these issues ale0
while a distinctio%t-n
hating delay and traneition
delay has been drawn in this paper we pmamtly have no
clear idea of how fundamental this difference ie. We have
presented circuits in which a Merence occurs and we have
derived a number of circuit propertiem that give sufficiency
conditions under which the two delay modes give the same
value [6],but we have not c l 4 the
with preciee neetk
sary and sufficient conditions under %ch those two delay
V reports
I
Tition
e
Y r
$is
555
Paper 34.3
I
I
I