TMPM340 Group
Product Introduction Guide
TMPM340 Group
(TMPM342)
The TMPM340 Group is a high-performance 32-bit RISC microprocessor product group based on the ARM Cortex-M3 core. In the TMPM340 group, the TMPM342 contains a microprocessor (MCU) and motor driver (MCD)
in one package.
The TMPM340 Group incorporates high-speed and high-performance analog circuits that are required for lens
control and image stabilization of a digital single-lens camera and surveillance camera.
It also incorporates high-resolution PPG output function for smooth control of motors.
A small package is available for implementation to mobile applications.
The TMPM340 Group has the MCD (Motor Control Driver) unit that contains a H-SW bridge driver (direct PWM
control and micro-step mode are selectable). By setting registers, DC motors, electromagnetic coils, or stepping
motors can be controlled as specified.
Application
Peripheral functions suitable for each application
High-resolution PPG output function (TMRD)
12-bit AD converter and 10-bit DA converter required for lens control
Surveillance
camera
High-resolution PPG output function (TMRD)
12-bit AD converter and 10-bit DA converter required for lens control
Digital single-lens
reflex camera
This document describes TMPM342 of the TMPM340 group.
Do not design your products or systems based on the information in this document.
Please contact your Toshiba sales representative for updated information before designing your products.
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2014/7/22
TMPM340 Group
Product Introduction Guide
M340Group
System Function
WDT
NVIC
ARM
Cortex
-M3
CORE
Debug
Timers
Analogs
FLASH
PLL /CG
RAM
Low Power
Mode
Back-up
RAM
Serial Communications
DMAC
TMRB
12-bit ADC
SIO/UART
(4 Byte FIFO)
H-SW Type
Bridge
driver
OP Amp
PORT
TMRD
16-bit
ΔΣADC
UART
Serial input
for MCD
control
EVR
(10-bit DAC)
PSC
EPHC
10-bit DAC
I2C
Protection
circuit
Hall Bias
control circuit
VSIO
SSP
Figure 1-1 Block diagram of TMPM340 Group
2014/7/22
MCD Functions
Page 2
Circuit for
Photo encoder
1.1 Product Lineup of the TMPM340 Group
TMPM340 Group
Product Introduction Guide
1.1 Product Lineup of the TMPM340 Group
MEMORY
(FLASH)
BGA
256 KByte
TMPM342FYXBG
PIN
142pin
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1.1 Product Lineup of the TMPM340 Group
TMPM340 Group
Product Introduction Guide
Table 1-1 A product list described in functional order (For MCU Block)
Product names
Peripheral functions
TMPM342FYXBG
Flash
256 KByte
RAM
RAM 30 KByte /
BACKUP RAM 2 KByte
INT
8
(Included 2 factors are connected to MCD internally)
NMI
0
DMA
DMA
2 units
(2 channels per unit,
16 factors)
PSC
PSC
1 unit
Input/Output
43
(Includes 12 5-V tolerant
inputs)
Input
20
Output
-
5V-tolerant
input
-
TMRB
16 channels
TMRD
2 units
(4channels per 1 unit)
PHC
2 channels
SIO/UART
3 channels
UART
1 channel
I2C/SIO
1 channel
VSIO
5 channels
SSP
4 channels
ADC
2 units
(8+4 channel)
 ADC
1 unit
(4 channels)
DAC
2 channels
System function
WDT
1 channel
Debug interface
Debug
SWD
Memory
External interrupt
Input/Output port
Timer functions
Serial communication function
Analog function
VFBGA142
(7mm x 7mm,
0.5mm pitch)
Package
2014/7/22
Page 4
1.1 Product Lineup of the TMPM340 Group
TMPM340 Group
Product Introduction Guide
Table 1-2 A product list described in functional order (For MCD Block)
Product names
Peripheral functions
TMPM342FYXBG
H-SW Bridge driver
7.5 channels
Op-amp
6 channels
Op-amp with
variable gain
function
4 channels
10-bit DAC
6 channels
Sensor signal processing
Constantcurrent control
circuit
2 channels
2-phase
Circuit for encoder
comparator with
hysteresis
adjustment
function
Nch SW of
photo encoder
for bias supply
3 channels
Internal connection function
for MCU
Serial input for MCD control
Protection circuit
2 units
TSD
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Available
2014/7/22
1.2 Functional Description
TMPM340 Group
Product Introduction Guide
1.2 Functional Description
1.2.1
MCU Block
1. ARM Cortex-M3 core is incorporated.
Mass data processing and calculation can be executed at high-speed.
2. Built-in Flash memory and RAM
Flash memory : Built-in Flash memory
RAM : Backup RAM for storing data in the low-power consumption mode is available.
3. Clock control (CG)
The built-in PLL can use an inexpensive oscillator even when the MCU operates at high speed.
Also, the built-in clock gear function can reduce a power consumption by slowing the core’s operation speed while peripheral functions operate at high speed.
4. Low power consumption function
The following low power consumption modes are available in the TMPM340 Group.
• IDLE mode: Stops the CPU and specified peripheral functions. Other peripheral functions operate
on the high-speed clock.
• STOP1 mode: Except a certain peripheral functions, all peripheral functions including the oscillation circuit stop. Power consumption is lower than IDLE mode.
• STOP2 mode: Except a certain peripheral functions, stops all functions and stops a power supply
to other peripheral functions. Therefore, the STOP2 mode can achieve a greater reduction in
power consumption than the STOP1 mode.
5. External interrupt function
The MCU has interrupt pins for external interrupt pins that can specify a 7-level of interrupt priority.
These external interrupt pins are also used for releasing the low-power consumption mode.
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1.2 Functional Description
TMPM340 Group
Product Introduction Guide
6. Bus matrix
The bus matrix is optimized to operate built-in multiple bus masters efficiently.
TMPM340 Group incorporates the following bus masters:
• DMA Controller (DMAC)
Two units of DMA controllers that have 2 channels per unit. Each channel has 16 startup factors.
In addition to the memory-memory transfer, data is transferred from/to the registers of builtin peripheral functions at high speed.
7. Programmable servo/sequence controller (PSC)
The PSC independently operates from the CPU. Since the PSC performs servo control or sequence
control for motors, calculation task of the CPU can be decentralized and whole process performance
will be improved.
The PSC can be started up by the CPU or peripheral circuits.
8. Input/output ports
Input/output ports (5 V-tolerant input ports included), input ports, output ports are incorporated.
Furthermore, 16 ports internally connect to MCD exist.
9. Timer function
The following timer functions are available in the TMPM340 Group.
• 16-bit timer/event counter (TMRB)
• High-resolution 16-bit timer (TMRD)
• 2-phase pulse input counter (PHC)
10. Serial communication function
The following serial communication functions are available in the TMPM340 Group.
• Serial channel (SIO/UART)
• Asynchronous serial communication interface (UART)
• Serial bus interface(I2C/SIO)
• Variable data length Serial Interface (VSIO)
• Synchronous serial bus interface (SSP)
11. Analog function
The following analog function is available in the TMPM340 Group.
• 12-bit Analog-to-Digital Converter (ADC)
• 16-bit  Analog-to-Digital Converter (DSADC)
• 10-bit Digital-to-Analog Converter (DAC)
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1.2 Functional Description
TMPM340 Group
Product Introduction Guide
12. System function
The following system function is available in the TMPM340 Group.
• Watchdog timer (WDT)
13. Endian
The following endian is available in the TMPM340 Group.
• Supports little-endian.
14. Debug interface
The following debug interface are available in the TMPM340 Group.
• SWD is supported.
• SWV pin and TRACEDATA/TRACECLK pin are supported as trace output pins.
1.2.2
MCD Block
The TMPM342 incorporates the Motor Control Driver (MCD).
The TMPM340 Group controls DC motors, electromagnetic coils, and stepping motors by setting registers.
The MCD has the following functions:
1. H-SW bridge driver
2. Analog sensor/encode signal process circuit
3. Comparator for encoding
4. Serial input for MCD control
5. Protection circuit
2014/7/22
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1.3 Operation Conditions
TMPM340 Group
Product Introduction Guide
1.3 Operation Conditions
1. Maximum operation frequency
• 40 MHz
2. Operation voltage range
• MCU Block
2.7 to 3.6V (for digital power supply)
2.7 to 3.6V (for analog power supply)
• MCD Block
3.1 to 3.5V (for analog power supply)
2.5 to 5.5V (for motor control driver power supply)
3. Operation temperature range
Table 1-3 Operation temperature range
Temperature range
-40 to 25 C
Flash write enable
-25 to 0 C
0 to 70 C
70 to 85 C
OK
NG
NG
MCU
Except when Flash write enable
In function operation
OK (note)
NG
OK
MCD
In stand by
OK
Note: Only a 10-bit DAC operates at -25 to 85C
1.4
Package
TMPM340 Group has the following package.
• VFBGA142 (7mm x 7mm, 0.5mm pitch)
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1.5 Functional Description
TMPM340 Group
Product Introduction Guide
1.5 Functional Description
This section describes the peripheral functions built-in the TMPM340 Group.
1.5.1
Flash Memory
The capacities and configurations of Flash memory for the TMPM340 Group are as follows:
Writing is performed in the units of page.
One word means 32 bits.
Table 1-4 Capacities and configurations of Flash memory
Product
TMPM342FYXBG
Block configuration (pcs)
Capacity
(KB)
128
(KB)
64
(KB)
32
(KB)
16
(KB)
256
0
3
1
2
Write time(s)
Erase time(s)
8
(KB)
Number of
words per
page
1page
1chip
1block
1chip
0
64
0.00125
1.28
0.1
0.4
Note:This table shows each register initial value after reset. A data transfer time is not included. A write time per
chip differs depending on users’ reprogramming method.
1.5.2
RAM
The RAM capacities for the TMPM340 Group are as follows:
Table 1-5 RAM capacity and configuration
2014/7/22
Product
RAM capacity
(KB)
Backup
RAM Capacity
(KB)
TMPM342FYXBG
30
2
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1.5 Functional Description
1.5.3
TMPM340 Group
Product Introduction Guide
Clock Control (CG)
The outline of the clock control circuit of the TMPM340 Group is described as below:
1. Internal high-speed oscillation circuit: 10 MHz  10%
2. Selectable from the external high-speed oscillation circuit or external clock input.
3. PLL (multiplier): The number of multiplications is selectable from a factor of 8 or 16 according to
oscillation frequencies of the high-speed oscillation circuit.
4. Clock gear: Any high-speed clock is selectable from 1/1, 1/2, 1/4, 1/8 or 1/16 (clock gear) as the system clock (fsys).
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1.5 Functional Description
1.5.4
TMPM340 Group
Product Introduction Guide
DMA Controller (DMAC)
The MCU incorporates two units of DMA controller containing 2 channels and 16 startup factors per unit.
1.5.4.1
Outline
The outline of the DMA controller is as follows:
Table 1-6 Outline of DMA (per unit)
Parameter
2014/7/22
Function
Description
Number of channels
2 channels
-
Number of startup
factors
16 factors
-
DMA startup trigger
Hardware start
Startup by a DMA request from peripheral
functions
Software start
Startup by modifying registers
Bus master
32 bits  1 (AHB)
Priority
Higher: channel 0
Lower: channel 1
FIFO
4 word  2 channels
Transfer data size
8/16/32 bits
Burst size
1/4/8/16/32/64/128/256
-
Number of transfers
Up to 4095
-
Address
Transfer source
address
Increment
not increment
Transfer destination
address
Increment
not increment
Fixed
Transfer data size can be set for transfer
source and destination respectively
Settings of source and destination addresses
can be chosen either from "increment" or "not
increment".
(Address wrapping is not supported.)
Endian
Little-endian
-
Transfer type
Peripheral to Memory
Memory to Peripheral
Memory to Memory
Peripheral to Peripheral
Interrupt function
Transfer completion interrupt (INTDMACxTC)
Error interrupt (INTDMACxERR)
-
Special function
Scatter/gather function
-
If "Memory to Memory" is selected as a transfer type, a hardware startup by DMA is not supported.
Allocations of peripheral functions as source
and destination are limited.
Page 12
1.5 Functional Description
1.5.4.2
TMPM340 Group
Product Introduction Guide
List of Startup Factors
The following tables list startup factors in each unit.
Table 1-7 A list of DMA startup factors
Startup
factor No.
Unit A (channel 0/1)
Unit B (channel 0/1)
Burst
Single
Burst
Single
0
UART reception
(channel 0)
UART reception
SIO/UART reception
(channel 0)

1
UART transmission
(channel0)
UART transmission
SIO/UART transmission
(channel 0)

2
SIO/UART reception
(channel 1)

SIO/UART reception
(channel 2)

3
SIO/UART transmission
(channel 1)

SIO/UART transmission
(channel 2)

4
TMRD 0 compare match
(Unit B, TMR0)

TMRD 0 compare match
(Unit A, TMR0)

5
TMRD 0 compare match
(Unit B, TMR1)

TMRD 0 compare match
(Unit A, TMR01)


conversion completion
(Unit B)
Normal AD
Normal AD

6
conversion completion
(Unit A)
7
conversion completion
(Unit A)

conversion completion
(Unit B)

8
PHC phase 0
(channel 0)

PHC phase 0
(channel 1)

9
PHC phase 1
(channel 0)

PHC phase 1
(channel 1)

10
PHC phase 2
(channel 0)

PHC phase 2
(channel 1)

11
PHC phase 3
(channel 0)

PHC phase 3
(channel 1)

12
TMRB timer register 1
compare match
(channel 4)

13
TMRB timer register 1
compare match
(channel 6)

Highest-priority AD
conversion completion

14
Variable data length
SIO(VSIO) reception

SSP transmission
(channel 2)
SSP transmission
(channel 2)
15
Variable data length
SIO(VSIO) transmission

SSP reception
(channel 2)
SSP reception
(channel 2)
Highest-priority AD
Highest-priority AD
Normal AD
conversion completion
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
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1.5 Functional Description
1.5.5
Programmable Servo/Sequence Controller (PSC)
1.5.5.1
Outline
The following table lists the major functions:
Table 1-8 Outline of PSC
Parameter
Function
Startup method of
PSC
Started up by CPU.
PSC register
Calculation registers
Started up by peripheral functions.
<Startup factor>
Started up by CPU
Started up by peripheral functions
Pointers
Control registers
Flag registers
Debug
Break
Step
Interrupt function
2014/7/22
PSC completion interrupt
PSC break interrupt
PSC step interrupt
PSC illegal instruction interrupt
PSC illegal address interrupt
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TMPM340 Group
Product Introduction Guide
1.5 Functional Description
1.5.6
TMPM340 Group
Product Introduction Guide
Timer Function
1.5.6.1
16-bit timer/event counter (TMRB)
(1)
Outline
The TMRB is a peripheral function that incorporates a 16-bit counter and can be used as a timer,
event counter or PPG output.
It captures the value of 16-bit counter at specific timing.
Multiple channels can be started simultaneously.
(2)
Operation mode
The TMRB has the following operation modes.
(a) Interval timer mode
This mode counts up a 16-bit counter at a specified clock count of the source clock.
When the counter matches a preset value, an interrupt request occurs.
The counter value can also be captured to the capture register at a specified timing (at a
change of software capture, capture trigger and input capture input pin).
(b) Event counter mode
This mode counts up a 16-bit counter using an external clock instead of the source clock in
the interval timer mode.
The interrupt and capture function can be used in the same way as the interval timer mode
(the pin used by an external clock input cannot be used as a capture input).
(c) Programmable rectangular wave output (PPG) mode
This mode outputs a rectangular waveform at a specific frequency and duty ratio to the output pins.
Either "active-low" or "active-high" logic can be selected as for the output pins.
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1.5 Functional Description
(3)
TMPM340 Group
Product Introduction Guide
Interrupt request
The TMRB has the following interrupt requests:
(a) Compare match interrupt
When the 16-bit up-counter matches a preset value, a compare match interrupt request
occurs. As the compare match interrupt request is a shared interrupt with an overflow interrupt,
the interrupt handler detects the factor by reading the status flag.
(b) Overflow interrupt
When the 16-bit up-counter has overflowed, an overflow interrupt request occurs. As the
overflow interrupt request is a shared interrupt with a compare match interrupt, the interrupt
handler detects the factor by reading the status flag.
(c) Input capture interrupt
When the capture register captures a value of the 16-bit up-counter, an input capture interrupt
request occurs.
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1.5 Functional Description
1.5.6.2
TMPM340 Group
Product Introduction Guide
High-resolution 16-bit timer (TMRD)
(1)
Outline
The TMRD is a peripheral function that incorporates two units of the timer unit and clock setting
circuit (prescaler). It can be used as a timer or rectangular output.
A rectangular output can be used in the 1-bit modulation and can be adjusted on a duty ratio that is
pseudo-higher resolution than fc.
These two timer units can operate independently or in an interlocked fashion.
(2)
Operation mode
The TMRB has the following operation modes. These operation modes can be switched in each
channel.
(a) 16-bit interval timer
1. Timer mode
Two timer units operate independently.
The mode is one that counts up a 16-bit counter at a specified clock count of the
source clock.
Two types of the counter operation are available. According to the setting, different
operations can be specified in each timer unit.
Regardless of the counter operation, if the value of the counter matches a specified
value, an interrupt request occurs.
2. Interlock timer (synchronous start) mode
The mode is one that the both counters in each timer unit can start simultaneously. A
timer cycle is settable respectively.
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1.5 Functional Description
TMPM340 Group
Product Introduction Guide
(b) 16-bit programmable rectangular waveform output (PPG)
This mode outputs a rectangular waveform at a specific frequency and duty ratio to the output pins.
Either "active-low" or "active-high" logic can be selected for the output pins.
1. PPG mode
Two timer units operate independently. In this mode, the TMRD can output programmable rectangular waveforms in frequency and duty ratios respectively.
These two units output two channels of rectangular waveforms with the same frequency respectively.
2. Interlock PPG mode
The mode is one in which two timer units operate in an interlocked fashion via the
comparator containing the phase shift function.
(3)
Interrupt request
The TMRD has the following interrupt requests:
(a) Compare match interrupt
When the 16-bit up-counter matches a preset value, a compare match interrupt request
occurs. As the compare match interrupt request is a shared interrupt with an overflow interrupt,
the interrupt handler detects the factor by reading the status flag.
(b) Overflow interrupt
When the 16-bit up-counter has overflowed, an overflow interrupt request occurs. As the
overflow interrupt request is a shared interrupt with a compare match interrupt, the interrupt
handler detects the factor by reading the status flag.
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1.5 Functional Description
1.5.6.3
TMPM340 Group
Product Introduction Guide
2-phase pulse input counter (PHC)
(1)
Outline
The PHC is a peripheral circuit that incorporates the 16-bit counter counting a 2-phase pulse which
has a 90 degree phase difference. It counts outputs from a rotary encoder.
The 16-bit counter has three selectable operation modes.
(2)
Operation mode
The PHC has the following counter operation modes. A combination of asynchronous 2-phase
pulse inputs determines whether the 16-bit counter counts up or counts down.
(a) Normal mode
The mode is one in which the 16-bit counter counts up/down every time a combination of the
2-phase pulse inputs changes four times.
(b) 4-fold multiplication mode
The mode is one in which the 16-bit counter counts up/down every time a combination of the
2-phase pulse inputs.
(c) Twofold multiplication mode
The mode is one in which the 16-bit counts up/down every time either of 2-phase pulse
inputs changes.
(3)
Interrupt request
The PHC has the following interrupt requests:
(a) Compare 0 match interrupt
When the 16-bit up-counter matches a preset value, an interrupt request occurs.
(b) Compare 1 match interrupt
When the 16-bit up-counter matches a preset value, an interrupt request occurs.
(c) Interrupts when the counter counts up or counts down
An interrupt occurs every time the counter counts up or counts down.
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1.5 Functional Description
1.5.7
TMPM340 Group
Product Introduction Guide
Serial Interface Function
1.5.7.1
Serial channel (SIO/UART)
(1)
Outline
The serial interface function is a peripheral function that switches the operation modes between the
synchronous communication mode (I/O interface mode) and asynchronous communication mode
(UART mode).
It has a 4-stage FIFO .
The serial interface function incorporates the baud-rate generator to communicate in various transfer rates.
(2)
Operation mode
The SIO/UART has the following operation modes:
(a) I/O interface mode
The I/O interface mode is the mode where data is transferred using the half-duplex or fullduplex communication system in synchronization with clock signals.
In the I/O interface mode, switching between a master and slave, designation of LSB and
MSB of transfer data, and designation of a transfer clock edge of the slave mode are possible.
The hold time of the last bit and level of the data output pin after the last bit is output can be
specified.
(b) UART mode
The UART mode is one in which data is transferred at a preset transfer rate.
The flow control is implemented using CTS.
The data bit length is selectable from 7-bit, 8-bit or 9-bit. When a 7-bit or 8-bit data length is
selected, a parity bit can be added.
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1.5 Functional Description
(3)
TMPM340 Group
Product Introduction Guide
Interrupt request
The SIO/UART has the following interrupt requests:
(a) I/O interface mode
1. Transmit interrupt
When the transmit double buffer is disabled, if data transmission is complete, a transmit interrupt request occurs.
When the transmit double buffer is enabled, if transmit data in the transmit buffer is
transferred to the shift register, a transmit interrupt request occurs.
When the transmit FIFO is enabled, if the transmit FIFO reaches to the specified the
fill level, a transmit interrupt request occurs.
2. Receive interrupt
When the receive double buffer is disabled, if data reception is complete, a receive
interrupt occurs.
If the receive double buffer is enabled, if receive data is transferred to the receive
buffer from the shift register, a receive interrupt request occurs.
When the receive FIFO is enabled, if the receive FIFO reaches the specified the fill
level, a receive interrupt request occurs.
(b) UART mode
1. Transmit interrupt
When the transmit double buffer is disabled, a transmit interrupt occurs immediately
before the STOP bit is output.
When the transmit double buffer is enabled, if transmit data of the transmit buffer is
transferred to the shift register, a transmit interrupt request occurs.
When the transmit FIFO is enabled, if the transmit FIFO reaches the specified the fill
level, a transmit interrupt request occurs.
2. Receive interrupt
When the double buffer is disabled, if data reception is complete, a receive interrupt
request occurs.
When the double buffer is enabled, if receive data is transferred to the receive buffer
from the shift register, a receive interrupt request occurs.
When the receive FIFO id enabled, if the receive FIFO reaches the specified the fill
level, a receive interrupt request occurs.
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1.5 Functional Description
1.5.7.2
TMPM340 Group
Product Introduction Guide
Asynchronous serial communication interface with flow control (UART)
(1)
Outline
The UART is a peripheral function that supports asynchronous serial communications.
It has a 32-stage FIFO.
(2)
Operation mode
The UART has the following operation modes:
(a) UART mode
This mode controls the data flow using CTS and RTS.
A status of the MODEM control pin can also be read by the status registers. The status of the
MODEM control pin can be controlled by the control registers.
Data bit length is selectable from 5-bit, 6-bit, 7-bit or 8-bit. In addition, a parity bit can be
added.
(3)
Interrupt request
The UART has the following interrupt request:
(a) UART interrupt request
When data reaches a preset level of the FIFO, an UART interrupt request occurs. If a transfer
error occurs, an UART interrupt request also occurs. Because a UART interrupt request is a
shared interrupt, an interrupt handler detects a factor by reading the status flag.
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1.5 Functional Description
1.5.7.3
TMPM340 Group
Product Introduction Guide
Serial bus interface (I2C/SIO)
(1)
Outline
The serial interface function is a peripheral function that can be used in I2C Bus mode.
It supports the standard mode and fast mode of I2C bus.
(2)
Maximum transfer rate
• Standard mode
100 kHz (Master mode and slave mode)
• Fast mode
400 kHz (Master mode and slave mode)
(3)
Interrupt request
The I2C has the following interrupt request.
(a) I2C interrupt request
An I2C interrupt request occurs when transmission or reception is complete.
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1.5 Functional Description
1.5.7.4
TMPM340 Group
Product Introduction Guide
Variable Data length Serial Interface (VSIO)
(1)
Outline
The VSIO is a peripheral function that can perform synchronous clock full-duplex serial communication with variable data length.
A Chip Select (CS) signals are used in communication.
A data length is changeable from 8 bits up to 40 bits in the units of 1 bit. An 8-bit 5-stage FIFO is
available for reception and transmission respectively
It supports master mode.
(2)
Operation mode
The VSIO can communicate 2 slaves using CS signals; however it communicates with one slave at
a time.
(3)
Interrupt request
The VSIO has the following interrupt requests:
(a) Receive interrupt request
When a receive completion interrupt or receive FIFO interrupt occurs as an interrupt factor, a
receive interrupt request occurs.
1. Receive completion interrupt
A receive interrupt request occurs when 1 word data reception is complete and a CS
signal becomes invalid.
2. Receive FIFO interrupt
When the receive FIFO reaches the specified the fill level, a receive FIFO interrupt
oc- curs.
(b) Transmit interrupt request
When a transmit completion interrupt or transmit FIFO interrupt occurs as an interrupt factor,
a transmit interrupt request occurs.
1. Transmit completion interrupt
A transmit interrupt request occurs when 1 word data transmission is complete and a
CS signal becomes invalid.
2. Transmit FIFO interrupt
When the transmit FIFO reaches the specified the fill level, a transmit FIFO interrupt
oc- curs.
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1.5 Functional Description
TMPM340 Group
Product Introduction Guide
(c) Error interrupt request
A parity error interrupt occurs when a parity error occurs.
1. Receive error (Overrun error) interrupt
A receive error interrupt occurs if next reception starts when the receive FIFO is full
and data exists in the receive shift register.
Page 25
2014/7/22
1.5 Functional Description
1.5.7.5
TMPM340 Group
Product Introduction Guide
Synchronous serial bus interface (SSP)
(1)
Outline
The peripheral function supports three types of transfer methods.
It has a 8-stage FIFO.
(2)
Operation mode
The SSP has the following operation modes:
(a) Motorola SPI (SPI) frame format
The SPI is a clock-synchronous serial interface developed by Freescale Semiconductor. SSP
is controlled by four-wire signals such as a clock, transmit data, receive data and slave select.
(b) TI synchronous serial interface (SSI) frame format
The SSI is a clock-synchronous serial interface developed by TI. The SSI is controlled by
four wire signals such as a clock, transmit data, receive data and frame signal.
(c) National Microwire (Microwire) frame format
The Microwire is a clock-synchronous serial interface developed by National Semiconductor. SSP is controlled by four-wire signals such as a clock, transmit data, receive data, chip
select.
(3)
Interrupt
The SSP has the following interrupts:
(a) SSP interrupt request
In transmission, empty area has been lower than the 4-stage of FIFO, and an SSP interrupt
request occurs. In reception, as the number of valid data is higher than the 4-stage of FIFO, a
SSP interrupt request occurs.
When a timeout or overrun occurs, a SSP interrupt request occurs.
Because a SSP interrupt request is a shared interrupt, an interrupt handler detects a factor by
reading the status flag.
2014/7/22
Page 26
1.5 Functional Description
1.5.8
TMPM340 Group
Product Introduction Guide
Analog Function
1.5.8.1
12-bit Analog-to-Digital Converter (ADC)
(1)
Outline
The MCU has a 12-bit AD converter that can convert data at high-speed.
The AD converter can be started up by software, trigger inputs and trigger signals from peripheral
functions.
The AD converter has the normal AD conversion function and highest-priority AD conversion
function.
It also has the AD conversion monitoring function in which an interrupt occurs when a preset conversion value is detected,
(2)
Operation mode
The ADC has the following operation modes:
(a) Channel Fixed single conversion mode
An analog input in a specified range is converted to a digital value.
(b) Channel Scan single conversion mode
An analog input in a specified range is converted to a digital value.
In this mode, the highest-priority AD conversion function cannot be used.
(c) Channel Fixed repeat conversion mode
Analog inputs in a specified range are repeatedly converted to digital values at a user-specified number of times.
In this mode, the highest-priority AD conversion function cannot be used.
(d) Channel Scan repeat conversion mode
Analog inputs in a specified range are repeatedly converted on a user-specified number of
times to digital values.
In this mode, the highest-priority AD conversion function cannot be used.
Page 27
2014/7/22
1.5 Functional Description
(3)
TMPM340 Group
Product Introduction Guide
Minimum conversion time
1.0s normal analog input @40 MHz AD conversion clock
(4)
Interrupt request
The ADC has the following interrupt requests:
(a) Normal AD conversion completion request
An AD conversion completion request occurs when the normal AD conversion is complete.
(b) Highest-priority AD conversion completion request
A highest-priority AD conversion completion request occurs when the highest-priority AD
conversion is complete.
(c) AD monitor function interrupt
An AD monitor function interrupt occurs when specified conversion value is detected.
2014/7/22
Page 28
1.5 Functional Description
1.5.8.2
TMPM340 Group
Product Introduction Guide
16-bit  type Analog-to-Digital Converter (DSADC)
(1)
Outline
16-bit type Analog-to-Digital Converter.
The AD converter can be started up by software, trigger inputs and trigger signals from peripheral
functions.
The AD converter has the normal AD conversion function and highest-priority AD conversion
function.
(2)
Operation mode
The DSADC has the following operation modes:
(a) Channel Fixed single conversion mode
An analog input in a specified range is converted to a digital value.
(b) Channel Scan single conversion mode
An analog input in a specified range is converted to a digital value.
In this mode, the highest-priority AD conversion function cannot be used.
(c) Channel Fixed repeat conversion mode
Analog inputs in a specified range are repeatedly converted to digital values at a userspecified number of times.
In this mode, the highest-priority AD conversion function cannot be used.
(d) Channel Scan repeat conversion mode
Analog inputs in a specified range are repeatedly converted on a user-specified number of
times to digital values.
In this mode, the highest-priority AD conversion function cannot be used.
Page 29
2014/7/22
1.5 Functional Description
(3)
TMPM340 Group
Product Introduction Guide
Minimum conversion time
66s @ fc=10MHz
(4)
Interrupt request
The DSADC has the following interrupt requests:
(a) Normal AD conversion completion request
An AD conversion completion request occurs when the normal AD conversion is complete.
(b) Highest-priority AD conversion completion request
A highest-priority AD conversion completion request occurs when the highest-priority AD
conversion is complete.
2014/7/22
Page 30
1.5 Functional Description
1.5.8.3
TMPM340 Group
Product Introduction Guide
10-bit Digital-to-Analog Converter (DAC)
(1)
Outline
This 10-bit digital analog converter outputs a preset voltage.
Reference voltage pins for resistors and DA converter can switch between connection and disconnection.
(2)
Maximum settling time
Maximum settling time : 100s
Page 31
2014/7/22
1.5 Functional Description
1.5.9
TMPM340 Group
Product Introduction Guide
System Function
1.5.9.1
Watchdog timer (WDT)
(1)
Outline
The WDT is a peripheral function that detects overflow of binary counter and generates an interrupt request or resets the MCU. This is caused when a binary counter cannot be cleared within the
preset detection time.
When WDT is programmed to clear the binary counter within the preset detection time beforehand, WDT can detect a MCU malfunction
(2)
Interrupt request
The WDT has the following interrupt requests:
a. Watchdog timer interrupt request
When WDT detects an overflow in the binary counter, it generates a watchdog timer interrupt request. The watchdog timer interrupt is a non-maskable interrupt.
2014/7/22
Page 32
1.5 Functional Description
TMPM340 Group
Product Introduction Guide
1.5.10 MCD Block Function
1.5.10.1 Outline
The MCD incorporates 7.5 channels of the H-SW bridge driver equipped with direct PWM control and
micro-step mode. The MCD controls DC motors, electromagnetic coils, and stepping motors by setting
registers of the driver.
1.5.10.2 MCD Block Internal Function
The MCD has the following functions:
(1)
H-SW bridge driver (7.5ch)
The MCD incorporates 7.5 channels bridge driver.
This bridge driver internally connects with PWM outputs of the MCU; therefore direct PWM control is enabled.
Of 7.5 channels, 4 channels can be switched to the external inputs and they support the micro-stepping mode.
(2)
Sensor signal process circuit
a. Analog amp
General-purpose Op-amp: 6 channels
b. General-purpose EVR (Electrical Variable Resistance)
10-bit DAC: 2 units
c. Hall bias control circuit
Consists of an 8-bit DAC and Op-amp:2 units
d. Circuit for photo encoder (FG)
Sets a reference voltage to the encoder waveform shaping circuit for the 2-phase encoder
Comparator with the output latch function (with variable hysteresis function) : 2
Nch SW for power bias of the photo encoder circuit (with GND connection) : 2
Page 33
2014/7/22
1.5 Functional Description
(3)
TMPM340 Group
Product Introduction Guide
Serial input for MCD control
16 bits (8 bits (address) + 8 bits (data)) synchronous communication can control various functions.
(4)
Protection circuit
The MCD incorporates the thermal shutdown circuit (TSD) as a protection circuit.
When the MCD detects the upper limit of a temperature, the protection circuit makes the H-SW
output off.
2014/7/22
Page 34
1.6 Pin Layout
TMPM340 Group
Product Introduction Guide
1.6 Pin Layout
A pin layout of TMPM340 Group (TMPM342) is shown below:
1
2
A
MODE DAVSS
B
ADAVSS
3
4
5
ADB
VDD3
ADA
VREFH
DA
VREFH
PF5
PF3
PF1
6
7
DVDD
3_A
8
9
10
11
12
13
OP4NIN OP0NIN
OP1NIN
OP5NIN OP2NIN
OP3NIN
PH0
ADA
VDD3 , OP4PIN OP0PIN
DAVDD3
OP1PIN
OP5PIN OP2PIN
OP3PIN
HB0F
C PJ0 PJ4 PF6 PF4 PF2 PF0
OP4OUT OP0OUT OP1OUT OP5OUT OP2OUT OP3OUT
HB1F
D PJ1 PJ5 PG3 PG2 PG1 PG0
EVR0
PF7
DAOUTB DAOUTA
EVR1
PB1
PB0 VM2
E PJ2
PJ6
RESET
㸫
㸫
㸫
㸫
㸫
㸫
HB0S
PB2 CO2 CO1
F PJ3
PJ7
㸫
PE0
㸫
㸫
㸫
㸫
㸫
HB1S
PB3 DO2 DO1
G
ADCV
REF02
OUT
ADC
VREFH
OUT
EFU
SE
PE1
㸫
㸫
㸫
㸫
㸫
PB4 PH5 EO1
H
ADBVSS,
ADCVSS
ADC
VREFL
OUT
PE3 PE2
㸫
㸫
㸫
㸫
㸫
PB5
PB6 EO2 FO1
J
ADB
VREFH, DVSS_A
ADC
VDD3
PE4 PD7
㸫
㸫
㸫
㸫
㸫
PB7
PH4 GO1 FO2
K
V30IN
PC4
ENC
OUT0
PICP
IN1
PA6 PA7
PH3 GO2 VM3
L PD0 PC0 PC2 PC3 PC7 PC5
ENC
OUT1
PICP
IN0
PA4 PA5
PH2 GO3
RNF3
PD4 PD2 PD3 PC6
PGND2
M PD6 PD5 PD1 PC1
DVSS_B
DVDD
3_B
PIDBA PIDBB
PA2 PA3 BO2 AO2
PGND1
N PH1
AVSS_C
AVDD
3_C
RVDD3
PA0
PA1 VM1 BO1 AO1
FTEST3
X2
DVSS_C
X1
Figure 1-2 Pin layout (TMPM342FYXBG, VFBGA142 TOP VIEW)
Page 35
2014/7/22
1.7 Pin Names and Functions
TMPM340 Group
Product Introduction Guide
1.7 Pin Names and Functions
1.7.1
Functional pin names and their functions
1.7.1.1
Pin Name of Peripheral Functions
Table 1-9 Peripheral functions, pin names and functions
Peripheral function
Pin name
Input
or
Output
Clock/mode control
SCOUT
Output
External interrupt
INTx
Input
PORT
Pxn
I/O
Port pin x
16-bit timer/event counter
TBxOUT
Output
Output pin
TDx0OUT0
Output
Timer output pin
TDx0OUT1
Output
Timer output pin
TDx1OUT0
Output
Timer output pin
TDx1OUT1
Output
Timer output pin
PHCxIN0
Input
2-phase pulse counter input pin
PHCxIN1
Input
2-phase pulse counter input pin
TXDx
Output
RXDx
Input
SCLKx
I/O
Clock input/output pin
CTSx
Input
Handshake input pin
U0TXD
Output
U0RXD
Input
Data input pin
U0CTS
Input
Handshake input pin
U0RTS
Output
Handshake output pin
VSIOTXD
Output
VSIO Data transmit pin
VSIORXD
Input
VSIO Data receive pin
VSIOSCK
I/O
VSIOCS0
Output
VSIO chip select pin
VSIOCS1
Output
VSIO chip select pin
SDA0
I/O
I2C bus mode data input/output pin
SCL0
I/O
I2C bus mode clock input/output pin
12-bit Analog-to-Digital Converter
AINAx
AINBx
Input
Analog input pin
16-bit 
Analog-to-Digital Converter
AINCxP
AINCxN
Input
Analog input pin
10-bit Digital -to-Analog Converter
DAOUTx
Output
Analog output pin
MOx _ OUT
Output
Step monitor output pin
MOx _ IN
Input
Step monitor input pin
CIN
DIN
EIN
FIN
Input
H-Bridge (ch.x) drive pulse input pin
High Resolution 16-bit Timer /
PPG Outputs
Function
Output pin for system clock (For MCD block)
External interrupt input pin x
External interrupt input pin has a noise filter (filter width: 30ns typ.).
2-phase pulse input counter
Data output pin
Data input pin
SIO/UART
Data output pin
UART
VSIO
VSIO clock pin
I2C/SIO
H Bridge circuit
2014/7/22
Page 36
1.7 Pin Names and Functions
1.7.1.2
TMPM340 Group
Product Introduction Guide
Debug pin Name
Table 1-10 Debug pin names and functions
1.7.1.3
Debug pin
names
Input
or
Output
SWDIO
I/O
SWCLK
Input
SWV
Output
Serial wire viewer output pin
TRACECLK
Output
Trace clock output pin
TRACEDATA0
Output
Trace data output pin 0
TRACEDATA1
Output
Trace data output pin 1
Functions
Serial wire data input/output pin
Serial wire clock input pin
Control Pin Name
Table 1-11 Control pin names and functions
Control pin
names
Input
or
Output
MODE
Input
Mode pin
Must be fixed to "Low" level.
RESET
Input
Reset signal input pin
Input
BOOT mode control pin
BOOT mode control pin is sampled on the rising edge of reset signal
input.
If BOOT mode control pin is "Low", MCU becomes the single boot mod;
if it is "High", the MCU enters the single chip mode.
BOOT
1.7.1.4
Functions
Clock pin Name
Table 1-12 Clock pin names and functions
Clock pin
names
Input
or
Output
X1
Input
High-speed oscillation connection pin
X2
Output
High-speed oscillation connection pin
Functions
Page 37
2014/7/22
1.7 Pin Names and Functions
1.7.1.5
Test pin Name
Table 1-13 Test pin names and functions
1.7.1.6
Test pin names
Input
or
Output
FTEST3
Input
Functions
TEST Input
Must be opened.
Pin name for MCD Block
Table 1-14 MCD Block pin name and function
2014/7/22
pin names
Input
or
Output
AO1, AO2
BO1, BO2
CO1, CO2
DO1, DO2
EO1, EO2
FO1, FO2
GO1, GO2
GO3
Output
H-Bridge output pin
OPxPIN
Input
OpAMPx + input pin
OPxNIN
Input
OpAMPx - input pin
OPxOUT
Output
OpAMPx output pin
DAOUTA
DAOUTB
Output
Analog output pin
PICPINx
Input
Encoder input pin
HBxF
Output
Hall bias Force output pin
HBxS
Input
Hall bias Sense input pin
PIDBx
Input
Photo diode bias output pin
Functions
Page 38
TMPM340 Group
Product Introduction Guide
1.7 Pin Names and Functions
1.7.1.7
TMPM340 Group
Product Introduction Guide
Power Supply Pin Name
Table 1-15 Power supply pin names and functions
Power supply pin
names
Functions
MCU Block
RVDD3
DVSS_C
DVDD3_A
DVDD3_B
DVSS
ADAVREFH
ADBVREFH
ADCVDD3
Power supply pin for regulators
RVDD3 supplies power to the following pins:
X1, X2
GND pin for regulators and oscillator
Power supply pin for digital
DVDD3_A and DVDD3__B supplies power to the following pins:
RESET, MODE, FTEST3
PA, PB, PC, PD, PE, PH
GND pin for digital
Reference power voltage pins for ADC Unit A
Reference power voltage pins for ADC Unit B
ADAVDD3 supplies power to the following pins:
PJ
Power supply pin for ADC
ADAVDD3
DAVDD3
Reference power voltage pins for ADC Unit A
ADAVDD3 supplies power to the following pins:
PF
Power supply pin for DAC
DAVDD3 supplies power to the following pins:
DA0, DA1
Page 39
2014/7/22
1.7 Pin Names and Functions
Table 1-15 Power supply pin names and functions
Power supply pin
names
ADBVDD3
Functions
Power supply pin for ADC Unit B
ADBVDD3 supplies power to the following pins:
PG
ADAVSS
GND pin for ADC Unit A
ADBVSS
ADCVSS
GND pin for ADC Unit B
DAVSS
DAVREFH
GND pin for ADC
GND pin for DAC
Reference power voltage pins for DAC
ADCVREFH
OUT
ADCVREFH output pin for  ADC
ADCVREFL
OUT
ADCVREFL output pin for  ADC
ADCVREF02
OUT
Reference power voltage output pin for  ADC
MCD Block
VM1
Power supply pin for MCD ch. A,B
AO1, AO2, BO1, BO2
VM2
Power supply pin for MCD ch. C,D,E,F
CO1, CO2, DO1, DO2, EO1, EO2, FO1, FO2
VM3
Power supply pin for ch. G
GO1, GO2, GO3
PGND1
GND pin for MCD (ch. A,B)
PGND2
GND pin for MCD (ch. C,D,E,F)
PGND3
GND pin for MCD (ch. G)
RNF3
AVDD3_C
AVSS_C
2014/7/22
Motor ch.G output current detection resistor connect pin
Power supply pin for MCD (Analog)
GND pin for MCD (Analog)
V30IN
Reference power pins for MCD (Analog)
(Reference power pins for 8-bit DAC for Hall Bias and
10-bit DAC for EVR)
EFUSE
Power supply pin for eFuse
(Note) Must be connected to AVDD3_C.
Page 40
TMPM340 Group
Product Introduction Guide
1.7 Pin Names and Functions
1.7.2
TMPM340 Group
Product Introduction Guide
Pin Name and Function
1.7.2.1
Conventions Used in the Table
Various conventional symbols are used in the following tables.
1. Functions A
Dual functions in which the pins are assigned to ports without the function register settings
are described.
2. Functions B
Dual functions in which the pins are assigned to ports by the register settings are described.
The numbers shown in the "Function B" Column correspond to the numbers of function registers.
3. Pin specifications
The symbols below have the following meanings:
• SMT/CMOS : Input gate
SMT : Schmitt trigger input
CMOS : CMOS input
• 5V_T: 5V tolerant (Only when the pin is used as an input pin.)
Yes : Support
N/A : Not available
• OD : Programmable open drain output
Yes : Support
N/A : Not available
• PU/PD : Programmable pull-up/pull-down
PU : Programmable pull-up is selectable.
PD : Programmable pull-down is selectable.
N/A : Not available
Page 41
2014/7/22
1.7 Pin Names and Functions
1.7.2.2
TMPM340 Group
Product Introduction Guide
PORT Pins and Shared Pins
Table 1-16 Pin numbers and pin names <PORT order> (1/4)
PinNo.
VFBGA
142
Functions B
PORT
Functions
A
1
2
3
4
Port specification
5
PU/
PD
OD
5V_T
SMT/
CMOS
PORT A
N8
PA0
TDA0
OUT0
TB4
OUT
PU
yes
N/A
SMT
N9
PA1
TDA0
OUT1
TB5
OUT
PU
yes
N/A
SMT
M9
PA2
TDA1
OUT0
TB6
OUT
PU
yes
N/A
SMT
M10
PA3
TDA1
OUT1
TB7
OUT
PU
yes
N/A
SMT
L9
PA4
TDB0
OUT0
CIN
PU
yes
N/A
SMT
L10
PA5
TDB0
OUT1
DIN
PU
yes
N/A
SMT
K9
PA6
TDB1
OUT0
EIN
PU
yes
N/A
SMT
K10
PA7
TDB1
OUT1
FIN
PU
yes
N/A
SMT
PU
yes
yes
SMT
PU
yes
yes
SMT
PU
yes
yes
SMT
PORT B
D12
PB0
TXD0
D11
PB1
RXD0
MO1_
OUT
E11
PB2
SCLK0
MO2_
OUT
F11
PB3
INT3
PU
yes
yes
SMT
G10
PB4
SCL0
PU
yes
yes
SMT
H10
PB5
SDA0
PU
yes
yes
SMT
H11
PB6
INT4
PU
yes
yes
SMT
J10
PB7
INT5
PU
yes
yes
SMT
L2
PC0
TXD1
U0TXD
PU
yes
yes
SMT
M4
PC1
RXD1
U0RXD
PU
N/A
yes
SMT
L3
PC2
SCLK1
U0CTS
PU
yes
yes
SMT
L4
PC3
INT5
U0RTS
PU
yes
yes
SMT
K6
PC4
PHC0
IN0
PU
yes
yes
SMT
CTS0
PORT C
2014/7/22
CTS1
Page 42
1.7 Pin Names and Functions
TMPM340 Group
Product Introduction Guide
Table 1-16 Pin numbers and pin names <PORT order> (2/4)
PinNo.
VFBGA
142
Functions B
PORT
Functions
A
1
2
3
4
Port specification
5
PU/
PD
OD
5V_T
SMT/
CMOS
L6
PC5
PHC0
IN1
PU
yes
yes
SMT
K5
PC6
PHC1
IN0
PU
yes
yes
SMT
L5
PC7
PHC1
IN1
PU
yes
yes
SMT
PORT D
L1
PD0
TXD2
VSIO
TXD
PU
yes
yes
SMT
M3
PD1
RXD2
VSIO
RXD
PU
yes
yes
SMT
K3
PD2
SCLK2
VSIO
SCK
PU
yes
yes
SMT
K4
PD3
INT7
VSIO
CS0
PU
yes
yes
SMT
K2
PD4
SP0DO
TB1
OUT
PU
yes
yes
SMT
M2
PD5
SP0DI
ITB2
OUT
PU
yes
yes
CMOS
M1
PD6
SP0
CLK
TB3
OUT
PU
yes
yes
SMT
J1
PD7
SP0
FSS
VSIO
CS1
PU
yes
yes
SMT
F4
PE0
INT0
PU
Yes
N/A
SMT
G4
PE1
INT1
PU
Yes
N/A
SMT
H4
PE2
INT2
TB8
OUT
PU
Yes
N/A
SMT
H3
PE3
TB9
OUT
PU
Yes
N/A
SMT
J3
PE4
TB0
OUT
PU
Yes
N/A
SMT
CTS2
PORT E
PORT F
C6
PF0
AINA0
PU
N/A
N/A
SMT
B5
PF1
AINA1
PU
N/A
N/A
SMT
C5
PF2
AINA2
PU
N/A
N/A
SMT
B4
PF3
AINA3
PU
N/A
N/A
SMT
C4
PF4
AINA4
PU
N/A
N/A
SMT
B3
PF5
AINA5
PU
N/A
N/A
SMT
C3
PF6
AINA6
PU
N/A
N/A
SMT
B2
PF7
AINA7
PU
N/A
N/A
SMT
Page 43
2014/7/22
1.7 Pin Names and Functions
TMPM340 Group
Product Introduction Guide
Table 1-16 Pin numbers and pin names <PORT order> (3/4)
PinNo.
VFBGA
142
Functions B
PORT
Functions
A
1
2
3
4
Port specification
5
PU/
PD
OD
5V_T
SMT/
CMOS
PORT G
D6
PG0
AINB0
PU
N/A
N/A
SMT
D5
PG1
AINB1
PU
N/A
N/A
SMT
D4
PG2
AINB2
PD
N/A
N/A
SMT
D3
PG3
AINB3
PU
N/A
N/A
SMT
PORT H
A13
PH0
SW
DIO
PU
N/A
N/A
SMT
N1
PH1
SW
CLK
PD
N/A
N/A
SMT
L11
PH2
TRACE
CLK
PU
N/A
N/A
SMT
K11
PH3
TRACE
DATA0/
SWV
PU
N/A
N/A
SMT
J11
PH4
TRACE
DATA1
PU
N/A
N/A
SMT
G11
PH5
BOOT
PU
N/A
N/A
SMT
C1
PJ0
AINC2P
PU
N/A
N/A
SMT
D1
PJ1
AINC2N
PU
N/A
N/A
SMT
E1
PJ2
AINC3P
PU
N/A
N/A
SMT
F1
PJ3
AINC3N
PU
N/A
N/A
SMT
C2
PJ4
AINC4P
PU
N/A
N/A
SMT
D2
PJ5
AINC4N
PU
N/A
N/A
SMT
E2
PJ6
AINC5P
PU
N/A
N/A
SMT
F2
PJ7
AINC5N
PU
N/A
N/A
SMT
PORT J
PORT K (Note) Port K internally connected with the MCD.
2014/7/22
PK0
TDA0
OUT0
TB4
OUT
CIN_
OUT
N/A
N/A
N/A
N/A
PK1
TDA0
OUT1
TB5
OUT
DIN_
OUT
N/A
N/A
N/A
N/A
PK2
TDA1
OUT0
TB6
OUT
EIN_
OUT
N/A
N/A
N/A
N/A
PK3
TDA1
OUT1
TB7
OUT
FIN_
OUT
N/A
N/A
N/A
N/A
PK4
TDB0
OUT0
N/A
N/A
N/A
N/A
PK5
TDB0
OUT1
N/A
N/A
N/A
N/A
Page 44
1.7 Pin Names and Functions
TMPM340 Group
Product Introduction Guide
Table 1-16 Pin numbers and pin names <PORT order> (4/4)
PinNo.
VFBGA
142
Functions B
PORT
Functions
A
1
PK6
TDB1
OUT0
PK7
TDB1
OUT1
2
3
4
TB9
OUT
Port specification
5
PU/
PD
OD
5V_T
SMT/
CMOS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PORT L (Note) Port L internally connected with the MCD.
PL0
TXD3
_OUT
N/A
N/A
N/A
N/A
PL1
SCLK3
_OUT
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PL4
N/A
N/A
N/A
N/A
PL5
N/A
N/A
N/A
N/A
PL6
N/A
N/A
N/A
N/A
PL2
PL3
SCOUT
PORT M (Note) Port M internally connected with the MCD.
PM0
INT8
MO1
_IN
PU
Yes
N/A
N/A
PM2
INT9
MO2
_IN
PU
Yes
N/A
N/A
Page 45
2014/7/22
1.7 Pin Names and Functions
1.7.2.3
Dedicated Pins
(1)
Control Pins
Table 1-17 Pin numbers and Pin names
Pin No.
Control pin names
VFBGA142
(2)
A1
MODE
E3
RESET
Clock Pins
Table 1-18 Pin numbers and Pin names
Pin No.
Clock pin names
VFBGA142
(3)
N4
X1
N2
X2
Test Pins
Table 1-19 Pin numbers and Pin names
Pin No.
Test pin names
VFBGA142
N13
(4)
FTEST3
Analog Output Pins
Table 1-20 Pin numbers and Pin names
Pin No.
Analog output pin names
VFBGA142
2014/7/22
D9
DAOUTA
D8
DAOUTB
Page 46
TMPM340 Group
Product Introduction Guide
1.7 Pin Names and Functions
(5)
TMPM340 Group
Product Introduction Guide
Pins for MCD Block
Table 1-21 Pin numbers and Pin names
Pin No.
MCD Block pin names
VFBGA142
N12
AO1
M12
AO2
N11
BO1
M11
BO2
E13
CO1
E12
CO2
F13
DO1
F12
DO2
G12
EO1
H12
EO2
H13
FO1
J13
FO2
J12
GO1
K12
GO2
L12
GO3
A8
OP0NIN
B8
OP0PIN
C8
OP0OUT
A9
OP1NIN
B9
OP1PIN
C9
OP1OUT
A11
OP2NIN
B11
OP2PIN
C11
OP2OUT
A12
OP3NIN
B12
OP3PIN
C12
OP3OUT
Page 47
2014/7/22
1.7 Pin Names and Functions
Table 1-21 Pin numbers and Pin names
Pin No.
MCD Block pin names
VFBGA142
2014/7/22
A7
OP4NIN
B7
OP4PIN
C7
OP4OUT
A10
OP5NIN
B10
OP5PIN
C10
OP5OUT
L8
PICPIN0
K8
PICPIN1
M7
PIDBA
M8
PIDBB
K7
PIDBB
L7
PIDBB
K7
ENCOUT0
L7
ENCOUT1
B13
HB0F
E10
HB0S
C13
HB1F
F10
HB1S
D7
EVR0
D10
EVR1
Page 48
TMPM340 Group
Product Introduction Guide
1.7 Pin Names and Functions
1.7.2.4
TMPM340 Group
Product Introduction Guide
Power Supply Pins
Table 1-22 Pin numbers and Pin names
Pin No.
Power supply pin names
VFBGA142
MCU Block
A6
DVDD3_A
M6
DVDD_3B
J2
DVDD_A
M5
DVDD_B
N7
RVDD3
N3
DVSS_C
A4
ADAVREFH
J1
ADBVREFH,
ADCVDD3
B6
ADAVDD3,
DAVDD3
A3
ADBVDD3
B1
ADAVSS
H1
ADBVSS,
ADCVSS
A2
DAVSS
A5
DAVREFH
G2
ADCVREFHOUT
H2
ADCVREFLOUT
G1
ADCVREF02OUT
N10
VM1
D13
VM2
K13
VM3
M13
PGND1
G13
PGND2
L13
RNF3
N6
AVDD3_C
N5
AVCC_C
K1
V30IN
G3
EFUSE
MCD Block
Page 49
2014/7/22
1.8 Port Equivalent Circuit Schematic
TMPM340 Group
Product Introduction Guide
1.8 Port Equivalent Circuit Schematic
The port equivalent circuit schematic is basically drawn by using the same gate symbols as those of the Standard
CMOS logic 74HCxx series.
The input protection resistance ranges from several tens to several hundreds of . The X2 damping resistance values shown in the following figures are typical values.
Note: Resistors without values in the following figures indicate input protection resistors.
1.8.1
Ports
PORT
Port Equivalent Circuit
Output data
P-ch
Open-drain enable
N-ch
Output enable
PA0 to 7, PC4 to 7
PD0 to 4, PD6 to7
PE0 to 4
PH0, PH2 to 4
DVDD3_A/DVDD3_B
Schmitt trigger
I/O port
Input data
Input enable
Pull-up enable
Programmable pull-up resistor
DVDD3_B
Output data
P-ch
Open-drain enable
N-ch
Output enable
PB0 to 7
PC0 to 3
Schmitt trigger
I/O port
5V tolerant inputport
Input enable
Input enable
Pull-up enable
Programmable pull-up resister
2014/7/22
Page 50
1.8 Port Equivalent Circuit Schematic
PORT
TMPM340 Group
Product Introduction Guide
Port Equivalent Circuit
Output data
P-ch
Open-drain enable
N-ch
Output enable
DVDD3_A
Schmitt trigger
PH1
I/O port
Input data
Input enable
Pull-down enable
Programmable pull-down resister
Output data
P-ch
Open-drain enable
N-ch
Output enable
PD5
DVDD3_B
I/O port
Input edata
Input enable
Pull-up enable
Programmable pull-up resister
Analog input
DVDD3_A/DVDD3_B
Schmitt trigger
I/O port
Input data
PF0 to 7
PG0 to 3
PJ0 to 7
Input enable
Pull-up enable
Programmable pull-up resister
Page 51
2014/7/22
1.8 Port Equivalent Circuit Schematic
PORT
TMPM340 Group
Product Introduction Guide
Port Equivalent Circuit
Output data
P-ch
Open-drain enable
N-ch
Output enable
PH5 / BOOT
DVDD3_B
I/O port
Input edata
Input enable
Pull-up enable
Programmable pull-up resister
'9''B$
DAOUTA, DAOUTB
2014/7/22
DA0
DA1
2XWSXW3257
Page 52
1.8 Port Equivalent Circuit Schematic
1.8.2
TMPM340 Group
Product Introduction Guide
Analog Power Supply Pins
PORT
Port Equivalent Circuit
ADAVDD3/ADBVDD3
ADC
ADAVREFH/ADBVREFH
ADAVSS/ADBVSS
ADAVREFH, ADBVREFL
Ladder
resistor
ADAVDD3/ADBVDD3
ADAVSS/ADBVSS
ADAVSS/ADBVSS
Page 53
2014/7/22
1.8 Port Equivalent Circuit Schematic
1.8.3
TMPM340 Group
Product Introduction Guide
Control Pins
PORT
Port Equivalent Circuit
DVDD3_A
MODE
(MCU)
Input pin
Schmitt trigger
Pull-down resister
MODE
DVDD3_A
500Ω (typ.)
MODE
(MCD)
(note) This pin must be connected to GND.
DVDD3_A
Pull up resister
RESET
Reset
Input pin
Schmitt trigger
1.8.4
Clocks
PORT
Port Equivalent Circuit
fosc
DVDD3_A
Oscillator circuit
500kΩ
(typ.)
X1
X2
High-speed
oscillator enable
X2
1kΩ (typ.)
DVDD3_A
X1
1.8.5
Test Pins
PORT
FTEST3
Port Equivalent Circuit
FTEST3
Open
(note) This pin must be opened
2014/7/22
Page 54
1.8 Port Equivalent Circuit Schematic
1.8.6
TMPM340 Group
Product Introduction Guide
Pins for MCD Block
PORT
Port Equivalent Circuit
VM1
VM1
AO1
BO1
3FK
AO1, AO2
BO1, BO2
AO2
BO2
3FK
1FK
1FK
PGND1
PGND1
VM2
CO1, CO2
DO1, DO2
EO1, EO2
FO1, FO2
CO1
DO1
EO1
FO1
3FK
VM2
CO2
DO2
EO2
FO2
3FK
1FK
1FK
PGND2
PGND2
VM3
VM3
2EJ
GO1, GO2, GO3
GO1
0EJ
GO2
GO3
2EJ
0EJ
RNF3
2EJ
0EJ
RNF3
Page 55
VM3
RNF3
2014/7/22
1.8 Port Equivalent Circuit Schematic
PORT
TMPM340 Group
Product Introduction Guide
Port Equivalent Circuit
AVDD3_C
100Ω (typ.)
OPxPIN
OP0NIN, OP1NIN
OP2NIN, OP3NIN
OP4NIN, OP4PIN
OP0PIN, OP1PIN
OP2PIN, OP3PIN
OP4PIN, OP5PIN
㸩
AVSS_C
࣮
AVDD3_C
100Ω (typ.)
OPxNIN
AVSS_C
AVDD3_C
OP0OUT
OP1OUT
OP2OUT
OP3OUT
OP4OUT
OP5OUT
20Ω (typ.)
㸩
Output
࣮
AVSS_C
AVDD3_C
8-bit DAC
20Ω (typ.)
㸩
Output pin
࣮
AVSS_C
HB0F, HB1F
HB0S, HB1S
AVDD3_C
100Ω (typ.)
Input pin
AVSS_C
Analog switch
AVDD3_C
Buffer
EVR0 to EVR1
100Ω (typ.)
EVR0
EVR1
Output pin
AVSS_C
Output enable
AVDD3_C
20Ω (typ.)
㸩
Input
PICP0 to PICP1
࣮
AVSS_C
4-bit DAC
2014/7/22
Page 56
1.8 Port Equivalent Circuit Schematic
PORT
TMPM340 Group
Product Introduction Guide
Port Equivalent Circuit
AVDD3_C
Output
PiDB0, PIDB1, PIDB2
Output enable
AVSS_C
DVDD3_A
Ω
(typ.)
Output PIN
ENCOUT0, ENCOUT1
DVSS_A
AVDD3_C
Input
V30IN
DAC
AVSS_C
Page 57
2014/7/22
1.9 Revision History
TMPM340 Group
Product Introduction Guide
1.9 Revision History
Revision
2014/7/22
Date
Note
Rev1.0
2014/ 7/ 2
First Release
Rev1.1
2014/ 7/22
Contents Revised
Page 58
TMPM340 Group
Product Introduction Guide
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the
information in this document, and related hardware, software and systems (collectively "Product") without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even
with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers
are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss
of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product,
create designs including the Product, or incorporate the Product into their own applications, customers must also refer to
and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the
specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the
"TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be
used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but
not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating
and determining the applicability of any information contained in this document, or in charts, diagrams, programs,
algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for
such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF
WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS
PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document,
Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA
ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA
for any infringement of patents or any other intellectual property rights of third parties that may result from the use of
Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or
otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS
OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO
LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR
INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF
OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS
OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION,
INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including
without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological
weapons or missile technology products (mass destruction weapons). Product and related software and technology may be
controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange
and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software
or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility
of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of
controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR
DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND
REGULATIONS.
Page 59
2014/7/22
TMPM340 Group
Product Introduction Guide
2014/7/22
Page 60