designfeature
Johan Strydom, Phd.
Vice President, Applications Engineering, Efficient Power Conversion Corp.
The eGaN FET-Silicon Power
Shoot-Out: 2: Drivers, Layout
TM
the first article of this
series (power electronics
technology, september 2010)
{1} , comparaed enhancement-mode Gallium nitride
(eGan™) power devices
with state-of-the-art silicon
MosFets, using different
yardsticks that significantly
influence in-circuit performance. eGan Fets differ from
their silicon counterparts
because of their significantly
faster switching speeds, so
we must explore the different
requirements for gate drive,
layout, and thermal management.
T
o determine the gate drive circuit requirements, and how they differ
from traditional silicon MOSFET drivers, it is necessary to compare
silicon against eGaN FET device parameters (Table 1). When considering gate drive requirements the three most important parameters for
eGaN FETs are:
(1) Maximum allowable gate voltage
(2) Gate threshold voltage
(3) “Body diode” voltage drop.
The maximum allowable gate-source voltage of 6 V{2} is low compared with
traditional silicon. Second, the gate threshold is also low compared to most power
MOSFETs, but does not suffer from as strong a negative temperature coefficient.
Third, the “body diode” forward drop can be a volt higher than comparable silicon
MOSFETs.
Gate pull-down resistance
A great advantage offered by eGaN FETs is the possible switching speed. However,
the higher di/dt and dV/dt that accompany this new capability not only require a
layout with less parasitic capacitance, resistance, and inductance, but also cause some
new considerations for the gate driver. Let’s consider a half- bridge with a high dV/
dt turn-on of a complementary device as shown in Fig. 1. The ‘Miller’ charge current
flows from the drain (switching node) through CGD and CGS to the source as well as
through CGD to RG (internal gate resistance) and RSink (gate driver sink resistance)
to the source. The requirement for avoiding dV/dt (Miller) turn-on of this device is
given by:
ª
(1)
Where:
α = Passive network time constant (RG + RSink) x (CGD
eGan Power Device
+ CGS)
dt = dV/dt switching time
CGD
Thus, to avoid Miller turn-on of an eGaN FET, it is necesGate Drive
sary to limit the total resistance path (internal gate resistance
CDS
RG and external gate drive sink resistance RSink) between the
RG
device
gate and its source. One can argue that, for devices
CGS
Keep
RSINK
VNODE < VTH
with good Miller ratios (QGD/QGS(VTH) < 1), this is not
required. Practically, since QGD increases with VD, this ratio
will slowly worsen with increasing switching voltage and
canít solely be relied on to prevent Miller turn-on.
High dV/dt current paths
By the same token, Equation (1) does not need to be
Fig. 1. effect of dV/dt on “off” device and requirements for avoiding adhered to at very low bus voltages where QGD/QGS(VTH) is
Miller turn-on that causes shoot-through.
still much less than one. To be safe, a gate drive pull-down
High dV/dt event
14
Power Electronics Technology | January 2011
www.powerelectronics.com
eGaN FETdrive
circuits
dead-time management that minimizes the “body diode”
conduction interval.
Bootstrip or ‘matching’ low-side diode
Silicon gate drivers and controllers tend to have an effecD1
tive
minimum dead-time around 20 ns (±10 ns) for low
~5.0 V
voltages,
and it increases with bus voltage to around 400 ns
Adjustable
M3
M4
pull-up
(±100
ns)
for 600 V drivers. With eGaN FETs, both the gate
C1
D
capacitance and Miller capacitance are significantly lower
Logic
R2
R1
U1
than equivalent silicon devices, leading to smaller turn-on
input
G
EPC GaN
M2
and turn-off delays as well as shorter switching times. These
shorter and less variable switching times allow for much
M1
S
Minimize loop
tighter dead-time control which, in turn, would be beneficial in reducing “body diode” conduction loss. A reduction
of dead-time between half and one-fourth the above values,
with a similar reduction in the variation, would be preferred.
Fig. 2. Discrete eGaN FET gate-driver solution showing method for
In the interim, it would be beneficial for an eGaN FET gate
complementary high-side and low-side supply voltage matching.
driver to have dead-time adjustment. This
can be done simply by either lengthening
resistance of 0.5 Ω or less is recommended
the pulse by delaying turn-off, or shortenfor higher voltage devices.
ing the pulse through delaying the turnon, depending on the gate drive source.
GATE PULL-UP RESISTANCE
Pin 7
Pin 6
Pin 1
Because the total Miller charge (QGD) is
much lower for an eGaN FET than for
GATE DRIVE SUPPLY REGULATION
Pin 5
Pin 2
a similar on-resistance power MOSFET,
The current maximum gate voltage limiit is possible to turn on the device much
tation of 6 V on the eGaN FET does
faster. As stated above, too high of a dV/dt
add restrictions to the gate drive supply
Pin 4
Pin 3
can actually reduce efficiency by creating
range, and requires at least some form of
shoot-through during the “hard” switching
supply regulation. Of greatest concern is
transition. It would therefore be advisable
the floating or high-side supply in a halfto have the ability to adjust the gate drive
bridge configuration. A simple implemenpull-up resistance to minimize transition Fig. 3. Partial schematic of a half bridge tation to improve matching between lowtime without inducing other unwanted converter showing controller, eGaN FET side (ground referenced) and high-side
loss mechanisms. This also allows adjust- driver and eGaN devices.
supplies is through the use of a “matching”
ment of the switch node voltage overshoot
Controller
and ringing for improved EMI. In power
MOSFET applications, this is achieved by
5V
placing a resistor and anti-parallel diode
VB
in series with the gate drive output. For
6
1
EPC
eGaN FETs, however, where the thresh2
H0
4
3
old voltage is low, this is not recomeGaN Driver
5
mended. The simplest general solution is
to split the gate pull-up and pull-down
SW
connections in driver and allow the inser7
To Load
tion of a discrete resistor as needed.
5V
The eGaN FET reverse bias or “body
VCC
diode” operation has the benefit of no
6
1
reverse-recovery losses. This advantage,
2
LO
however, can be offset by the higher
4
3
eGaN Driver
“body diode” forward voltage drop2. The
5
diode conduction losses can therefore be
significant, especially at low voltages and
GND
7
high frequencies. However, unlike diode
reverse recovery losses; these conduction
losses can be minimized through proper Fig. 4. eGaN FET friendly interface gate driver in 6-pin DFN package (bottom view).
5.6 V
www.powerelectronics.com
January 2011 | Power Electronics Technology
15
eGaN FETdrive
circuits
Table 1. Comparison beTween 100V si
mosFeTs and 100 V eGan™ FeTs
diode as shown for a discrete gate drive implementation in
Fig. 2.
FeT Type
TypiCal 100 V 100 V eGan™
This implementation is only suited for complementary
siliCon
switched,
half-bridge applications where the dead-time and
Maximum gate-source voltage
+/-20 V
+6 V /-5 V
“body diode” conduction is minimal. For applications where
Reverse ‘body diode’ voltage
~1 V
~1.5-2.5 V
the eGaN body diode conduction can be significantly longer
Gate threshold
2V–4V
0.7 V - 2.5 V
than the bootstrap diode turn-on time, the ~2 V “body
dV/dt capacitance (Miller) ratio
0.5-0.8
1.1
diode” voltage drop will add to the supply voltage and can
QGD(50 V)/QGS(VTH)
cause overvoltage of the high-side supply. In such cases,
Internal gate resistance
>1 Ω
<0.6 Ω
some form of post bootstrap supply regulation is required.
Change in RDS(ON) from 25°C to
>+70%
<+50%
Thus the limited overdrive headroom of eGaN FET does
125°C
increase the gate drive supply complexity when compared
Change in VTH from 25°C to 125°C
-33%
-3%
to silicon.
Gate to source leakage
few nA
few mA
Given the information on how the eGaN FET drive
Body diode reverse recovery charge
high
none
requirements differ from power MOSFETs, it is possible to
Avalanche capable
Yes
not rated
define an eGaN FET gate driver IC. At first, to leverage the
existing MOSFET controller and levelshifter infrastructure, a simple eGaN
D
eGan™ Power Device
FET driver interface IC is suggested.
This part is defined to interface between
Optional ‘bead’ to damp
HF LCR resonance
any controller and the eGaN FET as
CGD
shown in Fig. 3. The same part could
CDS
CSI induces
RG
Gate
G
also be used for synchronous rectificaopposing voltage
Drive
across gate
tion and single switch isolated topologies
CGS –
(such as flyback and forward). These
+
would also be suited for digital controlRSINK
lers where the gate drive function would
S
Negative freewheeling
normally be external to the controller
LCR Resonant tank
current decreasing at
complementary
anyway. The suggested device pin-out
CSI
device turn-on
and pin descriptions are given in Fig. 4
and Table 2, respectively.
Fig. 5. equivalent partial power circuit showing di/dt effect of “hard” turn-on of complemen- Layout considerations
tary device.
The maximum allowable gate voltage
of 6 V is only one volt above the recommended 5 V drive voltage. This
Table 2. suGGesTed eGan FeT Friendly
limited headroom requires an accurate
GaTe driVer iC pin desCripTions
gate drive supply, as well as a limited
pin
name
desCripTion
requiremenTs
inductance between the eGaN device
Input supply voltage
6-15 V operational
1
VCC
and gate driver as the inductance can
2
Input Logic input
Hysteretic input threshold,
cause a voltage overshoot on the gate.
possibly function of VCC
voltage
Although some overshoot is acceptable,
3
Delay Lengthens or shortens input pulse. Pull up resistor to Adjustable to +/- 100 ns
overshoot can be avoided entirely if the
5 V sets sink current to shorten pulse (leading edge). should be adequate.
gate inductance is limited to:
Alternatively, a pull-down resistor sets source current
to lengthen trailing edge
16
(2)
4
OL
Gate drive pull-down. Connects directly to eGaN
FET gate
MOSFET pull-down with
~0.5 Ω RDS(ON) @ 5 V)
5
OH
Gate drive pull-up Resistor between OH and OL sets
pull-up speed.
Can be combined with pin 4 for some applications.
MOSFET pull-up with ~2 Ω
RDS(ON)@ 5 V)
6
5V
Regulated output for gate drive. LDO from VCC pin.
Can tie VCC to 5 V if external 5 V supply is available.
Generate regulated 5 V
output for pull up
7
GND
Ground reference and gate drive return
Exposed pad for improved
thermal performance
Power Electronics Technology | January 2011
Where:
RSource = Source resistance on the
gate driver
LG = Loop inductance between the
gate driver and eGaN device
Thus, for a given gate loop inductance there will be a minimum source
www.powerelectronics.com
eGaN FETdrive
circuits
Complementary device VGS
VGS
resistance value to keep VGS from exceeding its maximum
limit.
With the EPC devices being chipscale packages with
negligible package inductance, the question of common
source inductance could be considered a layout issue rather
than a gate driver requirement. These aspects, however, are
much more intertwined to draw such a sharp distinction.
The addition of CSI (common source inductance) effectively reduces efficiency by inducing a voltage across the
CSI during di/dt that opposes the gate drive voltage, thus
increasing turn-on and turn-off times. It is therefore critical to minimize common source inductance for optimum
switching performance. In what seems to be at first glance
contradictory, the increase of CSI will decrease the possibility of Miller turn-on{3} if one accepts the cost of increased
switching loss that it entails. This is due to the fact that at
the “hard” turn-on of the complementary device, the current commutation di/dt across the CSI induces a negative
voltage across the gate to help keep the device off during
part of the voltage transition. What is not stated is that the
CSI, gate capacitance, and gate drive pull down loop now
forms an LCR resonant tank that needs to be damped to
VTH
0
Gate voltage negative first,
but rings positive later
Increased CSI
Capacitive
charging current
Ringing crosses VTH
Cross
conduction
current
0
IS
Deadtime
‘body diode’
conduction
VDS
0
Increasing
switching time
and
voltage ‘knee’
Fig. 6. Conceptual waveforms for circuit in Figure 2 during “hard”
turn-on of complementary device showing effect of CSI ringing.
avoid an equivalent positive voltage ringing across the gate.
This ringing could turn the device on again near the end,
or even past the end of the voltage transition. Although
increasing the gate drive sink resistance can help damp this
/2
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January 2011 | Power Electronics Technology
17
eGaN FETdrive
circuits
LCR resonance at the cost of increased Miller turn-on sensitivity, the addition of a ferrite bead that is resistive (lossy)
at the resonant frequency can achieve the same result with
less increase in Miller turn-on sensitivity. Please refer to
Fig. 5 for the equivalent circuit and Fig. 6 for conceptual
switching waveforms. This effect may sometimes be hard
to distinguish from dV/dt induced Miller turn-on. In short,
CSI is much more important to eGaN FETs than silicon,
VBUS
Gate Drive TG
As Close
As Possible
SW
Gate Drive BG
As Close
As Possible
GND
Top Layer
Layer 2
VBUS
SW
HF Bus
Capacitor
GND
Layer 3
Bottom Layer
Fig. 7. Suggested simple half bridge layout using 4-layer PCB.
Gate Drive TG
As Close
As Possible SW
Gate Drive BG
As Close
As Possible
VBUS
SW
SuggeSted LayoutS
Given the different considerations listed above, it is possible to develop some recommended layouts. The layouts
presented depict a half-bridge configuration, but following
the above requirements can be expanded for other applications as well.
Simple, as well as complex four layer
VBUS
PCBs are presented in Figs. 7 and 8,
respectively. It should be noted that the
copper thickness needs to be maximized
to limit resistive losses and improve therSW
mal spreading (2 oz copper on outer
layers is recommended). In both of these
layout examples, the source connection
of each part is brought underneath it to
GND
act as shield and minimize additional parasitic CGD. In the simpler layout (Fig. 7)
VBUS
the gate return connection is made on the
smaller source pad to separate gate return
current and device drain current paths in
the source , thus minimizing CSI.
SW
In the more complex design in Fig.
HF Bus
8., this is taken further by connecting
Capacitor
every source connection through Layer
GND
Two to the shield that now doubles as
the gate drive return path. Drain connections are brought out similarly on the
third layer. The trade-off here is that to
achieve a much lower CSI and overall
loop / layout inductance, the geometry
requires increased parasitic capacitance
VBUS
- in particular CDS (output capacitance)
- as there is still the need to minimize the
parasitic gate to drain capacitance.
thermaL ConSiderationS
HF Bus
Cap
GND
Top Layer
GND
Layer 2
VBUS
VBUS
HF Bus
Cap
SW
GND
GND
Layer 3
Bottom Layer
Fig. 8. example of a more complex half bridge layout using 4-layer PCB.
18
due to the higher di/dt and dV/dt and should be minimized
as much as possible through careful layout.
Power Electronics Technology | January 2011
Due to the fundamentally lower eGaN
on-resistance{4}, these devices are only
a fraction of the size of an equivalent
on-resistance power MOSFET die, and
therefore have a much higher equivalent thermal resistance. However, eGaN
FETs also have a much lower FOM1
and will therefore have offsetting lower
switching power losses.
Can this improvement in power
loss make up for the higher thermal
resistance?
In order to answer this question we
need to look at two common scenarios;
www.powerelectronics.com
eGaN FETdrive
circuits
40oC/W in still air {5,7}. This performance can be improved
significantly with increased airflow.
Pneumatic Plunger
30 PSI
Force
10 Ohm
resistor
“T” Type Thermocouple
#32 gauge
Drain Lead
(Kelvin)
Source Lead
(Kelvin)
Gate
Lead
QFN
Shim Spacer
DUT
Water-Cooled Heatsink
RthJC Test Set-Up
Fig. 9. Test setup for measuring ePC egan FeT “best-case” thermal
resistance.
(1) devices mounted as “flip chips” on a printed circuit
board without additional heatsinking, and (2) devices
mounted with dual-sided cooling.
Because eGaN FETs are constructed on a very thin layer
of heterojunction material on top of a standard silicon wafer
{4}, devices mounted directly onto PCBs without any backside cooling behave thermally like any similarly mounted
silicon device. The variables needed to completely understand the resulting thermal performance are, (1) PCB copper area, (2) Copper thickness, (3) PCB material, and (4)
airflow over the device.
Reference[6] tests several industry standard packages
mounted directly onto FR-4 PCB material. Measurements
were made on one square inch, 2-ounce Cu, and on devices
with only enough Cu to make electrical contact to the leads.
This methodology separated the effect of device footprint
from the cooling that comes from the copper on the PCB.
Relatively little impact was seen when different packages
were mounted on one square inch Cu (the minimum RTHJA
was 18oC/W for a D2PAK and the maximum was 34oC/W
for an SO-8) because the dominant thermal resistance factor was the heat dissipating through the PCB. Consistent
with these tests, EPC estimates that RTHJA for eGaN FETs
mounted to one square inch of 2 ounce Cu should be about
Heat Sink
Thermal Pad
EPC GaN Die
Fig. 10. Dual die under one heat sink with thermal pad.
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Double-SiDeD Cooling:
In order to determine the best possible top-side cooling
for EPC’s eGaN FETs, the setup in Fig. 9 was constructed.
RDS(ON) was used as the temperature sensitive parameter
and the heatsink was water cooled for these “best-case” thermal measurements. Across the family of EPCís eGaN FETs,
the data suggests a 12-14oC-mm2 normalized RTHJA when
cooling is primarily through the silicon substrate beneath the
eGaN FET active area. Under these conditions, EPC’s large
area eGaN FETs have an RTHJC of about 2oC/W and the
small area FETs have an RTHJA of about 8oC/W.
Practical implementations of double-sided cooling are
certainly less elaborate than the one shown in Fig. 9, and
result in higher final thermal impedance. Fig. 10 illlustrates a
configuration where two devices are simultaneously cooled
by one heat sink. Here, multiple die is placed under the same
heatsink; however, care must be taken to avoid mechanical
damage from uneven pressure on die that might be slightly
tilted or at different heights off the PCB. Thermally conductive materials such as from 3M{8}, Dow Corning {9}, or
Bergquist {10} have been successfully used to double-side cool
multiple die under one heatsink.
To realize full advantage from EPC’s eGaN FETs,
designers must understand how to design cost-effective drive
circuitry that works on a cost-effective PCB. In this installment, we looked at gate drive requirements, layout, and
thermal design considerations designers must consider to
develop products that leverage eGaN FET advantages.
In our next chapter, we will demonstrate an eGaN FETbased Power Over Ethernet (POE) design that has greater
power density than similar circuits using state-of-the-art
power MOSFETs.
RefeRences:
[1]http://powerelectronics.com/power_semiconductors/power_mosfets/fomuseful-method-compare-201009/
[2]EPC datasheet of EPC1001. http://epc-co.com/epc/documents/datasheets/
EPC1001_datasheet_final.pdf
[3]Fairchild Semiconductor AN-7019, “Limiting Cross-Conduction Current in
Synchronous Buck Converter Designs”, http://www.fairchildsemi.com/an/AN/
AN-7019.pdf#page=1
[4]EPC article, “Fundamentals of Gallium Nitride Power Transistors”, http://
epc-co.com/epc/documents/product-training/Appnote_GaNfundamentals.pdf
[5] International Rectifier, whitepaper, “A New
Generation of Wafer Level Packaged HEXFET
Devices” http://www.irf.com/technical-info/whitepaper/pcimflipfet.pdf
[6] International Rectifier, http://www.irf.com/technical-info/whitepaper/thermalpcim02.pdf
[7] EPC article, “Using Enhancement Mode GaN-onSilicon Power Transistors” , http://epc-co.com/epc/
documents/product-training/Using_GaN_r4.pdf
[8] 3M pads http://solutions.3m.com/wps/portal/3M/
en_WW/electronics/home/productsandservices/
products/TapesAdhesives/ThermalInterface/
[9] Dow Corning Pads: http://www.dowcorning.
PCB
com/content/etronics/etronicspadsfilm/
[10] Bergquist Pads: http://www.bergquistcompany.
com/thermal_materials/gap_pad/pdfs/gap-pad-vosoft/PDS_GP_VOS_12.08_E.pdf
January 2011 | Power Electronics Technology
19