New Simulation Techniques for PWM Converters
Ray Ridley
Ridley Engineering
152 Jacarauda Drive
Battle Creek, MI 49017
Phone: (616) 962-1 181
Abstract
New simulation techniques are presented which take
advantage of the special structure of PWM converter power
stages and their compensation circuits. These techniques
provide reduction of system order, and allow for the fastest
possible simulation without any iterative algorithms. This is
achieved while retaining accurate large-signal simulation
with details of cycle-by-cycle waveforms.
The formulation of the simulation equations is simple
enough to be programmed into a spreadsheet format,
providing easy access and interface to the user. Even with
the computational overhead of the spreadsheet, simulation
speeds are orders of magnitude faster than any other
available large-signal simulation techniques.
The objective of this work was to provide a simulator that
would only take a few seconds to run several hundred cycles
of converter operation, even with modest computer
resources. Working designers could then use this type of
simulator as an integral part of their design cycle to predict,
with a minimum of effort, power stage waveforms and the
closed loop transient responses of the most commonly-used
converters.
1. Introduction
Electrical simulation can be a powerhl tool in the design
cycle of
switching power supplies.
However, the
peculiarities of operation of PWM converters present a
formidable task to most standard simulation packages. Most
designers realize that it is impossible to simulate a full
power supply schematic Problems arise in defining which
details of the circuit should be simulated, excessively long
simulation times, and numerical convergence. These
problems prevent most engineers from actively using
large-signal simulation during the design cycle.
2. Existing Simulation Techniques
2.1 Example Buck PWM Circuit
Fig. 1 shows an example buck converter, with a feedback
control loop for voltage-mode control. There are two active
devices in the power circuit, an ideal operational amplifier
in the analog feedback network, and a sawtooth ramp to
generate the duty cycle control
1
Much simulation work in the past has concentrated on
general-purpose solutions which can be applied to almost
any power electronics circuit. Sophisticated algorithms
have been developed to take advantage of the piecewise
linear nature of power conversion circuits. Although these
approaches provide considerable speed-up of the simulation
process, they still do not take full advantage of the special
structure of PWM converters.
I
In this paper, a new technique is applied to some specific
converters to be simulated. The new technique takes
advantage of the same assumptions of operation of PWM
converters used in small-signal modeling. In addition,
further simplifications are introduced for the control circuit
simulation, to provide the fastest possible speed. Using
these techniques, the computations are completely
non-iterative, and hence not subject to numerical
convergence problems.
Fig. I : Buck Converter with Voltage-Mode Controller
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0-7803-09820/93 $3.00 1993 IEEE
A constant-frequency clock turns on the power switch, and
the intersection of the PWM ramp with the error voltage
from the feedback amplifier turns the power switch off.
2.2 Device-Level Simulation
Even this simple circuit is very difficult for standard circuit
analysis programs such as PSpice to simulate with a closed
feedback loop due the nonlinear time-varying network, and
the large disparity of circuit time constants. Such PWM
circuits have a combinationof very fast events when devices
are switching, and slower events for input and load
transients. In order to accurately model the switching
transitions of devices such as MOSFETs, which can go
from Illy-off to Illy-on in a matter of nanoseconds, the
simulator must often use picosecond resolution. However,
in order to simulate a full transient event, such as a step load
or input line change, it is often necessary to run a simulation
for hundreds of milliseconds. Clearly, this combination of
needs makes a full simulation of a power converter with
detailed device models impractical.
Most designers recognize the need to break simulation tasks
into two or more steps [l]. The details of device switching
are often critical to reliability of the circuit and it is useful to
simulate a few cycles of switching operation under extreme
cases of current and voltage stress. In order to verify
switching losses and snubber designs, exact device models
with all circuit parasitics can be simulated adequately with
standard software packages such as PSpice [2] or Saber [3].
2.3 Ideal-Switch Simulation
Once switching stresses and times have been adequately
modeled, an important simplification can be applied to
speed up simulation. Accurate and complex device models
are replaced with ideal switches, usually in the form of a
controlled resistances, which transition from a very large
value to a small value when a device is turned on.
This switching transition can be assigned a finite slew rate,
to model the actual device switching time. Some programs,
such as PSpice, require a finite switching time in order to
properly converge. Unfortunately, thls slew rate must often
be considerably different from that encountered in the real
circuit in order to make the simulation run reliably.
Ideally, all of the transition details of switching can be
ignored, and the slew rate of the devices can be assume to
be instantaneous.
The fastest simulators assume an
instantaneous change of switch condition, and do not waste
any time on analyzing the switching events in any detail
[4-61. The effect of the switching time on the long-term
transient behavior is usually negligible, and can be safely
ignored. If the switching time is significant relative to the
switching period, the converter would, of course, be very
inefficient.
Special-purpose simulators [5-61 use state-variable analysis
to calculate time-domain simulations. The linear circuit
which exists in between switching instants can be simulated
very rapidly. For each switch condition in the circuit, the
state-space representation is formulated:
where x is an n-state vector, A is an nxn matrix, U is the
m-input vector, and B is an mxn matrix.
Standard circuit analysis algorithms can be used to derive
the differential equations corresponding to the circuit. For
the circuit of Fig. 1, the system with this representation is
5th order, with two states in the power stage, and three in
the feedback compensator. The fact that the A matrix of the
differential equation (1) is relatively sparse is not utilized by
the simulation packages since they must work for the
general power electronics problem. Hence the so!ution to
the equation must be found for the general case:
where 0 is an n-th order state transition matrix. Solution for
the state-transition matrix is usually explicit with the fastest
simulation routines. During a given switch condition, a
standard integration step size is taken repeatedly, and the
matrix is fixed for this given step size. Rapid computation
is obtained by precalculating and storing state-transition
matrices which are used repeatedly during the simulation
[5,6]. This eliminates the need for iterative integration
routines, such as Runge-Cutta algorithms, for each fixed
time step.
However, the major nonlinearity of PWM converters is the
time-varying nature of the linear networks, and iteration is
always needed to find the switching time. At the end of a
switch condition, matrices for variable step sizes must be
used. The time of transition of the circuit from one linear
topology to the next is determined by voltages and currents
of the circuit. Some iteration is always needed to solve for
the time when transitions occur. In some programs, the
convergence is obtained by bisection methods, and again
taking advantage of precalculated and stored transition
matrices. Other programs use Newton-type algorithms for
convergence, and precalculate and store expansion terms of
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the state-transition matrix in order to reduce the numerical
computations needed [6].
Hence, such simulators provide good flexibility for any
converter which may arise, but do not provide the maximum
speed which is possible.
2.4 Average-Model Simulation
Another simplification step taken by some engineers is to
average the effect of switching action, and to replace the
circuit switches with non-switching, average devices which
can be simulated very rapidly. This is a powerful
technique, essential for large-system simulations with
multiple converters, but important details are lost in this
process.
Difficulties arise with average simulations when
nonlinearities in the power stage are encountered. For
example, there are different average models for continuous
and discontinuous conduction modes. The boundary
between these two modes is dependent upon the ripple
current in the inductor, and this information is lost in the
average simulation. Similarly, peak current limiting is
difficult to accurately account for.
Standard PWM converters and their controllers have
structures which are amenable to substantial simplification
and high-speed simulation of the closed-loop system through
the use of these techniques.
3.2 Reduction of System Order
The first important step in maximizing the speed of
simulation for PWM converters is to reduce the order of the
system as much as possible in order to avoid the use of
matrix exponential solutions. Existing simulation programs
resort to solution of matrix differential equations to find
state trajectories, and this is a numerically intensive task,
even for a fixed time step simulation.
There are five states associated with the power stage and
controller of Fig. 1 (six if you count the PWM ramp state).
However, this and most other PWM power converters have
states which are very loosely coupled, and simplifications to
the calculation of the state transition equations can be found
if all of these couplings are identified and simplified.
Firstly, the controller provides negligible loading upon the
power stage, allowing the third-order controller to be
separated from the second-order power stage.
3.2.1 Reduction of Power Stage Order
3. New Method for High-speed Simulation
3.1 Introduction
Another level of simulation is possible which takes
advantage of the features of PWM converters, and greatly
speeds up the simulation process without losing the ditai1 of
Details of the simulation
the switching
techniques are described in the remainder of this paper.
The new simulation techruque presented here provides the
fastest possible algorithm for simulation of switching power
supplies, without sacrificing any sipficant details of
operation. The speed advantage over existing ideal-switch
simulators is achieved with the following techniques:
1) Reduction of system order by generation of decoupled
subsystems.
2) Closed-form approximation of switching times to
completely eliminate iteration and minimize the number
of calculations.
3) Reduction of approximation emor though control
network pre-sampling.
Even though the power stage consists of only two states for
simple converters, it is beneficial to try to reduce this to two
first-order systems. Symbolic solution of even a two-state
system is complicated by the different solutions for different
conditions which may exist the circuit.
Reduction of the power stage order is straightforward. As
with small-signal modeling [7], a linear ripple
approximation can be made to reduce the two-state
simulation problem into two single-state problems. The
so,ution for an integration time step is then just a pair of
scalar equations. For example, during the on-time of the
converter, the voltage across the inductor, neglecting
parasitic elements, can be assumed to be a constant, given
by the input voltage minus the capacitor voltage. The value
of the inductor current at the end of the on time, denoted by
, isthengiven by:
ipl
IF1G i ,k+ , [Iv i - v z ] [ t k + l
-tk]
(3)
This equation is valid when the output ripple of the
converter is much smaller than the dc value, and the input
voltage is a constant or a slowly varying function. The
circuit and waveforms corresponding to this condition are
519
with the control network of Fig. 1 which must be accurately
simulated during closed-loop operation. Trying to program
the closed-form solution equations for a hrd-order system
is not a practical task, even with the assistance of modem
symbolic mathematicsprograms.
shown in Fig. 2a.
h+l
Only one assumption is used to simplify the simulation of
the feedback amplifier network. Fig. 3a shows the general
form of a compensator network with a three-pole, two-zero
set of asymptotes. This is a typical compensator that would
be used for voltage-mode control.
R.
1 -
cZ
'3
pgl
I
(b)
Fig. 2: Buck Converter Power Stage and Waveforms with
Linear-Ripple Assumptions
Control
The value of the capacitor voltage waveform, shown in Fig.
2b, at the end of the on-time is approximated by:
All of the variables on the right hand side of Equations (3,4)
are known with the exception of the end of the on-time,
denoted by tk+1 . If this can be found in a closed form, it is
then a simple matter to program the power stage simulation.
The solution for the on-time interval is presented in Section
3.3.
Of course, complete elimination of all parasitic elements is
not desirable, and has only been done here for the sake of
brevity. It is possible to include the series resistances in the
calculationsfor the inductor current and capacitor voltage to
provide a more accurate simulation.
3.2.2 Reduction of Controller Order
Reducing the order of the power stage is only part of the
problem, and this has been done before by many engineers
for simulation of open-loop power stages with fixed duty
cycles. However, there are also the three states associated
Fig. 3: Typical Feedback Compensators and their Gain
Asymptotes.
In order to speed up simulation times, it is assumed that the
branch consisting of capacitor C, and R, has a long time
constant relative to the switching frequency. For a type 3
compensator for voltage-mode control, this time constant
corresponds to the first zero of the compensation network.
The simplifying assumption then says that the zero of the
compensation must be at a significantly lower frequency
than the switching frequency. Of course, this is always true
for a well-designed power supply - the zero for the
compensation is placed before the resonant frequency of the
520
LC filter, which is much lower than the switching
frequency.
Equation (6) is first order, consisting of just an exponential
decay expression.
A current-mode control compensator typically uses the
network of Fig. 3b which has two poles and one zero. This
network can be obtained from that of Fig. 3a simply by
making the resistor R, large - again satisfying the constraint
for a large time constant. Similarly, a type 1 compensator,
or integrator, shown in Fig. 3c also can be obtained by
opening this branch with a large value of &, and opening
the other RC branch with a large value of &.
3.3 Pre-Determination of Switching Times
The time-constant assumption for this branch of the
compensator is therefore valid for all practical power
converter designs which are likely to be encountered. The
simplified circuit of Fig. 4 can then be used to calculate the
transition of the states for the capacitors C , and C, in closed
form.
R.
'2
Knowledge about the operation and design of PWM
converters resulted in the closed-form expressions of Eqs.
(3-6). However, these equations contain the variable &+,,
which is actually an implicit function of the controller and
power stage states. The second step in the high-speed
simulation is therefore to determine explicitly the switching
time of the devices of the converter, without resorting to
iterative routines. If this can be done accurately at the
beginning of each switch conhtion, all iteration can be
avoided, and the number of calculations can be minimized
by taking as large a time step as possible.
Most PWM convertersemploy a constant-frequency clock to
turn on the power switch. With voltage-mode control, the
c3
intersection of a PWM ramp with the continuous output
voltage of the error amplifier is used to determine the end of
the on-time. This is referred to as a naturally-sampled PWM
system [8].
Control
"e
Fig. 4: Simplified Compensatorfor Single-Cycle Simulation
Further simplification is not possible since the poles of the
remaining network can be at frequencies close to the
switching frequency, and there is considerable interaction in
the circuit of Fig. 4. Two symbolic equations can be found
to solve for the states of this circuit:
(a) Natural Sampling
/I
PWM Ramp
The slow-moving state corresponding to capacitor C, can
then be calculated in closed-form as:
(b) Sample-and-Hdd
Fig 5: Different types of P WM modulators
Equations (5a,b) are second order, but the symbolic solution
is much simpler than for a general second-order system
since the poles of the compensator are always real. Hence
only a single symbolic expression needs to be derived and
programmed.
521
The naturally-sampled modulator offers the benefits of ease
of implementation, and zero phase delay through the
modulator function.
However, the naturally-sampled
modulator is difficult to simulate with closed-form
expressions since the switching time is an implicit function
of the states of the converter. Even with the reductions in
system order applied in the previous sections of this paper, it
is not possible to solve explicitly for the switching time with
this kind of modulator.
therefore much less stable than the actual circuit waveforms
when the modulator is substituted for simulation purposes.
The simulation error can be greatly reduced by the use of
pre-sampling elsewhere in the circuit to cancel the error of
the sample-and-hold of the modulator. This is done by
simply mdfying Eq. (5). Instead of using the output
voltage sample vk,as the driving function for the control
network, the voltage
is used:
A second type of PWM modulator, referred to as a
first-order sample-and-hold modulator, is shown in Fig. 5b.
Here, the value of the error voltage is sampled at the
b e g k g of the switching period, and h s value is used to
intersect the PWM sawtooth signal and generate the turn-off
command.
v y zf2(vE2 vt,
Y
The sample-and-hold modulator is very simple to simulate
explicitly. The on-time of the power switch is given by:
fk+l
V?
- fk = t;;ts
Y
vt,
Y
V S ' Y lk+l
-t k )
(9)
and
(7)
This simple expression gives a simple solution for the
on-time, and allows Eqs. (3-6) to be solved explicitly.
Rigorous analysis of the effects of the pre-sampling has not
yet been done, but experimental results provide excellent
correlation between small-signal analysis predictions of
stability, simulations with this technique,
simulations
with other ideal-switch
For continuous-conduction mode operation, the off-time of
the power switch is always known for constant-frequency
operation. In discontinuous conduction mode, the time
interval corresponding to the off time while the inductor
current is greater than zero must also be determined. This is
also an implicit function, but when linear ripple is assumed,
the calculation of this time interval is trivial.
4. Application to Converter Circuits
4.1 PWM DC-DC Converter
The techniques described in this paper have been applied to
simulate a variety of power electronics circuits. l h s
includes the standard two-state PWM topologies, employing
either voltage-mode or current-mode control.
3.4 Reduction of Modulator Error
There are two errors introduced when approximating the
naturally-sampled modulator with a sample-and-hold.
Firstly, the error voltage will have a dc offset from its actual
value due to the ripple in this signal. Generally, this is a
small error, and not significant for design purposes.
A more serious error is that the sample-and-hold modulator
introduces a phase-delay term in the modulation function,
and this is given by [8]:
In addition to the details discussed so far, it is important to
include other practical circuit limitings and nonlinearities in
the simulation for the results to be meaningful. Fig. 6 shows
simulation waveforms for the converter of Fig. 1.
9
I
,
Output V o l a g e
5
where f, is the modulating frequency, and t, is the switching
period, This phase delay is quite severe, even with a
conservative feedback loop gain design. For example, at 2
one-tenth the switching frequency, the phase delay is 0 . 2 ~
radians, or thirty-six degrees. Hence, a converter with a
loop gain crossover frequency of one-tenth the switching
frequency would have thirty-six degree less phase margin
with a sample-and-hold modulator than with a
naturally-sampled modulator. Simulated waveforms are
, ,,,,,
I
0
522
00005
Inductor Current
,,,,,,,.................................
II
0001
00015
.....
I
0002
000%
Tme (seconds)
Fig. 6: Large-Signal Simulation of Closed-Loop Buck
0003
5. Conclusions
The simulation shows a start-up transient, steady-state
operation, and a step-load transient. During the simulation,
the converter encounters duty cycle limiting, peak current
protection,
error
amplifier
limiting,
and
discontinuous-conductionmode. The entire simulation, with
equations programmed into a spreadsheet, takes
approximately one second for two hundred cycles of
operation on a 486,66-MHzpersonal computer.
New simulation techniques have been described which allow
a cycle-by-cycle power supply simulation to be done with
no numerical iteration, and with a minimum of computation
time. This is achieved by applying knowledge about the
operation of PWM converters and their compensators to
reduce the order of the simulation, and to explicitly
calculate switching times.
4.2 Power Factor Correction Circuit
The techniques described here are applicable to a wide
variety of PWM converters, and have been demonstrated in
this paper for a current-mode controlled forward converter,
and an average current-mode controlled power factor
correction circuit. The simulation speed is unsurpassed, even
with the symbolic simulation equations programmed into a
spreadsheet format. Two hundred cycles of closed-loop
operation can be simulated in one second on a 66-MHz PC.
A circuit which is particularly difficult to simulate is a
switching PWM power factor correction circuit. Many
hundreds of cycles must be simulated just to see the
distortion of the current over a single half-line cycle. In [9]
a combination buck and boost power factor correction is
described which uses multiple current feedback loops, with
averaging compensators, to properly control the line current.
The techniques described in this paper were applied to the
simulation of this converter whch has six controller states in
its two current feedback loops.
35
30
25
,
References
1) G.A. Franz, "Multilevel Simulation Tools for Power
Converters". IEEE Amlied Power Electronics Conference
(APEC 90), pp. 629-633: 1990.
2) P.W. Tuinenga, Microsim Corporation, "A Guide to Circuit
Simulation and Analysis Using PSpice", Prentice-Hall
Publishers, 1988.
1
-
3) Saber Users Guide, 1989, Analogy, Inc., PO Box 1669,
Beaverton, Oregon 97075.
0
1
2
3
4
5
T i m (rm)
6
7
8
9
10
4) R.J. Dirkman, "The Simulation of Genera2 Circuits Containing
Ideal Switches",
IEEE Power Electronics Specialists
Conference(PESC87)Proceedings,pp.l85-194,1987.
5) R.C. Wong, H.A. Owen, Jr., T.G. Wilson, "A Fast Algorithm
for the Time-Domain Solution of Switched-Mode
Piecewise-Linear Systems", IEEE Power Electronics
Specialists Conference (PESC 84) Proceedings, pp.281-296,
1984.
6) C.J. Hsiao, R.B. Ridley, H. Naitoh, F.C. Lee,
"Circuit-OrientedDiscrete-Time Modeling and Simulation for
Switching Converters", IEEE Power Electronics Specialists
Conference (PESC 87) Proceedings, pp. 167-176, 1987.
0
1
2
3
T i m5
(rm)
9
Fig. 7: Simulation of Buck and Boost Power-Factor Circuit
The results of this simulation are shown in Fig. 7. The
simulation techniques described here and programmed into a
spreadsheet took approximately seven seconds to simulate
and plot 500 cycles of this converter operation, long enough
to see the distortion of the input line current.
lo
7) R.D. Middlebrook, S. Cuk, "A General UnZJied Approach to
Modeling Switching Converter Power Stages", IEEE Power
Electronics Specialists Conference (PESC 84), pp. 18-34,
1984.
8 ) R.D. Middlebrook, "PredictingModulator Phase Lag in PWM
Converter Feedback Loops", Powercon 8, Paper H-4, 1981.
9) R.B. Ridley, S. Kern, B. Fuld, "Analysisand Design of a Wide
Input Range Power Factor Correction Circuit for Three-phase
Applications", IEEE Applied Power Electronics Conference
(APEC '93), 1993.
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