TUNNEL DIODE/TRANSISTOR INTEGRATED CIRCUITS
Abstract
by
Qingmin Liu
As the minimum feature sizes in transistor technology are reached, circuit performance may also saturate. For this reason, it is important to consider new and
extraordinary ways to extend the performance of circuits. Integrated tunnel diodes
enable a variety of design alternatives for signal processing, analog-to-digital conversion, communications, and memory. It is the goal of this work to analyze and
explore the potential of tunnel diode/transistor (TDT) technology for increasing
speed and reducing power dissipation beyond what can be achieved with transistors
alone.
Circuit design requires accurate device models. In this work, a physics-based
small-signal equivalent circuit model for the resonant tunneling diode (RTD) has
been developed, which unifies previous models by Brown et al. for quantum inductance and by Lake and Yang for quantum capacitance, and provides analytic
expressions for both the quantum inductance and quantum capacitance. Further,
two new TDT circuits: a TDT differential comparator and a TDT frequency translator have been invented.
The TDT differential comparator is of special interest for use in direct digital synthesis applications. Circuit simulation shows a power dissipation of 3.5 mW/latch
at 100-GHz clock frequency with 60-dBc spur-free dynamic range (SFDR) can be
Qingmin Liu
obtained in the TDT comparator. In comparison with the conventional transistor
approach, power is reduced by approximately 1.6x at the same speed and SFDR.
The TDT frequency translator is of special interest for use in communication
systems for upconverting digital signals. The circuit consists of a transistor, a
tunnel diode, and an inductor. The transistor provides input-output isolation and
power gain relative to prior art at the expense of the immunity to the input voltage
variation.
A scalable self-aligned contact process for fabrication of the TDT circuits has
been developed using InP-based RTD and double heterojunction bipolar transistor
(DHBT). This novel approach uses silicon nitride sidewalls and a benzocyclobutene
(BCB) etchback to form self-aligned emitter-base contacts. InP/InGaAs DHBTs
have been fabricated and the test results demonstrate the feasibility of this sidewall
and etchback process. AlAs/InGaAs/InAs RTDs were also fabricated and demonstrated a peak current density of 1.8 mA/µm2 and a peak-to-valley current ratio of
1.8.
To my dear parents
Debao Liu and Shumin Guo
To my dear wife
Ying Shang
ii
CONTENTS
FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
CHAPTER 1: INTRODUCTION . . . . . . . . . .
1.1 Resonant Tunneling Diode . . . . . . . . . .
1.2 Prior Art - Tunnel Diode/Transistor Circuits
1.3 Accomplishments . . . . . . . . . . . . . . .
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CHAPTER 2: DEVICE DESIGN AND MODELING . . . . . . . . . . . . . .
2.1 Resonant Tunneling Diode . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 RTD Heterostructure Design . . . . . . . . . . . . . . . . . . .
2.1.2 RTD DC Model . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 RTD AC Model . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 RTD Maximum Frequency of Oscillation . . . . . . . . . . . .
2.2 Heterojunction Bipolar Transistor . . . . . . . . . . . . . . . . . . . .
2.2.1 HBT Heterostructure Design . . . . . . . . . . . . . . . . . . .
2.2.2 HBT SPICE Model . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 HBT Cut-Off Frequency and Maximum Oscillation Frequency
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CHAPTER 3: CIRCUIT DESIGN AND SIMULATION
3.1 Circuit Design Using Tunnel Diodes . . . . . . .
3.2 Differential Comparator . . . . . . . . . . . . .
3.3 Frequency Translator . . . . . . . . . . . . . . .
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57
CHAPTER 4: SELF-ALIGNED NITRIDE SIDEWALL PROCESS
4.1 Process Overview . . . . . . . . . . . . . . . . . . . . . . .
4.2 Nitride Sidewall Formation and BCB Etchback Process . .
4.3 DHBT Fabrication . . . . . . . . . . . . . . . . . . . . . .
4.4 RTD Fabrication . . . . . . . . . . . . . . . . . . . . . . .
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iii
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CHAPTER 5: SUMMARY AND CONCLUSIONS . . . . . . . . . . . . . . . 84
5.1 Summary of Achievements . . . . . . . . . . . . . . . . . . . . . . . . 84
5.2 Recommendations for Future Research . . . . . . . . . . . . . . . . . 87
APPENDIX A: FABRICATION PROCESS FLOW . . . . . . . . . . . . . . 91
APPENDIX B: ESTIMATION OF THE HETEROJUNCTION BIPOLAR
TRANSISTOR CUT-OFF FREQUENCY AND MAXIMUM OSCILLATION FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
APPENDIX C: DESIGN APPROACH USING TUNNEL DIODES FOR
LOWERING POWER IN DIFFERENTIAL COMPARATORS . . . . . . 105
APPENDIX D: TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
APPENDIX E: UNIFIED AC MODEL FOR THE RESONANT TUNNELING DIODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
APPENDIX F: LOW POWER, HIGH SPEED, AND MIXED-SIGNAL TUNNELING DEVICE TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . 123
APPENDIX G: VERTICAL SILICON TUNNEL DIODE ON HIGH RESISTIVITY SILICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
APPENDIX H: UNIFIED PHYSICS-BASED AC MODEL FOR THE RESONANT TUNNELING DIODE . . . . . . . . . . . . . . . . . . . . . . . . 129
APPENDIX I: PERFORMANCE-AUGMENTED CMOS USING BACKEND UNIAXIAL STRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
APPENDIX J: SILICON-BASED TUNNEL DIODES AND INTEGRATED
CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
iv
FIGURES
1.1
1.2
The measured current-voltage characteristic of an InP-based resonant
tunneling diode. The circuit symbol is defined in the inset. . . . . . .
2
Conduction band profiles of a resonant tunneling diode under different biases: (a) equilibrium, (b) resonance, and (c) off-resonance. . . .
4
2.1
Comparison of measured (circles) and simulated (line) current-voltage
characteristic of an AlAs/InGaAs/AlAs RTD. The simulation is based
on Broekaert’s model [19]. . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Resonant tunneling diode small-signal equivalent circuit models: series inductance model of (a) Gering et al. [20], and parallel inductance
model of (b) Brown et al. [21]. Model (c) of Broekaert et al. [19]
and Lake and Yang [23] adds the quantum capacitance to the series
inductance model. Unified small signal model proposed in this work
by (d) Liu and Seabaugh [22]. . . . . . . . . . . . . . . . . . . . . . . 16
2.3
InP-based resonant tunneling diode computed energy band diagram
(computed using the Schrödinger-Poisson solver, BandProf, of W. R.
Frensley). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4
The Fermi surface of the degenerate emitter electron gas. Tunneling
current is directed along the kZ direction. kF is the Fermi wave number in the emitter and kZ is the electron wave vector projected onto
the z-direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
Comparison of measured (circles) and simulated (line) S-parameter
at two selected biases. (a) 0.15 V (pre-peak region); (b) 0.45 V (near
the center of the NDR region). To avoid being indistinguishable between the measured and simulated curves, only 20% of the total 801
measured data points in each curve are shown. . . . . . . . . . . . . . 23
2.6
Comparison of the differential conductance extracted from the dc I-V
measurement (line) and S-parameter measurements (circles). . . . . . 24
2.7
Schematic band diagram of the RTD at (a) equilibrium, and (b) an
applied bias voltage of VA . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.8
The reciprocal of the quantum inductance, LQ , vs. bias showing good
agreement between extracted inductance from S-parameter measurements (circles) and the unified ac model (line). . . . . . . . . . . . . . 26
v
2.9
The total capacitance, CP , vs. bias showing close agreement between
extracted capacitance from S-parameter measurements (circles) and
the unified ac model (line). . . . . . . . . . . . . . . . . . . . . . . . . 28
2.10 The calculated RTD maximum oscillation frequency, fmax , vs. the
negative differential resistance, RD , where RS , CP , and τ are assumed
to be constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.11 The calculated RTD maximum oscillation frequency, fmax , vs. the
series resistance, RS , where RD , CP , and τ are assumed to be constant. 32
2.12 Calculated energy band diagram of InP/InGaAs double heterojunction bipolar transistor (computed using the Schrödinger-Poisson solver,
BandProf, of W. R. Frensley). . . . . . . . . . . . . . . . . . . . . . . 34
2.13 Calculated energy band diagram of InP/GaAsSb double heterojunction bipolar transistor (computed using the Schrödinger-Poisson solver,
BandProf, of W. R. Frensley). . . . . . . . . . . . . . . . . . . . . . . 35
2.14 The small-signal Gummel-Poon model for an InP HBT. . . . . . . . . 36
2.15 SPICE simulated Gummel plot and comparison with measured data.
The parameters used in the SPICE simulation are shown in Table 2.3. 38
2.16 SPICE simulated common-emitter characteristics. The parameters
used in the SPICE simulation are shown in Table 2.3. . . . . . . . . . 39
2.17 SPICE simulated small signal current gain and power gain frequency
dependence for a 1 µm2 device. The parameters used in the SPICE
simulation are shown in Table 2.3. . . . . . . . . . . . . . . . . . . . . 40
2.18 Schematic cross section of a heterojunction bipolar transistor. . . . . 43
3.1
Current-controlled clocked tunnel diode pair. . . . . . . . . . . . . . . 45
3.2
Load lines of the tunnel diode pair at two conditions: (a) ICT L is off;
and (b) ICT L is on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3
Schematic of a conventional transistor-only differential comparator. . 48
3.4
Schematic of a tunnel diode/transistor differential comparator. . . . . 49
3.5
Simulated output waveforms for the two comparator circuits of (a)
tunnel diode/transistor comparator, and (b) conventional bipolar transistor comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6
Simulated output spectrum of the synthesized passband signal for (a)
tunnel diode/transistor and (b) transistor-only differential comparator showing 60 dBc SFDR around 37.3 GHz. This simulation uses
high speed InP-based HBT and RTD models. . . . . . . . . . . . . . 54
vi
3.7
Layout for the RTD/HBT differential comparator. The circuit schematic
is shown in Fig. 3.4. Layout area is 1.8×1.1 mm2 . . . . . . . . . . . . 55
3.8
Schematic architectures of two types of receivers: (a) conventional
superheterodyne receiver [78] and (b) Cellonics receiver [41]. . . . . . 57
3.9
Cellonics tunnel diode frequency translation circuit diagram [79]. . . . 59
3.10 Notre Dame tunnel diode/transistor frequency translation circuit.
The circuit component and source values in the simulation are: L = 1
nH, VCC = 1 V, and the HBT and RTD areas are both 2 × 2 µm2 . . . 60
3.11 Simulated output waveform for the tunnel diode/transistor frequency
translation circuit. Circuit component values are given in the caption
of Fig. 3.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.12 Simulated frequency and magnitude of the output signal vs. the input
voltage for (a) the Cellonics frequency translation circuit of Fig. 3.9,
and (b) the tunnel diode/transistor frequency translation circuit of
Fig. 3.10. The circuit component values in the simulation are: L = 1
nH, VCC = 1 V, and the RTD area is 2 × 2 µm2 . . . . . . . . . . . . . 62
3.13 Layout for the RTD/HBT frequency translator. The circuit schematic
is shown in Fig. 3.10. Layout area is 0.8×0.5 mm2 . . . . . . . . . . . 64
4.1
Scale drawings of self-aligned emitter-base contact formation using a
nitride sidewall spacer. These drawings describe: (a) the emitter metallization, (b) the emitter mesa etch, (c) the silicon nitride sidewall
formation, and (d) the base metal deposition. . . . . . . . . . . . . . 67
4.2
Scale drawings of self-aligned emitter-base contact formation using
a nitride sidewall spacer. These drawings describe: (a) the BCB
deposition, (b) the BCB etchback, (c) the tungsten RIE etch, and
(d) the removal of the BCB. . . . . . . . . . . . . . . . . . . . . . . . 68
4.3
Optical micrographs of a 4x4 µm2 emitter HBT. The graphs show
the step-by-step HBT emitter, base and collector contact formation. . 70
4.4
RIE etch characteristic of silicon nitride in CHF3 . . . . . . . . . . . . 72
4.5
SEM micrograph of the silicon nitride sidewall on a GaAs substrate.
Silicon nitride is RIE etched in CHF3 plasma. . . . . . . . . . . . . . 73
4.6
RIE etch characteristic of silicon nitride in SF6 and Ar. . . . . . . . . 74
4.7
SEM micrograph of the silicon nitride sidewall on a GaAs substrate.
Silicon nitride is RIE etched in SF6 /Ar plasma. . . . . . . . . . . . . 74
4.8
RIE etch characteristic of BCB in SF6 and O2 . . . . . . . . . . . . . . 75
4.9
SEM micrograph of the BCB etchback process on an AlGaAs/GaAs
HBT wafer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
vii
4.10 Measured Gummel plot of an InP/InGaAs double heterojunction
bipolar transistor with nitride sidewall process. . . . . . . . . . . . . . 78
4.11 Measured common-emitter IC −VCE characteristic of an InP/InGaAs
double heterojunction bipolar transistor with nitride sidewall process. 80
4.12 Resonant tunneling diode DC test structure, (a) top view, (b) side
view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.13 Measured current-voltage characteristics of the resonant tunneling
diodes on wafers: (a) 060729A2BA02, (b) 060745A3AA01. . . . . . . 83
5.1
Scale drawings of a fully self-aligned HBT process. These drawings
describe the emitter metallization, the emitter mesa etch, the silicon
nitride sidewall formation, and the base metal deposition and etch. . 89
5.2
Scale drawings of a fully self-aligned HBT process. These drawings
describe the base and collector mesa etch, and the collector metal
deposition and etch. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
viii
ACKNOWLEDGMENTS
I would like to thank many people who have supported and helped me to finish
this thesis.
First, I wish to express my sincere gratitude to my advisor, Dr.
Alan C.
Seabaugh, for his valuable suggestions and directions concerning my work and life
during these years. He gave me a lot of encouragement and support when I felt
discouraged in the research work. I am very grateful to him for giving me this
opportunity to be his student.
Second, I would like to thank Dr. Fay, Dr. Porod, Dr. Csurgay and Dr. Jena for
agreeing to be my thesis readers and be members of my thesis defense examination
board. I am also very grateful to them for giving me a lot of valuable advice on my
research during these years.
I gratefully acknowledge the partial financial support of the Office of Naval Research and Raytheon Systems. Especially, I wish to thank Prem Chahal and Frank
Morris at Raytheon for providing RTDs. I would also like to thank Yung-Chung
Kao, Paul Pinsukanjana, Haijun Zhu, and Kevin Vargason, IntelliEPI Inc. for their
supporting material growth.
Finally, I am very grateful to my parents and my wife for their encouragement
and support. I really appreciate my friends and colleagues, Surajit Sutar, Yan Yan,
Jialin Zhao, Sajid Kabeer, Bin Wu, Shishir Rai, and Notre Dame colleagues, for
their help and for the unforgettable days we had.
ix
CHAPTER 1
INTRODUCTION
Since 1957, the tunnel diode, also called the Esaki diode, has been widely investigated for high-speed circuit applications, due to its intrinsic high switching
speed, and its multi-valued current-voltage (I−V) characteristic featuring negative
differential resistance (NDR) [1, 2, 3]. The resonant tunneling diode (RTD), first
demonstrated in 1974 [4], also features a multi-valued I−V characteristic, shown
in Fig. 1.1, and exhibits a high switching speed due to its small capacitance and
high current density. However, the tunnel diode (TD), denoting both the Esaki
diode and RTD, has not found wide use in commercial electronics. Therefore, it is
important to consider the impediments for use of tunnel diodes and how these can
be overcome.
First, the tunnel diode is a two-terminal device. Circuits constructed using
tunnel diodes lack isolation between input and output, i.e. the signals can propagate
from the output back to the input. The TD-only circuits also suffer from low
gain and fan-out [5, 6]. These deficiencies can be corrected by adding transistors
to the circuit, thereby providing input-output isolation, gain and fan-out. This
solution, however, requires development of an integrated tunnel diode technology,
i.e. a process for integration of tunnel diodes with transistors.
In the 1960s and 70s, lack of integration was a big problem for tunnel diodes,
as integrated circuits replaced discrete circuits becoming the mainstream technol1
0.15
Current (mA)
I
P
0.1
Circuit
Symbol
0.05
1x1 µm2
0
0
0.2
0.4
0.6
0.8
Voltage (V)
1
1.2
4a0301-R7556
Figure 1.1. The measured current-voltage characteristic of an InP-based resonant
tunneling diode. The circuit symbol is defined in the inset.
ogy in modern electronics [5]. Today, however, methods for integrating tunnel
diodes with transistors in compound semiconductor technologies are well known,
e.g. [7, 8, 9, 10, 11]. Silicon and SiGe tunnel diodes have also recently been developed using molecular beam epitaxy [12, 13] or rapid thermal and chemical vapor
deposition processes [14, 15], and integration methods for incorporation of tunnel
diodes with CMOS have been shown [16]. These integration methods provide a basis
for incorporating tunnel diodes with transistors to augment circuits performance.
Development of tunnel diode circuits has also been impeded by the lack of a
representative SPICE model in commercial computer-aided design (CAD) softwares.
A piecewise-linear approximation for the “N-shaped” I−V characteristic has been
used for a long time, e.g. [17]. Recently, Schulman [18] and Broekaert [19] have
derived a physics-based I−V model to describe the “N-shaped” characteristic of the
RTD. For the ac model of the RTD, several different equivalent circuits have been
2
proposed, e.g. [20, 21]. In the course of this work, an analytic model has been found
which yields the small-signal equivalent circuit model directly for the RTD [22], and
which unifies previous models by Brown [21] for quantum inductance and by Lake
and Yang [23] for quantum capacitance.
Nowadays commercial technologies such as CMOS depend largely on device scaling for improving circuit performance. As physical and technological limits determining minimum feature sizes are achieved, system improvement will depend more
and more on innovations in circuit design. It is important to consider augmentation technologies to enable new circuit explorations, e.g. in signal processing [24],
analog-to-digital conversion (ADC) [19], memory [25], and logic [11].
The remainder of this introductory chapter is organized as follows. Section 1.1
reviews the fundamentals of the resonant tunneling diode. Section 1.2 reviews the
prior art in tunnel diode/transistor (TDT) circuits. Finally, the accomplishments
of this research are summarized in Section 1.3.
1.1 Resonant Tunneling Diode
The RTD structure consists of a thin quantum well sandwiched between two
thin barriers and degenerately-doped emitter and collector regions as shown in Fig.
1.2, where E0 represents the quantized energy state in the quantum well. The
emitter and collector are degenerately doped so that the Fermi levels lie above the
conduction band edge in these two regions.
At equilibrium, the quantized energy state lies above the Fermi level in the emitter, Fig. 1.2(a), the net tunneling current is zero. As the applied positive bias at
the collector lowers the quantized state in the quantum well until it aligns with the
occupied electron states in the emitter, resonant tunneling occurs, Fig. 1.2(b). Elec-
3
Emitter
EF
Quantum
Well
Collector
E0
EF
(a)
EF
E
0
EF
qV
(b)
E
F
E
0
qV
E
F
(c)
Figure 1.2. Conduction band profiles of a resonant tunneling diode under different
biases: (a) equilibrium, (b) resonance, and (c) off-resonance.
trons in the emitter, whose longitudinal energy aligns with the quantized state, can
tunnel through this quantized state into the collector with a tunneling probability
approaching 1. The selection conditions for resonant tunneling, which depend in
detail on the energy-momentum relations between the emitter and quantum well,
have been worked out by Schulman [26]. The description given here is sufficient for
first-order understanding. As the number of these electrons available for tunneling
reaches a maximum, the tunneling current will reach a peak, and the corresponding
bias voltage is referred to as the peak voltage. As the bias exceeds the peak voltage,
4
the number of electrons which can tunnel into the quantum well decreases, resulting
in a decreased tunneling current which gives a negative differential resistance region
in the I−V characteristic. As the applied bias increases further, the quantized state
drops below the conduction band edge in the emitter and the resonant tunneling
path is broken, Fig. 1.2(c). Consequently, the current reaches a minimum value,
IV , which is determined by phonon-assisted tunneling and thermionic processes, and
the corresponding bias voltage is called the valley voltage. As the bias exceeds the
valley voltage, the current increases again. This current is comprised of at least
two components. One is the thermionic emission current since the bias lowers the
barriers as a result of potential drop in the emitter accumulation region. The other
excess current component is due to resonant tunneling through the second quantized
state in the quantum well.
The above discussion provides a physical picture of the tunneling process giving
rise to the multi-valued I−V characteristic and negative differential resistance of
the RTD. A detailed discussion of the RTD structures, dc and ac models, and high
frequency performance is given in Chapter 2.
1.2 Prior Art - Tunnel Diode/Transistor Circuits
Tunnel diode/transistor integrated circuits have been widely investigated due
to their simple architectures, high speed, and low power dissipation. TDT circuits
have been demonstrated for analog-to-digital conversion [19, 27], memory [7, 25],
logic (gates and flip-flops) [9, 11, 28], oscillators [29, 30], and chaos circuits [31, 32].
For analog-to-digital conversion, Broekaert et al. [19] first demonstrated a 4-bit
2-Gsps monolithic flash analog-to-digital converter, where RTDs were integrated
with heterostructure field-effect transistors (HFETs) and used in a flash circuit
5
architecture. More recently, a 3-bit 5-Gsps analog-to-digital converter was reported
also using RTDs and HFETs [27]. These converters show promise for extending the
ADC to X-band applications, but their use will depend on development of foundry
processes for TDT circuits.
In memory, an RTD/HFET low-standby-power static random-access memory
(SRAM) cell based on InP technology was demonstrated by van der Wagt et al.,
and it saved the power by 200x over the best previous GaAs-based memory cell
[25, 33]. This cell consisted of one HFET and two RTDs. In silicon technology, the
CMOS/TD SRAM, consisting of one transistor, two tunnel diodes and one stackedcapacitor, can reduce the chip area by 2x and standby power by 7x over conventional
6T SRAM [24].
In logic, a monostable-bistable transition circuit topology [34] has been explored
for high-speed logic gates and flip-flops. This circuit topology consists of two seriesconnected tunnel diodes monolithically-integrated with a parallel field-effect transistor [9, 16] or a bipolar transistor [11, 28]. Both 35 GHz single-ended [9] and 20
GHz differential [11] flip-flops have been demonstrated.
When the tunnel diode is biased in the NDR region, the circuit will oscillate. This
oscillation can be utilized to implement oscillators. A 5.8 GHz oscillator using a RTD
integrated with a heterojunction bipolar transistor (HBT) and a bond wire inductor
has been demonstrated with an output power of 3.3 dBm and a power efficiency of
8.84% [29]. Recently, a varactor-tuned voltage-controlled oscillator (VCO) using InP
RTD/HBT has been demonstrated with a center oscillation frequency of 5 GHz, a
tuning range of 710 MHz, a phase noise of -115 dBc/Hz with 1-MHz offset, and power
dissipation of 7.6 mW [30]. Compared to the conventional CMOS VCOs [35, 36],
this RTD/HBT VCO achieves comparable specifications with less components in
the circuit.
6
The strong nonlinearity of the tunnel diode has been investigated for chaos generation, a phenomenon which is being explored for communication and information
processing [37]. A simple chaos generation circuit, which consists of a tunnel diode,
an inductor, and a capacitor, has been proposed [37]. The output of this circuit
can be periodical or chaotic, which is determined by the circuit parameters. As the
output signal is designed to be periodical, the circuit can be used as a frequency
divider. Recently, Kawano et al. [31] has demonstrated an 88-GHz 2:1 RTD/HEMT
(high electron mobility transistor) frequency divider with a single sideband phase
noise less than -100 dBc/Hz at 1-MHz offset frequency, which is comparable to conventional frequency dividers [38, 39].
1.3 Accomplishments
The primary purpose of this thesis is to explore, through design, analysis, and
fabrication, InP-based RTD and HBT high speed and low power integrated circuits.
At the initial phase of this research, the equivalent circuit model of the resonant
tunneling diode was examined. InP based RTDs, provided by Raytheon Systems,
were measured using an Agilent 8510XF network analyzer. Previously published
models [19, 20, 21, 23] could not fit the measured S-parameters through the entire
frequency range (from 45-MHz to 30-GHz) and bias range (from 0 to post valley).
To resolve deficiencies in the prior models, a new unified small-signal equivalent
circuit model for the RTD was derived, and good agreement between this model
and measurement was obtained and published [22]. A detailed discussion of this
model is given in Chapter 2 and Appendix E.
In this research two new circuits which exploit the high speed and low power potential of resonant tunneling diodes have been conceived, designed and simulated: a
7
TDT differential comparator and a TDT frequency translator. The TDT differential
comparator circuit allows an increase in circuit speed while simultaneously lowering
power compared to a conventional transistor-only circuit [40]. The TDT frequency
translation circuit also lowers power relative to conventional circuit approach [41].
The design and simulation of these two new circuits are given in Chapter 3.
To fabricate the TDT circuits, a new self-aligned contact process using silicon
nitride sidewalls and a benzocyclobutene (BCB) etchback has been developed. The
emitter-base separation is set by the nitride sidewall thickness allowing scaling to
reduce access resistance. The nitride sidewall is formed by depositing a plasmaenhanced chemical vapor deposition (PECVD) Si3 N4 film, followed by an anisotropic
reactive ion etching (RIE). The nitride RIE etching conditions have been investigated and the formation of nitride sidewalls has been verified by scanning electron
microscopy (SEM). Device electric test results have demonstrated the feasibility of
this fabrication process. The detailed discussion of the fabrication process and the
device test results are given in Chapter 4 and Appendix A.
The remainder of this thesis is organized as follows. Chapter 2 discusses the RTD
and HBT structures design and SPICE models. Chapter 3 discusses circuit design
using tunnel diodes and two new TDT circuits: a TDT differential comparator
and a frequency translator. Chapter 4 discusses the fabrication process used to
construct the circuit. Device results for fabrication of InP RTDs and HBTs are
described. Chapter 5 summarizes the accomplishments and proposes future work.
The RTD/HBT process traveler is given in Appendix A. The equations for the HBT
performance estimates are attached as Appendix B. Published work is included as
Appendices C to J.
8
CHAPTER 2
DEVICE DESIGN AND MODELING
InP-based RTDs have been selected for this work because of their demonstrated
high peak current densities and high peak-to-valley current ratios [43, 44, 45]. Two
types of InP-based HBTs: InP/GaAsSb HBTs and InP/InGaAs HBTs are also utilized as they have demonstrated excellent high frequency performance with measured
cut-off frequency and maximum oscillation frequency over 300 GHz [46, 47, 48, 49].
This chapter summarizes the RTD and HBT heterostructure design and models
used for circuit simulation. In addition, the RTD maximum frequency of oscillation
is revisited in light of the new understanding of the RTD equivalent circuit obtained
in this work, and its dependence on the RTD negative differential resistance and
series resistance is also shown.
2.1 Resonant Tunneling Diode
2.1.1 RTD Heterostructure Design
The slew rate of a tunnel diode can be evaluated by [50]
dV
IP
1
= (1 −
),
dt
C
PV R
(2.1)
where IP is the peak current, C is the junction capacitance, IP /C is the speed
index, and P V R is the peak-to-valley current ratio. To obtain high switching speed,
9
it is necessary to maximize the peak current and peak-to-valley current ratio and
minimize the capacitance.
Since the first InP-based InAlAs/InGaAs/InAlAs RTD was reported by Inata
et al. [51], much research has been done to improve the peak current density and
peak-to-valley current ratio. By replacing the InAlAs barrier with a strained AlAs
barrier, Inata et al. [52] later demonstrated a peak-to-valley current ratio as high
as 14 with a peak current density of 0.23 mA/µm2 at room temperature. The
AlAs/InGaAs RTD has demonstrated the highest peak current density of any RTD,
6.8 mA/µm2 with the peak-to-valley current ratio of 2.5 [43]. Broekaert et al. [54]
incorporated InAs in the quantum well structure to lower the quantized energy state
in the well with respect to the emitter conduction band edge, thereby lowering the
RTD turn-on voltage. The AlAs/InGaAs/InAs RTDs have also demonstrated high
peak-to-valley current ratio of 50 [45] and peak current density of 4.5 mA/µm2 [44].
Another fully lattice-matched heterostructure is the AlAsSb/InGaAs barrier-well
structure. The AlAsSb/InGaAs RTD demonstrated a peak-to-valley current ratio
of 11 with a peak current density of 0.15 mA/µm2 and showed potential for further
development [53]. For this research, the AlAs/InGaAs/InAs RTD has been selected
because of its record current density and low turn-on voltage. The layer diagram
for the heterostructure is given in Table 2.1.
10
TABLE 2.1
STRUCTURAL PARAMETERS FOR AN InP-BASED RESONANT
TUNNELING DIODE. TYPICAL UNINTENTIONAL DOPING (UID) IN
THESE MATERIAL SYSTEMS IS N-TYPE WITH A DENSITY ≤ 1016 cm−3 .
THE In MOLE FRACTION IS 53% WHICH IS LATTICE-MATCHED TO InP
Material Thickness (nm)
InGaAs
40
InGaAs
5
InGaAs
2
AlAs
1.6
InGaAs
1.5
InAs
2.1
InGaAs
1.5
AlAs
1.6
InGaAs
2
InGaAs
5
InGaAs
60
Dopant Density (cm−3 ) Function
Si
3.0E19
emitter
Si
1.0E18
emitter
UID
spacer
UID
barrier
UID
well
UID
well/notch
UID
well
UID
barrier
UID
spacer
Si
1.0E18
collector
Si
3.0E19
collector
11
2.1.2 RTD DC Model
The tunneling current of the RTD is given by the Tsu-Esaki formula [56],
qm∗ kT
J=
2π 2 ~3
Z
µ
∞
dEZ Θ(EZ , V ) ln
0
1 + e(EF −EZ )/kT
1 + e(EF −EZ −eV )/kT
¶
,
(2.2)
where q is the fundamental charge, m∗ is the effective mass, k is Boltzmann’s constant, T is the temperature, ~ is Plank’s constant over 2π, EZ is the longitudinal
energy in the direction of current flow, V is the bias voltage, Θ(EZ , V ) is the transmission coefficient, and EF is the Fermi energy of the emitter. The transmission
coefficient can be approximated by a Lorentzian function [18],
Θ(EZ , V ) =
(Γ/2)2
,
[EZ − (E0 − eV /2)]2 + (Γ/2)2
(2.3)
where Γ is the resonance width. The transmission coefficient is negligible except
when EZ is close to E0 − eV /2. Therefore, we can replace EZ by E0 − eV /2 in the
logarithmic term in Eq. 2.2, leading to the tunneling current given by the Schulman
formula [18],
·
¸·
µ
¶¸
1 + e(EF −E0 +eV /2)/kT
π
E0 − eV /2
qm∗ kT Γ
J=
ln
+ arctan
.
4π 2 ~3
1 + e(EF −E0 −ev/2)/kT
2
Γ/2
(2.4)
Equation 2.4 gives the peak current and the NDR, but does not account for the postvalley current, which is due to tunneling through higher energy states in the well and
the barrier-controlled diode current. Broekaert [19] has provided additional analytic
expressions to describe the physics of this post-resonance I−V characteristic. In the
Broekaert model, the total current is expressed by,
IRT D (V ) = Ires1 (V ) + Ires2 (V ) + Ilkg (V )
(2.5)
where Ires1 and Ires2 are the tunneling current through the first and second quantized
states in the quantum well, Ilkg is the thermionic leakage current. The resonant
12
tunneling current for a symmetric RTD is expressed by,
Ires (V ) = IE (V ) − IE (−V )
(2.6)
with
·
µ
¶¸
AJP
2
VN − V
IE (V ) =
1 + arctan
2f
π
Γ
·
µ
¶¸
V − VT
nkT
ln 1 + exp
×
VN − VT
nkT
and
(2.7)
s
f =1−
2Γ
,
π(VN − VT )
(2.8)
where A is the device area, JP is the approximate peak current density, VN is the
voltage at which the maximum negative differential resistance occurs, VT is the
resonance turn-on voltage, Γ is the full-width at half maximum of the resonance, n
is a “lever” factor accounting for the voltage drop across the quantum well relative
to the applied bias, and kT is the thermal voltage. The thermal leakage current is
given by,
³
Ilkg (V ) = AJV
sinh
sinh
³
V
nV kT
VV
nV kT
´
´.
(2.9)
Based on Broekaert’s model, the RTD dc model parameters can be extracted by
fitting the measured I-V data to Eq. 2.5, as shown in Fig. 2.1. A close agreement
is typically obtained between the measured data and the fits based on Broekaert’s
model. Extracted parameters are listed in Table. 2.2 for the fit of Fig. 2.1; this is
the RTD model used for the TDT circuit simulations, described in Chapter 3. This
model is for an RTD fabricated by Raytheon Systems with a peak current density
of 1.1 mA/µm2 and peak-to-valley current ratio of 2.1.
13
6
Measured InP-based RTD
2
2
Simulated
(1.6) µm
Current (mA)
5
4
3
2
1
0
0
0.2
0.4
0.6
Voltage (V)
0.8
1
Figure 2.1. Comparison of measured (circles) and simulated (line) currentvoltage characteristic of an AlAs/InGaAs/AlAs RTD. The simulation is based on
Broekaert’s model [19].
14
TABLE 2.2
InP RESONANT TUNNELING DIODE SPICE DC MODEL PARAMETERS
PARAM.
JP 1
JP 2
VN 1
VN 2
VT 1
VT 2
Γ1
VALUE
1.255
4.170
0.3653
1.505
-0.03286
0.6562
0.09220
UNIT
mA/µm2
mA/µm2
V
V
V
V
V
Γ2
0.1871
V
n1
n2
JV
nV
VV
1.278
1.472
0.4510
1.289
1.000
mA/µm2
V
DESCRIPTION
Peak current density (Resonance 1)
Peak current density (Resonance 2)
Voltage of maximum NDR (Resonance 1)
Voltage of maximum NDR (Resonance 2)
Resonant turn-on voltage (Resonance 1)
Resonant turn-on voltage (Resonance 2)
Full-width at half maximum
of the resonance (Resonance 1)
Full-width at half maximum
of the resonance (Resonance 2)
Resonance lever factor (Resonance 1)
Resonance lever factor (Resonance 2)
Thermionic leakage current at VV
Thermionic leakage current ideality factor
Valley voltage
2.1.3 RTD AC Model
The prior art in small-signal equivalent circuits for the RTD can be classified
into two categories: a series-inductance model [20] and a parallel-inductance model
[21], see Fig. 2.2, where RS represents the contact resistance plus the semiconductor sheet resistance, GD represents the differential conductance (first derivative of
the dc I-V curve), L represents the series inductance, LQ represents the quantum
inductance, and CQ and C0 represent the quantum capacitance and the geometrical
depletion capacitance, respectively.
15
RS
RS
L
C0
C0
Gering
(a)
Brown
(b)
LQ
GD
RS
GD
LQ
GD
L
GD
RS
C0+CQ
C0+CQ
Broekaert, Lake
(c)
Liu and Seabaugh
(d)
Figure 2.2. Resonant tunneling diode small-signal equivalent circuit models: series
inductance model of (a) Gering et al. [20], and parallel inductance model of (b)
Brown et al. [21]. Model (c) of Broekaert et al. [19] and Lake and Yang [23] adds
the quantum capacitance to the series inductance model. Unified small signal model
proposed in this work by (d) Liu and Seabaugh [22].
In the series-inductance model, Fig. 2.2(a) and (c), a bias-independent inductance, which can be attributed to the wiring [57] appears in series with the parasitic resistance and the parallel combination of the tunneling conductance and the
junction capacitance. In the parallel-inductance model, the inductance, which is
attributed to the charging and discharging of the quantum well, appears in series
with the tunneling conductance which, in total, is in parallel with the junction
capacitance.
The capacitance in the equivalent circuit models should include both the geometrical capacitance of the device and the quantum capacitance, which is due to
the density of electrons stored in the quantum well changing as a function of bias.
16
However, in prior work, the quantum capacitance is either neglected [21, 59], or computed numerically [58]. Broekaert [19] gives a general expression for the geometrical
capacitance of the depletion layer and adds the quantum capacitance. However, in
his expression for the quantum capacitance, the sign is wrong. Recently, Lake and
Young [23] derived a simple analytic expression for the quantum capacitance and
corrected the sign. In their expression, the quantum capacitance exists only in the
NDR region and the quantum inductance is not considered.
The unified ac model for the RTD determined in the course of this work was
published [22]. This model provides the form of the small-signal equivalent circuit of the RTD, shown in Fig. 2.2(d), and leads to analytic expressions for both
the quantum inductance and quantum capacitance. Measurements of both dc I-V
characteristic and microwave frequency S-parameters of AlAs/InGaAs/InAs RTDs
support the validity of this equivalent circuit.
The unified ac RTD model is readily described using the band diagram of an
AlAs/InGaAs/InAs RTD under the bias voltage of V in Fig. 2.3. In this figure, JE
represents the emitter-to-well tunneling current density and JC represents the wellto-collector tunneling current density. The change in collector tunneling current in
response to a change in the quantum well charge can be expressed as
∆JC = ∆(νC QW ) ≈ νC ∆QW
(2.10)
where ∆QW is the change in stored charge in the quantum well and νC is the
electron escape rate (s−1 ) from the quantum well to the collector. Assuming νC is
weakly dependent on bias, ∆(νC QW ) is approximately equal to νC ∆QW for small
variations in applied bias. The tunneling current due to electrons tunneling back
from the collector to the quantum well is considered to be negligible.
17
2
1.5
Collector
1
J
0.5
J
E
C
E
F
0
E
E − qV
0
F
0
10
InGaAs
5
-1.5
InGaAs
AlAs
-1
AlAs
InGaAs
InAs
-0.5
InGaAs
Energy (eV)
Quantum
Well
Emitter
15
20
Position (nm)
Figure 2.3. InP-based resonant tunneling diode computed energy band diagram
(computed using the Schrödinger-Poisson solver, BandProf, of W. R. Frensley).
Similarly, the emitter current change resulting from a small bias variation is
given by
∆JE = ∆(ν0 QE ) − ∆(νE QW ) ≈ ν0 ∆QE − νE ∆QW
(2.11)
where QE is the change in the available tunneling charges in the emitter, ν0 is the
electron escape rate (s−1 ) from the emitter to the quantum well, and νE is the
electron escape rate (s−1 ) from the quantum well to the emitter. As in Eq. 2.10,
ν0 and νE are assumed to be weakly dependent on the bias, therefore ∆ν0 and ∆νE
are negligible.
18
The difference between JE and JC then describe the change in charge stored in
the quantum well,
d(∆QW )
= ∆JE − ∆JC .
dt
(2.12)
∆QW = ν0 ∆QE τ (1 − e−t/τ )
(2.13)
Solving Eq. 2.10−2.12 yields
where at t = 0 we assume ∆QW = 0, and τ is the electron lifetime in the quantum
well, which is defined as (νE + νC )−1 .
The electrons in the emitter that can tunnel into the quantum well through the
resonance state are those electrons whose longitudinal energy, EZ = ~2 kZ2 /2m∗ , are
resonant with the quantum-well ground-state energy. This corresponds with the
electrons indicated by the shaded disk in the E-k diagram of Fig. 2.4. The number
of these electrons is proportional to the shaded area of the disks, and to first order,
the area change is proportional to the bias voltage change. Thus, ∆QE can be
expressed as
∆QE = α∆V,
(2.14)
where α is a proportionality factor. Substituting Eq. 2.14 into Eq. 2.13 yields
∆QW = αν0 τ (1 − e−t/τ )∆V.
(2.15)
The change in the tunneling current density can then be written as
∆JC = αν0 νC τ (1 − e−t/τ )∆V
(2.16)
from which follows the differential conductance,
GD = A
∆JC
(t → ∞) = −Aqαν0 νC τ
∆V
(2.17)
where A is the device area. Thus, Eq. 2.16 can be rewritten as
∆JC =
GD
(1 − e−t/τ )∆V.
A
19
(2.18)
2
kX
∆(k Z ) = q∆V
*
2
2m
2
∆QE ∝ π ∆(k Z ) ∝ ∆V
∆kZ
kF
kZ
kY
Figure 2.4. The Fermi surface of the degenerate emitter electron gas. Tunneling
current is directed along the kZ direction. kF is the Fermi wave number in the
emitter and kZ is the electron wave vector projected onto the z-direction.
Eq. 2.18 can be transformed into the frequency domain to reveal the impedance
of the RTD. The Laplace transform of Eq. 2.18 is given by
∆JC (s) =
GD ∆V
,
A s(1 + sτ )
(2.19)
where ∆V (s) = ∆V /s. Thus, the impedance of the conduction current path is given
by
ZC (s) =
1
τ
∆V (s)
=
+s
.
A∆J(s)
GD
GD
(2.20)
From Eq. 2.20 the form of the equivalent circuit is apparently a differential conductance, GD , in series with a quantum inductance,
LQ =
τ
.
GD
(2.21)
Since the differential conductance is a function of the bias voltage, the quantum
inductance should be bias dependent.
20
The electrons stored in the quantum well image a positive charge in the collector. This mirrored charge changes with bias, resulting in a quantum capacitance.
Combining Eq. 2.15 and 2.17, the change in the image charge in the collector, ∆QC ,
is given by
∆QC = −∆QW = −
GD
∆V.
AνC
(2.22)
Therefore the corresponding quantum capacitance, CQ , is given by
CQ = A
∆QC
GD
.
=−
∆V
νC
(2.23)
The total capacitance, thus, can be expressed as
CP = C0 + CQ =
LW
GD
²A
−
+ 2LB + LD
νC
(2.24)
where C0 represents the geometrical capacitance, ² is the dielectric constant, and
LW , LB , and LD are the widths of the quantum well, barrier and depletion region,
respectively.
To verify this proposed equivalent circuit model, both dc I-V and microwave
frequency S-parameter measurements were made on AlAs/InGaAs/InAs RTDs with
dimensions as given in Fig. 2.3. The S-parameter measurements were made on
a coplanar microwave structure using 100 µm pitch ground-signal-ground probes
connected to a Raytheon 1.6 µm × 1.6 µm RTD in parallel with an integrated 25
Ω thin film resistor. The resistor was incorporated to suppress oscillations in the
RTD for biases in the NDR region. This RTD is the same as that shown in Fig.
2.1, which has the current through the parallel resistor removed by subtraction. In
this configuration, oscillations are circumvented, resulting in an accurate equivalent
circuit extraction through the NDR region and over the entire bias range.
S-parameters were measured from 45 MHz to 30 GHz, using an Agilent 8510XF
vector network analyzer with a port power of -33 dBm (corresponding to a maximum
21
peak-to-peak voltage at the device that is less than 30 mV). An Agilent 4155B semiconductor parameter analyzer was connected through the network analyzer’s bias
tee to provide the dc bias from 0 V to 0.81 V. A two-port LRM (line-reflect-match)
calibration was performed using a Cascade Microtech 104-783A W-band impedance
standard substrate (ISS). A Cascade Microtech 116-344 absorber was used to reduce
undesired mode content in the transmission lines and minimize external reflection.
As an example, Fig. 2.5 shows the measured S-parameter S11 and simulated S11
based on the proposed equivalent circuit at the bias V = 0.15 V (pre-peak region),
and 0.45 V (near the center of the NDR region). The simulation is in close agreement
with the measurement throughout the entire bias range.
22
0.06
-0.4
0.05
-0.42
-0.44
0.03
0.02
-0.46
Imag S11
Real S11
0.04
0.01
-0.48
0
(a)
-0.5
0
5
10
15
20
25
-0.01
30
Frequency (GHz)
0.02
-0.2
0.01
-0.22
-0.24
-0.01
-0.26
-0.02
-0.28
Imag S11
Real S11
0
-0.03
(b)
-0.3
0
5
10
15
20
25
-0.04
30
Frequency (GHz)
Figure 2.5. Comparison of measured (circles) and simulated (line) S-parameter at
two selected biases. (a) 0.15 V (pre-peak region); (b) 0.45 V (near the center of the
NDR region). To avoid being indistinguishable between the measured and simulated
curves, only 20% of the total 801 measured data points in each curve are shown.
23
Equivalent circuit parameters were extracted by fitting the measured S-parameter
data over the entire frequency and bias range. Fig. 2.6 compares the differential
conductance of the RTD, extracted from the S-parameter measurement, with the
derivative of the dc I-V curve. The differential conductance extracted from the
S-parameter measurement closely agrees with that extracted from dc I-V measure-
Differential Conductance, G D (mS)
ment.
20
15
10
5
0
-5
-10
0
0.2
0.4
0.6
0.8
Voltage (V)
Figure 2.6. Comparison of the differential conductance extracted from the dc I-V
measurement (line) and S-parameter measurements (circles).
24
The differential conductance in the pre-peak region in Fig. 2.6 shows a plateau
just below 0.2 V. This can be explained using Fig. 2.7, where the quantized state
E0 has a non-zero resonance width. The electrons in the emitter can tunnel into the
quantum well with a probability given by Eq. 2.3, drawn in Fig. 2.7. The shaded
area represents no corresponding electrons available in the emitter can tunnel into
the quantum well. Since the change in the differential conductance is proportional
to the change in the shaded area in Fig. 2.7(a), a higher differential conductance
occurs near zero bias, shown in Fig. 2.6. As the bias voltage, VA , increases and most
part of the probability curve would align below the Fermi level in the emitter, shown
in Fig. 2.7(b), the change in the shaded area would approach zero, resulting in a
constant differential conductance, i.e. a plateau in the I−V characteristic in Fig. 2.6.
Emitter
Well
Collector Emitter
Well
Collector
Probability
EF
1
E0
EF
E0
qVA
(a)
(b)
Figure 2.7. Schematic band diagram of the RTD at (a) equilibrium, and (b) an
applied bias voltage of VA .
25
Fig. 2.8 shows a comparison of the quantum inductance, LQ , extracted from the
S-parameter measurements and calculated from Eq. 2.21. Good agreement between
calculation and measured data is obtained with the greatest deviation observed
near the center of the NDR region. Since lifetime might be expected to vary with
bias, some deviations may be expected as in this model lifetime is assumed to be
constant. The extracted lifetime is 2.58 ps, which is comparable to the calculated
lifetime using Frensley’s Schrödinger-Poisson solver BandProf for the structure of
-1
Reciprocal of Inductance, L Q (nH )
Fig. 2.3 with a tunneling barrier of 1 nm and quantum well width of 3 nm.
8
6
4
τ = 2.58 ps
2
0
-2
-4
-6
0
0.2
0.4
0.6
0.8
Voltage (V)
Figure 2.8. The reciprocal of the quantum inductance, LQ , vs. bias showing good
agreement between extracted inductance from S-parameter measurements (circles)
and the unified ac model (line).
26
The total capacitance, CP , extracted from the S-parameter measurements and
calculated from Eq. 2.24 is plotted in Fig. 2.9. A similar close agreement is seen
in Fig. 2.9, where the escape rate, νC , is also assumed to be bias-independent, and
extracted to be (0.79 ps)−1 . The escape rate from the emitter to the quantum well
can be calculated from (1/τ −νC ) to be −0.88 ps−1 . This negative value indicates the
charge transfer direction is opposite to what has been assumed in the model. This
also indicates that the time constant which controls the charging and discharging
of the quantum well is longer than the electron lifetime in the quantum well. The
electron lifetime is typically associated with the process of electrons tunneling out
of the quantum well and results in a decrease in the quantum well charge. In this
model, the quantum well charge is increased by the tunneling-in process, thus the
change in the quantum well charge is controlled by the difference in the tunneling-in
and tunneling-out processes.
27
Capacitance, C P (fF)
40
35
30
25
C0 = 29.3 fF
20
1/ν = 0.79 ps
C
15
0
0.2
0.4
0.6
0.8
Voltage (V)
Figure 2.9. The total capacitance, CP , vs. bias showing close agreement between
extracted capacitance from S-parameter measurements (circles) and the unified ac
model (line).
28
2.1.4 RTD Maximum Frequency of Oscillation
To explore the RTD in high-speed applications, high-frequency performance of
the RTD must be characterized. The upper limit for the frequency at which the
RTD can be operated is given by the maximum frequency of oscillation, fmax , which
is defined as the frequency above which the magnitude of the diode S11 is below 0
dB. This definition indicates that at the frequency above the maximum frequency of
oscillation, the power gain of the RTD is below one, i.e. the RTD can no longer be
treated as an active device. An equivalent definition can also be found in Ref. [55],
where the maximum frequency of oscillation is defined as the frequency at which
the real part of the impedance of the RTD becomes zero.
Given the new equivalent circuit of the RTD in Fig. 2.2(d), the impedance of
the RTD can be expressed as
Z(ω) = RS + 1/[1/(RD + jωLQ ) + jωCP ],
(2.25)
where RD is the differential resistance, RS is the series resistance, CP is the total
capacitance including geometrical depletion capacitance and quantum capacitance,
and LQ is the quantum inductance, given by τ RD , and τ is the electron lifetime in
the quantum well. Letting the real part of the impedance equals to zero yields
4
2
2
2
ωmax
RD
CP2 τ 2 RS + ωmax
(RD
CP2 RS − 2RD RS CP τ ) + RS + RD = 0.
(2.26)
The maximum frequency of oscillation can be obtained by solving Eq. 2.26 for ωmax
(fmax = ωmax /2π),
s
p
2
RS2 CP2 − 4RD RS τ (RS CP + τ )
1 2RS τ − RD RS CP − RD
.
fmax =
2π
2RD RS CP τ 2
(2.27)
Similar expression can be found in Ref. [55], where Brown model [21] was used and
the quantum capacitance was neglected.
29
Equation 2.27 indicates that the maximum frequency of oscillation of the RTD
can be increased by reducing the election lifetime in the quantum well and the
capacitance. The lifetime can be reduced by thinning the barrier to provide an
energetically wider transmission resonance and a leakier quantum well. The capacitance can be reduced by increasing the depletion region width, which can be
done by employing a thicker spacer layer on the collector side of the RTD. However,
as the depletion region width increases, the transit time of the electron across the
depletion region will increase, and which can be estimated to be 10 fs/nm for the
InGaAs collector. For the structure in Table 2.1, the space layer is 2 nm and the
estimated collector depletion region transit time is 20 fs, therefore the transit time
effect is negligible.
To make it clear how the differential resistance affects the maximum frequency
of oscillation, a plot of the maximum frequency of oscillation as a function of the
differential resistance has been plotted, based on Eq. 2.27, in Fig. 2.10, where RS ,
CP , and τ (see inset of Fig. 2.10) are assigned constant values which can be achieved
in InP technology. Figure 2.10 indicates that the maximum frequency of oscillation
can be increased by reducing the value of the negative differential resistance. To
reduce the negative differential resistance, it is necessary to achieve a high peak
current, which can be achieved by reducing the barrier thickness. Further, the
differential resistance is dependent on the applied voltage. The minimum value of
the negative differential resistance can be obtained by biasing the RTD near the
center of the NDR region.
30
500
R =1Ω
S
C = 30 fF
P
τ = 1 ps
300
f
max
(GHz)
400
200
100
-1000
-800
-600
-400
R (Ω)
-200
0
D
Figure 2.10. The calculated RTD maximum oscillation frequency, fmax , vs. the
negative differential resistance, RD , where RS , CP , and τ are assumed to be constant.
Figure 2.11 shows the maximum frequency of oscillation as a function of the series resistance, where RD , CP , and τ are assigned constant values (see inset) which
can be achieved in InP technology. From Fig. 2.11, the maximum frequency of oscillation is achieved by minimizing the series resistance. The series resistance consists
of the metal-semiconductor contact resistances, the spreading resistance under the
contact, and the sheet resistance in the semiconductor between the emitter mesa
edge and the collector contact. For the structure in Table 2.1, the RTD collector
layer sheet resistance in the extrinsic collector region is the dominant component.
This extrinsic collector resistance can be reduced by decreasing the RTD emittercollector contact separation spacing.
31
600
R = -50 Ω
D
(GHz)
200
max
400
f
C = 30 fF
P
τ = 1 ps
0
0
2
4
6
8
10
R (Ω)
S
Figure 2.11. The calculated RTD maximum oscillation frequency, fmax , vs. the
series resistance, RS , where RD , CP , and τ are assumed to be constant.
32
2.2 Heterojunction Bipolar Transistor
2.2.1 HBT Heterostructure Design
The InP/InGaAs HBT has currently recorded the highest current gain cut-off
frequency, fT , and simultaneously measured maximum oscillation frequency, fmax ,
over 450 GHz, of any bipolar transistors [49]. This is not only attributed to the
high electron velocity in InGaAs, but is also a consequence of reduction of device
parasitics in the technology. The cut-off frequency, fT , is given by [60]
fT =
1
,
2π(τE + τB + τDC + τC )
(2.28)
where τE is the emitter charging time, τB is the base transit time, τDC is the collector
depletion layer transit time, and τC is the collector charging time. Using InGaAs
as a base material provides low base transit time, due to the high minority electron
mobility (2000−3000 cm2 /V·s) [63]. Further, the energy separation between the Γ
and L valley of InGaAs (∼ 0.55 eV ) is larger than the conduction band discontinuity
of the emitter-base junction (∼ 0.25 eV). The electrons, thus, can traverse the base
with a high injection velocity without intervalley scattering. The drawback of the
InP/InGaAs/InP double heterostructure is the “type I” straddling band lineup at
the base-collector junction. The conduction band discontinuity at the base-collector
junction blocks electrons entering the collector from the base, unless this barrier
is removed as for example by the incorporation of a set-back layer [61]. Quaternary step-grading of the base-collector has also been proposed and demonstrated to
suppress the blocking effect of the base-collector heterojunction [47, 62].
The band diagram of the InP/InGaAs DHBT is shown in Fig. 2.12. A lightlydoped (3×1016 cm−3 ) InGaAs set-back layer and a compositionally graded InAlGaAs
layer are introduced to eliminate the conduction band barrier at the base-collector
junction. The InGaAs base layer is also compositionally graded to form a quasi33
Emitter Base Collector Subcollector
1
Energy (eV)
EC
0.5
0
EF
-0.5
-1
E
-1.5
V
0
100
200 300 400
Position (nm)
500
600
Figure 2.12. Calculated energy band diagram of InP/InGaAs double heterojunction
bipolar transistor (computed using the Schrödinger-Poisson solver, BandProf, of W.
R. Frensley).
electric field, which increases the average electron drift velocity in the base, thereby
decreasing the base transit time. This graded base and collector structures shown
in Fig. 2.12 were designed by Intelligent Epitaxy Technology, Inc., Richardson, TX.
As an alternative, the GaAsSb/InP heterostructure offers a “type II” staggered
band lineup, shown in Fig. 2.13, which introduces no base-collector barrier. This
staggered band lineup requires no grading at the base-collector junction and provides a higher hole blocking barrier at the emitter-base junction. Compared with
InGaAs, the minority electron mobility in GaAsSb is low, 600−800 cm2 /V·s compared to 2000−3000 cm2 /V·s [63]. As a consequence, the GaAsSb base layer must
be thinner than the InGaAs base to achieve a comparable base transit time. This
thinner base may be expected to yield a higher base resistance, thus degrading the
34
EmitterBase Collector Subcollector
1
Energy (eV)
EC
0.5
0
EF
-0.5
-1
-1.5
EV
0
100
200 300 400
Position (nm)
500
600
Figure 2.13. Calculated energy band diagram of InP/GaAsSb double heterojunction
bipolar transistor (computed using the Schrödinger-Poisson solver, BandProf, of W.
R. Frensley).
maximum oscillation frequency, fmax , since fmax is inversely proportional to the
square root of the base resistance.
2.2.2 HBT SPICE Model
The Gummel-Poon (GP) model [64] has been used for a long time in the IC
industry for circuit simulation of the bipolar transistor, and it has been built into
commercial CAD software, such as HSPICE and ADS. The small-signal GummelPoon model is shown in Fig. 2.14, where rb , re , and rc are the base resistance, emitter
resistance, and collector resistance, respectively, rπ is the input resistance, rµ is the
base-collector resistance, Cπ is the base-emitter capacitance, Cµ is the base-collector
capacitance, and Csub is the collector-substrate capacitance. A detailed description
35
vµ
+
rµ
rb
rc
B
C
+
vπ
Cµ
rπ
Csub
Cπ
gmπvπ-gmµvµ
re
E
Figure 2.14. The small-signal Gummel-Poon model for an InP HBT.
of the Gummel-Poon model can be found in Getreu’s book [65].
The Gummel-Poon model is used here in the simulation of TDT circuits; and
model parameters are summarized in Table 2.3, where the dc model parameters
were fit from an InAlAs/InGaAs HBT from the 1998 UCSB Ph.D. thesis of B.
Agarwal. The junction depletion capacitances were calculated based on the device
geometry and the layer structures shown in Fig. 2.13, and the calculation equations
are discussed in Appendix B.
36
TABLE 2.3
InP HBT SPICE MODEL PARAMETERS FOR 1 µm2 DEVICE AREA
PARAM. VALUE UNITS
DESCRIPTION
BF
50
Ideal maximum forward current gain
BR
1
Ideal maximum reverse current gain
CJC
0.5
fF
Zero bias base/collector depletion capacitance
CJE
2.8
fF
Zero bias base/emitter depletion capacitance
CJS
0.0001
fF
Zero bias collector/substrate capacitance
EG
0.76
eV
Energy gap
FC
0.9
Forward bias depletion capacitance coefficient
IS
1.8
fA
Saturation current
ISC
0.14
fA
Base-collector leakage saturation current
ISE
0.36
fA
Base-emitter leakage saturation current
ITF
0
A
High current parameter for effect on TF
MJC
0.1
Base-collector junction grading coefficient
MJE
0.3
Base-emitter junction grading coefficient
MJS
0
Substrate-junction exponential factor
NC
1.1
Base-collector leakage current ideality factor
NE
1.2
Base-emitter leakage current ideality factor
NF
1
Base-emitter ideality factor
NR
1.1
Base-collector ideality factor
RB
100
Ω
Zero bias base resistance
PTF
2
Excess phase at f=1/2πf
RBM
100
Ω
Minimum base resistance at high currents
RC
6
Ω
Collector resistance
RE
10
Ω
Emitter resistance
TF
0.8
ps
Forward transit time
o
TNOM
27
C
Temperature
TR
10
ps
Reverse transit time
VAR
1
V
Reverse Early voltage
VAF
20
V
Forward Early voltage
VJC
0.7
V
Base-collector built-in potential
VJE
0.725
V
Base-emitter built-in potential
VJS
100
V
Substrate-junction built-in potential
XCJC
1
Fraction of Cjc goes to internal base pin
XTF
0
Coefficient for bias dependence of TF
XTI
1
Saturation current temperature coefficient
37
Shown in Fig. 2.15 are the dc model fits to the collector and base current data of
Agarwal. The emitter, base, and collector resistance are computed using a contact
resistivity of 3 × 10−7 Ωcm2 , a base sheet resistance of 1300 Ω/square, and baseemitter separation of 0.3 µm. The calculation equations are discussed in Appendix
B.
-2
10
SPICE model (line)
V =0V
-4
Current (A/µm2)
10
CB
IC
-6
10
I
B
-8
10
-10
10
data points from Agarwal
UCSB Ph. D. thesis 1998
Fig. 4.6
-12
10
0
0.2
0.4
0.6
Base-Emitter Voltage (V)
0.8
Figure 2.15. SPICE simulated Gummel plot and comparison with measured data.
The parameters used in the SPICE simulation are shown in Table 2.3.
38
The simulated common-emitter characteristic for the transistor model is shown
in Fig. 2.16. At the collector current density of 0.8 mA/µm2 , the dc current gain
is 16 and the output resistance is 8.8 kΩ. This small output resistance, indicated
by the large slope of the current-voltage characteristic in Fig. 2.16, arises from the
small early voltage in the model.
Collector Current (mA/µm2)
1
IB = 50 µA
0.8
40 µA
0.6
30 µA
0.4
20 µA
0.2
10 µA
0
0
1
2
Collector-Emitter Voltage (V)
Figure 2.16. SPICE simulated common-emitter characteristics. The parameters
used in the SPICE simulation are shown in Table 2.3.
39
The high frequency performance of the device is shown in Fig. 2.17. At the
current density of 1.35 mA/µm2 and the collector-emitter voltage of 2 V, the simulated cut-off frequency and maximum oscillation frequency are 165 GHz and 360
GHz, respectively. In the absence of experimental results at the beginning of this
work, these models were used to estimate the expected performance of the InP-HBT.
Gain (dB)
30
20
VCE = 2 V
VBE = 0.76 V
10
J = 1.35 mA/µm
fmax = 360 GHz
2
C
fT = 165 GHz
0
107
108
109
1010
1011
1012
1013
Frequency (GHz)
Figure 2.17. SPICE simulated small signal current gain and power gain frequency
dependence for a 1 µm2 device. The parameters used in the SPICE simulation are
shown in Table 2.3.
40
2.2.3 HBT Cut-Off Frequency and Maximum Oscillation Frequency
Useful figures of merit for the HBT are fT , the cut-off frequency, and fmax , the
maximum oscillation frequency. The cut-off frequency, Eq. 2.28, is defined as the
frequency at which the current gain is 0 dB. The four time constants determining
fT are τE , τB , τDC , and τC , and these ae summarized by Sunderland and Dapkus
[60]. The emitter charging time, τE , is given by
τE = (re +
VT
)(Cπ + Cµ ),
JE WE LE
(2.29)
where WE is the emitter width, and LE is the emitter length. The base transit time,
τB , is given by
τB =
XB2
,
2VT µnB
(2.30)
where XB is the base layer thickness and µnB is the minority electron mobility in
the base. The collector depletion layer transit time, τDC , is given by
τDC =
XC
,
2vsat
(2.31)
where XC is the collector depletion region width and vsat is the electron saturation
velocity in the collector. The last time constant, τC , is the collector charging time
and is given by
τC = rc Cµ .
(2.32)
The maximum oscillation frequency of the HBT is defined as the frequency at which
the unilateral power gain of the HBT equals unity, and is given by [66],
s
fT
fmax =
,
8πrb Cµ
(2.33)
where rb is the base resistance. The detailed discussions of calculating the cutoff frequency and maximum oscillation frequency of the HBT based on the device
geometry and layer structures are shown in Appendix B.
41
From Eq. 2.29−2.32, the cut-off frequency can be increased by lateral scaling
to decrease the emitter and collector charging time. It is also important to reduce
the base and collector depletion region transit time by reduce the base and collector
thickness. However, reducing the collector thickness will be traded off by lowering the breakdown voltage, and reducing the base thickness will increase the base
resistance, thereby decreasing the maximum oscillation frequency.
A reduction of the base resistance can be achieved by reducing the base-emitter
spacing, shown in Fig. 2.18, where the base resistance consists of three components:
the metal-semiconductor contact resistance, RBB , the extrinsic base resistance, Rbx ,
and the intrinsic base resistance, Rbi . Since the base is usually heavily-doped in heterojunction bipolar transistors, the metal-semiconductor contact resistance, RBB ,
can be small, as quantified in the upcoming example. Further, the base layer is designed thin to reduce the base transit time, thereby increasing the current gain and
cut-off frequency. Therefore the spreading resistances in the base semiconductor,
Rbx and Rbi , are usually dominant parts of the total base resistance. For example,
a 2 × 2 µm2 emitter InP/GaAsSb HBT with a 40 nm base doped to 4 × 1019 cm−3 ,
the intrinsic base resistance and the base contact resistance can be estimated to be
54 Ω and 4 Ω, respectively. For a base-emitter spacing of 1 µm, the extrinsic base
resistance is estimated to be 163 Ω. Decreasing the base-emitter spacing to 0.1 µm,
the extrinsic base resistance can be reduced to 16 Ω, and the total base resistance
will decrease by 66%.
42
XBE
WE
Emitter
Contact
Base
contact
Emitter
RBB
Base
Rbx
Collector
contact
Rbi
Collector
Subcollector
Figure 2.18. Schematic cross section of a heterojunction bipolar transistor.
43
CHAPTER 3
CIRCUIT DESIGN AND SIMULATION
This chapter summarizes the TDT differential comparator and the TDT frequency translator design and simulation. Tunnel diode circuit design using the
negative differential resistance and multi-stable I−V characteristics of the TD is
introduced in Section 3.1. A TDT differential comparator, utilizing the bi-stability
characteristic and the high switching speed of the tunnel diode, was invented in
this research. Circuit analysis and simulations show that the TDT differential comparator is faster and dissipates less power than its transistor-only counterpart. A
TDT frequency translation circuit based on Cellonics technology [41] is discussed in
Section 3.3. Adding a transistor to the frequency translation circuit increases the
frequency and the magnitude of the output signal, but decreases the input immunity.
3.1 Circuit Design Using Tunnel Diodes
The two unique attributes of the TD, the negative differential resistance and
the multi-valued current-voltage characteristic, along with its high-speed index are
attractive for circuit applications. The negative differential resistance enables the
creation of high-speed oscillators [68, 69]. The multi-valued I-V characteristic enables tunnel diodes to be used in logic circuits and memories [67, 25]. The basic
design concepts of these two categories of circuits are introduced as follows.
44
Tunnel diode oscillators can simply be obtained by biasing the tunnel diode
in the NDR region, and connecting the tunnel diode to a resonator. This type of
oscillator has been reported at frequencies as high as 712 GHz with an output power
density of 15 W/cm2 [68]. To increase the power, tunnel diode oscillator arrays can
be used. It has been reported that a 16-element InP-based Schottky-collector RTD
oscillator array produced a power density of 440 W/cm2 at 290 GHz [69].
The multi-stability characteristics of the tunnel diode can be exploited in highspeed digital application. In this case, the tunnel diode is biased out of the NDR
region, and the voltage switches between the stable states with high switching speed
due to the high speed index of the tunnel diode. A commonly used topology is the
clocked tunnel diode pair, Fig. 3.1, where the controlled-current source, ICT L , can
be implemented using a FET [9], an HBT [11], a photodiode [70], or other diodes
[67].
VCK
ICTL D2
VO
D1
Figure 3.1. Current-controlled clocked tunnel diode pair.
45
The operation of this tunnel diode bistable circuit can be understood through
the load lines, shown in Fig. 3.2. When the clock, VCK , is at a low level, the tunnel
diode pair is in a monostable state and the output voltage is low. When the clock
is high, the output node between the tunnel diodes is bistable, latching to either
a high or low voltage state, as determined by the tunnel diode peak currents and
the control current occurring at the rising edge of the clock. The peak current,
IP 2 , of the load diodes, D2 , is designed to be greater than the peak current, IP 1 ,
of the driver diodes, D1 , with the following relationship IP 2 < IP 1 + ICT L . This
relationship is set by the choice of device areas.
Driver Diode D
1
Current
Load Diode D2
ICTL
Load Diode D2
Driver Diode D1
Voltage
(a)
V
O
VCK
VO
Voltage
(b)
VCK
Figure 3.2. Load lines of the tunnel diode pair at two conditions: (a) ICT L is off;
and (b) ICT L is on.
46
In series-connected tunnel diodes, the diode with the lowest peak current switches
first in response to an applied voltage. Assuming the control current is off, Fig. 3.2a,
and the clock switches from low to high, the driver diode D1 switches because the
peak current of driver diode D1 is less than the peak current of load diode D2 . The
resulting output voltage, VO , is then in a high voltage state. If, on the other hand,
Fig. 3.2(b), the control current is on, and the clock switches from low to high, the
added control current through diode D2 causes load diode D2 to switch instead of D1 .
Diode D2 switches instead of D1 because of the design condition IP 2 < IP 1 + ICT L ,
and that the lowest current branch is the one to switch first. As a result, the output
remains in a low voltage state, Fig. 3.2(b).
3.2 Differential Comparator
Current-mode-switching differential comparators are widely used in high-speed
logic and mixed analog-digital circuits [71, 72, 73]. A conventional transistor-only
differential comparator is shown in Fig. 3.3 and consists of a differential transistor
pair, Q1 and Q2 , and output followers, Q3 and Q4 , which are used to buffer the
output signal. According to this circuit topology, there are limited options for
increasing the circuit speed. First of all, all the parasitics must be minimized. The
switching time of the differential pair is determined by the time delay at the input
node and output node, X. The time delay at the input node is inversely proportional
to the transistor’s transconductance. An increase in the tail current, IT AIL , can be
used to maximize transconductance. The transconductance maximum is limited by
the maximum power density of the technology. The time delay at the output node
is proportional to the collector resistance, RC , which can be reduced at the expense
of the output voltage swing which is equal to the product of the collector resistance
47
VCC
RC
Q3
Q4
X
VIN
VOUT
RL
RC
Q1 Q2
I1
ITAIL
VIN
VOUT
I2
RL
−VEE
Figure 3.3. Schematic of a conventional transistor-only differential comparator.
and the tail current.
A new approach using tunnel diodes in a differential comparator is shown in Fig.
3.4, where two tunnel diode pairs D1 −D3 and D2 −D4 are connected to the collector
outputs of the input differential transistor pair Q1 and Q2 . Emitter followers Q3
and Q4 are used to buffer the output signal.
The operation of this TDT differential comparator can be understood in terms
of the current-controlled clocked tunnel-diode pair discussed in Section 3.1. The
collector current of the input transistors, Q1 and Q2 , can be treated as the control
current. When the input to transistor Q1 is low, the tail current flows through
transistor Q2 . In this case, when the clock switches from low to high, driver diode
D1 switches because of the design condition IP 1 < IP 3 and the collector current of
transistor Q1 is off, resulting in a high voltage state at node X. If the input to
transistor Q1 is high, the tail current flows through Q1 . When the clock switches
48
VCC
D3
X
Q3
D4
CK
Q4
D1
D2
VOUT
VOUT
VIN
RL
Q1 Q2
I1
VIN
RL
I2
ITAIL
−VEE
Figure 3.4. Schematic of a tunnel diode/transistor differential comparator.
from low to high, the load diode D3 switches because of the design condition IP 3 <
IP 1 + IT AIL and as a result, node X remains at a low voltage state. This circuit
provides a return-to-zero (RZ) format output, which means the output is reset to
zero before the next pulse is generated.
The simulated output waveform of the TDT and transistor-only circuits of Figs.
3.3 and 3.4 are compared in Fig. 3.5. Each circuit has a bitstream applied as
indicated by the pattern of ones and zeros along the upper horizontal axis of the
figure. This bitstream has an amplitude of 400 mV with rising and falling time of
1 ps. The transistor-only circuit, which lacks the RZ format, is just sufficient in
49
1
0.2
1
0
1
0
1
0
1
1
1
V
OUT
(V)
0 (b)
-0.2
-0.4
-0.6
(a)
-0.8
0
20
40
60
80
100
t (ps)
Figure 3.5. Simulated output waveforms for the two comparator circuits of (a) tunnel
diode/transistor comparator, and (b) conventional bipolar transistor comparator.
speed to follow this waveform at 100 GHz. The TDT circuit which is clocked by a
100 GHz sinusoidal source achieves the RZ output. To drive the tunnel diode pair,
the off-chip clock may need to be buffered, e.g. using emitter followers, to the node
CK.
This TDT differential comparator circuit of Fig. 3.4 is faster and dissipates less
power than the conventional transistor-only differential comparator, Fig. 3.3. This
can be understood as follows. The open-circuit time constant at node X of the TDT
circuit of Fig. 3.4 is given by
τT DT ∼
= (RD1 //RD3 )(CBC1 + CBC3 + CD1 + CD3 ),
(3.1)
where, RD1 , RD3 and CD1 , CD3 are the resistances and capacitances of D1 and D3 ,
50
respectively, and CBC1 and CBC3 are the base-collector capacitances of Q1 and Q3 ,
respectively. The open-circuit time constant at node X of the transistor-only circuit,
Fig. 3.3, is given by
τT ∼
= RC (CBC1 + CBC3 ),
(3.2)
where RC is the collector resistance. For an equivalent output voltage swing at
node X of 600 mV and with a tail current of 1.5 mA, the transistor-only circuit
requires an RC of 400 Ω. With base-collector capacitance of approximately 0.5
fF/µm2 , the open-circuit time constant of the transistor-only circuit, τT , has a
magnitude of approximately 0.6 ps (CBC3 is typically larger in the transistor-only
circuit because a larger area output transistor is needed, as will be explained in the
next paragraph). In the TDT circuit, the parallel combination of the tunnel diode
resistance, RD1 //RD3 , is 60 Ω, and the tunnel diode capacitances (2 fF/µm2 ) added
to the base-collector capacitance at node X, result in an open-circuit time constant
of approximately 0.4 ps.
The total time delay of the differential pair can be expressed by
τD ∼
=
q
2
2
τIN
+ τOU
T,
(3.3)
where τIN is the time delay at the input and τOU T is the time delay at the output and
is equal to τT DT for the TDT circuit and τT for the transistor-only circuit. When the
TDT and transistor-only circuit operate at the same tail current, the input delay
for both circuits are identical and can be estimated by
CBE (Av + 1)CBC ∼ CBE
τIN ∼
+
+ τOU T ,
=
=
gm
gm
gm
(3.4)
where Av is the voltage gain, gm is the transconductance and equal to dIC /dVBE ,
and CBE is the base-emitter capacitance. Since the base-emitter capacitance is dominated by the diffusion capacitance as the transistor operates in the active region,
51
it can be estimated by
d(τf IC )
CBE ∼
= τf gm ,
=
d(VBE )
(3.5)
where τf is the forward transit time and is 0.8 ps from Table 2.3. From Eq. 3.3−3.5,
the total time delay of the differential pair is approximately 0.9 ps and 1 ps for the
TDT and transistor-only circuits, respectively. Therefore, the TDT circuit is faster
than the transistor-only circuit when they operate at the same tail current. In the
transistor-only circuit, speed improvements to equal the TDT circuit are obtained
by trading-off power and gain, i.e. by increasing the tail current and decreasing the
pull-up collector resistor.
Next consider the voltage gain of the output stage. The output of the differential
pair at node X in Fig. 3.4 can be replaced by a Thevenin equivalent voltage source,
VT H , in series with a Thevenin equivalent resistor equal to the output resistance,
RX , of the differential pair. The voltage gain of the output stage is given by
AV =
VOU T
=
VT H
1+
1
RX +rπ
(β+1)(RL //ro )
∼
=
1
1+
RX +rπ
(β+1)RL
,
(3.6)
where rπ is the input resistance of Q3 , ro is the output resistance of Q3 , RL is the load,
β is the ac current gain of Q3 , and ro À RL in the general case. From the previous
discussion, the output resistance is different in the two circuits, equaling RD1 //RD3
in the TDT circuit and RC in the transistor-only circuit and RD1 //RD3 < RC . To
obtain the same output voltage swing (voltage gain) in the two followers, the input
resistance, rπ , of Q3 in the transistor-only circuit has to be smaller than that in
the TDT circuit. Since rπ = βVT /IC , where VT is the thermal voltage, and IC is
the collector current of Q3 , the emitter follower in the transistor-only circuit has
to be biased at higher current, resulting in more power dissipation. Further, the
high collector current requires the transistor size to be increased, resulting in a
capacitance increase and speed reduction in the conventional circuit.
52
This TDT differential comparator is of special interest for use as a switching
element in direct digital synthesizers (DDS). A recently developed algorithm [74,
75], based on list decoding, for DDS provides an improved signal-to-noise ratio
(SNR), compared with conventional Σ∆ approaches. In both list decoding and Σ∆
approaches, a specially designed digital bitstream is output through a single-bit
digital-to-analog converter (DAC) and a reconstruction filter to form the analog
signal. The Fourier spectrum of the desired signal is embedded in the pattern of the
bitstream. A high-speed and high-linearity single-bit DAC is required to achieve
high SNR, because the severe distortion of the output signal is usually generated
from the nonlinearity of the DAC. The comparator circuits, proposed in this thesis,
are designed for use in such DDS applications.
To compare the power dissipation and linearity of both TDT and transistor-only
circuits, both circuits (Fig. 3.3 and 3.4) were simulated in Agilent ADS. The input
bitstream has a 100 Gbps bit rate, and an amplitude of 400 mV with rising and
falling time of 1 ps. The synthesized passband signal frequency is approximately
37.3 GHz. The simulated spectrums of the synthesized signal in both TDT and
transistor-only circuits are shown in Fig. 3.6. Approximately 60 dBc spur free dynamic range (SFDR) is obtained for both circuits, showing these two circuits have
approximately the same linearity. The power dissipation is reduced by approximately 4× in the TDT differential pair and 1.6× in the full TDT circuit. It is
reported that a conventional DDS utilizing a high speed, multi-bit DAC achieved
30 dBc SFDR, with a clock rate of 9.2 GHz, an output frequency of 4.56 GHz and
a power dissipation of 15 W [76]. The single-bit approach coupled with the TDT
comparator offers techniques to significantly lower power, improve speed, and extend
SFDR.
53
dB
100
80
60
40
20
(a)
32
34
36
38
Frequency (GHz)
40
42
dB
100
80
60
40
20
(b)
32
34
36
38
Frequency (GHz)
40
42
Figure 3.6. Simulated output spectrum of the synthesized passband signal for (a)
tunnel diode/transistor and (b) transistor-only differential comparator showing 60
dBc SFDR around 37.3 GHz. This simulation uses high speed InP-based HBT and
RTD models.
The TDT differential comparator has been layed out, as shown in Fig. 3.7. The
pads labeled IN and IN BAR were designed for the ground-signal-ground-signalground coplanar probe with 150 µm pitch size to provide the differential input
bitstream. The pads labeled OUT and OUT BAR were designed for the 150 µm
pitch ground-signal-ground (GSG) coplanar probes to output the synthesized sig54
nals. The pads labeled VEE, CLOCK, VCC, BIAS1, and BIAS2 were designed for
a special probe card, which has one 150 µm pitch GSG coplanar probe and seven
dc probes. The GSG probe will be connected to the pad labeled CK to provide the
clock signal and other dc probes will be connected to the dc pads to provide dc bias
for the circuit. The differential amplifier in the circuit was layed out symmetrically
to achieve equal phase delay in the two differential signals. Each dc pad was connected to a metal-dielectric-metal capacitor to obtain an ac ground. The resistors
were layed out assuming the resistivity of 25 Ω/2.
Figure 3.7. Layout for the RTD/HBT differential comparator. The circuit schematic
is shown in Fig. 3.4. Layout area is 1.8×1.1 mm2 .
55
Recently, it is noted that Yang’s group was working independently on the RTD/HBT
flip-flops utilizing the same circuit topology as in Fig. 3.4 for logic applications, and
demonstrated a 20-GHz single-ended input/output flip-flop [11] and a 10-GHz differential output flip-flop [77]. Their circuit was fabricated with InP/InGaAs single
heterojunction bipolar transistors (SHBTs) and AlAs/InGaAs/InAs RTDs using
optical lithography and the wet etching technique. The SHBT showed maximum fT
and fmax of 89 GHz and 133 GHz, respectively, and the RTD showed a peak current
density of 1 mA/µm2 and a peak-to-valley current ratio of 13 [77].
The demonstrated circuit [77] operated at 10 GHz with a power dissipation of
72.5 mW. The power dissipation is much higher than the simulation results in this
research [40], which might because the circuit is biased at high tail current. It is the
advantage of this TDT circuit that it can operate at a relative low tail current and
achieve the same speed compared to its transistors-only counterpart. Therefore, it
is expected to reduce the power dissipation by optimizing the circuit and device
design.
56
3.3 Frequency Translator
In 1918, Armstrong invented the superheterodyne radio receiver. To this day,
almost all radio and TV receivers being made are of this type. The receiver, Fig.
3.8(a), consists of an antenna, a radio-frequency (RF) section, a mixer and local
oscillator, an intermediate-frequency (IF) section, and a demodulator [78]. The incoming modulated wave is picked up by an antenna and amplified in the RF section.
The mixer and local oscillator convert the incoming signal to a predetermined intermediate frequency, which is lower than the incoming carrier frequency. The IF
section provides the amplification and selectivity. The output of the IF section is
applied to the demodulator to recover the baseband signal.
Antenna
RF
Section
IF
Section
Mixer
~
Demodulator
Local
Oscillator
(a)
Antenna
RF
Section
Frequency Translator/
Pulse Generator
Counter/
Decision
(b)
Figure 3.8. Schematic architectures of two types of receivers: (a) conventional
superheterodyne receiver [78] and (b) Cellonics receiver [41].
57
Cellonics Inc., Singapore, has recently invented a new demodulation technique
based on pulse generating and counting [41]. In the Cellonics receiver, Fig. 3.8(b),
a nonlinear circuit is used to generate pulses from the received signal and the demodulation is performed by counting the generated pulses. In the Cellonics circuit,
a slow time-varying input signal is converted to fast pulse trains. Cellonics calls this
process frequency translation.
The Cellonics receiver has several advantages over the conventional superheterodyne receiver [41]. First, no mixers, local oscillators or phase-locked loops (PLLs)
are needed in the Cellonics receiver, resulting in smaller chip area and lower power
consumption. In conventional receivers, thousands of carrier cycles are required to
extract one symbol because the receiver requires time to synchronize with the carrier signal. With Cellonics technology, information can be extracted in every carrier
cycle, which maximizes the transmission throughput.
The Cellonics frequency translation technology can also be used in the transmitter. Using the frequency translation circuit, the baseband signal is up-converted
to the RF frequency pulses with a tuned certain center frequency which is fit into
the FCC (Federal Communications Commission) specified band [79]. Similarly as
the Cellonics receiver, no mixers, local oscillators and PLLs are required in the
transmitter resulting lower power dissipation.
The Cellonics frequency translation circuit using the tunnel diode is shown in
Fig. 3.9 [79]. This circuit is, in essence, a tunnel diode oscillator circuit biased into
oscillation by a digital bitstream. When the input digital bit is at the low level, the
voltage applied to the tunnel diode, D1 , is less than the tunnel diode’s peak voltage,
resulting in an output low voltage. When the input digital bit is at a high level,
D1 will be biased in its NDR region, resulting in an oscillating output signal. The
oscillation frequency is determined by the inductor, L, and the capacitance of D1 .
58
D1
INPUT
OUTPUT
L
Figure 3.9. Cellonics tunnel diode frequency translation circuit diagram [79].
Since the tunnel diode is a two-terminal device, there is no isolation between
the input and output signals in the Cellonics frequency translation circuit. Here a
transistor is added to isolate the input and output signals. This circuit is shown in
Fig. 3.10 and works similarly to the Cellonics circuit. The simulated input-output
waveform of this TDT frequency translator is shown in Fig. 3.11. As the input
pulse signal voltage is at a low level, the output voltage is at a low level because the
transistor, Q1 , is off. As the input pulse signal switches to a high level, the tunnel
diode, D1 , is biased into its NDR region, resulting in an oscillating output signal. In
the simulation, an emitter follower is connected to the output of the TDT frequency
translator to drive the 50 Ω load, and the input voltage source resistance is 50 Ω.
59
VCC
L
Q1
INPUT
OUTPUT
D1
Figure 3.10. Notre Dame tunnel diode/transistor frequency translation circuit. The
circuit component and source values in the simulation are: L = 1 nH, VCC = 1 V,
and the HBT and RTD areas are both 2 × 2 µm2 .
1.6
1.6
Input
0.8
0.8
(V)
in
out
V (V)
V
Output
0
0
-0.8
0
200
400
Time (ps)
-0.8
600
Figure 3.11. Simulated output waveform for the tunnel diode/transistor frequency
translation circuit. Circuit component values are given in the caption of Fig. 3.10.
60
Since the negative differential resistance and the device capacitances are all bias
dependent, the frequency and magnitude of the output signal are both depended on
the input voltage. For the use of frequency translation, it is necessary to minimize
the frequency fluctuation according to the input variation. The simulated frequency
and magnitude of the output signal vs. the input voltage for both the Cellonics and
TDT frequency translation circuits are shown in Fig. 3.12. From Fig. 3.12, the
input voltage in the TDT circuit is approximately 0.7 V higher than that in the
Cellonics circuit, which is due to the transistor turn-on voltage is approximately 0.7
V.
By adding the transistor into the circuit, the frequency of the output signal
increases approximately by a factor of 2 and the output voltage magnitude increases
approximately 10%. The frequency is determined by the resonant in the circuit,
i.e. the inductance and capacitance. In the Cellonics circuit, the frequency is
determined by that series inductor, L, and the tunnel diode junction capacitance,
√
and is proportional to 1/ L. In the TDT circuit, the inductor is connected to the
base of the transistor, the equivalent inductance in the resonator should be equal to
p
L/(β + 1). Therefore, the output frequency is proportional to 1/ L/(β + 1), and
is higher than that in the Cellonics circuit for the same inductance.
From Fig. 3.12, it also can be seen that when the input voltage varies by 1%,
the maximum change in the output frequency is 0.7% and 0.5% in the TDT and
Cellonics circuit, respectively. In summary, adding a transistor into the Cellonics
frequency translation circuit provides isolation and power gain. The drawback is
that it degrades the immunity to the input voltage variation and increases the input
voltage.
61
15
600
10
400
5
200
0.4
0.5
(mV)
(a)
0
0.3
out, peak-to-peak
Frequency (GHz)
800
V
20
0
0.6
40
800
30
600
20
400
10
200
1
1.1
1.2
(mV)
(b)
0
out, peak-to-peak
V
Frequency (GHz)
Vin (V)
0
1.3
Vin (V)
Figure 3.12. Simulated frequency and magnitude of the output signal vs. the
input voltage for (a) the Cellonics frequency translation circuit of Fig. 3.9, and (b)
the tunnel diode/transistor frequency translation circuit of Fig. 3.10. The circuit
component values in the simulation are: L = 1 nH, VCC = 1 V, and the RTD area
is 2 × 2 µm2 .
62
It is noted that the circuit topology proposed by De Los Santos [29] can also
be used for the frequency translation, and the output frequency is proportional
√
to 1/ L. Therefore, in this research, connecting the inductor to the base of the
transistor can achieve higher output frequency compared to Cellonics and De Los
Santos circuits when they use the same inductance.
The TDT frequency translator has been layed out, as shown in Fig. 3.13. The
pads labeled OUT are designed for the 150 µm pitch GSG coplanar probes to output
the signals. The pads labeled VEE, VCC, and BIAS were designed for connecting
the dc probes to provide bias for the circuit. Each dc pad was connected to a
metal-dielectric-metal capacitor to obtain an ac ground. The resistors were layed
out assuming the resistivity of 25 Ω/2. The unlabeled pad beside the BIAS pad
was connected to the base of the transistor, and the wire inductor will be bonded
between this pad and the BIAS pad.
63
Figure 3.13. Layout for the RTD/HBT frequency translator. The circuit schematic
is shown in Fig. 3.10. Layout area is 0.8×0.5 mm2 .
64
CHAPTER 4
SELF-ALIGNED NITRIDE SIDEWALL PROCESS
To fabricate the TDT circuits, a new self-aligned contact process was demonstrated for the first time. The novelty of this process is using silicon nitride sidewalls
and a BCB etchback to obtain self-aligned emitter-base contacts. In this Chapter,
prior art in self-aligned emitter-base contact formation is first reviewed, Section 4.1.
The process developed in this research is outlined in Section 4.2. Two key steps of
this new process are the nitride sidewall formation and the BCB etchback process
and these are shown in detail in Section 4.3. Section 4.4 discusses the fabrication of
the InP/InGaAs DHBTs. Device test results prove the feasibility of this new sidewall and etchback process. Fabrication and testing of AlAs/InGaAs/InAs RTDs is
shown in Section 4.5
4.1 Process Overview
As discussed in Chapter 2, it is necessary to reduce the extrinsic base resistance
to increase the maximum oscillation frequency of the device, and the extrinsic base
resistance is proportional to the base-emitter contact spacing, therefore a self-aligned
contact process is required to minimize the emitter-base contact spacing. Prior
published self-aligned base-emitter contact processes are often based on either wetetching and lift-off [46, 49], or emitter and base regrowth [80, 81], and are considered
65
to have process yield limitations [82]. In the wet-etching and lift-off process, the
base-emitter separation, XBE , is critically depended on the emitter mesa lateral
etch from the wet chemical etchant, a process which is difficult to precisely control.
Further in the lift-off process, metal stringers are easily left which can short the baseemitter junction [73]. Therefore, the wet-etching and lift-off process is undesirable
for volume manufacturing of large-scale circuits consisting of thousands of submicron
devices with high yield [82]. As for the emitter or base regrowth process, additional
masks and surface cleaning before the regrowth are introduced, which increases the
process complexity and expense.
Recently, Vitesse [48] and Rockwell Scientific [83] have demonstrated high performance HBTs using dielectric-sidewall processes for the self-aligned emitter-base
contacts. Dielectric sidewalls allow the emitter mesa undercut to be minimized
and eliminates the lift-off process for the base metallization, resulting in high yield.
In Vitesse’s process, dielectric sidewalls are used for the emitter-base contacts, and
their Inp DHBT has demonstrated fT and fmax both over 300 GHz [48]. In Rockwell’s
process, the dielectric sidewall is also used for the emitter-base contact separation,
and a selective-base electroplating is required for the base contact. HBTs fabricated
in the Rockwell process have demonstrated 326 GHz fT and 305 GHz fmax [83].
In this work, a new self-aligned contact process using silicon nitride sidewalls
and a BCB etchback has been developed and is outlined as Figs. 4.1 and 4.2.
The emitter contact lithography and metallization uses in a lift-off process using
Ti/Pt/Au as the emitter contact metals, Fig. 4.1(a). The emitter mesa is etched in
a wet chemical etchant using the emitter contact as the etch mask, Fig. 4.1(b). The
silicon nitride sidewall is formed by depositing a PECVD Si3 N4 film, followed by an
anisotropic RIE etch in an SF6 /Ar plasma, Fig. 4.1(c). To form the base contact,
tungsten is blanket sputtered on the wafer, Fig.4.1(d). The surface is planarized by
66
200 nm
Emitter
Metallization
(a)
Ti/Pt/Au
Emitter
Collector
Base
Emitter Etch
Metal as Etch Mask
(b)
Ti/Pt/Au
Emitter
Collector
Base
Si3N4 sidewall
Silicon Nitride
Sidewall Formation
(c)
Ti/Pt/Au
Emitter
Collector
Base
W
Base Metal
Deposition
(d)
Ti/Pt/Au
Si3N4
Emitter
Si3N4
Collector
Base
Figure 4.1. Scale drawings of self-aligned emitter-base contact formation using a
nitride sidewall spacer. These drawings describe: (a) the emitter metallization, (b)
the emitter mesa etch, (c) the silicon nitride sidewall formation, and (d) the base
metal deposition.
67
Benzocyclobutene
(BCB)
BCB Deposition
(a)
W
Ti/Pt/Au
Si3N4
Emitter
Si3N4
Collector
Base
W
BCB
BCB
BCB Etchback
(b)
Ti/Pt/Au
Si3N4
Emitter
Si3N4
Collector
Base
BCB
W RIE Etch
BCB as Etch Mask
(c)
BCB
Ti/Pt/Au
W
Si3N4
W
Si3N4
Collector
Base
BCB Removal
(d)
Emitter
Ti/Pt/Au
W
Si3N4
Emitter
W
Si3N4
Collector
Base
Figure 4.2. Scale drawings of self-aligned emitter-base contact formation using a
nitride sidewall spacer. These drawings describe: (a) the BCB deposition, (b) the
BCB etchback, (c) the tungsten RIE etch, and (d) the removal of the BCB.
68
spinning on BCB followed by a reflow at 250 ◦ C for one hour, Fig. 4.2(a). The BCB
is then RIE etched in an SF6 /O2 plasma and the etch stops as soon as the tungsten
on top of the emitter mesa appears, Fig. 4.2(b). This part of the tungsten which
is on the top of the emitter mesa is etched off in an SF6 /Ar plasma and the base
contact metal is protected by the remaining BCB, 4.2(c). After removing the BCB,
the self-aligned emitter-base contact is obtained, Fig. 4.2(d). The collector contact
is formed by a lift-off process. The detailed description of the sidewall formation
and the BCB etchback is shown in the next section.
Optical micrographs of a fabricated 4×4 µm2 emitter InP/InGaAs HBT with
the sidewall process are shown in Fig. 4.3. It can be seen that the base metal wraps
around the emitter metal. The base and collector contacts are non-self-aligned and
the spacing is 2 µm. The opening in the collector metal was designed to assist the
acetone flowing and ease the metal lift-off process.
In addition to the device formation, the circuits of interest have required on-chip
resistors and capacitors. A 30 nm titanium thin film is deposited in a lift-off process
as the on-chip resistor. The on-chip metal-dielectric-metal capacitor is formed by
metal lift-off processes and a 300 nm PECVD silicon nitride deposition. The detailed
process flow is summarized in Appendix A.
69
Emitter
Emitter
Base
Emitter
Base
Collector
Figure 4.3. Optical micrographs of a 4x4 µm2 emitter HBT. The graphs show the
step-by-step HBT emitter, base and collector contact formation.
70
4.2 Nitride Sidewall Formation and BCB Etchback Process
The silicon nitride sidewall spacer is formed using an anisotropic etch for silicon
nitride. Different etch recipes, using SF6 , CF4 , or CHF3 , have been investigated.
The best sidewall process was achieved using an anisotropic etch for silicon nitride
in an SF6 /Ar plasma.
The silicon nitride film is deposited in a Unaxis 790 PECVD system with the
following recipe established by Shishir Rai: SiH4 /NH3 (40/4 sccm), 500 mTorr, 200
W, 250 o C. The nitride deposition rate is ∼ 20 nm/min.
To obtain a well-defined nitride sidewall, an anisotropic RIE process with a wellcontrolled etch rate is required. Silicon nitride etching is often performed using a
fluorine-producing gas, such as CF4 , SF6 , or CHF3 [84, 85, 86], and all three of
these gases were investigated; silicon nitride sidewalls were successfully observed
producing using CHF3 and SF6 , but not with CF4 .
Mele et al. [84] discussed anisotropic etching profile using CHF3 as the reactive
ion etchant. They suggest that CHF3 decomposes in the plasma to form a polymer
which deposits on the sidewall to suppress lateral fluorine etching [84]. However,
this polymer deposition on the surface causes the nitride etch rate to decrease as a
function of time [84], which increases the difficulties of etch time control.
To investigate the etch rate of the RIE etch for silicon nitride in the CHF3 plasma,
a 300 nm thick silicon nitride film was patterned with AZ1813 photoresist as the
etch mask. Samples were etched in a Plasma-Therm RIE 790 system for different
times, and after removing the photoresist, step-profiling was used to obtain the etch
depths vs. etch times, Fig. 4.4. The etch rate is approximately 6 Å/s and decreases
as a function of time.
To investigate the nitride sidewall formation using CHF3 , Ti/Au patterns were
formed using a lift-off process on a GaAs substrate, followed by depositing and
71
300
y = 38.625x R= 0.9898
Etch Depth (nm)
250
Etch Rate: 0.6 nm/s
200
150
100
50
CHF 20 sccm, 15 mT, 250 W
3
0
0
2
4
6
Etch Time (min)
8
10
Figure 4.4. RIE etch characteristic of silicon nitride in CHF3 .
etching a PECVD silicon nitride film in a CHF3 plasma. The deposited silicon
nitride thickness was 300 nm, and an over-etch factor of 1.4 was used. An SEM
micrograph, Fig. 4.5, shows the presence of the sidewall. However, the surfaces of
the GaAs substrate and the Ti/Au mesa are rough, which may because of a polymer
or silicon nitride residue. Since the etch rate is dependent on the polymer deposition
so that it decreases with time and is not repeatable, it is difficult to control the etch
time to obtain sidewalls with smooth surface using CHF3 .
Anisotropic etching of silicon nitride can also be achieved using an SF6 plasma,
which yields a more linear etch rate compared to using CHF3 , because no carbon
polymer is formed in the plasma. The same procedure, as described above, was
performed to determine the silicon nitride etch rate in the SF6 /Ar plasma, and the
result is shown in Fig. 4.6. Argon is used to improve the anisotropy of the etching.
The etch rate is estimated to be 17 Å/s, and is more constant and faster than using
72
SiNx
Ti/Au
GaAs
Figure 4.5. SEM micrograph of the silicon nitride sidewall on a GaAs substrate.
Silicon nitride is RIE etched in CHF3 plasma.
CHF3 .
An SEM micrograph of the nitride sidewall formed using SF6 /Ar is shown in Fig.
4.7. The deposited silicon nitride was 300 nm, an over-etch factor of 1.2 was used,
and the sidewall thickness was about 150 nm. The ratio of the vertical etch rate to
the lateral etch rate is approximately 2:1, which means to obtain a certain thickness
of sidewall, a doubled sidewall thickness of deposition is indicated. Compared to
Fig. 4.5, the GaAs and Ti/Au surfaces are smoother after the sidewall etch using
SF6 /Ar even with a smaller over-etch factor. Therefore, for this work, SF6 /Ar was
selected for the RTD/HBT process development.
73
Etch Depth (nm)
250
SF6/Ar: 2/18 sccm
200
15 mTorr, 150 W
150
100
50
Etch Rate: ~ 1.7 nm/s
0
0
50
100
Etch Time (s)
150
Figure 4.6. RIE etch characteristic of silicon nitride in SF6 and Ar.
Figure 4.7. SEM micrograph of the silicon nitride sidewall on a GaAs substrate.
Silicon nitride is RIE etched in SF6 /Ar plasma.
74
To investigate the BCB etchback process, first the BCB RIE etch rate was calibrated. The BCB was spun on the wafer with a spin speed of 5000 rpm for 30 s,
followed by a re-flow process in a Unaxis 790 PECVD system in nitrogen environment at 250 o C with the nitrogen pressure of 1 Torr and the flow rate of 500 sccm
for 1 hour. The BCB film thickness was measured to be approximately 1.3 µm.
The BCB was patterned with AZ1813 photoresist as the etch mask. Samples were
etched in a SF6 /O2 plasma for different times, and after removing the photoresist,
were step-profiled to obtain the etch depths for different etch times, Fig. 4.8. The
etch rate was found to be 3 nm/s.
1200
SF /O : 3.33/30 sccm,
6
Etch Depth (nm)
1000
2
300 mTorr, 60 W
800
600
400
200
Etch Rate: ~ 3 nm/s
0
0
1
2
3
4
5
Time (min)
Figure 4.8. RIE etch characteristic of BCB in SF6 and O2 .
75
6
7
The BCB etchback process was investigated on a AlGaAs/GaAs HBT pilot wafer.
The Ti/Au was formed by a lift-off process. The emitter mesa was defined by a wet
chemical etch in 1H2 SO4 :8H2 O2 :160H2 O using the emitter metal as etch mask. The
silicon nitride sidewall was formed by depositing and etching a nitride film in SF6 /Ar.
The silicon nitride deposition and etch conditions are the same as described above.
300 nm titanium and tungsten were sputtered for the base metal contact. BCB was
then deposited and etched back in SF6 /O2 using the same conditions as described
above. The etch stopped as the tungsten on top of the gold appeared, which can
be determined by step profiling of the emitter mesa. The SEM micrograph of this
etchback process is shown in Fig. 4.9. From Fig. 4.9, it can been seen that the
emitter mesa is lateral etched. It also can be seen that the emitter and base contacts
are separated by the silicon nitride sidewall, and the BCB surface is flat and can be
used as the etch mask in the following step of RIE etching off Ti/W on the top of
the emitter mesa.
Ti/Au
Ti/W
BCB
emitter mesa
SiNx
1.5 µm
Figure 4.9. SEM micrograph of the BCB etchback process on an AlGaAs/GaAs
HBT wafer.
76
4.3 DHBT Fabrication
The DHBT structures were grown by Intelligent Epitaxy Technology, Inc., Richardson, TX. The structures consist of a 50 nm InP emitter (Si: 3×1017 cm−3 ), a 40 nm
graded InGaAs base (C: 5×1019 cm−3 ), a 110 nm InP collector (Si: 3×1016 cm−3 ),
and a 200 nm InP subcollector (Si: 3×1019 cm−3 ). A 20 nm InGaAs setback layer (Si:
3×1016 cm−3 ) and a 24 nm compositional graded InAlGaAs layer (Si: 3×1016 cm−3 )
are used to suppress the current blocking at the base-collector junction. Heavily
doped InGaAs ohmic contact layers (Si: 3×1019 cm−3 ) are used for the emitter and
subcollector contacts.
The silicon nitride sidewall and BCB etchback process was used to fabricate the
InP/InGaAs DHBT. A representative measured Gummel plot is shown in Fig. 4.10.
From Fig. 4.10, the ideality factors of the base current and the collector current
are extracted to be 1.4 and 1.1, respectively, and which are close to those shown in
[49]. The dc current gain is extracted to be 51 at the base-emitter voltage of 0.8 V,
which achieves the expectation from the model that the maximum current gain is
50. The saturation current can also be extracted to be 34 fA, which is 20x larger
than that in the model.
77
-3
10
(20) µm
2
V
C
B
I , I (A)
10-5
BC
2
I
C
=0
I
-7
B
10
-9
10
n = 1.1
C
n = 1.4
B
-11
10
0.2
0.4
0.6
V
BE
0.8
(V)
Figure 4.10. Measured Gummel plot of an InP/InGaAs double heterojunction bipolar transistor with nitride sidewall process.
78
A measured dc IC −VCE characteristic is shown in Fig. 4.11. The low slope
in the saturation region indicates a large emitter or collector resistance, which is
approximately 30 Ω. Since during the fabrication, the thin InGaAs subcollector
(10 nm) was unexpectedly exposed to the O2 plasma, this InGaAs layer may be
damaged and result in a large contact resistance.
Micro-scale devices were not yielded in this process because of the difficulties in
the bondpad process. Devices with emitter dimensions of 2 µm and 4 µm shorted
due to an excessive lateral etch in the via process (approximately 2.6 µm more than
expected). Increasing the plasma power and reducing the SF6 pressure is expected
to reduce the lateral etch. DC test results on larger area transistors have demonstrated the feasibility of this nitride sidewall and BCB etchback process.
79
30
2
(20) µm
400 µA
2
25
300
15
200
C
I (mA)
20
10
100
5
I =0
B
0
0
0.5
1
1.5
V (V)
2
2.5
3
CE
Figure 4.11. Measured common-emitter IC −VCE characteristic of an InP/InGaAs
double heterojunction bipolar transistor with nitride sidewall process.
80
4.4 RTD Fabrication
To establish a suitable high current density AlAs/InGaAs/InAs RTD growth
process, RTDs were grown at IntelliEPI, and fabricated and tested at Notre Dame.
For this RTD development, a non-self-aligned process was performed. A 200 nm
Ti/Au was formed by a lift-off process for the RTD emitter contact. The RTD
structure was etched in 1H2 SO4 :8H2 O2 :160H2 O using the emitter metal as a mask.
The etch is nonselective and was terminated by dead reckoning just pass the double
barrier. DC I−V measuremenst were performed to determine the RTD peak current
density. Shown in Fig. 4.12 is an example of the RTD DC test structure, where
two probes were placed on two adjacent pads with different areas. This test configuration is equivalent to two RTDs with different areas back-to-back connected, and
most of the voltage drop appears across the smaller emitter area device.
Probe
InGaAs
(10)2 µm2
Au
(20)2 µm2
Au
80 x 475 µm2
Au
(10)2 µm2
80 x 475 µm2
Ti/Au
Ti/Au
RTD
RTD
InGaAs
InP HBT Emitter
Top view
Side view
Figure 4.12. Resonant tunneling diode DC test structure, (a) top view, (b) side
view.
81
The measured I−V characteristics of two RTDs with different barrier thickness
are shown in Fig. 4.13 (Other layer structures are shown in Table 2.1). A double
sweep technique (forward and backward sweep) was used due to the high series
resistance which originates from the high sheet resistance between the two test pads.
The estimated sheet resistance is approximately 25 Ω, which is close to the measured
result of 30 Ω. The forward bias corresponds to positive voltage on the smaller area
emitter pad. The peak voltages and currents for forward and reverse biases differ,
which indicates that the two barriers are asymmetric in thickness, composition or
strain. If the difference is solely due to thickness, since the barrier close to the RTD
emitter will have the greatest barrier height and will therefore limit the current the
most, the barrier close to the RTD collector, for both diodes, is thicker than the
barrier close to the RTD emitter. The peak current density increases by a factor of 4
between the two RTDs of Fig. 4.13 and the peak-to-valley current ratio degrades by
a factor of 4.5 when the barrier thickness reduces from 1.7 nm to 1.6 nm because the
tunneling current exponentially depends on the barrier width. For the TDT circuit,
a peak current density of 1 mA/µm2 and a peak-to-valley current ratio greater than
2 are needed, which are close to the test results on wafer 060745A3AA01. It is
reported that AlAs/InGaAs/InAs RTDs can achieve a peak current density of 1
mA/µm2 with a peak-to-valley current ratio of 13 [77].
82
0.04
0.02
Wafer ID: 060745A3AA01
Barrier Thickness: 1.6 nm
(10) µm Emitter
2
2
0.02
Current (A)
Current (A)
0.04
Wafer ID: 060729A2BA02
Barrier Thickness: 1.7 nm
0
-0.02
JP = 0.46 mA/µm
-0.06
2
2
0
PVR = 1.8
-0.02
PVR = 8.2
-0.04
(4) µm Emitter
J = 1.8 mA/µm2
2
P
-0.04
-2
-1
0
Voltage (V)
(a)
1
-2
2
-1
0
Voltage (V)
1
2
(b)
Figure 4.13. Measured current-voltage characteristics of the resonant tunneling
diodes on wafers: (a) 060729A2BA02, (b) 060745A3AA01.
83
CHAPTER 5
SUMMARY AND CONCLUSIONS
5.1 Summary of Achievements
Since 1990s, TDT technology has demonstrated potential in high-speed and lowpower applications, such as logic, signal processing and communications. In this
research, two new ways of using tunnel diodes have been investigated. In the course
of this investigation, the TDT differential comparator and the TDT frequency translator were conceived, designed, and simulated.
In the TDT differential comparator circuit, two clocked tunnel diode pairs were
connected to the output ports of the differential amplifier, which enables the TDT
comparator to operate at a lower tail current while achieving the same specifications
compared to the transistor-only comparator. InP-based RTDs and HBTs were used
in the mode simulation. Simulation results showed power dissipation reduced by
approximately 1.6× with the TDT approach at 100 GHz clock frequency. In this
research, the designed TDT comparator was of special interest for the single-bit
oversampling DAC for DDS applications. The circuit topology can also be used in
other low-power applications, e.g., in flip-flops and logic gates.
The TDT frequency translation circuit, consisting of a tunnel diode, a transistor, and an inductor, was designed for use in communication systems to upconvert
digital signals. This circuit functions as a frequency translator without a separate
mixer, local oscillator or PLLs, which can lead to smaller chip area and lower power
84
dissipation. Compared to the prior art based on tunnel diode alone, the added
transistor provides input/output isolation and power gain.
To fabricate these TDT circuits, a new self-aligned contact process utilizing
silicon nitride sidewalls and a BCB etchback was developed. This process allows
scaling of the transistor access resistance to achieve the frequency response needed
for circuit demonstrations and beyond. A baseline silicon nitride sidewall process
was established with an anisotropic etch for silicon nitride using an SF6 /Ar plasma,
and a baseline BCB etchback process was also developed. InP/InGaAs DHBTs were
fabricated using this sidewall process, and results from dc current-voltage measurements demonstrated the feasibility of this new process. AlAs/InGaAs/InAs RTDs
were also fabricated in a non-self-aligned process and demonstrated a peak current density of 1.8 mA/µm2 and a peak-to-valley current ratio of 1.8, close to the
requirements for circuit demonstrations.
In addition, a unified RTD small-signal equivalent circuit model was developed
to enable the circuit designs of this research. Analytic expressions for both the
quantum inductance and quantum capacitance were derived by a new approach.
The equivalent circuit model was verified by both DC I-V and microwave frequency
S-parameter measurements on Raytheon’s AlAs/InGaAs/InAs RTDs from 45 MHz
to 30 GHz. Based on this new finding, the high frequency response of the RTD
was investigated, which allowed a better understanding of the highest operation
frequency that the RTD can achieve.
As shown from the results of this investigation, TDT technology has advantages
in increasing circuit speed, reducing power dissipation and reducing circuit components for specific applications. However, there remain challenges and difficulties to
be overcome for the wider implementation of TDT technology. First, the operating
point of the TDT circuit critically depends on the peak current of the tunnel diode.
85
Since the peak current depends exponentially on the barrier thickness for RTDs and,
if one considers the possible extension of this technology to Si, the junction width
for the Esaki diode, it remains difficult to obtain reproducible device characteristics.
Accurately controlled uniform barrier thickness or junction width must be achieved.
In III-V technology, RTDs grown by MBE have shown well controlled and uniform
barriers, however these must be matched to the transistor currents in order to yield
circuits. In Si technology, no CMOS-compatible process has yielded characteristics
for Esaki diodes suitable for other than small scale circuit development. Furthermore, compared to CMOS digital circuits, the off current in TDT logic circuits will
be a few orders of magnitude higher because the tunnel diode cannot be completely
shut off. For these reasons, the integration of the tunnel diode with CMOS for
digital applications appears less attractive.
Reported high-speed III-V HBTs with fT and fmax over 300 GHz all operate at
a high current densities (> 4 mA/µm2 ) [46, 47, 48, 49]. Tunnel diode will need to
have a comparable peak current density, otherwise, the transistor has to operate at
a lower current density which will slow down the entire circuit speed. For silicon
tunnel diodes, the highest reported peak current density is 1.5 mA/µm2 , grown by
MBE [87]. For III-V RTDs, the highest reported peak current density is 6.8 mA/µm2
[43]. As the RTD operates at such high current density, the thermal stability needs
to be investigated because the RTD is usually grown on top of a transistor, and
there are several layers in the transistor which have poor thermal conductivities.
The thermal reliability of the tunnel diode is not well explored to date.
Overall, the TDT technology in III-V compound semiconductor is close to production for specific applications which require simultaneously high-speed and lowpower. In silicon, until a manufacturable process is developed for integrating the
tunnel diode with CMOS, CMOS technology will remain preferable.
86
5.2 Recommendations for Future Research
The Gummel-Poon model is used for the circuit simulation in this research.
Since the GP model is developed for Si BJTs, it can not accurately predict some
characteristics of InP HBTs. For examples, the base-collector capacitance are not
bias dependant as the collector is fully depleted. The conduction band barriers
at the base-emitter and base-collector junction of the InP/InGaAs DHBT are bias
dependant and will affect the base and collector current-voltage characteristics. A
more accurate SPICE model for the InP HBTs needs to be investigated for circuit
simulation and the model parameters should be extracted from the measurements
of HBTs.
The via process needs to be improved to yield the TDT circuits. During the via
etch process, the lateral etch needs to be minimize, thereby preventing a shorted
emitter-base contacts formed in the bondpad process. For the 2 µm emitter transistor, the lateral etch should be less than 100 nm and for the 4 µm emitter transistor,
the lateral etch should be less than 1 µm. To increase the transistor speed, further
scaling of the transistor size is required. The sidewall process for submicron devices
can be investigated using the e-beam lithography.
The process developed in this work self-aligns the base-emitter junction. By
extension it is possible to self-align both base and collector to the emitter metallization. Here, a new fully self-aligned process using silicon nitride-sidewalls and
metal reactive ion etching has been conceived for the submicron HBT fabrication.
The fabrication sequence is outlined as follows, shown in Fig. 5.1 and 5.2. The process starts with a blanket deposition of tungsten. The tungsten is patterned with
photoresist as the etch mask. The tungsten is then RIE etched to form the emitter
contact, Fig. 5.1(a). The emitter mesa is etched using the emitter contact as the
etch mask, Fig. 5.1(b). A silicon nitride sidewall is formed by depositing a PECVD
87
Si3 N4 film, followed by an anisotropic RIE etching, Fig. 5.1(c). To form the base
contact, tungsten is first blanket sputtered on the wafer, Fig. 5.1(d), followed by an
anisotropic RIE etching to form the tungsten base contact, Fig. 5.1(e).
Next the base and collector are etched using the tungsten as the etch mask,
Fig. 5.2(a). Forming a silicon nitride sidewall around the base mesa using a similar
process as that for the emitter sidewall, Fig. 5.2(b). Finally, blanket sputtering, Fig.
5.2(c), and anisotropically RIE etching of tungsten to form the collector contact,
Fig. 5.2(d).
This proposed process has several notable attributes. Only one mask is required
in the front-end process, which reduces lithography-induced errors. The fully selfaligned contacts enable the extrinsic resistances to be minimized. The metal lift-off
process at the emitter, base, and collector levels is eliminated to improve the yield.
88
400 nm
Emitter
Metallization
(a)
Base
W
Emitter
Collector
Subcollector
Base
W
Emitter Etch
Metal as Etch Mask
(b)
Emitter
Collector
Subcollector
Si3N4 sidewall
Silicon Nitride
Sidewall Formation
(c)
Base
W
Emitter
Collector
Subcollector
W
Base Metal
Deposition
(d)
Base
Emitter
Collector
Subcollector
Si3N4 sidewall
Tungsten RIE Etch
(e)
Base
W
W
W
Emitter
Collector
Subcollector
Figure 5.1. Scale drawings of a fully self-aligned HBT process. These drawings
describe the emitter metallization, the emitter mesa etch, the silicon nitride sidewall
formation, and the base metal deposition and etch.
89
Si3N4 sidewall
Base and Collector
Mesa Etch
(a)
W
W
W
Emitter
Collector
Subcollector
Si3N4 sidewall
Silicon Nitride
Sidewall Formation
(b)
W
W
W
Emitter
Collector
Subcollector
W
Collector Metal
Deposition
(c)
Emitter
Collector
Subcollector
Si3N4 sidewall
Tungsten RIE Etch
(d)
W
W
W
Emitter
W
W
Collector
Subcollector
Figure 5.2. Scale drawings of a fully self-aligned HBT process. These drawings
describe the base and collector mesa etch, and the collector metal deposition and
etch.
90
APPENDIX A
FABRICATION PROCESS FLOW
Purpose: Fabrication of TDT circuits using the HBT RTD mask.
RTD Emitter Metallization: RTD Emitter Mask − Layer 1
• Inspect the wafer under microscope
• Check the resistivity of the DI water
MΩ
• Solvent clean
◦ Soak in hot acetone 3 min - hot plate 60 ◦ C
◦ Soak in hot methanol 3 min - hot plate 60 ◦ C
• Prepare 2-1 etchant 2H2 O:1HCl - add acid to water - wait to cool
◦ Removes metals, lifts off organics, leaves oxide rich surface
• Rinse in DI 1 min
• Soak in 2-1 15 s
• DI rinse 10 s
• Blow dry with N2
• AZ5214E photoresist process
◦
◦
◦
◦
◦
Spin AZ5214E 5000 rpm 30 s (1.2 µm)
Hot plate soft bake 105 ◦ C 30 s
Expose
s, temperature
◦
Hot plate reversal bake 110 C 60 s
Measure intensity
W/cm2
91
◦
C
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
Expose 300 mJ/cm2 ,
s
Develop in AZ327 30 s, redevelop as necessary
DI rinse 1 min
Blow dry with N2
Inspect
UVO clean 2 min
Soak in 2-1 5 s
DI rinse 1 min
Blow dry with N2
Load without delay
s
• Evaporate
◦
◦
◦
nm Ti (2 Å/s)
nm Pt (2 Å/s)
nm Au (5 Å/s); Au spitting
• Lift-off
◦
◦
◦
◦
◦
◦
Soak in hot acetone − adjust to near boil
Vigorous spray with acetone
Rinse/spray with methanol
Blow dry with N2
Microscope inspect
Step profile, RTD emitter metal height
Å
RTD Emitter Mesa Etching:
• Solvent clean if necessary
• Mix 1H2 SO4 :8H2 O2 :160H2 O etchant (add acid to water). This needs to cool
before etching (InGaAs etch rate: 40-60 Å/s)
• Rinse 1 min in DI
• Etch in 1-8-160
◦ Ideal etch depth
s
Å. Ok if between
and
Å
• Rinse 1 min in DI
• Blow dry with N2
• Step profile, RTD mesa height
Å
92
HBT Emitter Metallization: HBT Emitter Mask − Layer 2
• Solvent clean if necessary
• Prepare 2-1 etchant 2H2 O:1HCl - add acid to water - wait to cool
• AZ5214E photoresist process
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
Spin AZ5214E 5000 rpm 30 s (1.2 µm)
Hot plate soft bake 105 ◦ C 30 s
Expose
s, temperature
◦
Hot plate reversal bake 110 C 60 s
Measure intensity
W/cm2
Expose 300 mJ/cm2 ,
s
Develop in AZ327 30 s, redevelop as necessary
DI rinse 1 min
Blow dry with N2
Inspect
UVO clean 2 min
Soak in 2-1 5 s
DI rinse 1 min
Blow dry with N2
Load without delay
◦
C
s
• Evaporate
◦
nm Ti (2 Å/s)
◦
nm Pt (2 Å/s)
◦
nm Au (5 Å/s); Au spitting
• Lift-off
◦
◦
◦
◦
◦
◦
Soak in hot acetone − adjust to near boil
Vigorous spray with acetone
Rinse/spray with methanol
Blow dry with N2
Microscope inspect
Step profile, HBT emitter metal height
93
Å
RTD Mesa Etching: RTD Mesa Etching Mask − Layer 3
• Solvent clean if necessary
• Wet chemical etching
◦ Mix 1H2 SO4 :8H2 O2 :160H2 O etchant (add acid to water). This needs to
cool before etching (InGaAs etch rate: 40-60 Å/s)
◦ Mix 1H3 PO4 :1HCl:1H2 O etchant (add acid to water). This needs to cool
before etching (InP etch rate: 50-70 Å/s)
◦ Rinse 1 min in DI
◦ Etch in 1-8-160 to a total depth of
s), selectivity stops
Å (
on InP
◦ Rinse 1 min in DI
◦ Blow dry with N2
◦ Step profile, HBT emitter height
Å
◦ Etch in 1-1-1 to a total depth of
Å (
s), selectivity stops on
the base
◦ Rinse 1 min in DI
◦ Blow dry with N2
◦ Step profile, HBT emitter height
Å
Sidewalls and BCB Process:
• Solvent clean if necessary
• Deposit SiNx 3000 Å (Recipe: SiH4 40 sccm, NH3 4 sccm; 200 W,
500 mTorr. Deposition rate: ∼ 20 nm/min)
• RIE etch
◦ O2 plasma clean if necessary
◦ Condition chamber (SF6 /Ar 2/18 sccm @ 15 mTorr, 150 W for 2 min)
◦ Etch (SF6 /Ar 2/18 sccm @ 15 mTorr, 150 W for
min,
DC
V); (SiNx etch rate: ∼ 17 Å/s)
◦ Selectivity stops on the HBT base
◦ Inspect under SEM if necessary
• Tungsten sputtering
◦ Base pressure
Torr; table spacing
◦ W sputtering for
min: Ar: 148 sccm @ 20 mTorr, forward
W, reflect power:
W, DC:
V
power:
94
◦ Step profile, deposition thickness
◦ Step profile, HBT emitter height
Å
Å
• Solvent clean if necessary
• Spin ADP, 1000 rpm for 10s, followed by 5000 rpm for 30 s
• Spin BCB 3022-35, 1000 rpm for 10 s, followed by 5000 rpm for 30s (∼ 1.3
µm)
• Cure in PECVD system
◦ N2 500 sccm @ 1000 mTorr
◦ 250 ◦ C for 1 hour
• Step profile, HBT emitter height
Å
• BCB RIE etch
◦ Condition chamber (SF6 /O2 3.33/30 sccm @ 300 mTorr, 60 W for 2 min)
◦ Etch (SF6 /O2 3.33/30 sccm @ 300 mTorr, 60 W for
min,
DC
V); (BCB etch rate 1747 Å/m)
◦ Etch stops when W appears
Å
◦ Step profile, HBT emitter height
• W RIE etch
◦ Condition chamber (SF6 /Ar 10/35 sccm @ 190 mTorr, 150 W for 2 min)
min,
◦ Etch (SF6 /Ar 10/35 sccm @ 190 mTorr, 150 W for
DC
V); (Etch rate ∼ 500 Å/s; Etch stops when Au appears)
• BCB removal
◦ Condition chamber (SF6 /O2 2/38 sccm @ 300 mTorr, 60 W for 2 min)
◦ Etch (SF6 /O2 2/38 sccm @ 300 mTorr, 60 W for
min,
V)
DC
◦ Step profile, HBT emitter height
Å
• Measure HBT emitter-base resistance, make sure emitter and base are not
shorted (base-emitter junction diodes)
• Inspect − optical, SEM test structures if necessary
95
HBT Base Contacts: HBT Base Mask − Layer 4
• Solvent clean if necessary
• Photoresist process
◦
◦
◦
◦
◦
◦
◦
Spin PR 1813, 800 rpm for 3s, followed by 2500 rpm for 30 sec
Soft bake 90 o C for 1 min
Expose
s
Develop in AZ327 for 30 sec, redevelop as necessary
s
Rinse in DI water
Blow dry with N2
Bake 120 o C for 1 min
• W RIE etch
◦ Condition chamber (SF6 /Ar 10/35 sccm @ 190 mTorr, 150 W for 2 min)
◦ Etch (SF6 /Ar 10/35 sccm @ 190 mTorr, 150 W for
min,
DC
V); (Etch rate ∼ 500 Å/s; Etch stops at the base)
• Wet chemical etching − collector definition etch
◦ Mix 1H2 SO4 :8H2 O2 :160H2 O etchant (add acid to water). This needs to
cool before etching (InGaAs etch rate: 40-60 Å/s)
◦ Mix 1H3 PO4 :1HCl:1H2 O etchant (add acid to water). This needs to cool
before etching (InP etch rate: 50-70 Å/s)
◦ Rinse 1 min in DI
◦ Etch in 1-8-160 to a total depth of
Å (
s), selectivity stops
on InP collector
◦ Rinse 1 min in DI
◦ Blow dry with N2
s), selectivity stops on
◦ Etch in 1-1-1 to a total depth of
Å (
InGaAs subcollector
◦ Rinse 1 min in DI
◦ Blow dry with N2
◦ Remove the photoresist by soaking in acetone/methanol
◦ Step profile, measure etch depth
96
Å
Isolation Etching: Isolation Etching Mask − Layer 5
• Solvent clean if necessary
• Photoresist process
◦
◦
◦
◦
◦
◦
◦
Spin PR 1813, 800 rpm for 3s, followed by 2500 rpm for 30 sec
Soft bake 90 o C for 1 min
Expose
s
Develop in AZ327 for 30 sec, redevelop as necessary
s
Rinse in DI water
Blow dry with N2
Bake 120 o C for 1 min
• Wet chemical etching
◦ Mix 1H2 SO4 :8H2 O2 :160H2 O etchant (add acid to water). This needs to
cool before etching (InGaAs etch rate: 40-60 Å/s)
◦ Mix 1H3 PO4 :1HCl:1H2 O etchant (add acid to water). This needs to cool
before etching (InP etch rate: 50-70 Å/s)
◦ Rinse 1 min in DI
◦ Etch in 1-8-160 to a total depth of
s), selectivity stops
Å (
on InP subcollector
◦ Rinse 1 min in DI
◦ Blow dry with N2
Å (
s), selectivity stops on
◦ Etch in 1-1-1 to a total depth of
InGaAs etch stop layer
◦ Rinse 1 min in DI
◦ Blow dry with N2
◦ Etch in 1-8-160 to a total depth of
Å (
s), selectivity stops
on InP substrate
◦ Rinse 1 min in DI
◦ Blow dry with N2
◦ Remove the photoresist by soaking in acetone/methanol
◦ Step profile, measure etch depth
97
Å
Resistor Process: Resistor Mask − Layer 6
• Solvent clean if necessary
• AZ5214E photoresist process
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
Spin AZ5214E 5000 rpm 30 s (1.2 µm)
Hot plate soft bake 105 ◦ C 30 s
Expose
s, temperature
Hot plate reversal bake 110 ◦ C 60 s
Measure intensity
W/cm2
Expose 300 mJ/cm2 ,
s
Develop in AZ327 30 s, redevelop as necessary
DI rinse 1 min
Blow dry with N2
Inspect
UVO clean 2 min
Load without delay
◦
C
s
• Evaporate
◦ 30 nm Ti (2 Å/s)
• Lift-off
◦
◦
◦
◦
◦
◦
Soak in hot acetone − adjust to near boil
Vigorous spray with acetone
Rinse/spray with methanol
Blow dry with N2
Microscope inspect
Step profile, resistor metal thickness
Å
HBT Collector Metallization: HBT Collector Mask − Layer 7
• Solvent clean if necessary
• AZ5214E photoresist process
◦ Spin AZ5214E 5000 rpm 30 s (1.2 µm)
◦ Hot plate soft bake 105 ◦ C 30 s
◦ Expose
s, temperature
98
◦
C
◦
◦
◦
◦
◦
◦
◦
◦
◦
Hot plate reversal bake 110 ◦ C 60 s
Measure intensity
W/cm2
Expose 300 mJ/cm2 ,
s
Develop in AZ327 30 s, redevelop as necessary
DI rinse 1 min
Blow dry with N2
Inspect
UVO clean 2 min
Load without delay
s
• Evaporate
◦ 20 nm Ti (2 Å/s)
◦ 10 nm Pt (2 Å/s)
◦ 150 nm Au (5 Å/s); Au spitting
• Lift-off
◦
◦
◦
◦
◦
◦
Soak in hot acetone − adjust to near boil
Vigorous spray with acetone
Rinse/spray with methanol
Blow dry with N2
Microscope inspect
Step profile, HBT collector metal height
Å
Capacitor Process: Capacitor Mask − Layer 8
• Solvent clean if necessary
• Deposit SiNx 3000 Å (Recipe: SiH4 40 sccm, NH3 4 sccm; 200 W,
500 mTorr. Deposition rate: ∼ 20 nm/min)
• AZ5214E photoresist process
◦
◦
◦
◦
◦
Spin AZ5214E 5000 rpm 30 s (1.2 µm)
Hot plate soft bake 105 ◦ C 30 s
Expose
s, temperature
◦
Hot plate reversal bake 110 C 60 s
Measure intensity
W/cm2
99
◦
C
◦
◦
◦
◦
◦
◦
◦
Expose 300 mJ/cm2 ,
s
Develop in AZ327 30 s, redevelop as necessary
DI rinse 1 min
Blow dry with N2
Inspect
UVO clean 2 min
Load without delay
s
• Evaporate
◦ 20 nm Ti (2 Å/s)
◦ 80 nm Au (5 Å/s); Au spitting
• Lift-off
◦
◦
◦
◦
◦
◦
Soak in hot acetone − adjust to near boil
Vigorous spray with acetone
Rinse/spray with methanol
Blow dry with N2
Microscope inspect
Step profile, capacitor top metal height
Via Process: Via Mask − Layer 9
• Solvent clean if necessary
• Photoresist process
◦
◦
◦
◦
◦
◦
Spin PR 1813, 800 rpm for 3s, followed by 2500 rpm for 30 sec
Soft bake 90 o C for 1 min
Expose
s
Develop in AZ327 for 30 sec, redevelop as necessary
s
Rinse in DI water
Blow dry with N2
• Via etching
◦ O2 plasma clean if necessary
◦ Condition chamber (SF6 20 sccm @ 20 mTorr, 50 W for 2 min)
100
Å
◦ Etch (SF6 20 sccm @ 20 mTorr, 50 W for
min,
DC
V); (Etch rate: 18 Å/s)
◦ Etch stops when Au contacts appear
◦ Remove the photoresist by soaking in acetone/methanol
◦ Step profile, etch depth
Å
Bondpad Process: Bondpad Mask − Layer 10
• Solvent clean if necessary
• AZ5214E photoresist process
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
Spin AZ5214E 5000 rpm 30 s (1.2 µm)
Hot plate soft bake 105 ◦ C 30 s
Expose
s, temperature
◦
Hot plate reversal bake 110 C 60 s
Measure intensity
W/cm2
Expose 300 mJ/cm2 ,
s
Develop in AZ327 30 s, redevelop as necessary
DI rinse 1 min
Blow dry with N2
Inspect
UVO clean 2 min
Load without delay
◦
s
• Evaporate
◦ 20 nm Ti (2 Å/s)
◦ 300 nm Au (5 Å/s); Au spitting
• Lift-off
◦
◦
◦
◦
◦
◦
Soak in hot acetone − adjust to near boil
Vigorous spray with acetone
Rinse/spray with methanol
Blow dry with N2
Microscope inspect
Step profile, deposition thickness
101
Å
C
APPENDIX B
ESTIMATION OF THE HETEROJUNCTION BIPOLAR TRANSISTOR
CUT-OFF FREQUENCY AND MAXIMUM OSCILLATION FREQUENCY
The cut-off frequency, fT , and maximum oscillation frequency, fmax , are given by
q
fT
1
1
fT = 2π
,
and
f
=
, respectively, where τE is the emitter
max
τE +τB +τDC +τC
8πRB CC
charging time, τB is the base transit time, τDC is the collector depletion layer transit
time, τC is the collector charging time, RB is the base resistance, and CC is the
collector capacitance. The time constants τE , τB , τDC , and τC are given as [60]
τE = (RE +
VT
)(CE + CC )
JE WE LE
XB2
τB =
2VT µnB
XC
τDC =
2νsat
τC = RC CC
(B.1)
(B.2)
(B.3)
(B.4)
where RE is the emitter resistance, VT is the thermal voltage, JE is the emitter
current density, WE is the emitter width, LE is the emitter length, CE is the emitter
capacitance, XB is the base thickness, µnB is the minority electron mobility, XC is
the collector thickness, νsat is the electron saturation velocity, and RC is the collector
resistance. The collector is so thin that we assume it is fully depleted.
The base-emitter junction depletion width is given by [66]
r
2²r InP
XdepE =
(ΦBE − VBE )
qNDE
102
(B.5)
where ²r InP is the dielectric constant of InP, NDE is the emitter doping concentration, ΦBE is the base-emitter junction built-in potential, and VBE is the baseemitter bias voltage. The base-emitter junction capacitance, CE , is estimated to
be CE = ²r InP WE LE /XdepE , where WE and LE are the width and length of the
emitter, respectively. The base-collector junction capacitance, CC , is estimated to
be CC = ²r InP WB LB /XC , where we assume the collector is fully depleted, and WB
and LB are the width and length of the base, respectively.
The emitter, base, and collector resistance are given by [66]
RE = REepi + REE
(B.6)
RB = Rbi + Rbx + RBB
(B.7)
RC = RCepi + RSCepi + RSCx + RCC
(B.8)
where REepi is the emitter epitaxial resistance, REE is the emitter contact resistance,
Rbi is the intrinsic base resistance, Rbx is the extrinsic base resistance, RBB is the
base contact resistance, RCepi is the collector epitaxial resistance, RSCepi is the subcollector epitaxial resistance, RSCx is the extrinsic sub-collector resistance, and RCC
is the collector contact resistance. Above resistances are given by [66]
REepi = ρcap
Xcap
(XE − XdepE )
+ ρE
WE LE
WE LE
ρσE
WE L E
ρB
Rbi =
8XB (WE /LE + LE /WE )
ρB
Rbx =
XB nbx
µ
¶
r
r
1
ρB ρσB
ρB
=
coth WBM
LBM
XB
XB ρσB
REE =
RBB
RCepi = ρC
103
XC
WB LB
(B.9)
(B.10)
(B.11)
(B.12)
(B.13)
(B.14)
RSCepi = ρ( SC)
RSCx =
RCC =
1
LCM
r
ρSC ρσSC
XSC
XSC
WB L B
ρSC
XSC nSCx
µ
r
coth WCM
(B.15)
(B.16)
ρSC
XSC ρσSC
¶
(B.17)
where ρcap , ρE , ρB , ρC , and ρSC are the resistivity of the emitter cap, the emitter, the
base, the collector, and the sub-collector, respectively, ρσE , ρσB , and ρσSC are the
contact resistivity of the emitter, the base, and the sub-collector, respectively. Xcap ,
XE , XC , and XSC are the thickness of the emitter cap, the emitter, the collector,
and the sub-collector, respectively. nbx and nSCx are the number of squares in the
extrinsic base and in the sub-collector extrinsic region, respectively. WEM , LEM
and WCM , LCM are the width and length of the base metal and the collector metal,
respectively.
104
APPENDIX C
DESIGN APPROACH USING TUNNEL DIODES FOR LOWERING POWER
IN DIFFERENTIAL COMPARATORS
The following article is the reprint from IEEE Transactions on Circuits and
Systems − II: Express Briefs, vol. 52, no.9, pp. 572-575, Sep. 2005.
I would like to express special gratitude to the co-author A. Seabaugh.
105
106
107
108
109
APPENDIX D
TUNNEL DIODE/TRANSISTOR DIFFERENTIAL COMPARATORS
The following article is the reprint from International Journal of High Speed
Electronics and Systems, vol. 14, no. 3, pp. 640-645, 2004.
I would like to express special gratitude to the co-authors S. Sutar and A.
Seabaugh.
110
111
112
113
114
115
116
APPENDIX E
UNIFIED AC MODEL FOR THE RESONANT TUNNELING DIODE
The following article is the reprint from IEEE Transactions on Electron Devices,
vol. 51, no. 5, pp. 653-657, 2004.
I would like to express special gratitude to the co-authors A. Seabaugh, P. Chahal, and F. Morris.
117
118
119
120
121
122
APPENDIX F
LOW POWER, HIGH SPEED, AND MIXED-SIGNAL TUNNELING DEVICE
TECHNOLOGY
The following article is the reprint from Proceedings of International COE Workshop on Nano Processes and Devices, and their Applications, pp. 37-38, 2005.
I would like to express special gratitude to the co-authors A. Seabaugh, S. Sutar,
Q. Zhang, W. Zhao, J. Zhao, Y. Yan, D. Wheeler, B. Wu, S. Kabeer, Z. Racz, and
P. Fay.
123
124
125
APPENDIX G
VERTICAL SILICON TUNNEL DIODE ON HIGH RESISTIVITY SILICON
The following article is the reprint from 62nd Device Research Conference Digest,
pp. 27-28, 2004.
I would like to express special gratitude to the co-authors Y. Yan, J. Zhao, W.
Zhao, and A. Seabaugh.
126
127
128
APPENDIX H
UNIFIED PHYSICS-BASED AC MODEL FOR THE RESONANT TUNNELING
DIODE
The following article is the reprint from 61st Device Research Conference, Late
News Papers, pp. 12-13, 2003.
I would like to express special gratitude to the co-author A. Seabaugh.
129
Unified Physics-Based AC Model for the Resonant Tunneling Diode
Qingmin Liu and Alan Seabaugh
Department of Electrical Engineering, University of Notre Dame, IN 46556-5637
Phone: (574) 631-4473, Email: seabaugh.1@nd.edu
The resonant tunneling diode (RTD) stands as the fastest, large-signal semiconductor switching
device with measured slew rates as high as 300 mV/ps [1]; The RTD has long been explored for
use in triggers, quantizers, oscillators, memory cells, and A/D converters [e.g. 2]. Circuit designs
using RTDs require an accurate small-signal equivalent circuit model, which is suitable and easy
to incorporate into computer-aided design (CAD) software. Two equivalent circuit models for the
RTD are commonly used: a series-inductance model [3] and a parallel-inductance model [4]. In
this paper, we present a new physics-based approach, which provides the form of the circuit and
analytic expressions for the bias dependent quantum inductance and capacitance. This model
unifies the previous models by Brown, et al. for the quantum inductance [4] and by Lake and
Yang [5] for the quantum capacitance, and extends the RTD SPICE model of Broekaert, et al. [2].
Our derivation parameterizes the sequential tunneling process between emitter and quantum well,
and quantum well and collector in terms of the emitter and quantum well charges and the
tunneling rates. We show that the change in the quantum well charge lags behind the bias
change, resulting in the existence of a quantum inductance in the tunneling current path, which is
given by LQ = τ / G D , where τ is the electron lifetime in the quantum well, and GD is the
differential conductance of the RTD. The change in the quantum well charge also induces a
change in the image charge in the collector that results in an additional quantum capacitance,
which adds to the geometrical capacitance. The total capacitance is derived to be
-1
C P = C 0 − G D / v C , where C0 is the geometrical capacitance, and vC is the electron escape rate (s )
from the quantum well to the collector.
Both dc current-voltage (I-V) and microwave frequency S-parameter measurements were made
on 1.6×1.6 µm2 AlAs/InGaAs/AlAs RTDs. Bias dependent (0 − 0.81 V) S-parameters were
measured from 45 MHz to 30 GHz using an Agilent 8510XF vector network analyzer with port
power of –33 dBm. Equivalent circuit parameters were extracted by fitting the measured Sparameter data over the entire frequency and bias range. Close agreement between calculation
and measured data is obtained. The dc and microwave frequency measurement and
characterization of AlAs/InGaAs/AlAs RTDs support the model theory.
We would like to thank Prem Chahal, Frank Morris, and Gary Frazier (Raytheon) for supplying
the RTDs and Patrick Fay (Notre Dame) for valuable discussions. This work was sponsored in
part by a Raytheon University Research Grant and the Office of Naval Research.
[1] E. Özbay, et al., IEEE Electron Dev. Lett. 14, 400-402 (1993).
[2] T. Broekaert, et al., IEEE J. Solid State Circ. 33, 1342-1349 (1998).
[3] J. M. Gering, et al., J. Appl. Phys. 61, 271-276 (1987).
[4] E. R. Brown, et al., Appl. Phys. Lett. 54, 934-936 (1989).
[5] R. Lake, et al., IEEE Trans. Electron Dev., 50, 785-789 (2003)
130
Quantum
Well
Emitter
1.5
Collector
J
0.5
E
0
J
E
C
F
E
0
E − eV
-0.5
0
5
InAs
10
Position (nm)
InGaAs
-1.5
InGaAs
AlAs
-1
AlAs
InGaAs
InGaAs
F
15
20
Reciprocal of Inductance L Q (nH-1)
Current (mA)
2
1
0
-1
2
(1.6) µm
2
-3
-0.8
-0.4
0
Voltage (V)
0.4
0.8
Fig. 2. AlAs/InGaAs/InAs/InGaAs/AlAs resonant
tunneling diode current-voltage characteristic.
Gd
LQ
10
5
0
-5
-10
0.2
0.4
Voltage (V)
0.6
0.8
8
6
τ = 2.58 ps
4
2
0
-2
-4
-6
0
Rs
0.2
0.4
Voltage (V)
0.6
0.8
Fig. 6. The reciprocal of the quantum inductance,
LQ, vs. bias showing good agreement between
measurement (circles) and calculation (solid line).
Cp
Fig. 3. Parallel-inductance equivalent circuit.
40
0.02
-0.2
0.01
-0.22
0
-0.24
-0.01
-0.26
-0.02
-0.28
-0.03
-0.3
-0.04
30
0
5
10
15
20
25
Imag S11
Real S11
15
Fig. 5. Comparison of the differential conductance
extracted from the dc I−V measurement (solid line)
with S-parameter measurement (circles).
3
-2
20
0
Fig. 1. Resonant tunneling diode computed energy
band diagram.
Capacitance C p (fF)
Energy (eV)
1
Differential Conductance G d (mS)
2
35
30
25
C = 29.3 fF
0
20
1/ν = 0.79 ps
C
15
0
Frequency (GHz)
0.2
0.4
Voltage (V)
0.6
0.8
Fig. 7. The total capacitance CP vs. bias showing
close agreement between measurement (circle) and
calculation (solid line).
Fig. 4. Comparison of the measured (circles) and
simulated (solid line) S-parameters at V = 0.45 V
(near the center of the NDR region).
131
APPENDIX I
PERFORMANCE-AUGMENTED CMOS USING BACK-END UNIAXIAL
STRAIN
The following article is the reprint from 60th Device Research Conference Digest,
pp. 41-42, 2002.
I would like to express special gratitude to the co-authors R. Belford, W. Zhao,
J. Potashnik, and A. Seabaugh.
132
133
134
APPENDIX J
SILICON-BASED TUNNEL DIODES AND INTEGRATED CIRCUITS
The following article is the reprint from 4th International Workshop on Quantum
Functional Devices, pp. 5-8, 2000.
I would like to express special gratitude to the co-authors A. Seabaugh, Z Hu,
D. Rink, and J. Wang.
135
136
137
138
139
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