INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Int. J. Circ. Theor. Appl. 2006; 34:251–264
Published online in Wiley InterScience (www.interscience.wiley.com). DOI: 10.1002/cta.334
Fast-scale bifurcation in power-factor-correction buck-boost
converters and eects of incompatible periodicities
Jianlong Zou1 , Xikui Ma1 , Chi K. Tse2 and Dong Dai1; ∗; †
1 School
2 Department
of Electrical Engineering; Xi’an Jiaotong University; Shaanxi; China
of Electronic and Information Engineering; Hong Kong Polytechnic University; Hong Kong; China
SUMMARY
In this paper, we derive the discrete-time model for the power-factor-correction (PFC) buck-boost
converter in terms of a stroboscopic switching map. Fast-scale instability is analysed through a fold
diagram, which exposes the periodicity of the operation as well as the locations of the critical phase
angles of the line voltage at which instability begins to occur along a half-line cycle. The asymmetrical locations of the critical phase angles along a half-line cycle is explained in terms of ‘underdeveloped’ bifurcation. Border collision bifurcations are observed and analysed in detail. Copyright ?
2006 John Wiley & Sons, Ltd.
KEY WORDS:
buck-boost converter; power factor correction; fast-scale instability; bifurcation; border
collision
1. INTRODUCTION
Some bifurcation phenomena have been reported recently for power-factor-correction (PFC)
boost converters operating in continuous conduction mode (CCM) under some standard types
of current-mode control [1–5]. For instance, fast-scale bifurcation corresponding to period
doubling at the switching frequency has been reported for the PFC boost converter under
peak current-mode control and average current-mode control [1–3]. Such bifurcation manifests
itself as instability occurring over some sub-intervals of the line cycle. Moreover, the slowscale bifurcation corresponding to sub-harmonic oscillations below the line frequency has been
reported for PFC boost converters under average current-mode control [4, 5].
∗ Correspondence to: Dong
† E-mail: ddai@ieee.org
Dai, School of Electrical Engineering, Xi’an Jiaotong University, Shaanxi, China.
Contract=grant sponsor: National Natural Science Foundation of China; contract=grant number: 50577047
Contract=grant sponsor: Hong Kong Polytechnic University Research Project; contract=grant number: G-YE04
Copyright ? 2006 John Wiley & Sons, Ltd.
Received 10 January 2005
Revised 26 August 2005
252
J. ZOU ET AL.
Apart from the boost converter, other dc–dc converters may be used for PFC, depending
upon the practical design requirements [6]. Due to its circuit simplicity and ability to provide
voltage step-up or step-down, the buck-boost converter represents a popular alternative for
PFC applications. In this paper, we investigate the fast-scale bifurcation behaviour of a PFC
buck-boost converter operating basically in CCM. The locations of the onset of fast-scale
bifurcation are examined in terms of the phase angles of the line cycle. In particular, we
observe the asymmetrical locations of the critical phase angles (i.e. phase angles along the
line cycle at which fast-scale instability begins) and identify its cause in terms of ‘underdeveloped’ bifurcation. Finally, we also observe the occurrence of border collision, which is
a characteristic type of bifurcation observed in power electronics [7–9].
This paper is organized as follows. Section 2 reviews the operation of the PFC buckboost converter, and derives the discrete-time model for analysis. In Section 3, fast-scale
bifurcation phenomena are studied using a fold diagram. In Section 4, the locations of the
critical phase angles are examined in terms of ‘underdeveloped’ bifurcation. Finally, border
collision bifurcations are studied in some detail in Section 5, and we give our conclusion in
Section 6.
2. DERIVATION OF THE ITERATIVE MAP FOR PFC BUCK-BOOST CONVERTER
The PFC buck-boost converter under study is shown in Figure 1, in which a typical peak
current-mode control is employed for achieving PFC. The voltage feedback loop consists of
a simple proportional control, which is adequate for the purpose of investigating fast-scale
bifurcation. The input voltage is a rectied version of the line voltage, i.e.
vin = Vm | sin !t | = Vm | sin (t)|
(1)
where Vm is the peak value of the line voltage, ! is the angular line frequency, and (t) = !t.
The reference current is time varying, which provides a sinusoidal template for controlling
the input current envelope, i.e.
iref = p1 p2 (Vref − vC (t))Vm | sin (t)|
(2)
where Vref is the output voltage reference, p1 ; p2 are the gains of the current and voltage
loops, and Ts is the switching period. Moreover, the line period is T = 2=!.
When the switch is closed, the diode is open. Under this condition, the inductor current
increases. The operation of the PFC buck-boost converter can be described by
Vm | sin (t)|
diL Vm | sin !t |
=
=
dt
L
L
(3)
dvC
1
=−
vC
dt
RC
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FAST-SCALE BIFURCATION IN POWER-FACTOR-CORRECTION BUCK-BOOST CONVERTERS
p1
253
p2
iref
Q
R
S
iL
clock
vin
V ref
D
C
L
R
vC
iL
Figure 1. The PFC buck-boost converter.
When the switch is turned o, the diode is forced to be closed and behaves as a short circuit.
This causes the inductor current to decrease. In this case, the PFC buck-boost converter is
described by
1
diL
= − vC
dt
L
1
dvC
1
= iL −
vC
dt
C
RC
(4)
Furthermore, under certain conditions (usually with a relatively small inductance or a relatively long switching period), the current can possibly drop to zero within a switching period.
When this happens, the system is described by
iL = 0
1
dvC
=−
vC
dt
RC
(5)
In summary, the system may have three possible states. The rst state corresponds to the
switch being closed, the second state to the switch being open and the inductor current being
non-zero, and the third state to the switch being open and the inductor current being zero. We
denote the time durations of these three states by tc , td and te , respectively. The system is said
to operate in CCM if te = 0. Moreover, if te ¿0, the system is said to operate in discontinuous
conduction mode (DCM).
A discrete-time model of the PFC buck-boost converter can be established through a stroboscopic switching map which is obtained by sampling the state at time instants that are
integer multiples of the switching period Ts . Let in = iL (nTs ), vn = vC (nTs ) and n = !nTs . The
discrete-time model for the PFC buck-boost converter can be derived for two cases:
1. During the interval of the rst state (the switch being turned on), the inductor current
reaches iref before the end of the switching period, i.e. tc ¡Ts .
2. During the interval of the rst state (the switch being turned on), the inductor current
does not climb enough to reach iref before the end of the switching period, i.e. tc = Ts .
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J. ZOU ET AL.
Case 1: tc ¡Ts : To nd (in+1 ; vn+1 ) in terms of (in ; vn ), our basic strategy is to ‘stack’ the
solutions of all involving sub-intervals. First, assuming that the switch is closed for
nTs ¡t¡nTs + tc , we get
iL (nTs + tc ) = in +
vC (nTs + tc ) = vn e
Vm
| cos n − cos(n + !tc )|
!L
(6)
−tc =RC
At the instant t = nTs + tc , we have iref (nTs + tc ) = p1 p2 Vm (Vref − vC (nTs + tc ))| sin(n + !tc )|.
Furthermore, iL (nTs + tc ) = iref (nTs + tc ). So, we can determine tc from the following equation:
in +
Vm
| cos n − cos(n + !tc )| = p1 p2 (Vref − vn e−tc =RC )Vm | sin(n + !tc )|
!L
(7)
Clearly, if tc turns out to be greater than Ts , then the situation belongs to Case 2. Let us
assume that tc ¡Ts . Then, for t¿nTs + tc , the inductor current begins to fall. If the time taken
for the inductor current to fall to zero is longer than (Ts − tc ), the operation is CCM, and we
have td = Ts − tc and te = 0. Otherwise, it is DCM.
To determine the operating mode, we need to nd td . Let us assume that the operation is
DCM, i.e. tc + td ¡Ts . Then, the values of in+1 and vn+1 can be solved from Equation (5) with
iL (nTs + tc + td ) and vC (nTs + tc + td ) as initial values, i.e.
in+1 = 0
vn+1 = vC (nTs + tc + td )e−(Ts −tc −td =RC)
(8)
where
vC (nTs + tc + td ) = − Letd [(a + b) cos(td ) + (b − a) sin(td )]
and td can be determined from
etd [a cos(td ) + b sin(td )] = 0
(9)
which gives
td = −
a
1
arctan
b
(10)
Clearly, if td turns out to be greater than Ts − tc , we have the CCM case. Under this
condition, the values of in+1 and vn+1 can be solved from Equation (4) with iL (nTs + tc ) and
vC (nTs + tc ) as the initial values, i.e.
in+1 = e(Ts −tc ) [a cos((Ts − tc )) + b sin((Ts − tc ))]
vn+1 = −Le(Ts −tc ) [(a + b) cos((Ts − tc )) + (b − a) sin((Ts − tc ))]
Copyright ? 2006 John Wiley & Sons, Ltd.
(11)
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FAST-SCALE BIFURCATION IN POWER-FACTOR-CORRECTION BUCK-BOOST CONVERTERS
255
where
1
2RC
1
1
=
−
LC 4R2 C 2
=−
(12)
(13)
a = p1 p2 (Vref − vn e−tc =RC )Vm | sin(n + !tc )|
1
b=−
vn e−tc =RC
+ a
L
Note that for most practical situations, R¿ 12
real.
(14)
(15)
L=C since C is relatively large. Hence, is
Case 2: tc = Ts : This case corresponds to the situation when the value of tc found from
Equation (7) is greater than Ts . As tc ¿Ts is not permitted, we have tc = Ts and the system
has only the ON state in a switching period Ts . The instantaneous values of in+1 and vn+1 can
be solved from Equation (3) with in and vn as the initial values, i.e.
in+1 = in +
vn+1 = vn e
Vm
| cos n − cos(n + !Ts )|
!L
(16)
−Ts =RC
Hence, using Equations (8), (11) and (16), we can nd (in+1 ; vn+1 ) from any given (in ; vn ).
In other words, we have essentially derived an iterative map for the PFC buck-boost converter.
3. FAST-SCALE BIFURCATION AND INCOMPATIBLE PERIODICITIES
For the PFC buck-boost converter, the input voltage is vin = Vm | sin !t | = Vm | sin |, and the
reference current is iref = p1 p2 (Vref − vC (t))Vm | sin |. It is obvious that the system can be
unstable for some . Therefore, can be used as a parameter for the purpose of studying the
bifurcation of the system.
We begin with a few quick simulations of this
√ system. The circuit component values used
for numerical studies are: Ts = 20 s, Vm = 110 2 V, Vref = 50–260 V, R = 100 , L = 2 mH,
C = 470 F, p1 = 0:02, and p2 = 0:01. Figure 2 shows the sampled-data waveforms‡ of the
inductor current for some values of Vref . In Figure 2(a), the system assumes its usual operating
regime. However, in Figures 2(b) and (c), period doubling at the switching period at certain
phase angle values of the half-line period is clearly evident.
To probe into the bifurcation behaviour of the system, we rst assume that does not
change with time. Then, the input voltage to the buck-boost converter is simply a dc voltage,
‡ The
sampled-data waveforms are plotted by sampling the actual waveforms at the switching frequency. Thus, the
detailed waveform within the switching period has been omitted.
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J. ZOU ET AL.
0.9
0.45
0.8
0.4
0.7
0.35
0.6
i (A)
n
in (A)
0.3
0.25
0.2
0.4
0.15
0.3
0.1
0.2
0.05
0.1
0
0.97
(a)
0.5
0.975
0.98
0.985
0.99
0.995
0
0.97
1
0.975
0.98
0.985
(b)
t(s)
0.99
0.995
1
t(s)
1.4
1.2
i (A)
n
1
0.8
0.6
0.4
0.2
0
0.97
0.975
(c)
0.98
0.985
0.99
0.995
1
t(s)
√
Figure 2. Sampled-data waveforms of inductor current for Ts = 20 s, Vm = 110 2V, R = 100, L = 2mH,
C = 470 F, p1 = 0:02, and p2 = 0:01: (a) Vref = 50 V; (b) Vref = 80 V; and (c) Vref = 120 V.
and is simply a parameter for varying the dc input voltage. The bifurcation diagram with
respect to is shown in Figure 3. Here, we set Vref = 260 V. We refer to this bifurcation
diagram as static bifurcation diagram, as the input voltage (equivalently the phase angle) is
kept constant for each set of points collected (for each value of ) in the diagram. We note
that the bifurcation pattern is symmetrical about = =2. The buck-boost converter becomes
chaotic through both period-doubling bifurcation and border collision.
Let us return to the actual system, in which = !t. Thus, varies with time, and so are
vin and iref . The sampled-data waveform of the inductor current can be computed according to
Equations (8), (11) and (16) with ! = 100 rad=s (i.e. line frequency being 50 Hz). Figure 4
shows a particular sampled-data waveform, from which we observe the following.
1. For certain sets of parameter values, within a half-line cycle, the system operates
‘regularly’ in one time interval, while it operates ‘chaotically’ in another time interval. This phenomenon is similar to that observed in the PFC boost converter, where it
has been termed fast-scale instability [1, 2].
Copyright ? 2006 John Wiley & Sons, Ltd.
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FAST-SCALE BIFURCATION IN POWER-FACTOR-CORRECTION BUCK-BOOST CONVERTERS
257
3.5
3
2.5
in (A)
2
1.5
1
0.5
0
π/2
θ (rad)
π/4
0
3π/4
π
Figure 3. Static bifurcation diagram assuming that does not change with time. That is, the input is dc
voltage and the converter is allowed to reach steady state for each value of . For this case, Vref = 260V
and all other parameters remain the same.
4
3.5
3
in (A)
2.5
2
1.5
1
0.5
0
1
1.005
1.01
1.015
t (s)
1.02
1.025
1.03
Figure 4. Sampled-data waveform of inductor current in of the PFC buck-boost converter for input
being sine voltage at 50 Hz and Vref being 260 V.
2. After a time duration of T=2, i.e. half-line cycle, the motion is nearly repeated. We
note further that unless T=2 is an exact integer multiple of Ts , the steady-state behaviour
during ∈ [k; (k + 1)] is not exactly the same as that during ∈ [(k + 1); (k + 2)],
where k is a non-negative integer.
In order to study the long-term behaviour of the PFC buck-boost converter, we ‘fold’ the
waveform over a period of T=2, i.e. phase angle . A fold diagram of folding period T=2 is
shown in Figure 5, which is dierent from the static bifurcation diagram shown in Figure 3.
Moreover, the periodicity of the operation depends upon the relative values of the switching
frequency and the line frequency.
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4
3.5
3
in (A)
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3 π
θ (rad)
Figure 5. Fold diagram of in with folding period equal a half-line cycle.
4
3.5
3
in (A)
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3 π
θ (rad)
Figure 6. Fold diagram of in with T=(2Ts ) = 10. For simplicity of simulation, the same Ts
is used as in the previous cases. Thus, T=2 = 10Ts .
Clearly, if the switching frequency approaches innity, the fold diagram should resemble
the static bifurcation diagram shown in Figure 3 because the input voltage can be regarded
as being essentially unchanged (very slowly changed) over many switching cycles and the
converter has sucient time to reach its respective steady state for the value of input voltage
corresponding to the phase angle concerned. The resulting sampled-data waveform is therefore
same as the static bifurcation diagram.
However, if the switching frequency is not very high compared to the line frequency,
e.g. T=2Ts = 10, the input voltage varies relatively fast and the sampled-data waveform of in
diers substantially from the static bifurcation diagram of Figure 3. Here, we set Vref = 260 V,
Ts = 20 s. Given any initial condition, (in ; vn ) is iterated to give the fold diagram of in , as
shown in Figure 6. We can see that the converter operates periodically with the period equal
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FAST-SCALE BIFURCATION IN POWER-FACTOR-CORRECTION BUCK-BOOST CONVERTERS
259
4.5
4
3.5
in (A)
3
2.5
2
1.5
1
0.5
0
0
2
4
6
8
3π
θ (rad)
Figure 7. Fold diagram of in with T=(2Ts ) = 50=3. For simplicity of simulation, the same Ts is
used as in the previous cases. Thus, 3T=2 = 50Ts .
4.5
4
3.5
in (A)
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
θ (rad)
2
2.5
3 π
√
Figure 8. Fold diagram of in with T=(2Ts ) = 25= 2.
to a half-line cycle, T=2, and in being always greater than 0 for any . Moreover, within the
half-line cycle, fast-scale instability is still possible.
In general, if T=2Ts is a rational number, i.e. T=2Ts = p=q with p and q being some integers
having no common factors, a convenient choice of the folding period is qT=2. For example,
for T = 1 ms and Ts = 30 s, i.e. T=2Ts = 50
3 , and the folding period is 3T=2, i.e. phase angle of
3. The fold diagram is shown in Figure 7, which clearly reveals a periodic operation with
period equal to 3T=2. However, if T=2Ts is an irrational number, periodic operation becomes
impossible although we may still fold the waveform over
√ a half-line cycle. The
√ fold diagram
shown in Figure 8 corresponds to T = 1 ms and Ts = 20 2 s, i.e. T=2Ts = 25= 2. A periodic
operation is clearly evident.
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J. ZOU ET AL.
4
3.5
3
in (A)
2.5
2
bifurcation diagram
1.5
1
fold diagram
0.5
0
0
0.5
1
1.5
θ (rad)
2
2.5
3
π
Figure 9. Comparison of static bifurcation diagram and fold diagram.
Combined plot of Figures 3 and 5.
4. LOCATIONS OF CRITICAL PHASE ANGLES AND ‘UNDERDEVELOPED’
BIFURCATION
In the foregoing section, we have discussed the fast-scale bifurcation behaviour of the PFC
buck-boost converter and the periodicity of the system using fold diagrams. Comparing the
static bifurcation diagram of Figure 3 and the fold diagram of Figure 5, noticeable dierences
are observed in the locations of the critical phase angles. Specically, as shown in Figure 9
(which is a combined plot of Figures 3 and 5), the critical phase angles are symmetrically
located about = =2 in the static bifurcation diagram, but not in the fold diagram.
In the process of developing the static bifurcation diagram, the input voltage is xed, corresponding to each phase angle , and the converter is allowed to reach the steady state when
the waveform information is extracted. Thus, the input is essentially dc voltage. However, for
the fold diagram, the input is a sine voltage varying at 50 Hz, i.e. is time varying. The
waveform information is collected as time elapses. Unlike in the case of the static bifurcation
diagram, the converter is not given sucient time to reach the respective steady state that
corresponds to the xed (input voltage value at that point in time). The resulting bifurcation
exhibits noticeable dierences from that given in the static bifurcation diagram. Thus, comparing to the static bifurcation diagram, the fold diagram can be regarded as being collected
‘pre-maturely’. We may say that the fold diagram reects an ‘underdeveloped’ bifurcation.
The major dierence is the loss of symmetry of the locations of the critical phase angles in
the ‘underdeveloped’ bifurcation.
5. BORDER COLLISION AND PARTIAL CCM (PCCM) OPERATION
In this section, we continue to study the fast-scale bifurcation of the PFC buck-boost converter,
and in particular the occurrence of border collision as varies with time. Some previous
discussions on border collision in dc–dc converters can be found in References [7, 9–13].
Copyright ? 2006 John Wiley & Sons, Ltd.
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8
261
tc+td=Ts
7
in (A)
6
fold diagram of (in, vn)
5
4
3
tc=Ts
2
1
0
0
0.5
1
1.5
2
2.5
3
π
124 120
v (V)
n
θ n (rad)
Figure 10. 3-dim fold diagram of (vn ; in ) showing the two border surfaces.
In general, border collision can be boiled down to a change in the topological sequence as
some parameter is varied [7, 14]. For PFC converters, the input voltage is like a time-varying
parameter. Border collision may occur if there is a change in the topological sequence at
some point in time as the input voltage (phase angle ) varies.
As mentioned in Section 2, the PFC buck-boost converter may operate in a few dierent
ways in terms of the topological sequence. If we assume its normal operation being in CCM,
it may enter DCM if tc + td is just less than Ts . It may also assume an ON state for the entire
period if tc = Ts . Thus, we can consider the two borders as tc = Ts and tc + td = Ts , where
the converter experiences a change in the topological sequence. For convenience, we let the
two borders be represented by in = F(n ; vn ) and in = G(n ; vn ) corresponding to tc = Ts and
tc + td = Ts , respectively. See the Appendix for detailed derivations of these border functions.
Figure 10 shows the fold diagram of (vn ; in ) with the two borders, in = F(n ; vn ) and
in = G(n ; vn ). For in ¡F(n ; vn ), i.e. (n ; vn ; in ) is below the surface F(n ; vn ), we have tc = Ts .
Then, the usual CCM is no longer maintained and the system operates in the ON state for
the entire switching period. Likewise, for in ¿G(n ; vn ), i.e. (n ; vn ; in ) is above the surface
G(n ; vn ), we have tc + td ¡Ts . Then, the system runs into DCM. Thus, if in ¿G(n ; vn ) along
the half-line cycle, the system enters DCM for some interval of the the half-line cycle. We
refer to this operating mode as partial continuous conduction mode (PCCM), as it maintains
CCM only for part of the half-line cycle.
6. CONCLUSION
In this paper, we have investigated the fast-scale bifurcation, which has been found in other
dc–dc converters, in a PFC buck-boost converter under a typical peak current-mode control.
The phenomenon has been described and interpreted in terms of ‘underdeveloped’ bifurcation.
The fold diagram is used as a tool to examine the periodicity and the bifurcation pattern as the
input voltage varies with time. It has been found that this converter can behave in dierent
regimes for dierent intervals of time along the half-line cycle. The critical phase angles
Copyright ? 2006 John Wiley & Sons, Ltd.
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J. ZOU ET AL.
separating regular and irregular operations can be identied and are found to be located
asymmetrically about mid-point of the half-line cycle. The loss of symmetry can be viewed
as a result of an ‘underdeveloped’ bifurcation, which is basically a manifestation where the
bifurcation diagram is plotted with the parameter being time varying, allowing no sucient
time for the system to reach its steady state when data is collected for construction of the
bifurcation diagram. The periodicity of the system has been shown to be aected by the ratio
of the switching period and the line period. When this ratio is a rational number, periodicity
is maintained, and vice versa. We have also considered the possibility of border collision,
which is typical of dc–dc converters, as the system enters DCM under certain conditions.
This mixed operating mode or partial continuous conduction mode further complicates the
operation of this converter.
The results reported in this paper will improve our understanding of the complex behaviour
of PFC converters, such as fast-scale bifurcation and border collision. As fast-scale bifurcation may degrade the power factor and aect electromagnetic compliance, it is necessary for
designers to select appropriate parameters in order to avoid fast-scale bifurcation, or to adopt
eective methods to eliminate fast-scale bifurcation under a very wide operating range.
APPENDIX A: DETERMINATION OF THE BORDER CORRESPONDING TO tc = Ts
The border condition for the converter to run into an ON state for the entire switching period
can be found by putting tc = Ts directly in Equation (7), i.e.
in = −
Vm
| cos n − cos(n + !Ts )| + p1 p2 (Vref − vn e−Ts =RC )Vm | sin(n + !Ts )|
!L
= F(n ; vn )
(A1)
APPENDIX B: DETERMINATION OF THE BORDER CORRESPONDING TO tc + td = Ts
There is no exact closed form expression for in corresponding to tc + td = Ts since the analytic
solution involves solving transcendental equations. Fortunately, in practice, the circuit parameters are often chosen such that the model can be dramatically simplied [7]. In the case of
the PFC buck-boost converter under study, the border corresponding to tc + td = Ts can be
determined by approximation. First, Equation (11) can be approximated as
where
in+1 ≈ a + b(Ts − tc )
(B1)
vn+1 ≈ −L[a + b + (b − a)(Ts − tc )]
(B2)
a ≈ p1 p2 Vref − vn
Copyright ? 2006 John Wiley & Sons, Ltd.
tc
1−
RC
Vm | sin n |
(B3)
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and
b≈−
1 vn
tc
1−
+ a
L
RC
263
(B4)
Equation (10) can be approximated as
td ≈ −
a
b
(B5)
Also, Equation (7) can be approximated as
Mtc
tc
in +
≈ p1 p2 Vref − vn 1 −
M
L
RC
(B6)
where M = Vm | sin n |. Then, we get
tc ≈
in + p1 p2 M (vn − Vref )
Mvn M
p1 p2
−
RC
L
(B7)
Putting Equation (B7) into Equations (B3)–(B5), and using tc + td = Ts , we get a quadratic
equation in in , i.e.
(Jvn + Bvn )(in + Kvn + A)2
+ (Bvn + D)(Bvn − Jvn Ts − Bvn Ts + vn =L − A − Kvn )(in + Kvn + A)
+ (Bvn + D)2 (−A − Kvn − vn Ts =L + ATs + Kvn Ts ) = 0
(B8)
where J = − 1=LRC, K = p1 p2 M , A = − KVref , B = K=RC, D = − K=p1 p2 L. The border corresponding to tc + td = Ts can be obtained by solving Equation (B8).
ACKNOWLEDGEMENTS
This work was supported by National Natural Science Foundation of China and Hong Kong Polytechnic
University Research Project (G-YE04).
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