13601DF
13 Gbps D Flip-Flop
Data Sheet
Inphi
13601DF
Applications
•
•
•
High-speed (up to 13 GHz) digital logic
High-speed (up to 13 Gbps) serial data transmission systems
Broadband test and measurement equipment
Features
•
•
•
•
•
Supports data rates up to 13 Gbps
Very low random jitter: 37 fs rms typical
Fast rise and fall times: < 25 ps
Low power consumption: 300 mW
Supports single-ended and differential operation
•
•
•
•
•
Output signal swing 1200 mVpp differential
Low Added Deterministic Jitter: 2 ps pp typical
Single power supply: +3.3 V
Available in QFN package
Evaluation board available
Description
The 13601DF D flip-flop (DFF) is designed to
support data rates up to 13 Gbps. The part is
nominally positive-edge triggered; however, by
reversing the positive and negative clock
connections, a negative-edge triggered application
can be accommodated.
All differential data and differential clock inputs
are on-chip DC coupled and terminated with 50 Ω
resistors to VCC. For direct-coupled applications,
the differential data outputs should be terminated
off chip with 50 Ω resistors to VCC (+3.3 V). For
2008-04-04
13601DF_DS_Ver2.3
applications requiring termination to DC levels
other than VCC (i.e. ground referenced systems),
external AC coupling to a good RF ground is
required. See the application note for various
termination examples.
The 13601DF operates from a single +3.3 V
power supply and is available in a 3 x 3 mm2 quad
flat no-lead (QFN) package. The packaged part is
also available on an evaluation board with SMA
connectors.
Inphi Proprietary
Page 1 of 9
Block Diagram
VCC
50 Ω
VCC
50 Ω
60 Ω
DINp
D
Dn
60 Ω
Q
Qn
DOUTp
DINn
DOUTn
VCC
50 Ω
50 Ω
CLKINp
CK
CKn
CLKINn
Absolute Maximum Ratings
•
•
•
Stresses beyond those listed here may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated in the “Operating Conditions” and “Electrical Specifications” of this datasheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter
Min
Max
Unit
–0.5
+3.6
V
Input Signals (Data & Clock)
VCC – 2
VCC + 1
V
Output Signals
VCC – 2
VCC + 1
V
Power Supply Voltage
Symbol
Conditions
VCC
Junction Temperature – Die
TJ
–5
+175
°C
Case Temperature – Package paddle
TC
–15
+125
°C
TSTORE
–40
+125
°C
RH
0
100
%
Clock and Data inputs
500
---
V
Data outputs
250
---
V
Power Supply
500
---
V
Shipping/Storage Temperature
Humidity
ESD Protection (Human Body Model)
ESD
Operating Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power Supply Voltage
VCC
± 5% Tolerance
+3.135
+3.300
+3.465
V
On-Chip Power Dissipation
PD
---
300
410
mW
Power Supply Current
ICC
70
91
115
mA
Operating Temperature (Junction) – Die
TJ
+15
---
+125
°C
Operating Temperature (Case) – Package
TC
Bottom of paddle
–5
---
+85
°C
RJC (θJC) Bottom of paddle
---
51
---
°C/W
Thermal Resistance – junction to paddle
2008-04-04
13601DF_DS_Ver2.3
Inphi Proprietary
Page 2 of 9
Electrical Specifications
!
WARNING – To prevent damage to the part:
•
DC power must be turned off prior to connecting or disconnecting any cables.
Electrical specifications guaranteed when the part is operated within the specified operating conditions.
Parameter
Symbol
Maximum Data Rate
Conditions
10–12
BER (NRZ format)
Min
Typ
Max
Unit
13
---
---
Gbps
13
---
---
GHz
---
---
1
V/ns
Maximum Clock Frequency
fMAX
Minimum Clock Slew Rate
SMIN
Input High Level (Data & Clock)
VIH
VCC – 0.5
---
VCC + 0.5
V
Input Low Level (Data & Clock)
VIL
VCC – 1.0
---
VCC
V
300
---
2000
mVpp
300
---
1000
mVpp
Freq. < 13 GHz and
Input common mode
(VICM) ≤ VCC
10
---
---
dB
VIH ≤ VCC+0.3V
280
300
---
deg
VIH > VCC+0.3V
260
300
---
deg
900
1200
1400
mVpp
Input Amplitude (Data & Clock)
At crossing of CLKINp
and CLKINn
VINPP & Differential peak-to-peak
VCLKPP Single-ended peak-to-peak
Input Return Loss (Data & Clock) 1
RLIN
Clock Phase Margin
CPM
Data Output Amplitude2
DOUT
Differential peak-to-peak
Output High Voltage
VOH
DC coupled
VCC – 50
VCC – 4
VCC
mV
Output Common Mode
VOCM
DC coupled
---
VCC – 300
---
mV
Output Rise/Fall Time
tr/tf
20–80%
---
16
25
ps
Freq. < 13 GHz
10
---
---
dB
JD
Peak-to-peak at 12.5 Gbps
---
2
4
ps
Added Random Jitter4, 6
JR
RMS at 10 GHz
---
37
80
fs
Clock to Data Output Delay4
tQ
Packaged
50
65
80
ps
Output Return
Loss3
Added Deterministic
RLOUT
Jitter4, 5
Notes:
1 Inputs are designed to be a broadband match a 50 Ω impedance and are terminated with a 50 Ω resistor to V .
CC
2 Outputs are CML. Values are based on DC measurements.
3 Outputs are designed to be a broadband match a 50 Ω impedance and are terminated with a 60 Ω resistor to V .
CC
4 Valid when clock to data phase is near center of CPM window. Propagation delay is based on simulations.
5 The added deterministic jitter (J ) specified is the total peak-to-peak jitter measured using a 231-1 PRBS data pattern
D
less the measured peak-to-peak jitter of the input clock source.
6 The added random jitter (J ) is the calculated RMS jitter based on residual phase noise measurements.
R
2008-04-04
13601DF_DS_Ver2.3
Inphi Proprietary
Page 3 of 9
Timing Diagram
DIN =
1
2
3
4
5
DINp - DINn
CLKIN =
CLKINp - CLKINn
50%
50%
1/fCLK
tQ
DOUTn
1
80%
80%
2
20%
DOUTp
20%
tf
tr
Note: Not drawn to scale
D-Flip Flop Truth Table
Inputs
DINpk-1
DINnk-11
L
H
Outputs
1
DOUTpk
DOUTnk1
H
L
H
L
H
L
CLKINp
CLKINn
DIN1n, CLKINn and DOUTn are complementary signals to DIN1p, CLKINp and DOUTp,
respectively.
1
H
L
2008-04-04
Denotes a HIGH voltage level
Denotes a LOW voltage level
Denotes a rising clock transition
Denotes a falling clock transition
13601DF_DS_Ver2.3
Inphi Proprietary
Page 4 of 9
Typical DC Operating Characteristics
Supply Current versus Supply Voltage with
Temperature as a Parameter
OUTP Amplitude versus Supply Voltage with
Temperature as a Paramater
0.69
100
OUTP Amplitude (V)
Supply Current (mA)
105
95
90
-5 C
25 C
85
0.66
-5 C
0.63
25 C
85 C
85 C
0.60
3
80
3
3.1
3.2
3.3
3.4
Power Supply (V)
3.5
Figure 1. Power supply current vs. power supply
voltage
VCM (mV)
VOH (mV)
-4
-6
-8
-10
-5
25
85
-16
-3.5
-3.4
-3.3
-3.2
3.5
-3.1
-3
-280
-285
-290
-295
-300
-305
-310
-315
-320
-325
3.6
-5
25
85
-3.6
-3.5
-3.4
Figure 3. Single-ended, output high level (on wafer)
vs. power supply
13601DF_DS_Ver2.3
-3 .3
-3.2
-3.1
-3
VCC (V)
VCC (V)
2008-04-04
3.4
Av erage Co mmon M ode (>20 Devices) vs.
Supply with T em perature as a Param eter
0
-3.6
3.3
Figure 2. Single-ended, peak-to-peak output
amplitude (on wafer) vs. power supply
-2
-14
3.2
Supply Voltage (V)
Average VOH (>20 Devices) vs. Supp ly with Temperature
as a Parameter
-12
3.1
3.6
Figure 4. Output common mode (on wafer) vs. power
supply
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Page 5 of 9
Time Domain Operating Characteristics
Figure 5. Output DOUTp (QFN package)
10 Gbps 231–1 PRBS data input
100 mV/div 20 ps/div.
O UT P D e term in istic Jitter v ers us S up p ly
V o ltag e w ith T e m p eratu re a s a P aram a ter
O UT P Ran d o m Jitter ve rsu s S u p p ly V o ltag e
w ith T em p eratu re as a P ara m ater
1.90
Deterministic Jitter (ps)
Random Jitter (ps)
0.230
-5 C
0.225
25 C
85 C
0.220
0.215
0.210
1.85
1.80
1.75
-5 C
1.70
25 C
85 C
1.65
1.60
0.205
3
3.1
3.2
3.3
3.4
3.5
3
3.6
3.1
25 C
85 C
15
14
13
3.5
3.6
OUTP Fall Time versus Supply Voltage with
Temperature as a Paramater
13
OUTP Fall Time (ps)
OUTP Rise Time (ps)
-5 C
16
3.4
Figure 7. Output deterministic jitter (on wafer) vs.
power supply - refer to note #3 under Electrical Spec.
OUTP Rise Time versus Supply Voltage with
Temperature as a Parameter
17
3.3
S upply V oltage (V )
S upply V oltage (V )
Figure 6. Output random jitter (on wafer) vs. power
supply - refer to note #3 under Electrical Spec.
3.2
12
-5 C
25 C
11
85 C
10
9
8
12
3
3.1
3.2
3.3
3.4
3.5
3.6
Supply Voltage (V)
Figure 8. Output rise time (on wafer) vs. power supply
2008-04-04
13601DF_DS_Ver2.3
3
3.1
3.2
3.3
3.4
3.5
3.6
Supply Voltage (V)
Figure 9. Output Fall Time (on wafer) vs. Power
Supply
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Page 6 of 9
Typical Return Losses
All S-parameter measurements were made single-ended. S-parameters for the packaged part are not given here
due to the unavailability of calibration standards for the evaluation board.
|S11| vs. Fr equency, 0.0 V Data Input, All Conditions, Die #113
|S11| vs. Frequency (25 C, 3.3 V), 0.0 V Data Input; N=33
0
0
-5
-5
-10
-10
-15
-15
-5 C 3.5 V
|S1 1| (dB)
|S11| (dB )
-5 C 3.3 V
-20
-25
-5 C 3.1 V
25 C 3.5 V
25 C 3.3 V
-20
25 C 3.1 V
-25
-30
-30
-35
-35
-40
-40
85 C 3.5 V
85 C 3.3 V
85 C 3.1 V
0
5
10
15
20
25
30
Specification
0
5
10
Frequency (GHz)
15
20
25
30
Frequency (GHz)
Figure 10. Data Input |S11| versus frequency of 33 die
on wafer at Vcc = 3.3 V and 25° C; Input common
mode = Vcc.
Figure 11. Data Input |S11| versus frequency of one
dice on wafer at Vcc = 3.3 V and 25° C; Input
common mode = Vcc.
|S11| vs. Frequency, 0.0 V Clock Input, All Conditions, Die #113
|S11| vs. Frequency (25 C, 3.3 V), 0.0 V Clock Input; N=33
0
0
-5
-5
-10
-10
-15
-15
-5 C 3.5 V
|S1 1| (dB)
|S1 1| (dB)
-5 C 3.3 V
-20
-25
-5 C 3.1 V
25 C 3.5 V
25 C 3.3 V
-20
25 C 3.1 V
-25
85 C 3.5 V
-30
-30
85 C 3.3 V
-35
-35
-40
-40
0
5
10
15
20
25
30
85 C 3.1 V
Specif ication
0
5
10
Frequency (GHz)
15
20
25
30
Frequency (GHz)
Figure 12. Clock Input |S11| versus frequency of 33
die on wafer at Vcc = 3.3 V and 25° C; Input common
mode = Vcc.
Figure 13. Clock Input |S11| versus frequency of one
dice on wafer at Vcc = 3.3 V and 25° C; Input
common mode = Vcc.
|S22| vs. Frequency (25 C, 3.3 V), DC-Coupled, Logic Low; N=33
|S22| vs. Frequency, DC Logic Low Out, All Conditions, Die #113
0
0
-5
-5
-10
-10
-15
-15
-5 C 3.5 V
|S2 2| (dB)
|S2 2| (dB)
-5 C 3.3 V
-20
-25
-5 C 3.1 V
25 C 3.5 V
25 C 3.3 V
-20
25 C 3.1 V
-25
-30
-30
-35
-35
-40
-40
85 C 3.5 V
85 C 3.3 V
85 C 3.1 V
0
5
10
15
20
25
30
Frequency (GHz)
Figure 14. Data Output |S22| versus frequency of 33
die on wafer at Vcc = 3.3 V and 25° C; Output in logic
low state. The output logic high state has about 3dB
more margin.
2008-04-04
13601DF_DS_Ver2.3
Specification
0
5
10
15
20
25
30
Frequency (GHz)
Figure 15. Data Output |S22| versus frequency of one
dice on wafer at Vcc = 3.3 V and 25° C; Output in
logic low state. The output logic high state has about
3dB more margin.
Inphi Proprietary
Page 7 of 9
QFN Package Outline Drawing and Pin Assignment
Name
Pin
Description
Function
DINp
3
Non-inverting Data Input
Input
DINn
2
Inverting Data Input
Input
CLKINp
6
Non-inverting Clock Input
Input
CLKINn
7
Inverting Clock Input
Input
DOUTp
11
Non-inverting Data Output
Output
DOUTn
10
Inverting Data Output
Output
GND
1, 4, 5, 8, 9, 12, 14,
paddle
Ground
Supply
VCC
13, 15, 16
Power Supply: Connect to +3.3 V
Supply
Note:
The paddle is the heat dissipation path and must be tied to the PCB ground planes by means of thermal vias.
2008-04-04
13601DF_DS_Ver2.3
Inphi Proprietary
Page 8 of 9
Order Information
Part No.
Description
13601DF-S02QFN
13 Gbps D Flip-Flop (+3.3 V Supply) in QFN Package
13601DF-S02QFN-EVB
13 Gbps D Flip-Flop (+3.3 V Supply) in QFN Package on an
Evaluation Board with SMA Connectors
Contact Information
Inphi Corporation
2393 Townsgate Road, Suite 101
Westlake Village, CA 91361
• Phone:
• Fax:
• E-mail:
(805) 446-5100
(805) 446-5189
products@inphi-corp.com
‚Visit us on the Internet at: http://www.inphi-corp.com
For each customer application, customer’s technical experts must validate all parameters. Inphi Corporation reserves the right to change
product specifications contained herein without prior notice. No liability is assumed as a result of the use or application of this product.
No circuit patent licenses are implied. Contact Inphi Corporation’s marketing department for the latest information regarding this product.
Qualification Notification
The 13601DF-S02 is fully qualified. Please contact Inphi for the qualification report.
Inphi Corporation will honor the full warranty as outlined in Section 5 of Inphi’s Standard
Customer Purchase Order Terms and Conditions.
Version Updates
From Version 2.2 to 2.3 (dated 2008-04-04)
1. Added the typical random and deterministic jitter numbers to the Features section (page 1).
2. Changed the jitter specifications in the Electrical Specifications table (page 3):
a. Changed “Deterministic Jitter” parameter name to “Added Deterministic Jitter”.
i. Added “at 12.5 Gbps” to the Test Conditions.
ii. Changed typical spec from 3 ps to 2 ps.
iii. Changed Max spec from 6 ps to 4 ps.
iv. Modified note #5.
b. Changed “Random Jitter” parameter name to “Added Random Jitter”.
i. Added “at 10 GHz” to the Test Conditions.
ii. Changed typical spec from 0.3 ps to 37 fs.
iii. Changed Max spec from 0.6 ps to 80 fs.
iv. Added note #6.
3. Added the requirement to use thermal vias from the package paddle to the PCB in the notes of the
QFN Package Outline Drawing and Pin Assignment section (page 8).
2008-04-04
13601DF_DS_Ver2.3
Inphi Proprietary
Page 9 of 9