a
CMOS ⴞ5 V/+5 V
4 ⍀ Single SPDT Switches
ADG619/ADG620
FEATURES
6 ⍀ (Max) On Resistance
0.8 ⍀ (Max) On-Resistance Flatness
2.7 V to 5.5 V Single Supply
ⴞ2.7 V to ⴞ5.5 V Dual Supply
Rail-to-Rail Operation
8-Lead SOT-23 Package, 8-Lead Micro-SOIC Package
Typical Power Consumption (<0.1 ␮W)
TTL/CMOS Compatible Inputs
FUNCTIONAL BLOCK DIAGRAM
ADG619/ADG620
S2
D
S1
IN
APPLICATIONS
Automatic Test Equipment
Power Routing
Communication Systems
Data Acquisition Systems
Sample and Hold Systems
Avionics
Relay Replacement
Battery-Powered Systems
SWITCHES SHOWN FOR A LOGIC "1" INPUT
GENERAL DESCRIPTION
Table I. Truth Table for the ADG619/ADG620
The ADG619 and the ADG620 are monolithic, CMOS SPDT
(single pole, double throw) switches. Each switch conducts
equally well in both directions when on.
IN
Switch S1
Switch S2
0
1
ON
OFF
OFF
ON
The ADG619/ADG620 offers low On-Resistance of 4 Ω, which
is matched to within 0.7 Ω between channels. These switches also
provide low power dissipation yet give high switching speeds.The
ADG619 exhibits break-before-make switching action, thus
preventing momentary shorting when switching channels. The
ADG620 exhibits make-before-break action.
The ADG619/ADG620 are available in 8-lead SOT-23 packages and 8-lead Micro-SOIC packages.
PRODUCT HIGHLIGHTS
1. Low On Resistance (RON) (4 Ω typ)
2. Dual ± 2.7 V to ± 5.5 V or Single 2.7 V to 5.5 V
3. Low Power Dissipation. CMOS construction ensures low
power dissipation.
4. Fast tON/tOFF
5. Tiny 8-Lead SOT-23 Package and 8-Lead Micro-SOIC Package
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADG619/ADG620–SPECIFICATIONS
DUAL SUPPLY1 (V
DD =
+5 V ⴞ 10%, VSS = –5 V ⴞ 10%, GND = 0 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.)
Parameter
+25ⴗC
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
–40ⴗC to
+85ⴗC
Unit
Test Conditions/Comments
8
V
Ω typ
Ω max
VDD = +4.5 V, VSS = –4.5 V
VS = ± 4.5 V, IS = –10 mA,
Test Circuit 1
Ω typ
Ω max
Ω typ
Ω max
VS = ± 4.5 V, IS = –10 mA
1.35
0.8
1.2
VSS to VDD
4
6
On Resistance Match Between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
0.7
1.1
0.7
± 0.01
± 0.25
± 0.01
± 0.25
VDD = +5.5 V, VSS = –5.5 V
VS = ± 4.5 V, VD = ⫿4.5 V,
Test Circuit 2
VS = VD = ± 4.5 V, Test Circuit 3
±1
nA typ
nA max
nA typ
nA max
2.4
0.8
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns min
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3.3 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 0 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF,
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 10
RL = 50 Ω, CL = 5 pF, Test Circuit 9
f = 1 MHz
f = 1 MHz
±1
0.005
CIN, Digital Input Capacitance
VS = ± 3.3 V, IS = –10 mA
2
2
DYNAMIC CHARACTERISTICS
ADG619
tON
tOFF
Break-Before-Make Time Delay, tBBM
80
120
45
75
40
155
90
10
ADG620
tON
Charge Injection
110
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–67
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
Bandwidth –3 dB
CS (OFF)
CD, CS (ON)
190
25
95
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
µA typ
µA max
tOFF
Make-Before-Break Time Delay, tMBB
40
65
200
330
160
85
400
10
POWER REQUIREMENTS
IDD
1.0
ISS
0.001
1.0
VDD = +5.5 V, VSS = –5.5 V
Digital Inputs = 0 V or 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG619/ADG620
SINGLE SUPPLY1
(VDD = +5 V ⴞ 10%, VSS = 0 V, GND = 0 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.)
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
ADG619
tON
tOFF
Break-Before-Make Time Delay, tBBM
B Version
–40ⴗC to
+25ⴗC
+85ⴗC
Unit
Test Conditions/Comments
12.5
V
Ω typ
Ω max
VDD = 4.5 V, VSS = 0 V
VS = 0 V to 4.5 V, IS = –10 mA,
Test Circuit 1
1.2
0.5
0.8
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to 4.5 V, IS = –10 mA
0 V to VDD
7
ß10
0.8
1
0.5
± 0.01
± 0.25
± 0.01
± 0.25
±1
2.4
0.8
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns min
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF,
VS1 = VS2 = 3.3 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3.3 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF,
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 10
RL = 50 Ω, CL = 5 pF, Test Circuit 9
f = 1 MHz
f = 1 MHz
±1
2
280
110
10
ADG620
tON
Charge Injection
6
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–67
dB typ
Channel-to-Channel Crosstalk
–67
dB typ
Bandwidth –3 dB
CS (OFF)
CD, CS (ON)
190
25
95
MHz typ
pF typ
pF typ
0.001
µA typ
µA max
tOFF
Make-Before-Break Time Delay, tMBB
50
85
210
340
170
110
420
10
POWER REQUIREMENTS
IDD
1.0
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
VDD = 5.5 V
VS = 1 V/4.5 V, VD = 4.5 V/1 V,
Test Circuit 2
VS = VD = 1 V/4.5 V,
Test Circuit 3
nA typ
nA max
nA typ
nA max
0.005
120
220
50
75
70
VS = 1.5 V to 3.3 V, IS = –10 mA
–3–
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
ADG619/ADG620
ABSOLUTE MAXIMUM RATINGS 1
PIN CONFIGURATIONS
(TA = 25°C unless otherwise noted)
8-Lead SOT-23
(RT-8)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6.5 V
Analog Inputs2 . . . . . . . . . . . . . . . . VSS –0.3 V to VDD +0.3 V
Digital Inputs2 . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 50 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Micro-SOIC Package
␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
␪JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
SOT-23 Package
␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . 229.6°C/W
␪JC Thermal Impedance . . . . . . . . . . . . . . . . . . 91.99°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C
D 1
S1 2
GND
8
ADG619/
ADG620
3
S2
7
VSS
6
IN
TOP VIEW
VDD 4 (Not to Scale) 5 NC
NC = NO CONNECT
8-Lead Micro-SOIC
(RM-8)
8 S2
D 1
S1 2
3
ADG619/
ADG620
7
VSS
6 IN
TOP VIEW
VDD 4 (Not to Scale) 5 NC
GND
NC = NO CONNECT
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
ORDERING GUIDE
Model
Temperature Range
Branding
Information*
Package Description
Package Option
ADG619BRM
ADG619BRT
ADG620BRM
ADG620BRT
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
SVB
SVB
SWB
SWB
Micro-SOIC (microSmall Outline IC)
SOT-23 (Plastic Surface Mount)
Micro-SOIC (microSmall Outline IC)
SOT-23 (Plastic Surface Mount)
RM-8
RT-8
RM-8
RT-8
*Branding on SOT-23 and Micro-SOIC packages is limited to three characters due to space constraints.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG619/ADG620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADG619/ADG620
TERMINOLOGY
Mnemonic
Description
V DD
VSS
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be
tied to ground at the device.
Ground (0 V) Reference
Positive Supply Current
Negative Supply Current
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
Ohmic Resistance Between D and S
On Resistance Match Between Any Two Channels, i.e., RON Max – RON Min.
Flatness is Defined as the Difference Between the Maximum and Minimum Value of On Resistance as
Measured Over the Specified Analog Signal Range.
Source Leakage Current With the Switch “OFF”
Channel Leakage Current With the Switch “ON”
Analog Voltage on Terminals D, S
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
“OFF” Switch Source Capacitance
“ON” Switch Capacitance
Delay Between Applying the Digital Control Input and the Output Switching On
Delay Between Applying the Digital Control Input and the Output Switching Off
“ON” Time, Measured Between the 80% Points of Both Switches, When Switching From One Address
State to Another
“OFF” Time or “ON” Time Measured Between the 90% Points of Both Switches, When Switching from
One Address State to Another
A Measure of the Glitch Impulse Transfered From the Digital Input to the Analog Output During Switching
A Measure of Unwanted Signal that is Coupled Through From One Channel to Another as a Result of
Parasitic Capacitance
A Measure of Unwanted Signal Coupling Through an “OFF” Switch
The Frequency Response of the “ON” Switch
The Loss Due to the ON Resistance of the Switch
GND
IDD
ISS
S
D
IN
RON
DRON
RFLAT(ON)
IS (OFF)
ID, IS (ON)
VD (VS)
VINL
VINH
IINL(IINH)
CS (OFF)
CD, CS (ON)
tON
tOFF
tMBB
t BBM
Charge Injection
Crosstalk
Off Isolation
Bandwidth
Insertion Loss
Typical Performance Characteristics
18
VDD, VSS = ⴞ2.5V
16
6
TA = 25ⴗC
VSS = 0V
5
VDD = 3V
14
VDD, VSS = ⴞ3V
ON RESISTANCE – ⍀
ON RESISTANCE – ⍀
7
6
VDD = 2.7V
ON RESISTANCE – ⍀
8
12
5
10
VDD, VSS = ⴞ3.3V
4
VDD, VSS = ⴞ4.5V
3
VDD = 3.3V
VDD, VSS = ⴞ5V
2
8
VDD = 4.5V
6
VDD = 5V
TA = –40ⴗC
2
4
TA = 25ⴗC
0
–5 –4
2
0
–3 –2
–1 0 1
VD, VS – V
2
3
4
5
TPC 1. On Resistance vs. VD (VS) –
Dual Supply
REV. 0
0
1
3
2
VD, VS – V
4
5
TPC 2. On Resistance vs. VD (VS) –
Single Supply
–5–
TA = +25ⴗC
3
1
1
TA = +85ⴗC
4
VDD = +5V
VSS = –5V
0
–5 –4 –3 –2
1
–1 0
VD, VS – V
2
3
4
5
TPC 3. On Resistance vs. VD (VS) for
Different Temperatures – Dual Supply
ADG619/ADG620–Typical Performance Characteristics
0.5
9
0.4
LEAKAGE CURRENTS – nA
ON RESISTANCE – ⍀
8
TA = +85ⴗC
7
6
TA = +25ⴗC
5
TA = –40ⴗC
4
3
VDD = 5V
VSS = 0V
2
0.3
0
–0.2
–0.3
–0.5
3
2
VD, VS – V
4
5
ID, I S (ON)
–0.1
0
1
IS (OFF)
0.1
–0.4
250
20
10
0
30 40 50 60
TEMPERATURE – ⴗC
70
80
tOFF
40
VDD ⴝ 5V
VSS ⴝ 0V
20
0
–5 –4 –3
–2
–1
0 1
VS – V
2
3
4
TPC 7. Charge Injection vs. Source
Voltage
–10
0
–20
–2
–30
–4
–40
–50
–60
VDD = +5V
VSS = –5V
TA = 25ⴗC
–70
–80
0.2
1
10
FREQUENCY – MHz
–20
0
20
40
60
TEMPERATURE – C
80
TPC 8. tON/tOFF Times vs. Temperature
ATTENUATION – dB
ATTENUATION – dB
0
–40
5
VDD ⴝ +5V
VSS ⴝ –5V
ALTERNATION – dB
TIME – ns
CHARGE INJECTION – pC
tON
100
60
50
IS (OFF)
–0.2
–0.3
0
10
20
30 40 50 60
TEMPERATURE – ⴗC
70
80 0
–30
VDD ⴝ +5V
VSS ⴝ –5V
120
VDD ⴝ 5V
VSS ⴝ 0V
–0.1
–20
VDD ⴝ 5V
VSS ⴝ 0V
140
100
0
–10
160
150
ID, I S (ON)
0.1
TPC 6. Leakage Currents vs.
Temperature – Single Supply
180
VDD ⴝ +5V
VSS ⴝ –5V
0.2
–0.5
80 0
TA = 25ⴗC
200
0.3
–0.4
TPC 5. Leakage Currents vs.
Temperature – Dual Supply
TPC 4. On Resistance vs. VD (VS) for
Different Temperatures – Single Supply
VDD = 5V
VSS = 0V
VD = 4.5V/1V
VS = 1V/4.5V
0.4
0.2
1
0
0.5
VDD = +5V
VSS = –5V
VD = ⴞ4.5V
VS = ⴟ4.5V
LEAKAGE CURRENTS – nA
10
–40
–50
–60
–70
–80
VDD = +5V
VSS = –5V
TA = 25ⴗC
–90
–100
0.03
1
10
FREQUENCY – MHz
100
TPC 9. Off Isolation vs. Frequency
VDD = +5V
VSS = –5V
TA = 25ⴗC
–6
–8
–10
–12
100
TPC 10. Crosstalk vs. Frequency
0.2
1
10
100
FREQUENCY – MHz
1000
TPC 11. On Response vs. Frequency
–6–
REV. 0
ADG619/ADG620
TEST CIRCUITS
IDS
V1
S
VS
IS (OFF)
D
ID (OFF)
S
ID (ON)
D
VD
VS
RON = V1/I DS
Test Circuit 1. On Resistance
0.1␮F
0.1␮F
S
50%
VIN
D
CL
35pF
GND
50%
90%
90%
VOUT
RL
300⍀
VOUT
t ON
t OFF
Test Circuit 4. Switching Times
VDD VSS
0.1␮F
0.1␮F
S1
VS1
VIN
VDD VSS
D2
D
S2
VS2
RL2
300⍀
IN
VIN
CL2
35pF
VOUT
VOUT
50%
0V
50%
90%
90%
0V
GND
t BBM
t BBM
Test Circuit 5. Break-Before-Make Time Delay, tBBM (ADG619 Only)
0.1␮F
VDD VSS
0.1␮F
VDD VSS
VS1
VIN
VD
RL1
300⍀
VS1
IN
VIN
RL2
300⍀
GND
CL2
35pF
CL1
35pF
0V
50%
50%
VS1
80%VD
80%VD
VS2
t MBB
Test Circuit 6. Make-Before-Break Time Delay, tMBB (ADG620 Only)
RS
VS
VDD
VSS
VDD
VSS
D
S
VIN
VOUT
CL
1nF
IN
GND
S2
∆VOUT
VOUT
S1
∆VOUT
QINJ = CL ⴛ ∆VOUT
Test Circuit 7. Charge Injection
REV. 0
–7–
A
Test Circuit 3. On Leakage
VDD VSS
IN
D
VD
Test Circuit 2. Off Leakage
VDD VSS
VS
S
NC
ADG619/ADG620
VDD
VSS
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
S
VS
50⍀
VOUT
RL
50⍀
GND
OFF ISOLATION = 20 LOG
R
50⍀
IN
VS
GND
VOUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VS
VOUT
VS
Test Circuit 10. Channel-to-Channel Crosstalk
Test Circuit 8. Off Isolation
VDD
D
S2
D
VIN
VSS
S1
R
50⍀
50⍀
50⍀
0.1␮F
VDD
VOUT
IN
VSS
0.1␮F
0.1␮F
C02617–.8–10/01(0)
VDD
0.1␮F
VSS
0.1␮F
0.1␮F
VDD
NETWORK
ANALYZER
VSS
S
50⍀
IN
VS
D
VOUT
VIN
RL
50⍀
GND
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH
VS WITHOUT SWITCH
Test Circuit 9. Bandwidth
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Micro-SOIC Package
(RM-8)
8-Lead Plastic Surface Mount Package
(RT-8)
0.122 (3.10)
0.114 (2.90)
5
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
PIN 1
0.0256 (0.65) BSC
6
5
1
2
3
4
PIN 1
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
7
0.071 (1.80)
0.059 (1.50)
4
0.006 (0.15)
0.002 (0.05)
8
PRINTED IN U.S.A.
8
0.122 (3.10)
0.110 (2.80)
0.077
(1.95)
BSC
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
33ⴗ
27ⴗ
0.051 (1.30)
0.035 (0.90)
0.028 (0.71)
0.016 (0.41)
0.006 (0.15)
0.000 (0.00)
–8–
0.026
(0.65) BSC
0.057 (1.45)
0.035 (0.90)
0.015 (0.38)
0.009 (0.22)
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
10ⴗ
0ⴗ
0.022 (0.55)
0.014 (0.35)
REV. 0