ADVANCED ANALOG CIRCUIT
DESIGN TECHNIQUES
Spring 2013
C
S
M
Edgar Sánchez-Sinencio
A
Office: 318-E WERC
e-mail: sanchez@ece.tamu.edu
When: TR 9:35-10:50am
Where: ETB 1003
1
Analog and Mixed-Signal Center at Texas A&M University
ELEN 607
Advanced Analog Circuit Design
Techniques
Required background:
1. How to optimally bias your CMOS circuits
2. How to use MOS transistor models
3. Derive transfer functions from small signal circuits
- Use of nodal admittance matrix
1. Stability Criteria.
- How to determine pole and zeros.?
- Routh Hurtwitz Criteria
- Reduction of a higher-order system into a
2nd-order function
1. How to design:
1. Inverting Amplifiers
2. Current mirrors and current sources
3. Differential pairs, and low noise amplifiers
4. Simple Transconductor Amplifiers
5. Two Stage Conventional Operational Amplifiers
2
Analog and Mixed Signal Center, TAMU (ESS)
6. Basic common-mode feedback structures for Fully
Differential Operational Amplifiers
7 Common Mode Feedback Concept
Required background (continues):
• Use CADENCE for
• Noise Analysis
• Monte Carlo Analysis
• S/N ratio determination
• Pole and zero determination
• Temperature effects
• Use of non-linear dependent sources
• Use of SIMULINK for systems analysis,
modeling and characterization
3
Analog and Mixed Signal Center, TAMU (ESS)
What is the motivation?
The knowledge and applications of analog circuits in medical
electronics, modern mixed-signal VLSI chips for multimedia,
perception, control, instrumentation and telecommunication are vital
design element of any practical system.
• What are the challenges in designing low voltage circuits ?
- To perform with technologies smaller than 90 nm
- To operate with power supplies smaller than 1 volt
- To design circuits with the same performance or better
than circuits designed for larger power supplies
-To come with new design alternatives
4
Analog and Mixed Signal Center, TAMU (ESS)
Why Low-Voltage Analog Integrated Circuits?
• Modern CMOS feature size is continuing to be
scaled down to have a high fT and large component
density. In addition the maximum allowable power
supply voltage continuously decreases.
• Therefore portable batterypowered equipment also
necessitates low-voltage lowpower circuit design.
5
( continues)
• Why are we concerned in designing low voltage circuits ?
- Designers could not use conventional cascode structures,
and other conventional design methodologies yielding high
signal swing.
- Circuits must have the same performance or better than
circuits designed for larger power supplies
- Circuit performance with technologies smaller than 65 nm
must be better than circuits for larger technologies.
-Third-generation communication applications require circuits
( and systems) with improved dynamic range over a much
wider bandwidth.
- New building blocks and systems must be designed to
satisfy the needs of portable, lighter, cheaper and faster
equipment
6
• When transistors operate in saturation, how deep in saturation
should they operate ?
Vds >Vgs-Vt ? By how much ? How can one answer this question?
• Can one model transistor with one equation valid for all regions of
operation?
• If LV circuits do not allow cascode circuits, what are the alternatives?
-Floating Gate
- Bulk Driven
- Nested Gm-C ( cascade plus optimal feedback compensation)
- Self Cascode Transistor
7
- NP Differential Pairs
Analog and Mixed Signal Center, TAMU (ESS)
Global Microsystems Growth Forecasts*
Telecommunication & Communications Marker
Semiconductor Market
Embedded Technology Market
Intelligent Wireless Microsystems
Image Sensors
Biotechnology Market
Medical Devices Market
Biophotonics Chip Products
Biochips Market
BioMEMS
Microfluidics Technology Market
Semiconductors in Industrial/Medical Applications
Lab-on-Chip
Laser Transmitters
Worldwide MEMS Systems
Optical Components
* From CMC Microsystems Annual Report 2009 (www.cmc.ca)
13% (2005-2012)
6% (2008-2013)
4.1% (2008-2013)
56.4% (2008-2013)
7.2% (2008-2013)
12.3% (2005-2010)
6.2% (2007-2012)
11% (2004-2014)
12.7% (2006-2013)
17% (2008-2012)
14% (2006-2011)
8.8% (2007-2013)
36%(2004-2012)
11% (2006-2011)
15% (2005-2010)
14% (2007-2012)
AMSC-TAMU by Edgar Sanchez-Sinencio
8
Technology Forecast
(from
http://www.itrs.net/
Year of
Production
2009
2011
2013
Supply
Voltage(V)#
1/2.5
0.93/1.8
DRAM ½ Pitch
(nm) (contacted)
52
Gate length(nm)
2015
ITRS Roadmap 2009)
2017
2019
0.87/1.8 0.81
0.76
0.71
40
32
25
20
15.9
37/250
28/180
22/180
Threshold
Voltage (V)
0.33
0.31
0.29
0.27
0.25
0.23
Gm/gds at
30(220)
30(160)
30(160)
1/f noise
(uv2.um2/Hz)
100/500
80/180
70/180
NFmin(dB)
0.20
<0.2
<0.2
Peak Ft (GHz)
240/40
320/50
400/50
Peak Fmax
(GHz)
370/40
480/50
590/50
5(10)Lmin
# one data is for Performance RF/Analog and the other for Precision Analog/RF Driver
9
Remarks.• Power supply reduction helps digital circuits for power
consumption but hurts analog voltage swing which should
not be reduced.
• Inherent transistor voltage gain decreases with reduced
size technology, this implies larger number of stages to
compensate the overall voltage gain.
• Threshold voltages do not reduce linearly with size of
technology, making the design with low VDD harder for
analog circuits
10
AMSC-TAMU by Edgar Sánchez-Sinencio
Concerns about low power supply voltage
VTH
Scaling down size technology and
supply voltage does not scale linearly
the “ VTH hat ”
VTH
Mister 3.3 volts IC
Mister 0.6 volts IC
• Also VDSAT does not scale down linearly with power supply
nor with smaller size technologies.
11
Remarks on low power supply voltage integrated
circuits
Technology trends show that in every generation:
• Circuit delay is scaling down by 30%
• Supply voltages are also scaling by 30%
• Transistor’s threshold voltage is reduced by nearly 15%
• Transistor density and digital performance are double
approximately every two years.
• Higher power dissipation and temperature.
Reference . W. M. Elgharbawy and M. A. Bayoumi, “Leakage Sources and Possible Solutions in Nanometer
CMOS Technologies
” IEEE Circuits and Systems Magazine, pp. 6-15, Fourth Quarter 2005
12
TRANSISTOR REGIONS OF OPERATION
• How to determine how much bias current is needed for
certain application ?
• When a designer operates transistors in saturation,
what does it mean VDS > VDS(SAT) ?
• Can a circuit have their transistors operating in the
(moderate inversion) transition region ? What transistor
model equation can be employed ?
13
One Equation-All Regions Transistor Model
•
•
Features of ACM model:
– physics-based model,
– universal and continuous expression for any inversion level
– independent of technology, temperature, geometry and gate voltage,
– same model for analysis, characterization and design.
Main design equations: (design parameters: I, gm, if)
1
I

t g m n
fT 
1 i f
2
 t
2 1  i f  1
2L2
gm
W
1

L Coxt 1  i f  1
VDSAT
t
W

L

 1 i
f

1  4
gm
 I

2Coxt 
 1
 t g m n 
I  transistor drain current
gm  transconductance in saturation
n  slope factor
t  thermal voltage
if  inversion level of the transistor defined as
i f  I I s , where I  nC  W is the
2 L
normalization current.
2
t
s
ox
if << 1  weak inversion,
if >> 1  strong inversion.
14
•Current-based MOSFET
model(drain current split into
a forward and a reversed term:
ID  IF  IR
2
W 1
VGB  nVSB ( DB )  VT 0 

L 2n
V V
VDB  GB T 0
n
I F ( R )  Cox
•Forward saturation
I F  I R and I D  I F
•Normalized output characteristic:
 1  if 1 
VDS

 1  i f  1  i r  ln 
 1  i 1 
t
r


I F( R )
W
ISQ =technological parameter
if (r) 
IS  ISQ  
IS
L
(slightly dependent on VG)
15
The Saturation Voltage
A
gms
gmd
= gain in CG configuration


VDSSAT
1

 ln A   1   1  i f  1
t
 A
1

1   — saturation level
 A
10
10
1
0
•Strong inversion
VDSSAT  t it  (VG  VT ) / n
VDSsat
10
A = 100
-1
A = 30
A = 10
•Weak inversion
VDSSAT  t . ln A
10
-2
-2
10
-1
10
0
10
1
10
10
Inversion level – if-
2
3
10
4
10
16
Drain Current and Aspect Ratio
g m  2  GBW  CL
I D  g m  n  t
1 1 if
2
gm  1  1  i f
W


L   Cox  t 
id

10
10
10




10
10
2
1
0
I BIAS
2  g m  n  t
W L
g m 2    Cox   t 
-1
-2
10
-2
10
0
10
2
10
Normalized ID and W/L vs. if
normalized
normalizedIDID
normalized
normalizedW/L
W/L
WI (if1)
MI (if=8)
1/2
1
4 / if
1
SI (if1)
if / 4
2/
if
17
4
id
Correlation Between Area and Frequency Response
CL GBW
WL  2
Cox
fT

Correlation Between Junction Capacitance (CJ) and Frequency Response
Parasitic capacitance  GBW/fT
CJ  CJ   W  L DIF
LDIF
W
CJ
CJ L DIF GBW
2
CL
Cox L
fT
CJ
18
BIPOLAR
MOS
IBIAS=IC
DC Circuit
Transconductance
-to-current-ratio
(gm/ID)
CL
+
VI
-
+
VO
-
gm 1

IC t
VA

t
DC Gain
(Avo)
A vo
Gain-Bandwidth
Product (GBW)
GBW 
Intrinsic Cutoff
Frequency (fT)
fT 
Minimum Output
Voltage (VO)
IBIAS=ID
1 IC
2CL  t
1
2
VCEsat
 6 to 8
t
CL
+
VI
-
+
VO
-

gm 1 
2

I D t  n 1  1  i f




VA 
2
Avo  
t  n 1  1  i f


GBW 
fT 






1 ID 
2
2 CL t  n 1  1  i f


1
2
VDSsat
t





2








1  i f 1

1  i f 1  4
19
20
Design Methodology
1 - Select the inversion level (if)
for 'optimal' design (ID, W/L).
I D  g m  n  t
2


gm
W
1



  t  1  i f  1 
L   Cox


VDSsat
t
2 - Choose both W and L. If
fTGBW, add the parasitic
capacitances (CJ, Cov) to CL.
1 1 if



1  i f 1  4
CJ  Cov
1
CJLDIF  CGDO GBW
2
CL
LCox
fT
3 - Verify if the spec for Avo is met. Otherwise, increase the channel
length and/or reduce id (cascode/cascade design can be necessary).
4 - Take into account VDSsat and the parasitic capacitance of the
current source.
21
• Process technology to choose
• Cost
• Performance
• Compatibility
• Design approach and testing time
• Floating Gate
• Bulk-driven
• LV techniques
• Region of operation
• Weak inversion
• Moderate inversion
• Ohmic region
• Saturation ( strong inversion)
22
Small Size Technology
• The good news is that we will be able to run our
ICs faster i.e., circuit delay is scaling down by 30% every
generation.
• The bad news is that leakage power dissipation
increases in a much faster rate than dynamic
power
100
20
0.01
.001
Power (W)
Leakage Power
Active Power
1970
1990
2000
23
Example: 90nm
• sub-threshold leakage increases exponentially with
every 65mV decrease in threshold voltage
24
LEAKAGE SOURCES IN CMOS CIRCUITS
1. Subthreshold leakage in the channel in an OFF
transistor between the source and drain
terminals (Isub)
2.
Reverse-bias source/drain junction leakage (IRB)
3. Gate leakage ( IGATE)
25
NMOS TRANSISTOR and ITS THREE MAIN LEAKAGE SOURCES
Isolation Oxide
VDS
VGS
gate
source
source
gate
drain
p
n+
n+
n+
p
p
p
n+
p
n+
p
p
p
n+
n+
p
substrate
drain
ID
p
n+
p
p
p
p
p
p
p
p- substrate
Top view
VGS = 0, VDS = 0 (cutoff)
Well
Drain
IRB
IGate
Well
Gate
IRB
Source
Isub
26
High Speed Amplifiers Remarks
• Op Amps usually have more than one high
impedance node, this slow significantly the speed
of amplifier. Recall that poles are inversely
proportional to time constants. Thus large
impedance node imply poles near the origin.
• Transconductance Amplifiers have ideally only
one high impedance node, all the internal nodes
are low impedance. This produces low voltage
gains but the highest frequency response.
27
Course Objectives:
To understand at the macromodel level the circuit design
parameter tradeoffs.
To design optimal circuits, that is circuits that meet the
specifications with minimum area, design time and/or power.
To identify the effect of the non-idealities of actual circuits
and how to overcome these problems.
28
Next we review the conventional Op Amp Design
frequency response compensation techniques
and also we introduced a simple LV CurrentMode based Op Amp using resistors as
transconductors. Difference Differential
Amplifiers are also introduced.
29
UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER
VDD
M4
M3
Vin
C p1
M2
M1
1

in
V
2
High
Impedance
v o1
Node 3
M8
Cp2
M7
M5
Vbs
M6
3
CL
M9
VSS
is a low impedance
vo
AV3 ~ 1
M1=M2; M3=M4
Ignoring zeros we can model this topology as:
Vin
V

in
+ Input
-
io1
1
Stage
R o1
C p1
Second
Stage
 gm6
go6  go7
io2
2
Ro 2
Cp2
g o 2  g 04
C p1
AV1 0  
g m1
g o1  g o 3
AVT s  
AV 1 0  AV 2 0  AV 3 0 
g
;  p3  m 8
1  s  p1 1  s  p2 1  s  p3 
CL
; AV2 0  
;  p1 
Output
Stage
3
Ro 3
;  p2 
CL
vo
go6  go7
C p2
30
30
UNCOMPENSATED CMOS OPERATIONAL
AMPLIFIER STABILITY ISSUES
• The low frequency voltage gain is high enough for a number of
applications.
• The open loop poles are far from the origin, this can cause stability
problems for closed loop applications.
• Closed loop poles might end very close to the jw axis and some in
the RHP.
• How to tackle this stability problem will be discussed next.
31
Two-Stage Uncompensated Amplifier
VDD
M3
M4
M6
I o
2
Io
2

vin
M2
M1
I6

vin
Ig
Vout
Io
I7
M7
M5
VSS
Uncompensated Operational Amplifier
 A V  A V1A V 2 
g m2
g m6
g 02  g 04 g 06  g 07
Large voltage gain
 Poles are close to the j axis causing stability problems
32
32
Employing a simple capacitor will split correctly the poles but will generate a
Zero in the RHP.
Using an RC compensation can eliminate the zero and split poles. The resistor
can be implemented with transistor in the ohmic region.
VDD
M4
M3
M8
A

v in
M6
M2
M1
CC
M1
0
M11
Vout
B
M9
M5
v bias
M7
VSS
Improved internally compensated CMOS operational
amplifier. Better bias for the output stage (M8 and M9)
33
Analog and Mixed Signal Center, TAMU (ESS)
33
A variation at the output stage with class – AB is shown below.
VDD

M4 vDS4

M3

vin
M2
M1
v GS6
+
v GS 9
I o
2
Io
2
M9
IL
M8
CL
CC
I10
+
M5
I6
M6

v in
Io
Vbias
+
M7
v GS 7
-
M10
VSS
CMOS op-amp with class-AB output stage and RC pole splitting.
34
34
“Pole Splitting” can be carried out with a compensation capacitor
feedback and a voltage buffer as shown below
M3
M8
M4
M10 M12
Ibias

vin
M1
M2
Out
 CC
vin
M7
M5
M6
M9
M11
Two-Stage amplifier with source follower compensation scheme
• Without M12 and M11 a zero in the PRH
• With buffer (voltage follower), zero is eliminated and pole splitting
(due to CC ) is kept.
35
35
An Improved Frequency Compensation
Technique for CMOS Operational
Amplifiers using Current Buffers
ECEN 607 (ESS)
Courtesy of Hatem Osman
Background.Two-Stage Op-amp with Miller compensation
•
The first stage is a differential-input/single-ended output stage,
and the second stage is a class A or class AB inverting output
stage.
Cc
VIN,p
VIN,n
gm1
•
VOUT
gm2
ro1
Cp
•
Transfer Function
•
Pole/zero locations
DC Gain
ro2
CL
RHP zero
Dominant Pole
Non-dominant Pole
37
Two-Stage Op-amp with Miller compensation
•
Pole Splitting
Cc
•
VIN,p
VIN,n
gm1
•
VOUT
gm2
ro1
Cp
Pole/zero locations
ro2
CL
Pole-zero position diagram
Increasing Cc achieves sufficient pole-splitting thus improving the PM. However, the
larger Cc shifts the RHP zero to lower frequencies thus ruining the PM.
38
Miller Op-amp with Nulling Resistance
•
Introducing a small series resistance in series with Cc may
cancel the RHP zero or shift it to the LHP.
Rc
Cc
•
VIN,p
VIN,n
gm1
VOUT
gm2
ro1
Cp
Pole/zero locations
ro2
CL
No zero
LHP zero – Can be used to cancel the
first non-dominant pole.
•
Disadvantages:
•
To achieve a sufficient phase margin, second pole cross-over of the unity gain
frequency should be avoided.
Thus, the Op-amp stability is severely degraded for capacitive loads of the same
order as compensation capacitor.
39
Improved compensation technique
•
The RHP zero is a result of the feed-forward path through Cc.
Cc
VIN,p
V1
gm1
VIN,n
ro1
•
VOUT
gm2
Cp
ro2
CL
The RHP zero can be eliminated if we cut the feed-forward path
and make the compensation capacitor unidirectional.
Virtual Ground
Cc
VIN,p
VIN,n
V1
gm1
VOUT
gm2
ro1
Cp
ro2
CL
40
Improved compensation technique
Virtual Ground
•
Cc
VIN,p
VIN,n
V1
gm1
VOUT
gm2
ro1
Cp
DC Gain
ro2
CL
Dominant Pole
Non-dominant Pole
41
Improved compensation technique
Miller compensation with nulling
resistance
Improved compensation technique
Dominant pole
Dominant pole
Non-dominant pole
Non-dominant pole
Gain-bandwidth product
Gain-bandwidth product
Phase margin
Phase margin
42
Circuit Implementation
•
Miller compensation with nulling resistance.
VDD
VB,p
VIN,n
VB,p
Mp,0
Mp,1
Mp,2
VIN,p
Mp,1
Rc
VOUT
Cc
CL
Mn,1
Mn,1
Mn,2
VSS
•
Improved compensation technique.
VDD
VB,p
VIN,n
Mp,1
VB,p
Mp,0
Mp,2
Cc
VIN,p
Mp,1
VB,p
Mp,3
Mp,4
VOUT
Mn,1
Mn,1
VB,n
CL
Mn,3
Mn,2
VSS
43
Other performance parameters- PSR
•
Miller compensation with nulling resistance.
VDD
VIN,n
VB,p
Mp,0
Mp,1
Mp,2
VIN,p
Mp,1
Rc
VOUT
Cc
VSS PSR
VB,p
-20log(Av,0)
CL
Mn,1
Mn,1
freq
Mn,2
fp1
VSS
•
Improved compensation technique.
VDD
VIN,n
Mp,1
VB,p
Mp,0
Mp,2
Cc
VIN,p
Mp,1
VB,p
Mp,3
Mp,4
VSS PSR
VB,p
VOUT
-20log(Av,0)
Mn,1
Mn,1
VB,n
CL
Mn,3
freq
fp1
Mn,2
•
VSS
1/ro1Cp
GBW
Better PSR at high
frequencies.
44
Design Example – Miller Compensation
•
Design an OTA with GBW > 5MHz, CL=10pF, PM>70, and SR> 2
V/µs.
•
Choose Cc=CL/2= 5 pF.
VDD
VB,p
VIN,n
Mp,1
VB,p
Mp,0
•
GBW > 5MHz
•
SR > 2 V/µS
•
PM > 70°
Mp,2
VIN,p
Mp,1
Rc
VOUT
Cc
CL
Mn,1
Mn,1
VSS
Mn,2
Let
Then
•
Choose Rc > 1/gm2
45
Design Example – Miller Compensation
•
Simulation results
OL Transfer function
Positive supply rejection
Negative supply rejection
Transient step response
46
Design Example – Miller Compensation
•
Capacitive load driving capability
•
PM > 70° for CL < 15 pF.
47
Design Example – Improved Compensation
•
Design an OTA with GBW > 5MHz, CL=10pF, PM>70, and SR> 2
V/µs.
•
Choose Cc=CL/2= 5 pF.
VDD
VB,p
VIN,n
Mp,1
VB,p
Mp,0
Mp,2
Mp,4
VOUT
Mn,1
Mn,1
VB,n
GBW > 5MHz
•
SR > 2 V/µS
Cc
VIN,p
Mp,1
VB,p
Mp,3
•
CL
Mn,3
Mn,2
In order to make the current transformer
biased during slewing interval
•
PM > 70°
VSS
Let
Then
 Let’s use gm2=6gm1 like the miller Opamp to make a comparison between
the capacitive driving capability.
 For the same capacitive load driving
capability, the second stage will
consume less current making it suitable
for low power applications
48
Design Example – Improved Compensation
•
Simulation results
OL Transfer function
Positive supply rejection
Negative supply rejection
Transient step response
49
Design Example – Improved Compensation
•
Capacitive load driving capability
•
PM > 70° for CL < 100 pF.
50
Design Example – Improved Compensation
•
Summary of Simulation results
Parameter
Spec
Miller
Compensation
Improved
Compensation
GBW
> 5MHz
5.5 MHz
6 MHz
PM
> 70°
75°
87.6°
SR+
> 2 V/µs
2.75 V/µs
3 V/µs
SR-
> 2 V/µs
3 V/µs
3.15 V/µs
PSR-
-
-65.6 dB
At (0-3.1 kHz)
-51.9 dB
At (0-245.4 kHz)
PSR+
-
-97.2 dB
At (0-44 kHz)
-37.2 dB
At (0-538.9 kHz)
DC gain
-
64.5 dB
51.3 dB
Current
consumption
-
80 µA
110 µA
Capacitive load
driving capability
-
PM > 70° for
CL < 15 pF
PM > 70° for
CL < 100 pF
51
Using another current buffer Op Amp topology.
M3
M4
M12
Ibias

v in
M8
M7
M1
M2

v in
Vout
M11
CC
M5
M6
M9
M10
Two-Stage amplifier with Current Buffer compensation scheme.
• Improve SR at the expense of power consumption.
52
52
Differential Output Two Stage Amp with a capacitor compensation
with a current Buffer ( Common Gate)
53
54
Note that this and previous structure are fully differential but this approach
could be used for single output topologies.
Compensation using a current buffer ( current gain)
Note that the current-mirror introduces an extra inversion which must be taken
into consideration for the single ended version.
P.J. Hurst, Lewis, S.H. ; Keane, J.P. ; Aram, F. ; Dyer, K.C.
“ Miller compensation using current buffers in fully differential CMOS two-stage operational
amplifiers” IEEE Transactions on Circuits and Systems I, Volume: 51 , Issue: 2, Feb. 2004
55
Besides the above zero the
amp has three poles
Elements of Current-Mirror Cc compensated
Note that the common-gate and current mirror topologies under ideal case are
almost identical, however in practice the one using current-mirrors is more power hungry
and has a larger parasitic capacitance CB
56
Summary for Two Stage Op Amp Architecture Designs
• Roots close to the j axis for uncompensated
Q6
s p1 s p
2
Vin
Vin
 I ss
Vbias
CL
I bias
• Potentially unstable for some values of CL
Ibias = CLSR*2.5
Q7
Q5
Q6
Q9
Vin
Vin
I bias
 I ss
Vbias
Vo
Q7
Q10
Q5
Q6
Q9
Vin
Vin
 I ss
Vbias
Q5
Vo
CC
Pole splitting => one dominant pole
s p1
I bias
Q7
Q10
• Improved output stage optimal bias of Q6 and Q7
• No significant change of pole locations.
Av (0) -> +
Av () -> -
 s
z1
p2
z1 Phase deteriorates phase margin
The good and the bad news
57
Analog and Mixed Signal Center, TAMU (ESS)
Two possible solutions to cancel z1 and keeping sp2 > t =GBW and sp1 small
Vo
Vo
Vin
Vin
CC
CL
CC
I ss
I ss
Vbias
Internally Compensated
with RC CC
Vbias
Q10
Q11
Internally Compensated
with unity gain buffer
(Q10, Q11)
Operational Amplifier (conventional) Architectures.
Reader.- See the internally Op Amp compensated with current gain
buffer in previous pages
58
Analog and Mixed Signal Center, TAMU (ESS)
Folded Cascode, Two stage and
Class A/AB two stage Amplifiers
59
Techniques for Wideband Amplifiers
Focus the improvement in the load of the differential pair
R
Current Mirror
at the output load
Frequency Dependent
Current Mirror (FDCM)
CF >> Cgs
Conventional
Wideband Alternative
CF
Ib
0.1K < R < 1K
CF
Low Frequency
Behavior
High Frequency
Behavior
T. Itakura and T. Iida, “A Feedforward Technique with Frequency-Dependent Current Mirrors for a Low-Voltage
60
Wideband Amplifier,” IEEE J. Solid-State Circuits, Vol. 31, No.6, pp. 847-849, June 1996.
An example of its use:
M P3
VDD
R3
vin
Ib
M P2
M P1
CF1
M P4
vin
vo
CL
CF2
M P3
R1
M n1
M n2 R2
M n4
 VSS
Wideband Amplifier with Feedforward Technique
• What is the optimal value of R1 as a function og GmP3 ?
• CF1 by passes two current mirrors.
• CF2 is fed forward to the input of another FDCM and signal
is amplified.
61
Next, we discuss different families of wideband reported in the
literature.
RL
vo
M n3

vin
A
vo
M n2
M n1
B
CF
RL
M n4
A

vin
• An alternative is to
connect CF instead
to nodes B to nodes A
B
RSS
CF
F. Centurelli et al, “A Bootstrap Technique for Wideband Amplifiers,” IEEE Trans. on Circuits
And Systesm – I, Vol. 49, No. 10, pp. 1474-1480, October 2002
62
FOLDED-CASCODE WIDEBAND AMPLIFIER
Vb4
M P4
Vb4
M P3
Vb1
Vb1
M P2

vin
R F1
M P1
Vb1

vin
Vb 2
C F2
M n5
Vb1
Vout
Vb2
CL
I tail
M n3
M n4
M n3

vin

vin
C F1
C LVOUT
I tail
( See page 11 for cascode)
M n4
FC with Capacitive Feedforward
Conventional Folded-Cascode (FC)
V DD
I bias
Vb1
R F1
Vb1
Vo
CL
C F1
R F2
Vo
Vb 2
Vb1
Vin
Vo
C F2
Vb 2
CL
 VSS
Differential Wideband Amplifier
63
F. Opt Eynde, W. Sansen, “A CMOS Wideband Amplifier with 800MHz Bandwidth,” IEEE Custom Integrated Circuits Conf., pp. 9.1.1-9.1.4, 1991
VDD
M5
M12
M6
M14
Vbias
IB
M1
vin
B
ib
M3
ON
io -
iR
M13
io-
OP
X
Figure 1
ON
-
A
ix
Figure 1
ON
V-
M8
R
X
X
IB
IB
IB
OP
v+
io+
M2
M4
M9
M10
VSS
Fig. 1 Transconductance Amp
Basic Structure based on current-mode
OP
io+
M11
Fig 2
Pseudo Differential Op Amp
iR = Vin/R
iX = - iR
IB > iR
E.K.F. Lee, “ Low-Voltage Opamp Design and Differential Difference Amplifier Design Using Linear Transconductor with Resistor Input
, “ IEEE Trans. Circuits and Systems II,vol. 47, pp 776-778, Aug. 2000
64
VDD
Transimpedance
amplifier
Vbias
CC
vo
io+
v+
Figure 2
io-
v-
R1
R1
VSS
Fig 3 VCVS Amplifier: Op Amp
io1+
v1+
v1-
Figure 2
Transimpedance
amplifier
vo
io2+
v2+
v2-
io1-
Figure 2
io2-
DDA
65
References
SS Rajput, SS Jamuar, Low voltage analog circuit design techniques, IEEE Circuits and
Systems Magazine, pp. 24-42, 2002
S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial,
IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp 179-196, February 2000
E. Sánchez-Sinencio and Andreas G. Andreou, Eds. “ Low-Voltage/Low-Power Integrated
Circuits and Systems “, IEEE Press, Piscataway, NJ 1999
X. Xie, M.C. Schneider, E. Sanchez-Sinencio and S.H.K. Embabi, “ Sound Design of Low
Power Nested Transconductance-Capacitance Compensation Amplifiers”, IEE
Electronics Letters, Vol. 35, pp.956-958, June 1999.
A.
Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and
Low-Power Analog and Mixed-Signal Circuits and Systems, IEEE Trans. on Circuits
and Systems I, vol. 42, No. 11, November 1995
J. Crols, J.; Steyaert, M.; Switched-opamp: an approach to realize full CMOS switched
capacitor circuits at very low power supply voltages” IEEE Journal of Solid-State
Circuits,, Volume: 29 , Issue: 8 , Aug. 1994 Pages:936 - 942
66
Analog & Mixed-Signal Center (AMSC)
References
Very low-voltage analog signal processing based quasi-floating gate transistors,J
Ramirez-Angulo, AJ Lopez-Martin, RG Carvajal, et all, IEEE J. Solid-State Circuits, pp
434- 442, March 2004
Low threshold CMOS circuits with low standby current
Stan, M.R. Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium
on , 10-12 Aug. 1998 Pages:97 - 99
A dynamic threshold voltage MOSFET (DTMOS) for ultra low voltage operation Assaderaghi, F.;
Sinitsky, D.; Parke, S.; Bokor, J.; Ko, P.K.; Chenming Hu;
Electron Devices Meeting, 1994. Technical Digest., International , 11-14 Dec. 1994 Pages:809 812
Resizing rules for MOS analog-design reuse
Galup-Montoro, C.; Schneider, M.C.; Coitinho, R.M.;
Design & Test of Computers, IEEE ,Volume: 19 , Issue: 2 , March-April 2002 Pages:50 - 58
An MOS transistor model for analog circuit design .Cunha, A.I.A.; Schneider, M.C.; GalupMontoro, C.; Solid-State Circuits, IEEE Journal of ,Volume: 33 , Issue: 10 , Oct. 1998
Pages:1510 – 151
Series-parallel association of FET's for high gain and high frequency applications
Galup-Montoro, C.; Schneider, M.C.; Loss, I.J.B.; Solid-State Circuits, IEEE Journal 67
of ,Volume: 29 , Issue: 9 , Sept. 1994 Pages:1094 - 1101
Analog & Mixed-Signal Center (AMSC)
References
S. M. Mallya abd J. H. Nevin, “ Design Procedures for a Fully Differential Folded Cascode CMOS
Operational Amplifier”, IEEE J. of Solid-State Circuits, Vol 24, No. 6, pp1737-1740,
December 1989.
D. B. Ribner, M. A. Copeland. and M. Milkovic, “8OMHz low offsetfully-differential and singleended opamps,” in Proc. IEEE Custom Integruted Circuits Con/., 1983, pp. 74-75.
This reference discusses three different Op Amp topologies:
S. Rabii and B. A. Wooley, “ A 1.8V-V Digital Audio Sigma-Delta Modulator in 0.8-um CMOS”,
IEEE J. of Solid-State Circuits, Vol. 32, N0. 6, pp. 783-796, June 1997
68
Analog & Mixed-Signal Center (AMSC)